sys/dev/serial/rc/rc.c

   1 /*
   2  * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
   3  * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD: src/sys/i386/isa/rc.c,v 1.53.2.1 2001/02/26 04:23:10 jlemon Exp $
  28  * $DragonFly: src/sys/dev/serial/rc/rc.c,v 1.15 2005/06/16 21:12:40 dillon Exp $
  29  *
  30  */
  31
  32 /*
  33  * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
  34  *
  35  */
  36
  37 #include "use_rc.h"
  38
  39 /*#define RCDEBUG*/
  40
  41 #include <sys/param.h>
  42 #include <sys/systm.h>
  43 #include <sys/tty.h>
  44 #include <sys/proc.h>
  45 #include <sys/conf.h>
  46 #include <sys/dkstat.h>
  47 #include <sys/fcntl.h>
  48 #include <sys/interrupt.h>
  49 #include <sys/kernel.h>
  50 #include <sys/thread2.h>
  51 #include <machine/clock.h>
  52 #include <machine/ipl.h>
  53
  54 #include <bus/isa/i386/isa_device.h>
  55
  56 #include <i386/isa/ic/cd180.h>
  57 #include "rcreg.h"
  58
  59 /* Prototypes */
  60 static int     rcprobe         (struct isa_device *);
  61 static int     rcattach        (struct isa_device *);
  62
  63 #define rcin(port)      RC_IN  (nec, port)
  64 #define rcout(port,v)   RC_OUT (nec, port, v)
  65
  66 #define WAITFORCCR(u,c) rc_wait0(nec, (u), (c), __LINE__)
  67 #define CCRCMD(u,c,cmd) WAITFORCCR((u), (c)); rcout(CD180_CCR, (cmd))
  68
  69 #define RC_IBUFSIZE     256
  70 #define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
  71 #define RC_OBUFSIZE     512
  72 #define RC_IHIGHWATER   (3 * RC_IBUFSIZE / 4)
  73 #define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
  74 #define LOTS_OF_EVENTS  64
  75
  76 #define RC_FAKEID       0x10
  77
  78 #define RC_PROBED 1
  79 #define RC_ATTACHED 2
  80
  81 #define GET_UNIT(dev)   (minor(dev) & 0x3F)
  82 #define CALLOUT(dev)    (minor(dev) & 0x80)
  83
  84 /* For isa routines */
  85 struct isa_driver rcdriver = {
  86         rcprobe, rcattach, "rc"
  87 };
  88
  89 static  d_open_t        rcopen;
  90 static  d_close_t       rcclose;
  91 static  d_ioctl_t       rcioctl;
  92
  93 #define CDEV_MAJOR      63
  94 static struct cdevsw rc_cdevsw = {
  95         /* name */      "rc",
  96         /* maj */       CDEV_MAJOR,
  97         /* flags */     D_TTY | D_KQFILTER,
  98         /* port */      NULL,
  99         /* clone */     NULL,
 100
 101         /* open */      rcopen,
 102         /* close */     rcclose,
 103         /* read */      ttyread,
 104         /* write */     ttywrite,
 105         /* ioctl */     rcioctl,
 106         /* poll */      ttypoll,
 107         /* mmap */      nommap,
 108         /* strategy */  nostrategy,
 109         /* dump */      nodump,
 110         /* psize */     nopsize,
 111         /* kqfilter */  ttykqfilter
 112 };
 113
 114 /* Per-board structure */
 115 static struct rc_softc {
 116         u_int           rcb_probed;     /* 1 - probed, 2 - attached */
 117         u_int           rcb_addr;       /* Base I/O addr        */
 118         u_int           rcb_unit;       /* unit #               */
 119         u_char          rcb_dtr;        /* DTR status           */
 120         struct rc_chans *rcb_baserc;    /* base rc ptr          */
 121 } rc_softc[NRC];
 122
 123 /* Per-channel structure */
 124 static struct rc_chans  {
 125         struct rc_softc *rc_rcb;                /* back ptr             */
 126         u_short          rc_flags;              /* Misc. flags          */
 127         int              rc_chan;               /* Channel #            */
 128         u_char           rc_ier;                /* intr. enable reg     */
 129         u_char           rc_msvr;               /* modem sig. status    */
 130         u_char           rc_cor2;               /* options reg          */
 131         u_char           rc_pendcmd;            /* special cmd pending  */
 132         u_int            rc_dtrwait;            /* dtr timeout          */
 133         u_int            rc_dcdwaits;           /* how many waits DCD in open */
 134         u_char           rc_hotchar;            /* end packed optimize */
 135         struct tty      *rc_tp;                 /* tty struct           */
 136         u_char          *rc_iptr;               /* Chars input buffer         */
 137         u_char          *rc_hiwat;              /* hi-water mark        */
 138         u_char          *rc_bufend;             /* end of buffer        */
 139         u_char          *rc_optr;               /* ptr in output buf    */
 140         u_char          *rc_obufend;            /* end of output buf    */
 141         struct callout   rc_dtr_ch;
 142         u_char           rc_ibuf[4 * RC_IBUFSIZE];  /* input buffer         */
 143         u_char           rc_obuf[RC_OBUFSIZE];  /* output buffer        */
 144 } rc_chans[NRC * CD180_NCHAN];
 145
 146 static int rc_scheduled_event = 0;
 147 static struct callout rc_wakeup_ch;
 148
 149 /* for pstat -t */
 150 static struct tty rc_tty[NRC * CD180_NCHAN];
 151 static const int  nrc_tty = NRC * CD180_NCHAN;
 152
 153 /* Flags */
 154 #define RC_DTR_OFF      0x0001          /* DTR wait, for close/open     */
 155 #define RC_ACTOUT       0x0002          /* Dial-out port active         */
 156 #define RC_RTSFLOW      0x0004          /* RTS flow ctl enabled         */
 157 #define RC_CTSFLOW      0x0008          /* CTS flow ctl enabled         */
 158 #define RC_DORXFER      0x0010          /* RXFER event planned          */
 159 #define RC_DOXXFER      0x0020          /* XXFER event planned          */
 160 #define RC_MODCHG       0x0040          /* Modem status changed         */
 161 #define RC_OSUSP        0x0080          /* Output suspended             */
 162 #define RC_OSBUSY       0x0100          /* start() routine in progress  */
 163 #define RC_WAS_BUFOVFL  0x0200          /* low-level buffer ovferflow   */
 164 #define RC_WAS_SILOVFL  0x0400          /* silo buffer overflow         */
 165 #define RC_SEND_RDY     0x0800          /* ready to send */
 166
 167 /* Table for translation of RCSR status bits to internal form */
 168 static int rc_rcsrt[16] = {
 169         0,             TTY_OE,               TTY_FE,
 170         TTY_FE|TTY_OE, TTY_PE,               TTY_PE|TTY_OE,
 171         TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
 172         TTY_BI|TTY_OE, TTY_BI|TTY_FE,        TTY_BI|TTY_FE|TTY_OE,
 173         TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
 174         TTY_BI|TTY_PE|TTY_FE|TTY_OE
 175 };
 176
 177 /* Static prototypes */
 178 static ointhand2_t rcintr;
 179 static void rc_hwreset          (int, int, unsigned int);
 180 static int  rc_test             (int, int);
 181 static void rc_discard_output   (struct rc_chans *);
 182 static void rc_hardclose        (struct rc_chans *);
 183 static int  rc_modctl           (struct rc_chans *, int, int);
 184 static void rc_start            (struct tty *);
 185 static void rc_stop              (struct tty *, int rw);
 186 static int  rc_param            (struct tty *, struct termios *);
 187 static inthand2_t rcpoll;
 188 static void rc_reinit           (struct rc_softc *);
 189 #ifdef RCDEBUG
 190 static void printrcflags();
 191 #endif
 192 static timeout_t rc_dtrwakeup;
 193 static timeout_t rc_wakeup;
 194 static void disc_optim          (struct tty     *tp, struct termios *t, struct rc_chans *);
 195 static void rc_wait0            (int nec, int unit, int chan, int line);
 196
 197 /**********************************************/
 198
 199 /* Quick device probing */
 200 static int
 201 rcprobe(dvp)
 202         struct  isa_device      *dvp;
 203 {
 204         int             irq = ffs(dvp->id_irq) - 1;
 205         int    nec = dvp->id_iobase;
 206
 207         if (dvp->id_unit > NRC)
 208                 return 0;
 209         if (!RC_VALIDADDR(nec)) {
 210                 printf("rc%d: illegal base address %x\n", dvp->id_unit, nec);
 211                 return 0;
 212         }
 213         if (!RC_VALIDIRQ(irq)) {
 214                 printf("rc%d: illegal IRQ value %d\n", dvp->id_unit, irq);
 215                 return 0;
 216         }
 217         rcout(CD180_PPRL, 0x22); /* Random values to Prescale reg. */
 218         rcout(CD180_PPRH, 0x11);
 219         if (rcin(CD180_PPRL) != 0x22 || rcin(CD180_PPRH) != 0x11)
 220                 return 0;
 221         /* Now, test the board more thoroughly, with diagnostic */
 222         if (rc_test(nec, dvp->id_unit))
 223                 return 0;
 224         rc_softc[dvp->id_unit].rcb_probed = RC_PROBED;
 225
 226         return 0xF;
 227 }
 228
 229 static int
 230 rcattach(dvp)
 231         struct  isa_device      *dvp;
 232 {
 233         int            chan, nec = dvp->id_iobase;
 234         struct rc_softc         *rcb = &rc_softc[dvp->id_unit];
 235         struct rc_chans         *rc  = &rc_chans[dvp->id_unit * CD180_NCHAN];
 236         static int              rc_started = 0;
 237         struct tty              *tp;
 238
 239         dvp->id_ointr = rcintr;
 240
 241         /* Thorooughly test the device */
 242         if (rcb->rcb_probed != RC_PROBED)
 243                 return 0;
 244         rcb->rcb_addr   = nec;
 245         rcb->rcb_dtr    = 0;
 246         rcb->rcb_baserc = rc;
 247         rcb->rcb_unit   = dvp->id_unit;
 248         /*rcb->rcb_chipid = 0x10 + dvp->id_unit;*/
 249         printf("rc%d: %d chans, firmware rev. %c\n", rcb->rcb_unit,
 250                 CD180_NCHAN, (rcin(CD180_GFRCR) & 0xF) + 'A');
 251
 252         for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
 253                 callout_init(&rc->rc_dtr_ch);
 254                 rc->rc_rcb     = rcb;
 255                 rc->rc_chan    = chan;
 256                 rc->rc_iptr    = rc->rc_ibuf;
 257                 rc->rc_bufend  = &rc->rc_ibuf[RC_IBUFSIZE];
 258                 rc->rc_hiwat   = &rc->rc_ibuf[RC_IHIGHWATER];
 259                 rc->rc_flags   = rc->rc_ier = rc->rc_msvr = 0;
 260                 rc->rc_cor2    = rc->rc_pendcmd = 0;
 261                 rc->rc_optr    = rc->rc_obufend  = rc->rc_obuf;
 262                 rc->rc_dtrwait = 3 * hz;
 263                 rc->rc_dcdwaits= 0;
 264                 rc->rc_hotchar = 0;
 265                 tp = rc->rc_tp = &rc_tty[chan + (dvp->id_unit * CD180_NCHAN)];
 266                 ttychars(tp);
 267                 tp->t_lflag = tp->t_iflag = tp->t_oflag = 0;
 268                 tp->t_cflag = TTYDEF_CFLAG;
 269                 tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
 270         }
 271         rcb->rcb_probed = RC_ATTACHED;
 272         if (!rc_started) {
 273                 cdevsw_add(&rc_cdevsw, -1, rcb->rcb_unit);
 274                 register_swi(SWI_TTY, rcpoll, NULL, "rcpoll");
 275                 callout_init(&rc_wakeup_ch);
 276                 rc_wakeup(NULL);
 277                 rc_started = 1;
 278         }
 279         return 1;
 280 }
 281
 282 /* RC interrupt handling */
 283 static void
 284 rcintr(unit)
 285         int             unit;
 286 {
 287         struct rc_softc        *rcb = &rc_softc[unit];
 288         struct rc_chans        *rc;
 289         int                    nec, resid;
 290         u_char                 val, iack, bsr, ucnt, *optr;
 291         int                             good_data, t_state;
 292
 293         if (rcb->rcb_probed != RC_ATTACHED) {
 294                 printf("rc%d: bogus interrupt\n", unit);
 295                 return;
 296         }
 297         nec = rcb->rcb_addr;
 298
 299         bsr = ~(rcin(RC_BSR));
 300
 301         if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
 302                 printf("rc%d: extra interrupt\n", unit);
 303                 rcout(CD180_EOIR, 0);
 304                 return;
 305         }
 306
 307         while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
 308 #ifdef RCDEBUG_DETAILED
 309                 printf("rc%d: intr (%02x) %s%s%s%s\n", unit, bsr,
 310                         (bsr & RC_BSR_TOUT)?"TOUT ":"",
 311                         (bsr & RC_BSR_RXINT)?"RXINT ":"",
 312                         (bsr & RC_BSR_TXINT)?"TXINT ":"",
 313                         (bsr & RC_BSR_MOINT)?"MOINT":"");
 314 #endif
 315                 if (bsr & RC_BSR_TOUT) {
 316                         printf("rc%d: hardware failure, reset board\n", unit);
 317                         rcout(RC_CTOUT, 0);
 318                         rc_reinit(rcb);
 319                         return;
 320                 }
 321                 if (bsr & RC_BSR_RXINT) {
 322                         iack = rcin(RC_PILR_RX);
 323                         good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
 324                         if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
 325                                 printf("rc%d: fake rxint: %02x\n", unit, iack);
 326                                 goto more_intrs;
 327                         }
 328                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 329                         t_state = rc->rc_tp->t_state;
 330                         /* Do RTS flow control stuff */
 331                         if (  (rc->rc_flags & RC_RTSFLOW)
 332                             || !(t_state & TS_ISOPEN)
 333                            ) {
 334                                 if (  (   !(t_state & TS_ISOPEN)
 335                                        || (t_state & TS_TBLOCK)
 336                                       )
 337                                     && (rc->rc_msvr & MSVR_RTS)
 338                                    )
 339                                         rcout(CD180_MSVR,
 340                                                 rc->rc_msvr &= ~MSVR_RTS);
 341                                 else if (!(rc->rc_msvr & MSVR_RTS))
 342                                         rcout(CD180_MSVR,
 343                                                 rc->rc_msvr |= MSVR_RTS);
 344                         }
 345                         ucnt  = rcin(CD180_RDCR) & 0xF;
 346                         resid = 0;
 347
 348                         if (t_state & TS_ISOPEN) {
 349                                 /* check for input buffer overflow */
 350                                 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
 351                                         resid  = ucnt;
 352                                         ucnt   = rc->rc_bufend - rc->rc_iptr;
 353                                         resid -= ucnt;
 354                                         if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
 355                                                 rc->rc_flags |= RC_WAS_BUFOVFL;
 356                                                 rc_scheduled_event++;
 357                                         }
 358                                 }
 359                                 optr = rc->rc_iptr;
 360                                 /* check foor good data */
 361                                 if (good_data) {
 362                                         while (ucnt-- > 0) {
 363                                                 val = rcin(CD180_RDR);
 364                                                 optr[0] = val;
 365                                                 optr[INPUT_FLAGS_SHIFT] = 0;
 366                                                 optr++;
 367                                                 rc_scheduled_event++;
 368                                                 if (val != 0 && val == rc->rc_hotchar)
 369                                                         setsofttty();
 370                                         }
 371                                 } else {
 372                                         /* Store also status data */
 373                                         while (ucnt-- > 0) {
 374                                                 iack = rcin(CD180_RCSR);
 375                                                 if (iack & RCSR_Timeout)
 376                                                         break;
 377                                                 if (   (iack & RCSR_OE)
 378                                                     && !(rc->rc_flags & RC_WAS_SILOVFL)) {
 379                                                         rc->rc_flags |= RC_WAS_SILOVFL;
 380                                                         rc_scheduled_event++;
 381                                                 }
 382                                                 val = rcin(CD180_RDR);
 383                                                 /*
 384                                                   Don't store PE if IGNPAR and BREAK if IGNBRK,
 385                                                   this hack allows "raw" tty optimization
 386                                                   works even if IGN* is set.
 387                                                 */
 388                                                 if (   !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
 389                                                     || ((!(iack & (RCSR_PE|RCSR_FE))
 390                                                     ||  !(rc->rc_tp->t_iflag & IGNPAR))
 391                                                     && (!(iack & RCSR_Break)
 392                                                     ||  !(rc->rc_tp->t_iflag & IGNBRK)))) {
 393                                                         if (   (iack & (RCSR_PE|RCSR_FE))
 394                                                             && (t_state & TS_CAN_BYPASS_L_RINT)
 395                                                             && ((iack & RCSR_FE)
 396                                                             ||  ((iack & RCSR_PE)
 397                                                             &&  (rc->rc_tp->t_iflag & INPCK))))
 398                                                                 val = 0;
 399                                                         else if (val != 0 && val == rc->rc_hotchar)
 400                                                                 setsofttty();
 401                                                         optr[0] = val;
 402                                                         optr[INPUT_FLAGS_SHIFT] = iack;
 403                                                         optr++;
 404                                                         rc_scheduled_event++;
 405                                                 }
 406                                         }
 407                                 }
 408                                 rc->rc_iptr = optr;
 409                                 rc->rc_flags |= RC_DORXFER;
 410                         } else
 411                                 resid = ucnt;
 412                         /* Clear FIFO if necessary */
 413                         while (resid-- > 0) {
 414                                 if (!good_data)
 415                                         iack = rcin(CD180_RCSR);
 416                                 else
 417                                         iack = 0;
 418                                 if (iack & RCSR_Timeout)
 419                                         break;
 420                                 (void) rcin(CD180_RDR);
 421                         }
 422                         goto more_intrs;
 423                 }
 424                 if (bsr & RC_BSR_MOINT) {
 425                         iack = rcin(RC_PILR_MODEM);
 426                         if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
 427                                 printf("rc%d: fake moint: %02x\n", unit, iack);
 428                                 goto more_intrs;
 429                         }
 430                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 431                         iack = rcin(CD180_MCR);
 432                         rc->rc_msvr = rcin(CD180_MSVR);
 433                         rcout(CD180_MCR, 0);
 434 #ifdef RCDEBUG
 435                         printrcflags(rc, "moint");
 436 #endif
 437                         if (rc->rc_flags & RC_CTSFLOW) {
 438                                 if (rc->rc_msvr & MSVR_CTS)
 439                                         rc->rc_flags |= RC_SEND_RDY;
 440                                 else
 441                                         rc->rc_flags &= ~RC_SEND_RDY;
 442                         } else
 443                                 rc->rc_flags |= RC_SEND_RDY;
 444                         if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
 445                                 rc_scheduled_event += LOTS_OF_EVENTS;
 446                                 rc->rc_flags |= RC_MODCHG;
 447                                 setsofttty();
 448                         }
 449                         goto more_intrs;
 450                 }
 451                 if (bsr & RC_BSR_TXINT) {
 452                         iack = rcin(RC_PILR_TX);
 453                         if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
 454                                 printf("rc%d: fake txint: %02x\n", unit, iack);
 455                                 goto more_intrs;
 456                         }
 457                         rc = rcb->rcb_baserc + ((rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH);
 458                         if (    (rc->rc_flags & RC_OSUSP)
 459                             || !(rc->rc_flags & RC_SEND_RDY)
 460                            )
 461                                 goto more_intrs;
 462                         /* Handle breaks and other stuff */
 463                         if (rc->rc_pendcmd) {
 464                                 rcout(CD180_COR2, rc->rc_cor2 |= COR2_ETC);
 465                                 rcout(CD180_TDR,  CD180_C_ESC);
 466                                 rcout(CD180_TDR,  rc->rc_pendcmd);
 467                                 rcout(CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
 468                                 rc->rc_pendcmd = 0;
 469                                 goto more_intrs;
 470                         }
 471                         optr = rc->rc_optr;
 472                         resid = rc->rc_obufend - optr;
 473                         if (resid > CD180_NFIFO)
 474                                 resid = CD180_NFIFO;
 475                         while (resid-- > 0)
 476                                 rcout(CD180_TDR, *optr++);
 477                         rc->rc_optr = optr;
 478
 479                         /* output completed? */
 480                         if (optr >= rc->rc_obufend) {
 481                                 rcout(CD180_IER, rc->rc_ier &= ~IER_TxRdy);
 482 #ifdef RCDEBUG
 483                                 printf("rc%d/%d: output completed\n", unit, rc->rc_chan);
 484 #endif
 485                                 if (!(rc->rc_flags & RC_DOXXFER)) {
 486                                         rc_scheduled_event += LOTS_OF_EVENTS;
 487                                         rc->rc_flags |= RC_DOXXFER;
 488                                         setsofttty();
 489                                 }
 490                         }
 491                 }
 492         more_intrs:
 493                 rcout(CD180_EOIR, 0);   /* end of interrupt */
 494                 rcout(RC_CTOUT, 0);
 495                 bsr = ~(rcin(RC_BSR));
 496         }
 497 }
 498
 499 /* Feed characters to output buffer */
 500 static void rc_start(tp)
 501 struct tty *tp;
 502 {
 503         struct rc_chans       *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 504         int                    nec = rc->rc_rcb->rcb_addr;
 505
 506         if (rc->rc_flags & RC_OSBUSY)
 507                 return;
 508         crit_enter();
 509         rc->rc_flags |= RC_OSBUSY;
 510         cpu_disable_intr();
 511         if (tp->t_state & TS_TTSTOP)
 512                 rc->rc_flags |= RC_OSUSP;
 513         else
 514                 rc->rc_flags &= ~RC_OSUSP;
 515         /* Do RTS flow control stuff */
 516         if (   (rc->rc_flags & RC_RTSFLOW)
 517             && (tp->t_state & TS_TBLOCK)
 518             && (rc->rc_msvr & MSVR_RTS)
 519            ) {
 520                 rcout(CD180_CAR, rc->rc_chan);
 521                 rcout(CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
 522         } else if (!(rc->rc_msvr & MSVR_RTS)) {
 523                 rcout(CD180_CAR, rc->rc_chan);
 524                 rcout(CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
 525         }
 526         cpu_enable_intr();
 527         if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
 528                 goto out;
 529 #ifdef RCDEBUG
 530         printrcflags(rc, "rcstart");
 531 #endif
 532         ttwwakeup(tp);
 533 #ifdef RCDEBUG
 534         printf("rcstart: outq = %d obuf = %d\n",
 535                 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
 536 #endif
 537         if (tp->t_state & TS_BUSY)
 538                 goto    out;    /* output still in progress ... */
 539
 540         if (tp->t_outq.c_cc > 0) {
 541                 u_int   ocnt;
 542
 543                 tp->t_state |= TS_BUSY;
 544                 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
 545                 cpu_disable_intr();
 546                 rc->rc_optr = rc->rc_obuf;
 547                 rc->rc_obufend = rc->rc_optr + ocnt;
 548                 cpu_enable_intr();
 549                 if (!(rc->rc_ier & IER_TxRdy)) {
 550 #ifdef RCDEBUG
 551                         printf("rc%d/%d: rcstart enable txint\n", rc->rc_rcb->rcb_unit, rc->rc_chan);
 552 #endif
 553                         rcout(CD180_CAR, rc->rc_chan);
 554                         rcout(CD180_IER, rc->rc_ier |= IER_TxRdy);
 555                 }
 556         }
 557 out:
 558         rc->rc_flags &= ~RC_OSBUSY;
 559         crit_exit();
 560 }
 561
 562 /* Handle delayed events. */
 563 void
 564 rcpoll(void *dummy)
 565 {
 566         struct rc_chans *rc;
 567         struct rc_softc *rcb;
 568         u_char        *tptr, *eptr;
 569         struct tty    *tp;
 570         int            chan, icnt, nec, unit;
 571
 572         if (rc_scheduled_event == 0)
 573                 return;
 574 repeat:
 575         for (unit = 0; unit < NRC; unit++) {
 576                 rcb = &rc_softc[unit];
 577                 rc = rcb->rcb_baserc;
 578                 nec = rc->rc_rcb->rcb_addr;
 579                 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
 580                         tp = rc->rc_tp;
 581 #ifdef RCDEBUG
 582                         if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
 583                             RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
 584                                 printrcflags(rc, "rcevent");
 585 #endif
 586                         if (rc->rc_flags & RC_WAS_BUFOVFL) {
 587                                 cpu_disable_intr();
 588                                 rc->rc_flags &= ~RC_WAS_BUFOVFL;
 589                                 rc_scheduled_event--;
 590                                 cpu_enable_intr();
 591                                 printf("rc%d/%d: interrupt-level buffer overflow\n",
 592                                         unit, chan);
 593                         }
 594                         if (rc->rc_flags & RC_WAS_SILOVFL) {
 595                                 cpu_disable_intr();
 596                                 rc->rc_flags &= ~RC_WAS_SILOVFL;
 597                                 rc_scheduled_event--;
 598                                 cpu_enable_intr();
 599                                 printf("rc%d/%d: silo overflow\n",
 600                                         unit, chan);
 601                         }
 602                         if (rc->rc_flags & RC_MODCHG) {
 603                                 cpu_disable_intr();
 604                                 rc->rc_flags &= ~RC_MODCHG;
 605                                 rc_scheduled_event -= LOTS_OF_EVENTS;
 606                                 cpu_enable_intr();
 607                                 (*linesw[tp->t_line].l_modem)(tp, !!(rc->rc_msvr & MSVR_CD));
 608                         }
 609                         if (rc->rc_flags & RC_DORXFER) {
 610                                 cpu_disable_intr();
 611                                 rc->rc_flags &= ~RC_DORXFER;
 612                                 eptr = rc->rc_iptr;
 613                                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
 614                                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
 615                                 else
 616                                         tptr = rc->rc_ibuf;
 617                                 icnt = eptr - tptr;
 618                                 if (icnt > 0) {
 619                                         if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
 620                                                 rc->rc_iptr   = rc->rc_ibuf;
 621                                                 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
 622                                                 rc->rc_hiwat  = &rc->rc_ibuf[RC_IHIGHWATER];
 623                                         } else {
 624                                                 rc->rc_iptr   = &rc->rc_ibuf[RC_IBUFSIZE];
 625                                                 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
 626                                                 rc->rc_hiwat  =
 627                                                         &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
 628                                         }
 629                                         if (   (rc->rc_flags & RC_RTSFLOW)
 630                                             && (tp->t_state & TS_ISOPEN)
 631                                             && !(tp->t_state & TS_TBLOCK)
 632                                             && !(rc->rc_msvr & MSVR_RTS)
 633                                             ) {
 634                                                 rcout(CD180_CAR, chan);
 635                                                 rcout(CD180_MSVR,
 636                                                         rc->rc_msvr |= MSVR_RTS);
 637                                         }
 638                                         rc_scheduled_event -= icnt;
 639                                 }
 640                                 cpu_enable_intr();
 641
 642                                 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
 643                                         goto done1;
 644
 645                                 if (   (tp->t_state & TS_CAN_BYPASS_L_RINT)
 646                                     && !(tp->t_state & TS_LOCAL)) {
 647                                         if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
 648                                             && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
 649                                             && !(tp->t_state & TS_TBLOCK))
 650                                                 ttyblock(tp);
 651                                         tk_nin += icnt;
 652                                         tk_rawcc += icnt;
 653                                         tp->t_rawcc += icnt;
 654                                         if (b_to_q(tptr, icnt, &tp->t_rawq))
 655                                                 printf("rc%d/%d: tty-level buffer overflow\n",
 656                                                         unit, chan);
 657                                         ttwakeup(tp);
 658                                         if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
 659                                             || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
 660                                                 tp->t_state &= ~TS_TTSTOP;
 661                                                 tp->t_lflag &= ~FLUSHO;
 662                                                 rc_start(tp);
 663                                         }
 664                                 } else {
 665                                         for (; tptr < eptr; tptr++)
 666                                                 (*linesw[tp->t_line].l_rint)
 667                                                     (tptr[0] |
 668                                                     rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF], tp);
 669                                 }
 670 done1: ;
 671                         }
 672                         if (rc->rc_flags & RC_DOXXFER) {
 673                                 cpu_disable_intr();
 674                                 rc_scheduled_event -= LOTS_OF_EVENTS;
 675                                 rc->rc_flags &= ~RC_DOXXFER;
 676                                 rc->rc_tp->t_state &= ~TS_BUSY;
 677                                 cpu_enable_intr();
 678                                 (*linesw[tp->t_line].l_start)(tp);
 679                         }
 680                 }
 681                 if (rc_scheduled_event == 0)
 682                         break;
 683         }
 684         if (rc_scheduled_event >= LOTS_OF_EVENTS)
 685                 goto repeat;
 686 }
 687
 688 static  void
 689 rc_stop(tp, rw)
 690         struct tty     *tp;
 691         int                     rw;
 692 {
 693         struct rc_chans        *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 694         u_char *tptr, *eptr;
 695
 696 #ifdef RCDEBUG
 697         printf("rc%d/%d: rc_stop %s%s\n", rc->rc_rcb->rcb_unit, rc->rc_chan,
 698                 (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
 699 #endif
 700         if (rw & FWRITE)
 701                 rc_discard_output(rc);
 702         cpu_disable_intr();
 703         if (rw & FREAD) {
 704                 rc->rc_flags &= ~RC_DORXFER;
 705                 eptr = rc->rc_iptr;
 706                 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
 707                         tptr = &rc->rc_ibuf[RC_IBUFSIZE];
 708                         rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
 709                 } else {
 710                         tptr = rc->rc_ibuf;
 711                         rc->rc_iptr = rc->rc_ibuf;
 712                 }
 713                 rc_scheduled_event -= eptr - tptr;
 714         }
 715         if (tp->t_state & TS_TTSTOP)
 716                 rc->rc_flags |= RC_OSUSP;
 717         else
 718                 rc->rc_flags &= ~RC_OSUSP;
 719         cpu_enable_intr();
 720 }
 721
 722 static  int
 723 rcopen(dev, flag, mode, td)
 724         dev_t           dev;
 725         int             flag, mode;
 726         struct thread *td;
 727 {
 728         struct rc_chans *rc;
 729         struct tty      *tp;
 730         int             unit, nec, error = 0;
 731
 732         unit = GET_UNIT(dev);
 733         if (unit >= NRC * CD180_NCHAN)
 734                 return ENXIO;
 735         if (rc_softc[unit / CD180_NCHAN].rcb_probed != RC_ATTACHED)
 736                 return ENXIO;
 737         rc  = &rc_chans[unit];
 738         tp  = rc->rc_tp;
 739         dev->si_tty = tp;
 740         nec = rc->rc_rcb->rcb_addr;
 741 #ifdef RCDEBUG
 742         printf("rc%d/%d: rcopen: dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
 743 #endif
 744         crit_enter();
 745
 746 again:
 747         while (rc->rc_flags & RC_DTR_OFF) {
 748                 error = tsleep(&(rc->rc_dtrwait), PCATCH, "rcdtr", 0);
 749                 if (error != 0)
 750                         goto out;
 751         }
 752         if (tp->t_state & TS_ISOPEN) {
 753                 if (CALLOUT(dev)) {
 754                         if (!(rc->rc_flags & RC_ACTOUT)) {
 755                                 error = EBUSY;
 756                                 goto out;
 757                         }
 758                 } else {
 759                         if (rc->rc_flags & RC_ACTOUT) {
 760                                 if (flag & O_NONBLOCK) {
 761                                         error = EBUSY;
 762                                         goto out;
 763                                 }
 764                                 error = tsleep(&rc->rc_rcb, PCATCH, "rcbi", 0);
 765                                 if (error)
 766                                         goto out;
 767                                 goto again;
 768                         }
 769                 }
 770                 if (tp->t_state & TS_XCLUDE &&
 771                     suser(td)) {
 772                         error = EBUSY;
 773                         goto out;
 774                 }
 775         } else {
 776                 tp->t_oproc   = rc_start;
 777                 tp->t_param   = rc_param;
 778                 tp->t_stop    = rc_stop;
 779                 tp->t_dev     = dev;
 780
 781                 if (CALLOUT(dev))
 782                         tp->t_cflag |= CLOCAL;
 783                 else
 784                         tp->t_cflag &= ~CLOCAL;
 785
 786                 error = rc_param(tp, &tp->t_termios);
 787                 if (error)
 788                         goto out;
 789                 (void) rc_modctl(rc, TIOCM_RTS|TIOCM_DTR, DMSET);
 790
 791                 if ((rc->rc_msvr & MSVR_CD) || CALLOUT(dev))
 792                         (*linesw[tp->t_line].l_modem)(tp, 1);
 793         }
 794         if (!(tp->t_state & TS_CARR_ON) && !CALLOUT(dev)
 795             && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) {
 796                 rc->rc_dcdwaits++;
 797                 error = tsleep(TSA_CARR_ON(tp), PCATCH, "rcdcd", 0);
 798                 rc->rc_dcdwaits--;
 799                 if (error != 0)
 800                         goto out;
 801                 goto again;
 802         }
 803         error = (*linesw[tp->t_line].l_open)(dev, tp);
 804         disc_optim(tp, &tp->t_termios, rc);
 805         if ((tp->t_state & TS_ISOPEN) && CALLOUT(dev))
 806                 rc->rc_flags |= RC_ACTOUT;
 807 out:
 808         crit_exit();
 809
 810         if(rc->rc_dcdwaits == 0 && !(tp->t_state & TS_ISOPEN))
 811                 rc_hardclose(rc);
 812
 813         return error;
 814 }
 815
 816 static  int
 817 rcclose(dev, flag, mode, td)
 818         dev_t           dev;
 819         int             flag, mode;
 820         struct thread *td;
 821 {
 822         struct rc_chans *rc;
 823         struct tty      *tp;
 824         int unit = GET_UNIT(dev);
 825
 826         if (unit >= NRC * CD180_NCHAN)
 827                 return ENXIO;
 828         rc  = &rc_chans[unit];
 829         tp  = rc->rc_tp;
 830 #ifdef RCDEBUG
 831         printf("rc%d/%d: rcclose dev %x\n", rc->rc_rcb->rcb_unit, unit, dev);
 832 #endif
 833         crit_enter();
 834         (*linesw[tp->t_line].l_close)(tp, flag);
 835         disc_optim(tp, &tp->t_termios, rc);
 836         rc_stop(tp, FREAD | FWRITE);
 837         rc_hardclose(rc);
 838         ttyclose(tp);
 839         crit_exit();
 840         return 0;
 841 }
 842
 843 static void rc_hardclose(rc)
 844 struct rc_chans *rc;
 845 {
 846         int nec = rc->rc_rcb->rcb_addr;
 847         struct tty *tp = rc->rc_tp;
 848
 849         crit_enter();
 850         rcout(CD180_CAR, rc->rc_chan);
 851
 852         /* Disable rx/tx intrs */
 853         rcout(CD180_IER, rc->rc_ier = 0);
 854         if (   (tp->t_cflag & HUPCL)
 855             || (!(rc->rc_flags & RC_ACTOUT)
 856                && !(rc->rc_msvr & MSVR_CD)
 857                && !(tp->t_cflag & CLOCAL))
 858             || !(tp->t_state & TS_ISOPEN)
 859            ) {
 860                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
 861                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
 862                 (void) rc_modctl(rc, TIOCM_RTS, DMSET);
 863                 if (rc->rc_dtrwait) {
 864                         callout_reset(&rc->rc_dtr_ch, rc->rc_dtrwait,
 865                                 rc_dtrwakeup, rc);
 866                         rc->rc_flags |= RC_DTR_OFF;
 867                 }
 868         }
 869         rc->rc_flags &= ~RC_ACTOUT;
 870         wakeup((caddr_t) &rc->rc_rcb);  /* wake bi */
 871         wakeup(TSA_CARR_ON(tp));
 872         crit_exit();
 873 }
 874
 875 /* Reset the bastard */
 876 static void rc_hwreset(unit, nec, chipid)
 877         int    unit, nec;
 878         unsigned int    chipid;
 879 {
 880         CCRCMD(unit, -1, CCR_HWRESET);            /* Hardware reset */
 881         DELAY(20000);
 882         WAITFORCCR(unit, -1);
 883
 884         rcout(RC_CTOUT, 0);             /* Clear timeout  */
 885         rcout(CD180_GIVR,  chipid);
 886         rcout(CD180_GICR,  0);
 887
 888         /* Set Prescaler Registers (1 msec) */
 889         rcout(CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
 890         rcout(CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
 891
 892         /* Initialize Priority Interrupt Level Registers */
 893         rcout(CD180_PILR1, RC_PILR_MODEM);
 894         rcout(CD180_PILR2, RC_PILR_TX);
 895         rcout(CD180_PILR3, RC_PILR_RX);
 896
 897         /* Reset DTR */
 898         rcout(RC_DTREG, ~0);
 899 }
 900
 901 /* Set channel parameters */
 902 static int rc_param(tp, ts)
 903         struct  tty    *tp;
 904         struct termios          *ts;
 905 {
 906         struct rc_chans *rc = &rc_chans[GET_UNIT(tp->t_dev)];
 907         int    nec = rc->rc_rcb->rcb_addr;
 908         int      idivs, odivs, val, cflag, iflag, lflag, inpflow;
 909
 910         if (   ts->c_ospeed < 0 || ts->c_ospeed > 76800
 911             || ts->c_ispeed < 0 || ts->c_ispeed > 76800
 912            )
 913                 return (EINVAL);
 914         if (ts->c_ispeed == 0)
 915                 ts->c_ispeed = ts->c_ospeed;
 916         odivs = RC_BRD(ts->c_ospeed);
 917         idivs = RC_BRD(ts->c_ispeed);
 918
 919         crit_enter();
 920
 921         /* Select channel */
 922         rcout(CD180_CAR, rc->rc_chan);
 923
 924         /* If speed == 0, hangup line */
 925         if (ts->c_ospeed == 0) {
 926                 CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan, CCR_ResetChan);
 927                 WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
 928                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
 929         }
 930
 931         tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
 932         cflag = ts->c_cflag;
 933         iflag = ts->c_iflag;
 934         lflag = ts->c_lflag;
 935
 936         if (idivs > 0) {
 937                 rcout(CD180_RBPRL, idivs & 0xFF);
 938                 rcout(CD180_RBPRH, idivs >> 8);
 939         }
 940         if (odivs > 0) {
 941                 rcout(CD180_TBPRL, odivs & 0xFF);
 942                 rcout(CD180_TBPRH, odivs >> 8);
 943         }
 944
 945         /* set timeout value */
 946         if (ts->c_ispeed > 0) {
 947                 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
 948
 949                 if (   !(lflag & ICANON)
 950                     && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
 951                     && ts->c_cc[VTIME] * 10 > itm)
 952                         itm = ts->c_cc[VTIME] * 10;
 953
 954                 rcout(CD180_RTPR, itm <= 255 ? itm : 255);
 955         }
 956
 957         switch (cflag & CSIZE) {
 958                 case CS5:       val = COR1_5BITS;      break;
 959                 case CS6:       val = COR1_6BITS;      break;
 960                 case CS7:       val = COR1_7BITS;      break;
 961                 default:
 962                 case CS8:       val = COR1_8BITS;      break;
 963         }
 964         if (cflag & PARENB) {
 965                 val |= COR1_NORMPAR;
 966                 if (cflag & PARODD)
 967                         val |= COR1_ODDP;
 968                 if (!(cflag & INPCK))
 969                         val |= COR1_Ignore;
 970         } else
 971                 val |= COR1_Ignore;
 972         if (cflag & CSTOPB)
 973                 val |= COR1_2SB;
 974         rcout(CD180_COR1, val);
 975
 976         /* Set FIFO threshold */
 977         val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
 978         inpflow = 0;
 979         if (   (iflag & IXOFF)
 980             && (   ts->c_cc[VSTOP] != _POSIX_VDISABLE
 981                 && (   ts->c_cc[VSTART] != _POSIX_VDISABLE
 982                     || (iflag & IXANY)
 983                    )
 984                )
 985            ) {
 986                 inpflow = 1;
 987                 val |= COR3_SCDE|COR3_FCT;
 988         }
 989         rcout(CD180_COR3, val);
 990
 991         /* Initialize on-chip automatic flow control */
 992         val = 0;
 993         rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
 994         if (cflag & CCTS_OFLOW) {
 995                 rc->rc_flags |= RC_CTSFLOW;
 996                 val |= COR2_CtsAE;
 997         } else
 998                 rc->rc_flags |= RC_SEND_RDY;
 999         if (tp->t_state & TS_TTSTOP)
1000                 rc->rc_flags |= RC_OSUSP;
1001         else
1002                 rc->rc_flags &= ~RC_OSUSP;
1003         if (cflag & CRTS_IFLOW)
1004                 rc->rc_flags |= RC_RTSFLOW;
1005         else
1006                 rc->rc_flags &= ~RC_RTSFLOW;
1007
1008         if (inpflow) {
1009                 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
1010                         rcout(CD180_SCHR1, ts->c_cc[VSTART]);
1011                 rcout(CD180_SCHR2, ts->c_cc[VSTOP]);
1012                 val |= COR2_TxIBE;
1013                 if (iflag & IXANY)
1014                         val |= COR2_IXM;
1015         }
1016
1017         rcout(CD180_COR2, rc->rc_cor2 = val);
1018
1019         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1020                 CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1021
1022         disc_optim(tp, ts, rc);
1023
1024         /* modem ctl */
1025         val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
1026         if (cflag & CCTS_OFLOW)
1027                 val |= MCOR1_CTSzd;
1028         rcout(CD180_MCOR1, val);
1029
1030         val = cflag & CLOCAL ? 0 : MCOR2_CDod;
1031         if (cflag & CCTS_OFLOW)
1032                 val |= MCOR2_CTSod;
1033         rcout(CD180_MCOR2, val);
1034
1035         /* enable i/o and interrupts */
1036         CCRCMD(rc->rc_rcb->rcb_unit, rc->rc_chan,
1037                 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1038         WAITFORCCR(rc->rc_rcb->rcb_unit, rc->rc_chan);
1039
1040         rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1041         if (cflag & CCTS_OFLOW)
1042                 rc->rc_ier |= IER_CTS;
1043         if (cflag & CREAD)
1044                 rc->rc_ier |= IER_RxData;
1045         if (tp->t_state & TS_BUSY)
1046                 rc->rc_ier |= IER_TxRdy;
1047         if (ts->c_ospeed != 0)
1048                 rc_modctl(rc, TIOCM_DTR, DMBIS);
1049         if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1050                 rc->rc_flags |= RC_SEND_RDY;
1051         rcout(CD180_IER, rc->rc_ier);
1052         crit_exit();
1053         return 0;
1054 }
1055
1056 /* Re-initialize board after bogus interrupts */
1057 static void rc_reinit(rcb)
1058 struct rc_softc         *rcb;
1059 {
1060         struct rc_chans       *rc, *rce;
1061         int                    nec;
1062
1063         nec = rcb->rcb_addr;
1064         rc_hwreset(rcb->rcb_unit, nec, RC_FAKEID);
1065         rc  = &rc_chans[rcb->rcb_unit * CD180_NCHAN];
1066         rce = rc + CD180_NCHAN;
1067         for (; rc < rce; rc++)
1068                 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1069 }
1070
1071 static  int
1072 rcioctl(dev, cmd, data, flag, td)
1073 dev_t           dev;
1074 u_long          cmd;
1075 int             flag;
1076 caddr_t         data;
1077 struct thread *td;
1078 {
1079         struct rc_chans       *rc = &rc_chans[GET_UNIT(dev)];
1080         int                   error;
1081         struct tty                     *tp = rc->rc_tp;
1082
1083         error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td);
1084         if (error != ENOIOCTL)
1085                 return (error);
1086         error = ttioctl(tp, cmd, data, flag);
1087         disc_optim(tp, &tp->t_termios, rc);
1088         if (error != ENOIOCTL)
1089                 return (error);
1090         crit_enter();
1091
1092         switch (cmd) {
1093             case TIOCSBRK:
1094                 rc->rc_pendcmd = CD180_C_SBRK;
1095                 break;
1096
1097             case TIOCCBRK:
1098                 rc->rc_pendcmd = CD180_C_EBRK;
1099                 break;
1100
1101             case TIOCSDTR:
1102                 (void) rc_modctl(rc, TIOCM_DTR, DMBIS);
1103                 break;
1104
1105             case TIOCCDTR:
1106                 (void) rc_modctl(rc, TIOCM_DTR, DMBIC);
1107                 break;
1108
1109             case TIOCMGET:
1110                 *(int *) data = rc_modctl(rc, 0, DMGET);
1111                 break;
1112
1113             case TIOCMSET:
1114                 (void) rc_modctl(rc, *(int *) data, DMSET);
1115                 break;
1116
1117             case TIOCMBIC:
1118                 (void) rc_modctl(rc, *(int *) data, DMBIC);
1119                 break;
1120
1121             case TIOCMBIS:
1122                 (void) rc_modctl(rc, *(int *) data, DMBIS);
1123                 break;
1124
1125             case TIOCMSDTRWAIT:
1126                 error = suser(td);
1127                 if (error != 0) {
1128                         crit_exit();
1129                         return (error);
1130                 }
1131                 rc->rc_dtrwait = *(int *)data * hz / 100;
1132                 break;
1133
1134             case TIOCMGDTRWAIT:
1135                 *(int *)data = rc->rc_dtrwait * 100 / hz;
1136                 break;
1137
1138             default:
1139                 crit_exit();
1140                 return ENOTTY;
1141         }
1142         crit_exit();
1143         return 0;
1144 }
1145
1146
1147 /* Modem control routines */
1148
1149 static int rc_modctl(rc, bits, cmd)
1150 struct rc_chans       *rc;
1151 int                             bits, cmd;
1152 {
1153         int    nec = rc->rc_rcb->rcb_addr;
1154         u_char         *dtr = &rc->rc_rcb->rcb_dtr, msvr;
1155
1156         rcout(CD180_CAR, rc->rc_chan);
1157
1158         switch (cmd) {
1159             case DMSET:
1160                 rcout(RC_DTREG, (bits & TIOCM_DTR) ?
1161                                 ~(*dtr |= 1 << rc->rc_chan) :
1162                                 ~(*dtr &= ~(1 << rc->rc_chan)));
1163                 msvr = rcin(CD180_MSVR);
1164                 if (bits & TIOCM_RTS)
1165                         msvr |= MSVR_RTS;
1166                 else
1167                         msvr &= ~MSVR_RTS;
1168                 if (bits & TIOCM_DTR)
1169                         msvr |= MSVR_DTR;
1170                 else
1171                         msvr &= ~MSVR_DTR;
1172                 rcout(CD180_MSVR, msvr);
1173                 break;
1174
1175             case DMBIS:
1176                 if (bits & TIOCM_DTR)
1177                         rcout(RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1178                 msvr = rcin(CD180_MSVR);
1179                 if (bits & TIOCM_RTS)
1180                         msvr |= MSVR_RTS;
1181                 if (bits & TIOCM_DTR)
1182                         msvr |= MSVR_DTR;
1183                 rcout(CD180_MSVR, msvr);
1184                 break;
1185
1186             case DMGET:
1187                 bits = TIOCM_LE;
1188                 msvr = rc->rc_msvr = rcin(CD180_MSVR);
1189
1190                 if (msvr & MSVR_RTS)
1191                         bits |= TIOCM_RTS;
1192                 if (msvr & MSVR_CTS)
1193                         bits |= TIOCM_CTS;
1194                 if (msvr & MSVR_DSR)
1195                         bits |= TIOCM_DSR;
1196                 if (msvr & MSVR_DTR)
1197                         bits |= TIOCM_DTR;
1198                 if (msvr & MSVR_CD)
1199                         bits |= TIOCM_CD;
1200                 if (~rcin(RC_RIREG) & (1 << rc->rc_chan))
1201                         bits |= TIOCM_RI;
1202                 return bits;
1203
1204             case DMBIC:
1205                 if (bits & TIOCM_DTR)
1206                         rcout(RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1207                 msvr = rcin(CD180_MSVR);
1208                 if (bits & TIOCM_RTS)
1209                         msvr &= ~MSVR_RTS;
1210                 if (bits & TIOCM_DTR)
1211                         msvr &= ~MSVR_DTR;
1212                 rcout(CD180_MSVR, msvr);
1213                 break;
1214         }
1215         rc->rc_msvr = rcin(CD180_MSVR);
1216         return 0;
1217 }
1218
1219 /* Test the board. */
1220 int rc_test(nec, unit)
1221         int    nec;
1222         int             unit;
1223 {
1224         int     chan = 0;
1225         int     i = 0, rcnt;
1226         unsigned int    iack, chipid;
1227         unsigned short  divs;
1228         static  u_char  ctest[] = "\377\125\252\045\244\0\377";
1229 #define CTLEN   8
1230 #define ERR(s)  { \
1231                 printf("rc%d: ", unit); printf s ; printf("\n"); \
1232                 crit_exit(); return 1; }
1233
1234         struct rtest {
1235                 u_char  txbuf[CD180_NFIFO];     /* TX buffer  */
1236                 u_char  rxbuf[CD180_NFIFO];     /* RX buffer  */
1237                 int     rxptr;                  /* RX pointer */
1238                 int     txptr;                  /* TX pointer */
1239         } tchans[CD180_NCHAN];
1240
1241         crit_enter();
1242
1243         chipid = RC_FAKEID;
1244
1245         /* First, reset board to inital state */
1246         rc_hwreset(unit, nec, chipid);
1247
1248         divs = RC_BRD(19200);
1249
1250         /* Initialize channels */
1251         for (chan = 0; chan < CD180_NCHAN; chan++) {
1252
1253                 /* Select and reset channel */
1254                 rcout(CD180_CAR, chan);
1255                 CCRCMD(unit, chan, CCR_ResetChan);
1256                 WAITFORCCR(unit, chan);
1257
1258                 /* Set speed */
1259                 rcout(CD180_RBPRL, divs & 0xFF);
1260                 rcout(CD180_RBPRH, divs >> 8);
1261                 rcout(CD180_TBPRL, divs & 0xFF);
1262                 rcout(CD180_TBPRH, divs >> 8);
1263
1264                 /* set timeout value */
1265                 rcout(CD180_RTPR,  0);
1266
1267                 /* Establish local loopback */
1268                 rcout(CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1269                 rcout(CD180_COR2, COR2_LLM);
1270                 rcout(CD180_COR3, CD180_NFIFO);
1271                 CCRCMD(unit, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1272                 CCRCMD(unit, chan, CCR_RCVREN | CCR_XMTREN);
1273                 WAITFORCCR(unit, chan);
1274                 rcout(CD180_MSVR, MSVR_RTS);
1275
1276                 /* Fill TXBUF with test data */
1277                 for (i = 0; i < CD180_NFIFO; i++) {
1278                         tchans[chan].txbuf[i] = ctest[i];
1279                         tchans[chan].rxbuf[i] = 0;
1280                 }
1281                 tchans[chan].txptr = tchans[chan].rxptr = 0;
1282
1283                 /* Now, start transmit */
1284                 rcout(CD180_IER, IER_TxMpty|IER_RxData);
1285         }
1286         /* Pseudo-interrupt poll stuff */
1287         for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1288                 i = ~(rcin(RC_BSR));
1289                 if (i & RC_BSR_TOUT)
1290                         ERR(("BSR timeout bit set\n"))
1291                 else if (i & RC_BSR_TXINT) {
1292                         iack = rcin(RC_PILR_TX);
1293                         if (iack != (GIVR_IT_TDI | chipid))
1294                                 ERR(("Bad TX intr ack (%02x != %02x)\n",
1295                                         iack, GIVR_IT_TDI | chipid));
1296                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1297                         /* If no more data to transmit, disable TX intr */
1298                         if (tchans[chan].txptr >= CD180_NFIFO) {
1299                                 iack = rcin(CD180_IER);
1300                                 rcout(CD180_IER, iack & ~IER_TxMpty);
1301                         } else {
1302                                 for (iack = tchans[chan].txptr;
1303                                     iack < CD180_NFIFO; iack++)
1304                                         rcout(CD180_TDR,
1305                                             tchans[chan].txbuf[iack]);
1306                                 tchans[chan].txptr = iack;
1307                         }
1308                         rcout(CD180_EOIR, 0);
1309                 } else if (i & RC_BSR_RXINT) {
1310                         u_char ucnt;
1311
1312                         iack = rcin(RC_PILR_RX);
1313                         if (iack != (GIVR_IT_RGDI | chipid) &&
1314                             iack != (GIVR_IT_REI  | chipid))
1315                                 ERR(("Bad RX intr ack (%02x != %02x)\n",
1316                                         iack, GIVR_IT_RGDI | chipid))
1317                         chan = (rcin(CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1318                         ucnt = rcin(CD180_RDCR) & 0xF;
1319                         while (ucnt-- > 0) {
1320                                 iack = rcin(CD180_RCSR);
1321                                 if (iack & RCSR_Timeout)
1322                                         break;
1323                                 if (iack & 0xF)
1324                                         ERR(("Bad char chan %d (RCSR = %02X)\n",
1325                                             chan, iack))
1326                                 if (tchans[chan].rxptr > CD180_NFIFO)
1327                                         ERR(("Got extra chars chan %d\n",
1328                                             chan))
1329                                 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1330                                         rcin(CD180_RDR);
1331                         }
1332                         rcout(CD180_EOIR, 0);
1333                 }
1334                 rcout(RC_CTOUT, 0);
1335                 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1336                         if (tchans[chan].rxptr >= CD180_NFIFO)
1337                                 iack++;
1338                 if (iack == CD180_NCHAN)
1339                         break;
1340         }
1341         for (chan = 0; chan < CD180_NCHAN; chan++) {
1342                 /* Select and reset channel */
1343                 rcout(CD180_CAR, chan);
1344                 CCRCMD(unit, chan, CCR_ResetChan);
1345         }
1346
1347         if (!rcnt)
1348                 ERR(("looses characters during local loopback\n"))
1349         /* Now, check data */
1350         for (chan = 0; chan < CD180_NCHAN; chan++)
1351                 for (i = 0; i < CD180_NFIFO; i++)
1352                         if (ctest[i] != tchans[chan].rxbuf[i])
1353                                 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1354                                     chan, i, ctest[i], tchans[chan].rxbuf[i]))
1355         crit_exit();
1356         return 0;
1357 }
1358
1359 #ifdef RCDEBUG
1360 static void printrcflags(rc, comment)
1361 struct rc_chans  *rc;
1362 char             *comment;
1363 {
1364         u_short f = rc->rc_flags;
1365         int    nec = rc->rc_rcb->rcb_addr;
1366
1367         printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1368                 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1369                 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1370                 (f & RC_ACTOUT) ?"ACTOUT " :"",
1371                 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1372                 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1373                 (f & RC_DORXFER)?"DORXFER " :"",
1374                 (f & RC_DOXXFER)?"DOXXFER " :"",
1375                 (f & RC_MODCHG) ?"MODCHG "  :"",
1376                 (f & RC_OSUSP)  ?"OSUSP " :"",
1377                 (f & RC_OSBUSY) ?"OSBUSY " :"",
1378                 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1379                 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1380                 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1381
1382         rcout(CD180_CAR, rc->rc_chan);
1383
1384         printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1385                 rc->rc_rcb->rcb_unit, rc->rc_chan,
1386                 rcin(CD180_MSVR),
1387                 rcin(CD180_IER),
1388                 rcin(CD180_CCSR));
1389 }
1390 #endif /* RCDEBUG */
1391
1392 static void
1393 rc_dtrwakeup(chan)
1394         void    *chan;
1395 {
1396         struct rc_chans  *rc;
1397
1398         rc = (struct rc_chans *)chan;
1399         rc->rc_flags &= ~RC_DTR_OFF;
1400         wakeup(&rc->rc_dtrwait);
1401 }
1402
1403 static void
1404 rc_discard_output(rc)
1405         struct rc_chans  *rc;
1406 {
1407         cpu_disable_intr();
1408         if (rc->rc_flags & RC_DOXXFER) {
1409                 rc_scheduled_event -= LOTS_OF_EVENTS;
1410                 rc->rc_flags &= ~RC_DOXXFER;
1411         }
1412         rc->rc_optr = rc->rc_obufend;
1413         rc->rc_tp->t_state &= ~TS_BUSY;
1414         cpu_enable_intr();
1415         ttwwakeup(rc->rc_tp);
1416 }
1417
1418 static void
1419 rc_wakeup(chan)
1420         void    *chan;
1421 {
1422         if (rc_scheduled_event != 0) {
1423                 crit_enter();
1424                 rcpoll(NULL);
1425                 crit_exit();
1426         }
1427         callout_reset(&rc_wakeup_ch, 1, rc_wakeup, NULL);
1428 }
1429
1430 static void
1431 disc_optim(tp, t, rc)
1432         struct tty      *tp;
1433         struct termios  *t;
1434         struct rc_chans *rc;
1435 {
1436
1437         if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON))
1438             && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK))
1439             && (!(t->c_iflag & PARMRK)
1440                 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
1441             && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN))
1442             && linesw[tp->t_line].l_rint == ttyinput)
1443                 tp->t_state |= TS_CAN_BYPASS_L_RINT;
1444         else
1445                 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
1446         rc->rc_hotchar = linesw[tp->t_line].l_hotchar;
1447 }
1448
1449 static void
1450 rc_wait0(nec, unit, chan, line)
1451         int     nec, unit, chan, line;
1452 {
1453         int rcnt;
1454
1455         for (rcnt = 50; rcnt && rcin(CD180_CCR); rcnt--)
1456                 DELAY(30);
1457         if (rcnt == 0)
1458                 printf("rc%d/%d: channel command timeout, rc.c line: %d\n",
1459                       unit, chan, line);
1460 }