2 * Copyright (c) 1989, 1990 William F. Jolitz.
3 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 2007 The FreeBSD Foundation
5 * Copyright (c) 2008 The DragonFly Project.
6 * Copyright (c) 2008 Jordan Gordeev.
9 * Portions of this software were developed by A. Joseph Koshy under
10 * sponsorship from the FreeBSD Foundation and Google, Inc.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 #include "opt_atpic.h"
40 #include "opt_compat.h"
42 #include <machine/asmacros.h>
43 #include <machine/psl.h>
44 #include <machine/trap.h>
45 #include <machine/segments.h>
51 .globl lwkt_switch_return
53 /*****************************************************************************/
55 /*****************************************************************************/
57 * Trap and fault vector routines.
59 * All traps are 'interrupt gates', SDT_SYSIGT. An interrupt gate pushes
60 * state on the stack but also disables interrupts. This is important for
61 * us for the use of the swapgs instruction. We cannot be interrupted
62 * until the GS.base value is correct. For most traps, we automatically
63 * then enable interrupts if the interrupted context had them enabled.
64 * This is equivalent to the i386 port's use of SDT_SYS386TGT.
66 * The cpu will push a certain amount of state onto the kernel stack for
67 * the current process. See x86_64/include/frame.h.
68 * This includes the current RFLAGS (status register, which includes
69 * the interrupt disable state prior to the trap), the code segment register,
70 * and the return instruction pointer are pushed by the cpu. The cpu
71 * will also push an 'error' code for certain traps. We push a dummy
72 * error code for those traps where the cpu doesn't in order to maintain
73 * a consistent frame. We also push a contrived 'trap number'.
75 * The cpu does not push the general registers, we must do that, and we
76 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and
77 * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we
78 * must load them with appropriate values for supervisor mode operation.
85 * Interrupts are enabled for all traps, otherwise horrible livelocks
86 * can occur with the smp_invltlb and cpusync ode.
89 #define TRAP_NOEN(a) \
91 movq $0,TF_XFLAGS(%rsp) ; \
92 movq $(a),TF_TRAPNO(%rsp) ; \
93 movq $0,TF_ADDR(%rsp) ; \
94 movq $0,TF_ERR(%rsp) ; \
98 /* Regular traps; The cpu does not supply tf_err for these. */
101 movq $0,TF_XFLAGS(%rsp) ; \
102 movq $(a),TF_TRAPNO(%rsp) ; \
103 movq $0,TF_ADDR(%rsp) ; \
104 movq $0,TF_ERR(%rsp) ; \
131 /* This group of traps have tf_err already pushed by the cpu */
132 #define TRAP_ERR(a) \
134 movq $(a),TF_TRAPNO(%rsp) ; \
135 movq $0,TF_ADDR(%rsp) ; \
136 movq $0,TF_XFLAGS(%rsp) ; \
148 * alltraps entry point. Use swapgs if this is the first time in the
149 * kernel from userland. Reenable interrupts if they were enabled
150 * before the trap. This approximates SDT_SYS386TGT on the i386 port.
155 .type alltraps,@function
157 /* Fixup %gs if coming from userland */
158 testb $SEL_RPL_MASK,TF_CS(%rsp)
162 testq $PSL_I,TF_RFLAGS(%rsp)
166 movq %rdi,TF_RDI(%rsp)
167 alltraps_pushregs_no_rdi:
168 movq %rsi,TF_RSI(%rsp)
169 movq %rdx,TF_RDX(%rsp)
170 movq %rcx,TF_RCX(%rsp)
173 movq %rax,TF_RAX(%rsp)
174 movq %rbx,TF_RBX(%rsp)
175 movq %rbp,TF_RBP(%rsp)
176 movq %r10,TF_R10(%rsp)
177 movq %r11,TF_R11(%rsp)
178 movq %r12,TF_R12(%rsp)
179 movq %r13,TF_R13(%rsp)
180 movq %r14,TF_R14(%rsp)
181 movq %r15,TF_R15(%rsp)
182 FAKE_MCOUNT(TF_RIP(%rsp))
184 .type calltrap,@function
189 jmp doreti /* Handle any pending ASTs */
192 * alltraps_noen entry point. Unlike alltraps above, we want to
193 * leave the interrupts disabled. This corresponds to
194 * SDT_SYS386IGT on the i386 port.
198 .type alltraps_noen,@function
200 /* Fixup %gs if coming from userland */
201 testb $SEL_RPL_MASK,TF_CS(%rsp)
204 jmp alltraps_pushregs
208 movq $T_DOUBLEFLT,TF_TRAPNO(%rsp)
209 movq $0,TF_ADDR(%rsp)
211 movq $0,TF_XFLAGS(%rsp)
212 movq %rdi,TF_RDI(%rsp)
213 movq %rsi,TF_RSI(%rsp)
214 movq %rdx,TF_RDX(%rsp)
215 movq %rcx,TF_RCX(%rsp)
218 movq %rax,TF_RAX(%rsp)
219 movq %rbx,TF_RBX(%rsp)
220 movq %rbp,TF_RBP(%rsp)
221 movq %r10,TF_R10(%rsp)
222 movq %r11,TF_R11(%rsp)
223 movq %r12,TF_R12(%rsp)
224 movq %r13,TF_R13(%rsp)
225 movq %r14,TF_R14(%rsp)
226 movq %r15,TF_R15(%rsp)
227 testb $SEL_RPL_MASK,TF_CS(%rsp)
231 call dblfault_handler
237 movq $T_PAGEFLT,TF_TRAPNO(%rsp)
238 /* Fixup %gs if coming from userland */
239 testb $SEL_RPL_MASK,TF_CS(%rsp)
243 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
244 movq %cr2,%rdi /* preserve %cr2 before .. */
245 movq %rdi,TF_ADDR(%rsp) /* enabling interrupts. */
246 movq $0,TF_XFLAGS(%rsp)
247 testq $PSL_I,TF_RFLAGS(%rsp)
248 jz alltraps_pushregs_no_rdi
250 jmp alltraps_pushregs_no_rdi
253 * We have to special-case this one. If we get a trap in doreti() at
254 * the iretq stage, we'll reenter with the wrong gs state. We'll have
255 * to do a special the swapgs in this case even coming from the kernel.
256 * XXX linux has a trap handler for their equivalent of load_gs().
260 movq $T_PROTFLT,TF_TRAPNO(%rsp)
261 movq $0,TF_ADDR(%rsp)
262 movq $0,TF_XFLAGS(%rsp)
263 movq %rdi,TF_RDI(%rsp) /* free up a GP register */
266 * Fixup %gs if coming from userland. Handle the special case where
267 * %fs faults in doreti at the iretq instruction itself.
269 leaq doreti_iret(%rip),%rdi
270 cmpq %rdi,TF_RIP(%rsp) /* special iretq fault case */
272 testb $SEL_RPL_MASK,TF_CS(%rsp) /* check if from userland */
277 testq $PSL_I,TF_RFLAGS(%rsp)
278 jz alltraps_pushregs_no_rdi
280 jmp alltraps_pushregs_no_rdi
283 * Fast syscall entry point. We enter here with just our new %cs/%ss set,
284 * and the new privilige level. We are still running on the old user stack
285 * pointer. We have to juggle a few things around to find our stack etc.
286 * swapgs gives us access to our PCPU space only.
290 movq %rsp,PCPU(scratch_rsp)
291 movq PCPU(common_tss) + TSS_RSP0, %rsp
292 /* Now emulate a trapframe. Make the 8 byte alignment odd for call. */
294 /* defer TF_RSP till we have a spare register */
295 movq %r11,TF_RFLAGS(%rsp)
296 movq %rcx,TF_RIP(%rsp) /* %rcx original value is in %r10 */
297 movq PCPU(scratch_rsp),%r11 /* %r11 already saved */
298 movq %r11,TF_RSP(%rsp) /* user stack pointer */
300 movq $KUDSEL,TF_SS(%rsp)
301 movq $KUCSEL,TF_CS(%rsp)
303 movq $T_FAST_SYSCALL,TF_TRAPNO(%rsp) /* for the vkernel */
304 movq $0,TF_XFLAGS(%rsp) /* note: used in signal frame */
305 movq %rdi,TF_RDI(%rsp) /* arg 1 */
306 movq %rsi,TF_RSI(%rsp) /* arg 2 */
307 movq %rdx,TF_RDX(%rsp) /* arg 3 */
308 movq %r10,TF_RCX(%rsp) /* arg 4 */
309 movq %r8,TF_R8(%rsp) /* arg 5 */
310 movq %r9,TF_R9(%rsp) /* arg 6 */
311 movq %rax,TF_RAX(%rsp) /* syscall number */
312 movq %rbx,TF_RBX(%rsp) /* C preserved */
313 movq %rbp,TF_RBP(%rsp) /* C preserved */
314 movq %r12,TF_R12(%rsp) /* C preserved */
315 movq %r13,TF_R13(%rsp) /* C preserved */
316 movq %r14,TF_R14(%rsp) /* C preserved */
317 movq %r15,TF_R15(%rsp) /* C preserved */
318 FAKE_MCOUNT(TF_RIP(%rsp))
325 * Here for CYA insurance, in case a "syscall" instruction gets
326 * issued from 32 bit compatability mode. MSR_CSTAR has to point
327 * to *something* if EFER_SCE is enabled.
329 IDTVEC(fast_syscall32)
333 * NMI handling is special.
335 * First, NMIs do not respect the state of the processor's RFLAGS.IF
336 * bit and the NMI handler may be invoked at any time, including when
337 * the processor is in a critical section with RFLAGS.IF == 0. In
338 * particular, this means that the processor's GS.base values could be
339 * inconsistent on entry to the handler, and so we need to read
340 * MSR_GSBASE to determine if a 'swapgs' is needed. We use '%ebx', a
341 * C-preserved register, to remember whether to swap GS back on the
344 * Second, the processor treats NMIs specially, blocking further NMIs
345 * until an 'iretq' instruction is executed. We therefore need to
346 * execute the NMI handler with interrupts disabled to prevent a
347 * nested interrupt from executing an 'iretq' instruction and
348 * inadvertently taking the processor out of NMI mode.
350 * Third, the NMI handler runs on its own stack (tss_ist1), shared
351 * with the double fault handler.
356 movq $(T_NMI),TF_TRAPNO(%rsp)
357 movq $0,TF_ADDR(%rsp)
359 movq $0,TF_XFLAGS(%rsp)
360 movq %rdi,TF_RDI(%rsp)
361 movq %rsi,TF_RSI(%rsp)
362 movq %rdx,TF_RDX(%rsp)
363 movq %rcx,TF_RCX(%rsp)
366 movq %rax,TF_RAX(%rsp)
367 movq %rbx,TF_RBX(%rsp)
368 movq %rbp,TF_RBP(%rsp)
369 movq %r10,TF_R10(%rsp)
370 movq %r11,TF_R11(%rsp)
371 movq %r12,TF_R12(%rsp)
372 movq %r13,TF_R13(%rsp)
373 movq %r14,TF_R14(%rsp)
374 movq %r15,TF_R15(%rsp)
376 testb $SEL_RPL_MASK,TF_CS(%rsp)
377 jnz nmi_needswapgs /* we came from userland */
378 movl $MSR_GSBASE,%ecx
380 cmpl $VM_MAX_USER_ADDRESS >> 32,%edx
381 jae nmi_calltrap /* GS.base holds a kernel VA */
385 /* Note: this label is also used by ddb and gdb: */
387 FAKE_MCOUNT(TF_RIP(%rsp))
395 movq TF_RDI(%rsp),%rdi
396 movq TF_RSI(%rsp),%rsi
397 movq TF_RDX(%rsp),%rdx
398 movq TF_RCX(%rsp),%rcx
401 movq TF_RAX(%rsp),%rax
402 movq TF_RBX(%rsp),%rbx
403 movq TF_RBP(%rsp),%rbp
404 movq TF_R10(%rsp),%r10
405 movq TF_R11(%rsp),%r11
406 movq TF_R12(%rsp),%r12
407 movq TF_R13(%rsp),%r13
408 movq TF_R14(%rsp),%r14
409 movq TF_R15(%rsp),%r15
414 * This function is what cpu_heavy_restore jumps to after a new process
415 * is created. The LWKT subsystem switches while holding a critical
416 * section and we maintain that abstraction here (e.g. because
417 * cpu_heavy_restore needs it due to PCB_*() manipulation), then get out of
418 * it before calling the initial function (typically fork_return()) and/or
419 * returning to user mode.
421 * The MP lock is not held at any point but the critcount is bumped
422 * on entry to prevent interruption of the trampoline at a bad point.
424 * This is effectively what td->td_switch() returns to. It 'returns' the
425 * old thread in %rax and since this is not returning to a td->td_switch()
426 * call from lwkt_switch() we must handle the cleanup for the old thread
427 * by calling lwkt_switch_return().
429 * fork_trampoline(%rax:otd, %rbx:func, %r12:arg)
431 ENTRY(fork_trampoline)
433 call lwkt_switch_return
434 movq PCPU(curthread),%rax
435 decl TD_CRITCOUNT(%rax)
438 * cpu_set_fork_handler intercepts this function call to
439 * have this call a non-return function to stay in kernel mode.
441 * initproc has its own fork handler, start_init(), which DOES
444 * %rbx - chaining function (typically fork_return)
445 * %r12 -> %rdi (argument)
446 * frame-> %rsi (trap frame)
448 * void (func:rbx)(arg:rdi, trapframe:rsi)
450 movq %rsp, %rsi /* pass trapframe by reference */
451 movq %r12, %rdi /* arg1 */
452 call *%rbx /* function */
454 /* cut from syscall */
460 * Return via doreti to handle ASTs.
462 * trapframe is at the top of the stack.
468 * To efficiently implement classification of trap and interrupt handlers
469 * for profiling, there must be only trap handlers between the labels btrap
470 * and bintr, and only interrupt handlers between the labels bintr and
471 * eintr. This is implemented (partly) by including files that contain
472 * some of the handlers. Before including the files, set up a normal asm
473 * environment so that the included files doen't need to know that they are
483 #include <x86_64/ia32/ia32_exception.S>
493 #include <x86_64/x86_64/apic_vector.S>
502 #include <x86_64/isa/atpic_vector.S>