2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <machine/globaldata.h>
33 #include <machine/smp.h>
34 #include <machine/md_var.h>
35 #include <machine_base/apic/mpapic.h>
36 #include <machine/segments.h>
37 #include <sys/thread2.h>
39 #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
41 /* EISA Edge/Level trigger control registers */
42 #define ELCR0 0x4d0 /* eisa irq 0-7 */
43 #define ELCR1 0x4d1 /* eisa irq 8-15 */
45 static void lapic_timer_calibrate(void);
46 static void lapic_timer_set_divisor(int);
47 static void lapic_timer_intr_reload(sysclock_t);
48 static void lapic_timer_fixup_handler(void *);
50 void lapic_timer_fixup(void);
51 void lapic_timer_process(void);
52 void lapic_timer_process_frame(struct intrframe *);
53 void lapic_timer_intr_test(void);
54 void lapic_timer_oneshot_intr_enable(void);
57 int lapic_timer_enable;
59 TUNABLE_INT("hw.lapic_timer_test", &lapic_timer_test);
60 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
63 * pointers to pmapped apic hardware.
66 volatile ioapic_t **ioapic;
68 static sysclock_t lapic_timer_freq;
69 static int lapic_timer_divisor_idx = -1;
70 static const uint32_t lapic_timer_divisors[] = {
71 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
72 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
74 #define APIC_TIMER_NDIVISORS \
75 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
79 * Enable APIC, configure interrupts.
82 apic_initialize(boolean_t bsp)
88 * setup LVT1 as ExtINT on the BSP. This is theoretically an
89 * aggregate interrupt input from the 8259. The INTA cycle
90 * will be routed to the external controller (the 8259) which
91 * is expected to supply the vector.
93 * Must be setup edge triggered, active high.
95 * Disable LVT1 on the APs. It doesn't matter what delivery
96 * mode we use because we leave it masked.
98 temp = lapic.lvt_lint0;
99 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
100 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
101 if (mycpu->gd_cpuid == 0)
102 temp |= APIC_LVT_DM_EXTINT;
104 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
105 lapic.lvt_lint0 = temp;
108 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
110 temp = lapic.lvt_lint1;
111 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
112 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
113 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
114 lapic.lvt_lint1 = temp;
117 * Mask the apic error interrupt, apic performance counter
120 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
121 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
123 /* Set apic timer vector and mask the apic timer interrupt. */
124 timer = lapic.lvt_timer;
125 timer &= ~APIC_LVTT_VECTOR;
126 timer |= XTIMER_OFFSET;
127 timer |= APIC_LVTT_MASKED;
128 lapic.lvt_timer = timer;
131 * Set the Task Priority Register as needed. At the moment allow
132 * interrupts on all cpus (the APs will remain CLId until they are
133 * ready to deal). We could disable all but IPIs by setting
134 * temp |= TPR_IPI_ONLY for cpu != 0.
137 temp &= ~APIC_TPR_PRIO; /* clear priority field */
140 * If we are NOT running the IO APICs, the LAPIC will only be used
141 * for IPIs. Set the TPR to prevent any unintentional interrupts.
143 temp |= TPR_IPI_ONLY;
149 * enable the local APIC
152 temp |= APIC_SVR_ENABLE; /* enable the APIC */
153 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
156 * Set the spurious interrupt vector. The low 4 bits of the vector
159 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
160 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
161 temp &= ~APIC_SVR_VECTOR;
162 temp |= XSPURIOUSINT_OFFSET;
167 * Pump out a few EOIs to clean out interrupts that got through
168 * before we were able to set the TPR.
175 lapic_timer_calibrate();
176 if (lapic_timer_enable)
177 cputimer_intr_reload = lapic_timer_intr_reload;
179 lapic_timer_set_divisor(lapic_timer_divisor_idx);
183 apic_dump("apic_initialize()");
188 lapic_timer_set_divisor(int divisor_idx)
190 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
191 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
195 lapic_timer_oneshot(u_int count)
199 value = lapic.lvt_timer;
200 value &= ~APIC_LVTT_PERIODIC;
201 lapic.lvt_timer = value;
202 lapic.icr_timer = count;
206 lapic_timer_oneshot_quick(u_int count)
208 lapic.icr_timer = count;
212 lapic_timer_calibrate(void)
216 /* Try to calibrate the local APIC timer. */
217 for (lapic_timer_divisor_idx = 0;
218 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
219 lapic_timer_divisor_idx++) {
220 lapic_timer_set_divisor(lapic_timer_divisor_idx);
221 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
223 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
224 if (value != APIC_TIMER_MAX_COUNT)
227 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
228 panic("lapic: no proper timer divisor?!\n");
229 lapic_timer_freq = value / 2;
231 kprintf("lapic: divisor index %d, frequency %u Hz\n",
232 lapic_timer_divisor_idx, lapic_timer_freq);
236 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
240 gd->gd_timer_running = 0;
242 count = sys_cputimer->count();
243 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
244 systimer_intr(&count, 0, frame);
248 lapic_timer_process(void)
250 struct globaldata *gd = mycpu;
252 if (__predict_false(lapic_timer_test)) {
253 gd->gd_timer_running = 0;
254 kprintf("%d proc\n", gd->gd_cpuid);
256 lapic_timer_process_oncpu(gd, NULL);
261 lapic_timer_process_frame(struct intrframe *frame)
263 struct globaldata *gd = mycpu;
265 if (__predict_false(lapic_timer_test)) {
266 gd->gd_timer_running = 0;
267 kprintf("%d proc frame\n", gd->gd_cpuid);
269 lapic_timer_process_oncpu(gd, frame);
274 lapic_timer_intr_test(void)
276 struct globaldata *gd = mycpu;
278 if (!gd->gd_timer_running) {
279 gd->gd_timer_running = 1;
280 KKASSERT(lapic_timer_freq != 0);
281 lapic_timer_oneshot_quick(lapic_timer_freq);
286 lapic_timer_intr_reload(sysclock_t reload)
288 struct globaldata *gd = mycpu;
290 reload = (int64_t)reload * lapic_timer_freq / sys_cputimer->freq;
294 if (gd->gd_timer_running) {
295 if (reload < lapic.ccr_timer)
296 lapic_timer_oneshot_quick(reload);
298 gd->gd_timer_running = 1;
299 lapic_timer_oneshot_quick(reload);
304 lapic_timer_oneshot_intr_enable(void)
308 timer = lapic.lvt_timer;
309 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
310 lapic.lvt_timer = timer;
312 lapic_timer_fixup_handler(NULL);
316 lapic_timer_fixup_handler(void *dummy __unused)
318 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
320 * Detect the presence of C1E capability mostly on latest
321 * dual-cores (or future) k8 family. This feature renders
322 * the local APIC timer dead, so we disable it by reading
323 * the Interrupt Pending Message register and clearing both
324 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
327 * "BIOS and Kernel Developer's Guide for AMD NPT
328 * Family 0Fh Processors"
329 * #32559 revision 3.00
331 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
332 (cpu_id & 0x0fff0000) >= 0x00040000) {
335 msr = rdmsr(0xc0010055);
336 if (msr & 0x18000000) {
337 struct globaldata *gd = mycpu;
339 kprintf("cpu%d: AMD C1E detected\n",
341 wrmsr(0xc0010055, msr & ~0x18000000ULL);
344 * We are kinda stalled;
347 gd->gd_timer_running = 1;
348 lapic_timer_oneshot_quick(2);
355 * This function is called only by ACPI-CA code currently:
356 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
357 * module controls PM. So once ACPI-CA is attached, we try
358 * to apply the fixup to prevent LAPIC timer from hanging.
361 lapic_timer_fixup(void)
363 if (lapic_timer_test || lapic_timer_enable) {
364 lwkt_send_ipiq_mask(smp_active_mask,
365 lapic_timer_fixup_handler, NULL);
371 * dump contents of local APIC registers
376 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
377 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
378 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
388 #define IOAPIC_ISA_INTS 16
389 #define REDIRCNT_IOAPIC(A) \
390 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
392 static int trigger (int apic, int pin, u_int32_t * flags);
393 static void polarity (int apic, int pin, u_int32_t * flags, int level);
395 #define DEFAULT_FLAGS \
401 #define DEFAULT_ISA_FLAGS \
410 io_apic_set_id(int apic, int id)
414 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
415 if (((ux & APIC_ID_MASK) >> 24) != id) {
416 kprintf("Changing APIC ID for IO APIC #%d"
417 " from %d to %d on chip\n",
418 apic, ((ux & APIC_ID_MASK) >> 24), id);
419 ux &= ~APIC_ID_MASK; /* clear the ID field */
421 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
422 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
423 if (((ux & APIC_ID_MASK) >> 24) != id)
424 panic("can't control IO APIC #%d ID, reg: 0x%08x",
431 io_apic_get_id(int apic)
433 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
442 extern int apic_pin_trigger; /* 'opaque' */
445 io_apic_setup_intpin(int apic, int pin)
447 int bus, bustype, irq;
448 u_char select; /* the select register is 8 bits */
449 u_int32_t flags; /* the window register is 32 bits */
450 u_int32_t target; /* the window register is 32 bits */
451 u_int32_t vector; /* the window register is 32 bits */
454 select = pin * 2 + IOAPIC_REDTBL0; /* register */
457 * Always clear an IO APIC pin before [re]programming it. This is
458 * particularly important if the pin is set up for a level interrupt
459 * as the IOART_REM_IRR bit might be set. When we reprogram the
460 * vector any EOI from pending ints on this pin could be lost and
461 * IRR might never get reset.
463 * To fix this problem, clear the vector and make sure it is
464 * programmed as an edge interrupt. This should theoretically
465 * clear IRR so we can later, safely program it as a level
470 flags = io_apic_read(apic, select) & IOART_RESV;
471 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
472 flags |= IOART_DESTPHY | IOART_DELFIXED;
474 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
475 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
479 io_apic_write(apic, select, flags | vector);
480 io_apic_write(apic, select + 1, target);
485 * We only deal with vectored interrupts here. ? documentation is
486 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
489 * This test also catches unconfigured pins.
491 if (apic_int_type(apic, pin) != 0)
495 * Leave the pin unprogrammed if it does not correspond to
498 irq = apic_irq(apic, pin);
502 /* determine the bus type for this pin */
503 bus = apic_src_bus_id(apic, pin);
506 bustype = apic_bus_type(bus);
508 if ((bustype == ISA) &&
509 (pin < IOAPIC_ISA_INTS) &&
511 (apic_polarity(apic, pin) == 0x1) &&
512 (apic_trigger(apic, pin) == 0x3)) {
514 * A broken BIOS might describe some ISA
515 * interrupts as active-high level-triggered.
516 * Use default ISA flags for those interrupts.
518 flags = DEFAULT_ISA_FLAGS;
521 * Program polarity and trigger mode according to
524 flags = DEFAULT_FLAGS;
525 level = trigger(apic, pin, &flags);
527 apic_pin_trigger |= (1 << irq);
528 polarity(apic, pin, &flags, level);
532 kprintf("IOAPIC #%d intpin %d -> irq %d\n",
537 * Program the appropriate registers. This routing may be
538 * overridden when an interrupt handler for a device is
539 * actually added (see register_int(), which calls through
540 * the MACHINTR ABI to set up an interrupt handler/vector).
542 * The order in which we must program the two registers for
543 * safety is unclear! XXX
547 vector = IDT_OFFSET + irq; /* IDT vec */
548 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
549 target |= IOART_HI_DEST_BROADCAST;
550 flags |= io_apic_read(apic, select) & IOART_RESV;
551 io_apic_write(apic, select, flags | vector);
552 io_apic_write(apic, select + 1, target);
558 io_apic_setup(int apic)
564 apic_pin_trigger = 0; /* default to edge-triggered */
566 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
567 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
569 for (pin = 0; pin < maxpin; ++pin) {
570 io_apic_setup_intpin(apic, pin);
573 if (apic_int_type(apic, pin) >= 0) {
574 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
575 " cannot program!\n", apic, pin);
580 /* return GOOD status */
583 #undef DEFAULT_ISA_FLAGS
587 #define DEFAULT_EXTINT_FLAGS \
596 * Setup the source of External INTerrupts.
599 ext_int_setup(int apic, int intr)
601 u_char select; /* the select register is 8 bits */
602 u_int32_t flags; /* the window register is 32 bits */
603 u_int32_t target; /* the window register is 32 bits */
604 u_int32_t vector; /* the window register is 32 bits */
606 if (apic_int_type(apic, intr) != 3)
609 target = IOART_HI_DEST_BROADCAST;
610 select = IOAPIC_REDTBL0 + (2 * intr);
611 vector = IDT_OFFSET + intr;
612 flags = DEFAULT_EXTINT_FLAGS;
614 io_apic_write(apic, select, flags | vector);
615 io_apic_write(apic, select + 1, target);
619 #undef DEFAULT_EXTINT_FLAGS
623 * Set the trigger level for an IO APIC pin.
626 trigger(int apic, int pin, u_int32_t * flags)
631 static int intcontrol = -1;
633 switch (apic_trigger(apic, pin)) {
639 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
643 *flags |= IOART_TRGRLVL;
651 if ((id = apic_src_bus_id(apic, pin)) == -1)
654 switch (apic_bus_type(id)) {
656 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
660 eirq = apic_src_bus_irq(apic, pin);
662 if (eirq < 0 || eirq > 15) {
663 kprintf("EISA IRQ %d?!?!\n", eirq);
667 if (intcontrol == -1) {
668 intcontrol = inb(ELCR1) << 8;
669 intcontrol |= inb(ELCR0);
670 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
673 /* Use ELCR settings to determine level or edge mode */
674 level = (intcontrol >> eirq) & 1;
677 * Note that on older Neptune chipset based systems, any
678 * pci interrupts often show up here and in the ELCR as well
679 * as level sensitive interrupts attributed to the EISA bus.
683 *flags |= IOART_TRGRLVL;
685 *flags &= ~IOART_TRGRLVL;
690 *flags |= IOART_TRGRLVL;
699 panic("bad APIC IO INT flags");
704 * Set the polarity value for an IO APIC pin.
707 polarity(int apic, int pin, u_int32_t * flags, int level)
711 switch (apic_polarity(apic, pin)) {
717 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
721 *flags |= IOART_INTALO;
729 if ((id = apic_src_bus_id(apic, pin)) == -1)
732 switch (apic_bus_type(id)) {
734 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
738 /* polarity converter always gives active high */
739 *flags &= ~IOART_INTALO;
743 *flags |= IOART_INTALO;
752 panic("bad APIC IO INT flags");
757 * Print contents of apic_imen.
759 extern u_int apic_imen; /* keep apic_imen 'opaque' */
765 kprintf("SMP: enabled INTs: ");
766 for (x = 0; x < 24; ++x)
767 if ((apic_imen & (1 << x)) == 0)
769 kprintf("apic_imen: 0x%08x\n", apic_imen);
774 * Inter Processor Interrupt functions.
780 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
782 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
783 * vector is any valid SYSTEM INT vector
784 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
786 * A backlog of requests can create a deadlock between cpus. To avoid this
787 * we have to be able to accept IPIs at the same time we are trying to send
788 * them. The critical section prevents us from attempting to send additional
789 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
790 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
791 * to occur but fortunately it does not happen too often.
794 apic_ipi(int dest_type, int vector, int delivery_mode)
799 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
800 unsigned int eflags = read_eflags();
802 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
805 write_eflags(eflags);
808 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
809 delivery_mode | vector;
810 lapic.icr_lo = icr_lo;
816 single_apic_ipi(int cpu, int vector, int delivery_mode)
822 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
823 unsigned int eflags = read_eflags();
825 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
828 write_eflags(eflags);
830 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
831 icr_hi |= (CPU_TO_ID(cpu) << 24);
832 lapic.icr_hi = icr_hi;
835 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
836 | APIC_DEST_DESTFLD | delivery_mode | vector;
839 lapic.icr_lo = icr_lo;
846 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
848 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
849 * to the target, and the scheduler does not 'poll' for IPI messages.
852 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
858 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
862 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
863 icr_hi |= (CPU_TO_ID(cpu) << 24);
864 lapic.icr_hi = icr_hi;
867 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
868 | APIC_DEST_DESTFLD | delivery_mode | vector;
871 lapic.icr_lo = icr_lo;
879 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
881 * target is a bitmask of destination cpus. Vector is any
882 * valid system INT vector. Delivery mode may be either
883 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
886 selected_apic_ipi(u_int target, int vector, int delivery_mode)
890 int n = bsfl(target);
892 single_apic_ipi(n, vector, delivery_mode);
898 * Timer code, in development...
899 * - suggested by rgrimes@gndrsh.aac.dev.com
903 * Load a 'downcount time' in uSeconds.
906 set_apic_timer(int us)
911 * When we reach here, lapic timer's frequency
912 * must have been calculated as well as the
913 * divisor (lapic.dcr_timer is setup during the
914 * divisor calculation).
916 KKASSERT(lapic_timer_freq != 0 &&
917 lapic_timer_divisor_idx >= 0);
919 count = ((us * (int64_t)lapic_timer_freq) + 999999) / 1000000;
920 lapic_timer_oneshot(count);
925 * Read remaining time in timer.
928 read_apic_timer(void)
931 /** XXX FIXME: we need to return the actual remaining time,
932 * for now we just return the remaining count.
935 return lapic.ccr_timer;
941 * Spin-style delay, set delay time in uS, spin till it drains.
946 set_apic_timer(count);
947 while (read_apic_timer())