sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_ringbuffer.h"
  34 #include <linux/workqueue.h>
  35
  36 extern struct drm_i915_private *i915_mch_dev;
  37
  38 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  39
  40 #define BEGIN_LP_RING(n) \
  41         intel_ring_begin(LP_RING(dev_priv), (n))
  42
  43 #define OUT_RING(x) \
  44         intel_ring_emit(LP_RING(dev_priv), x)
  45
  46 #define ADVANCE_LP_RING() \
  47         __intel_ring_advance(LP_RING(dev_priv))
  48
  49 /**
  50  * Lock test for when it's just for synchronization of ring access.
  51  *
  52  * In that case, we don't need to do it when GEM is initialized as nobody else
  53  * has access to the ring.
  54  */
  55 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  56         if (LP_RING(dev->dev_private)->buffer->obj == NULL)                     \
  57                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  58 } while (0)
  59
  60 static inline u32
  61 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  62 {
  63         if (I915_NEED_GFX_HWS(dev_priv->dev))
  64                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  65         else
  66                 return intel_read_status_page(LP_RING(dev_priv), reg);
  67 }
  68
  69 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  70 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  71 #define I915_BREADCRUMB_INDEX           0x21
  72
  73 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  74 {
  75         /* XXX: We don't care about dri1 */
  76         return;
  77 }
  78
  79 static void i915_write_hws_pga(struct drm_device *dev)
  80 {
  81         struct drm_i915_private *dev_priv = dev->dev_private;
  82         u32 addr;
  83
  84         addr = dev_priv->status_page_dmah->busaddr;
  85         if (INTEL_INFO(dev)->gen >= 4)
  86                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  87         I915_WRITE(HWS_PGA, addr);
  88 }
  89
  90 /**
  91  * Frees the hardware status page, whether it's a physical address or a virtual
  92  * address set up by the X Server.
  93  */
  94 static void i915_free_hws(struct drm_device *dev)
  95 {
  96         struct drm_i915_private *dev_priv = dev->dev_private;
  97         struct intel_engine_cs *ring = LP_RING(dev_priv);
  98
  99         if (dev_priv->status_page_dmah) {
 100                 drm_pci_free(dev, dev_priv->status_page_dmah);
 101                 dev_priv->status_page_dmah = NULL;
 102         }
 103
 104         if (ring->status_page.gfx_addr) {
 105                 ring->status_page.gfx_addr = 0;
 106 #if 0   /* We don't care about dri1 */
 107                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 108 #endif
 109         }
 110
 111         /* Need to rewrite hardware status page */
 112         I915_WRITE(HWS_PGA, 0x1ffff000);
 113 }
 114
 115 void i915_kernel_lost_context(struct drm_device *dev)
 116 {
 117         struct drm_i915_private *dev_priv = dev->dev_private;
 118         struct drm_i915_private *master_priv = dev_priv;
 119         struct intel_engine_cs *ring = LP_RING(dev_priv);
 120         struct intel_ringbuffer *ringbuf = ring->buffer;
 121
 122         /*
 123          * We should never lose context on the ring with modesetting
 124          * as we don't expose it to userspace
 125          */
 126         if (drm_core_check_feature(dev, DRIVER_MODESET))
 127                 return;
 128
 129         ringbuf->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 130         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 131         ringbuf->space = ringbuf->head - (ringbuf->tail + I915_RING_FREE_SPACE);
 132         if (ringbuf->space < 0)
 133                 ringbuf->space += ringbuf->size;
 134
 135 #if 0
 136         if (!dev->primary->master)
 137                 return;
 138
 139         master_priv = dev->primary->master->driver_priv;
 140 #endif
 141         if (ringbuf->head == ringbuf->tail && master_priv->sarea_priv)
 142                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 143 }
 144
 145 static int i915_dma_cleanup(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = dev->dev_private;
 148         int i;
 149
 150         /* Make sure interrupts are disabled here because the uninstall ioctl
 151          * may not have been called from userspace and after dev_private
 152          * is freed, it's too late.
 153          */
 154         if (dev->irq_enabled)
 155                 drm_irq_uninstall(dev);
 156
 157         mutex_lock(&dev->struct_mutex);
 158         for (i = 0; i < I915_NUM_RINGS; i++)
 159                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 160         mutex_unlock(&dev->struct_mutex);
 161
 162         /* Clear the HWS virtual address at teardown */
 163         if (I915_NEED_GFX_HWS(dev))
 164                 i915_free_hws(dev);
 165
 166         return 0;
 167 }
 168
 169 static int i915_initialize(struct drm_device *dev, drm_i915_init_t *init)
 170 {
 171         struct drm_i915_private *dev_priv = dev->dev_private;
 172         int ret;
 173
 174         dev_priv->sarea = drm_getsarea(dev);
 175         if (!dev_priv->sarea) {
 176                 DRM_ERROR("can not find sarea!\n");
 177                 i915_dma_cleanup(dev);
 178                 return -EINVAL;
 179         }
 180
 181         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 182             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 183
 184         if (init->ring_size != 0) {
 185                 if (LP_RING(dev_priv)->buffer->obj != NULL) {
 186                         i915_dma_cleanup(dev);
 187                         DRM_ERROR("Client tried to initialize ringbuffer in "
 188                                   "GEM mode\n");
 189                         return -EINVAL;
 190                 }
 191
 192                 ret = intel_render_ring_init_dri(dev,
 193                                                  init->ring_start,
 194                                                  init->ring_size);
 195                 if (ret) {
 196                         i915_dma_cleanup(dev);
 197                         return ret;
 198                 }
 199         }
 200
 201         dev_priv->dri1.cpp = init->cpp;
 202         dev_priv->dri1.back_offset = init->back_offset;
 203         dev_priv->dri1.front_offset = init->front_offset;
 204         dev_priv->dri1.current_page = 0;
 205         dev_priv->sarea_priv->pf_current_page = 0;
 206
 207
 208         /* Allow hardware batchbuffers unless told otherwise.
 209          */
 210         dev_priv->dri1.allow_batchbuffer = 1;
 211
 212         return 0;
 213 }
 214
 215 static int i915_dma_resume(struct drm_device *dev)
 216 {
 217         struct drm_i915_private *dev_priv = dev->dev_private;
 218         struct intel_engine_cs *ring = LP_RING(dev_priv);
 219
 220         DRM_DEBUG_DRIVER("%s\n", __func__);
 221
 222         if (ring->buffer->virtual_start == NULL) {
 223                 DRM_ERROR("can not ioremap virtual address for"
 224                           " ring buffer\n");
 225                 return -ENOMEM;
 226         }
 227
 228         /* Program Hardware Status Page */
 229         if (!ring->status_page.page_addr) {
 230                 DRM_ERROR("Can not find hardware status page\n");
 231                 return -EINVAL;
 232         }
 233         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 234                                 ring->status_page.page_addr);
 235         if (ring->status_page.gfx_addr != 0)
 236                 intel_ring_setup_status_page(ring);
 237         else
 238                 i915_write_hws_pga(dev);
 239
 240         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 241
 242         return 0;
 243 }
 244
 245 static int i915_dma_init(struct drm_device *dev, void *data,
 246                          struct drm_file *file_priv)
 247 {
 248         drm_i915_init_t *init = data;
 249         int retcode = 0;
 250
 251         if (drm_core_check_feature(dev, DRIVER_MODESET))
 252                 return -ENODEV;
 253
 254         switch (init->func) {
 255         case I915_INIT_DMA:
 256                 retcode = i915_initialize(dev, init);
 257                 break;
 258         case I915_CLEANUP_DMA:
 259                 retcode = i915_dma_cleanup(dev);
 260                 break;
 261         case I915_RESUME_DMA:
 262                 retcode = i915_dma_resume(dev);
 263                 break;
 264         default:
 265                 retcode = -EINVAL;
 266                 break;
 267         }
 268
 269         return retcode;
 270 }
 271
 272 /* Implement basically the same security restrictions as hardware does
 273  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 274  *
 275  * Most of the calculations below involve calculating the size of a
 276  * particular instruction.  It's important to get the size right as
 277  * that tells us where the next instruction to check is.  Any illegal
 278  * instruction detected will be given a size of zero, which is a
 279  * signal to abort the rest of the buffer.
 280  */
 281 static int validate_cmd(int cmd)
 282 {
 283         switch (((cmd >> 29) & 0x7)) {
 284         case 0x0:
 285                 switch ((cmd >> 23) & 0x3f) {
 286                 case 0x0:
 287                         return 1;       /* MI_NOOP */
 288                 case 0x4:
 289                         return 1;       /* MI_FLUSH */
 290                 default:
 291                         return 0;       /* disallow everything else */
 292                 }
 293                 break;
 294         case 0x1:
 295                 return 0;       /* reserved */
 296         case 0x2:
 297                 return (cmd & 0xff) + 2;        /* 2d commands */
 298         case 0x3:
 299                 if (((cmd >> 24) & 0x1f) <= 0x18)
 300                         return 1;
 301
 302                 switch ((cmd >> 24) & 0x1f) {
 303                 case 0x1c:
 304                         return 1;
 305                 case 0x1d:
 306                         switch ((cmd >> 16) & 0xff) {
 307                         case 0x3:
 308                                 return (cmd & 0x1f) + 2;
 309                         case 0x4:
 310                                 return (cmd & 0xf) + 2;
 311                         default:
 312                                 return (cmd & 0xffff) + 2;
 313                         }
 314                 case 0x1e:
 315                         if (cmd & (1 << 23))
 316                                 return (cmd & 0xffff) + 1;
 317                         else
 318                                 return 1;
 319                 case 0x1f:
 320                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 321                                 return (cmd & 0x1ffff) + 2;
 322                         else if (cmd & (1 << 17))       /* indirect random */
 323                                 if ((cmd & 0xffff) == 0)
 324                                         return 0;       /* unknown length, too hard */
 325                                 else
 326                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 327                         else
 328                                 return 2;       /* indirect sequential */
 329                 default:
 330                         return 0;
 331                 }
 332         default:
 333                 return 0;
 334         }
 335
 336         return 0;
 337 }
 338
 339 static int i915_emit_cmds(struct drm_device *dev, int *buffer, int dwords)
 340 {
 341         struct drm_i915_private *dev_priv = dev->dev_private;
 342         int i, ret;
 343
 344         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->buffer->size - 8)
 345                 return -EINVAL;
 346
 347         for (i = 0; i < dwords;) {
 348                 int sz = validate_cmd(buffer[i]);
 349
 350                 if (sz == 0 || i + sz > dwords)
 351                         return -EINVAL;
 352                 i += sz;
 353         }
 354
 355         ret = BEGIN_LP_RING((dwords+1)&~1);
 356         if (ret)
 357                 return ret;
 358
 359         for (i = 0; i < dwords; i++)
 360                 OUT_RING(buffer[i]);
 361         if (dwords & 1)
 362                 OUT_RING(0);
 363
 364         ADVANCE_LP_RING();
 365
 366         return 0;
 367 }
 368
 369 int
 370 i915_emit_box(struct drm_device *dev,
 371               struct drm_clip_rect *box,
 372               int DR1, int DR4)
 373 {
 374         struct drm_i915_private *dev_priv = dev->dev_private;
 375         int ret;
 376
 377         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 378             box->y2 <= 0 || box->x2 <= 0) {
 379                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 380                           box->x1, box->y1, box->x2, box->y2);
 381                 return -EINVAL;
 382         }
 383
 384         if (INTEL_INFO(dev)->gen >= 4) {
 385                 ret = BEGIN_LP_RING(4);
 386                 if (ret)
 387                         return ret;
 388
 389                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 390                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 391                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 392                 OUT_RING(DR4);
 393         } else {
 394                 ret = BEGIN_LP_RING(6);
 395                 if (ret)
 396                         return ret;
 397
 398                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 399                 OUT_RING(DR1);
 400                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 401                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 402                 OUT_RING(DR4);
 403                 OUT_RING(0);
 404         }
 405         ADVANCE_LP_RING();
 406
 407         return 0;
 408 }
 409
 410 /* XXX: Emitting the counter should really be moved to part of the IRQ
 411  * emit. For now, do it in both places:
 412  */
 413
 414 static void i915_emit_breadcrumb(struct drm_device *dev)
 415 {
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417
 418         dev_priv->dri1.counter++;
 419         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 420                 dev_priv->dri1.counter = 0;
 421         if (dev_priv->sarea_priv)
 422                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 423
 424         if (BEGIN_LP_RING(4) == 0) {
 425                 OUT_RING(MI_STORE_DWORD_INDEX);
 426                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 427                 OUT_RING(dev_priv->dri1.counter);
 428                 OUT_RING(0);
 429                 ADVANCE_LP_RING();
 430         }
 431 }
 432
 433 static int i915_dispatch_cmdbuffer(struct drm_device *dev,
 434                                    drm_i915_cmdbuffer_t *cmd,
 435                                    struct drm_clip_rect *cliprects,
 436                                    void *cmdbuf)
 437 {
 438         int nbox = cmd->num_cliprects;
 439         int i = 0, count, ret;
 440
 441         if (cmd->sz & 0x3) {
 442                 DRM_ERROR("alignment");
 443                 return -EINVAL;
 444         }
 445
 446         i915_kernel_lost_context(dev);
 447
 448         count = nbox ? nbox : 1;
 449
 450         for (i = 0; i < count; i++) {
 451                 if (i < nbox) {
 452                         ret = i915_emit_box(dev, &cliprects[i],
 453                                             cmd->DR1, cmd->DR4);
 454                         if (ret)
 455                                 return ret;
 456                 }
 457
 458                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 459                 if (ret)
 460                         return ret;
 461         }
 462
 463         i915_emit_breadcrumb(dev);
 464         return 0;
 465 }
 466
 467 static int i915_dispatch_batchbuffer(struct drm_device *dev,
 468                                      drm_i915_batchbuffer_t *batch,
 469                                      struct drm_clip_rect *cliprects)
 470 {
 471         struct drm_i915_private *dev_priv = dev->dev_private;
 472         int nbox = batch->num_cliprects;
 473         int i, count, ret;
 474
 475         if ((batch->start | batch->used) & 0x7) {
 476                 DRM_ERROR("alignment");
 477                 return -EINVAL;
 478         }
 479
 480         i915_kernel_lost_context(dev);
 481
 482         count = nbox ? nbox : 1;
 483         for (i = 0; i < count; i++) {
 484                 if (i < nbox) {
 485                         ret = i915_emit_box(dev, &cliprects[i],
 486                                             batch->DR1, batch->DR4);
 487                         if (ret)
 488                                 return ret;
 489                 }
 490
 491                 if (!IS_I830(dev) && !IS_845G(dev)) {
 492                         ret = BEGIN_LP_RING(2);
 493                         if (ret)
 494                                 return ret;
 495
 496                         if (INTEL_INFO(dev)->gen >= 4) {
 497                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 498                                 OUT_RING(batch->start);
 499                         } else {
 500                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 501                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 502                         }
 503                 } else {
 504                         ret = BEGIN_LP_RING(4);
 505                         if (ret)
 506                                 return ret;
 507
 508                         OUT_RING(MI_BATCH_BUFFER);
 509                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 510                         OUT_RING(batch->start + batch->used - 4);
 511                         OUT_RING(0);
 512                 }
 513                 ADVANCE_LP_RING();
 514         }
 515
 516
 517         if (IS_G4X(dev) || IS_GEN5(dev)) {
 518                 if (BEGIN_LP_RING(2) == 0) {
 519                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 520                         OUT_RING(MI_NOOP);
 521                         ADVANCE_LP_RING();
 522                 }
 523         }
 524
 525         i915_emit_breadcrumb(dev);
 526         return 0;
 527 }
 528
 529 static int i915_dispatch_flip(struct drm_device *dev)
 530 {
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         int ret;
 533
 534         if (!dev_priv->sarea_priv)
 535                 return -EINVAL;
 536
 537         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 538                           __func__,
 539                          dev_priv->dri1.current_page,
 540                          dev_priv->sarea_priv->pf_current_page);
 541
 542         i915_kernel_lost_context(dev);
 543
 544         ret = BEGIN_LP_RING(10);
 545         if (ret)
 546                 return ret;
 547
 548         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 549         OUT_RING(0);
 550
 551         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 552         OUT_RING(0);
 553         if (dev_priv->dri1.current_page == 0) {
 554                 OUT_RING(dev_priv->dri1.back_offset);
 555                 dev_priv->dri1.current_page = 1;
 556         } else {
 557                 OUT_RING(dev_priv->dri1.front_offset);
 558                 dev_priv->dri1.current_page = 0;
 559         }
 560         OUT_RING(0);
 561
 562         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 563         OUT_RING(0);
 564
 565         ADVANCE_LP_RING();
 566
 567         dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 568
 569         if (BEGIN_LP_RING(4) == 0) {
 570                 OUT_RING(MI_STORE_DWORD_INDEX);
 571                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 572                 OUT_RING(dev_priv->dri1.counter);
 573                 OUT_RING(0);
 574                 ADVANCE_LP_RING();
 575         }
 576
 577         dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 578         return 0;
 579 }
 580
 581 static int i915_quiescent(struct drm_device *dev)
 582 {
 583         i915_kernel_lost_context(dev);
 584         return intel_ring_idle(LP_RING(dev->dev_private));
 585 }
 586
 587 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 588                             struct drm_file *file_priv)
 589 {
 590         int ret;
 591
 592         if (drm_core_check_feature(dev, DRIVER_MODESET))
 593                 return -ENODEV;
 594
 595         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 596
 597         mutex_lock(&dev->struct_mutex);
 598         ret = i915_quiescent(dev);
 599         mutex_unlock(&dev->struct_mutex);
 600
 601         return ret;
 602 }
 603
 604 static int i915_batchbuffer(struct drm_device *dev, void *data,
 605                             struct drm_file *file_priv)
 606 {
 607         struct drm_i915_private *dev_priv = dev->dev_private;
 608         drm_i915_sarea_t *sarea_priv;
 609         drm_i915_batchbuffer_t *batch = data;
 610         int ret;
 611         struct drm_clip_rect *cliprects = NULL;
 612
 613         if (drm_core_check_feature(dev, DRIVER_MODESET))
 614                 return -ENODEV;
 615
 616         sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv;
 617
 618         if (!dev_priv->dri1.allow_batchbuffer) {
 619                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 620                 return -EINVAL;
 621         }
 622
 623         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 624                         batch->start, batch->used, batch->num_cliprects);
 625
 626         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 627
 628         if (batch->num_cliprects < 0)
 629                 return -EINVAL;
 630
 631         if (batch->num_cliprects) {
 632                 cliprects = kcalloc(batch->num_cliprects,
 633                                     sizeof(*cliprects),
 634                                     GFP_KERNEL);
 635                 if (cliprects == NULL)
 636                         return -ENOMEM;
 637
 638                 ret = copy_from_user(cliprects, batch->cliprects,
 639                                      batch->num_cliprects *
 640                                      sizeof(struct drm_clip_rect));
 641                 if (ret != 0) {
 642                         ret = -EFAULT;
 643                         goto fail_free;
 644                 }
 645         }
 646
 647         mutex_lock(&dev->struct_mutex);
 648         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 649         mutex_unlock(&dev->struct_mutex);
 650
 651         if (sarea_priv)
 652                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 653
 654 fail_free:
 655         kfree(cliprects);
 656
 657         return ret;
 658 }
 659
 660 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 661                           struct drm_file *file_priv)
 662 {
 663         struct drm_i915_private *dev_priv = dev->dev_private;
 664         drm_i915_sarea_t *sarea_priv;
 665         drm_i915_cmdbuffer_t *cmdbuf = data;
 666         struct drm_clip_rect *cliprects = NULL;
 667         void *batch_data;
 668         int ret;
 669
 670         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 671                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 672
 673         if (drm_core_check_feature(dev, DRIVER_MODESET))
 674                 return -ENODEV;
 675
 676         sarea_priv = (drm_i915_sarea_t *) dev_priv->sarea_priv;
 677
 678         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 679
 680         if (cmdbuf->num_cliprects < 0)
 681                 return -EINVAL;
 682
 683         batch_data = kmalloc(cmdbuf->sz, M_DRM, M_WAITOK);
 684         if (batch_data == NULL)
 685                 return -ENOMEM;
 686
 687         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 688         if (ret != 0) {
 689                 ret = -EFAULT;
 690                 goto fail_batch_free;
 691         }
 692
 693         if (cmdbuf->num_cliprects) {
 694                 cliprects = kcalloc(cmdbuf->num_cliprects,
 695                                     sizeof(*cliprects), GFP_KERNEL);
 696                 if (cliprects == NULL) {
 697                         ret = -ENOMEM;
 698                         goto fail_batch_free;
 699                 }
 700
 701                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 702                                      cmdbuf->num_cliprects *
 703                                      sizeof(struct drm_clip_rect));
 704                 if (ret != 0) {
 705                         ret = -EFAULT;
 706                         goto fail_clip_free;
 707                 }
 708         }
 709
 710         mutex_lock(&dev->struct_mutex);
 711         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 712         mutex_unlock(&dev->struct_mutex);
 713         if (ret) {
 714                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 715                 goto fail_clip_free;
 716         }
 717
 718         if (sarea_priv)
 719                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 720
 721 fail_clip_free:
 722         kfree(cliprects);
 723 fail_batch_free:
 724         kfree(batch_data);
 725
 726         return ret;
 727 }
 728
 729 static int i915_emit_irq(struct drm_device *dev)
 730 {
 731         struct drm_i915_private *dev_priv = dev->dev_private;
 732 #if 0
 733         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 734 #endif
 735
 736         i915_kernel_lost_context(dev);
 737
 738         DRM_DEBUG_DRIVER("\n");
 739
 740         dev_priv->dri1.counter++;
 741         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 742                 dev_priv->dri1.counter = 1;
 743         if (dev_priv->sarea_priv)
 744                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 745
 746         if (BEGIN_LP_RING(4) == 0) {
 747                 OUT_RING(MI_STORE_DWORD_INDEX);
 748                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 749                 OUT_RING(dev_priv->dri1.counter);
 750                 OUT_RING(MI_USER_INTERRUPT);
 751                 ADVANCE_LP_RING();
 752         }
 753
 754         return dev_priv->dri1.counter;
 755 }
 756
 757 static int i915_wait_irq(struct drm_device *dev, int irq_nr)
 758 {
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760 #if 0
 761         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 762 #endif
 763         int ret = 0;
 764         struct intel_engine_cs *ring = LP_RING(dev_priv);
 765
 766         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 767                   READ_BREADCRUMB(dev_priv));
 768
 769 #if 0
 770         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 771                 if (master_priv->sarea_priv)
 772                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 773                 return 0;
 774         }
 775
 776         if (master_priv->sarea_priv)
 777                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 778 #else
 779         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 780                 if (dev_priv->sarea_priv) {
 781                         dev_priv->sarea_priv->last_dispatch =
 782                                 READ_BREADCRUMB(dev_priv);
 783                 }
 784                 return 0;
 785         }
 786
 787         if (dev_priv->sarea_priv)
 788                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 789 #endif
 790
 791         if (ring->irq_get(ring)) {
 792                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ,
 793                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 794                 ring->irq_put(ring);
 795         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 796                 ret = -EBUSY;
 797
 798         if (ret == -EBUSY) {
 799                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 800                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 801         }
 802
 803         return ret;
 804 }
 805
 806 /* Needs the lock as it touches the ring.
 807  */
 808 static int i915_irq_emit(struct drm_device *dev, void *data,
 809                          struct drm_file *file_priv)
 810 {
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         drm_i915_irq_emit_t *emit = data;
 813         int result;
 814
 815         if (drm_core_check_feature(dev, DRIVER_MODESET))
 816                 return -ENODEV;
 817
 818         if (!dev_priv || !LP_RING(dev_priv)->buffer->virtual_start) {
 819                 DRM_ERROR("called with no initialization\n");
 820                 return -EINVAL;
 821         }
 822
 823         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 824
 825         mutex_lock(&dev->struct_mutex);
 826         result = i915_emit_irq(dev);
 827         mutex_unlock(&dev->struct_mutex);
 828
 829         if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
 830                 DRM_ERROR("copy_to_user\n");
 831                 return -EFAULT;
 832         }
 833
 834         return 0;
 835 }
 836
 837 /* Doesn't need the hardware lock.
 838  */
 839 static int i915_irq_wait(struct drm_device *dev, void *data,
 840                          struct drm_file *file_priv)
 841 {
 842         struct drm_i915_private *dev_priv = dev->dev_private;
 843         drm_i915_irq_wait_t *irqwait = data;
 844
 845         if (drm_core_check_feature(dev, DRIVER_MODESET))
 846                 return -ENODEV;
 847
 848         if (!dev_priv) {
 849                 DRM_ERROR("called with no initialization\n");
 850                 return -EINVAL;
 851         }
 852
 853         return i915_wait_irq(dev, irqwait->irq_seq);
 854 }
 855
 856 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 857                          struct drm_file *file_priv)
 858 {
 859         struct drm_i915_private *dev_priv = dev->dev_private;
 860         drm_i915_vblank_pipe_t *pipe = data;
 861
 862         if (drm_core_check_feature(dev, DRIVER_MODESET))
 863                 return -ENODEV;
 864
 865         if (!dev_priv) {
 866                 DRM_ERROR("called with no initialization\n");
 867                 return -EINVAL;
 868         }
 869
 870         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 871
 872         return 0;
 873 }
 874
 875 /**
 876  * Schedule buffer swap at given vertical blank.
 877  */
 878 static int i915_vblank_swap(struct drm_device *dev, void *data,
 879                      struct drm_file *file_priv)
 880 {
 881         /* The delayed swap mechanism was fundamentally racy, and has been
 882          * removed.  The model was that the client requested a delayed flip/swap
 883          * from the kernel, then waited for vblank before continuing to perform
 884          * rendering.  The problem was that the kernel might wake the client
 885          * up before it dispatched the vblank swap (since the lock has to be
 886          * held while touching the ringbuffer), in which case the client would
 887          * clear and start the next frame before the swap occurred, and
 888          * flicker would occur in addition to likely missing the vblank.
 889          *
 890          * In the absence of this ioctl, userland falls back to a correct path
 891          * of waiting for a vblank, then dispatching the swap on its own.
 892          * Context switching to userland and back is plenty fast enough for
 893          * meeting the requirements of vblank swapping.
 894          */
 895         return -EINVAL;
 896 }
 897
 898 static int i915_flip_bufs(struct drm_device *dev, void *data,
 899                           struct drm_file *file_priv)
 900 {
 901         int ret;
 902
 903         if (drm_core_check_feature(dev, DRIVER_MODESET))
 904                 return -ENODEV;
 905
 906         DRM_DEBUG_DRIVER("%s\n", __func__);
 907
 908         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 909
 910         mutex_lock(&dev->struct_mutex);
 911         ret = i915_dispatch_flip(dev);
 912         mutex_unlock(&dev->struct_mutex);
 913
 914         return ret;
 915 }
 916
 917 static int i915_getparam(struct drm_device *dev, void *data,
 918                          struct drm_file *file_priv)
 919 {
 920         struct drm_i915_private *dev_priv = dev->dev_private;
 921         drm_i915_getparam_t *param = data;
 922         int value;
 923
 924         if (!dev_priv) {
 925                 DRM_ERROR("called with no initialization\n");
 926                 return -EINVAL;
 927         }
 928
 929         switch (param->param) {
 930         case I915_PARAM_IRQ_ACTIVE:
 931                 value = dev->irq_enabled ? 1 : 0;
 932                 break;
 933         case I915_PARAM_ALLOW_BATCHBUFFER:
 934                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 935                 break;
 936         case I915_PARAM_LAST_DISPATCH:
 937                 value = READ_BREADCRUMB(dev_priv);
 938                 break;
 939         case I915_PARAM_CHIPSET_ID:
 940                 value = dev->pdev->device;
 941                 break;
 942         case I915_PARAM_HAS_GEM:
 943                 value = 1;
 944                 break;
 945         case I915_PARAM_NUM_FENCES_AVAIL:
 946                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 947                 break;
 948         case I915_PARAM_HAS_OVERLAY:
 949                 value = dev_priv->overlay ? 1 : 0;
 950                 break;
 951         case I915_PARAM_HAS_PAGEFLIPPING:
 952                 value = 1;
 953                 break;
 954         case I915_PARAM_HAS_EXECBUF2:
 955                 /* depends on GEM */
 956                 value = 1;
 957                 break;
 958         case I915_PARAM_HAS_BSD:
 959                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 960                 break;
 961         case I915_PARAM_HAS_BLT:
 962                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 963                 break;
 964         case I915_PARAM_HAS_VEBOX:
 965                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
 966                 break;
 967         case I915_PARAM_HAS_RELAXED_FENCING:
 968                 value = 1;
 969                 break;
 970         case I915_PARAM_HAS_COHERENT_RINGS:
 971                 value = 1;
 972                 break;
 973         case I915_PARAM_HAS_EXEC_CONSTANTS:
 974                 value = INTEL_INFO(dev)->gen >= 4;
 975                 break;
 976         case I915_PARAM_HAS_RELAXED_DELTA:
 977                 value = 1;
 978                 break;
 979         case I915_PARAM_HAS_GEN7_SOL_RESET:
 980                 value = 1;
 981                 break;
 982         case I915_PARAM_HAS_LLC:
 983                 value = HAS_LLC(dev);
 984                 break;
 985         case I915_PARAM_HAS_WT:
 986                 value = HAS_WT(dev);
 987                 break;
 988         case I915_PARAM_HAS_ALIASING_PPGTT:
 989                 value = dev_priv->mm.aliasing_ppgtt || USES_FULL_PPGTT(dev);
 990                 break;
 991         case I915_PARAM_HAS_WAIT_TIMEOUT:
 992                 value = 1;
 993                 break;
 994         case I915_PARAM_HAS_SEMAPHORES:
 995                 value = i915_semaphore_is_enabled(dev);
 996                 break;
 997         case I915_PARAM_HAS_PINNED_BATCHES:
 998                 value = 1;
 999                 break;
1000         case I915_PARAM_HAS_EXEC_NO_RELOC:
1001                 value = 1;
1002                 break;
1003         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1004                 value = 1;
1005                 break;
1006         case I915_PARAM_CMD_PARSER_VERSION:
1007                 value = i915_cmd_parser_get_version();
1008                 break;
1009         default:
1010                 DRM_DEBUG("Unknown parameter %d\n", param->param);
1011                 return -EINVAL;
1012         }
1013
1014         if (copy_to_user(param->value, &value, sizeof(int))) {
1015                 DRM_ERROR("copy_to_user failed\n");
1016                 return -EFAULT;
1017         }
1018
1019         return 0;
1020 }
1021
1022 static int i915_setparam(struct drm_device *dev, void *data,
1023                          struct drm_file *file_priv)
1024 {
1025         struct drm_i915_private *dev_priv = dev->dev_private;
1026         drm_i915_setparam_t *param = data;
1027
1028         if (!dev_priv) {
1029                 DRM_ERROR("called with no initialization\n");
1030                 return -EINVAL;
1031         }
1032
1033         switch (param->param) {
1034         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1035                 break;
1036         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1037                 break;
1038         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1039                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1040                 break;
1041         case I915_SETPARAM_NUM_USED_FENCES:
1042                 if (param->value > dev_priv->num_fence_regs ||
1043                     param->value < 0)
1044                         return -EINVAL;
1045                 /* Userspace can use first N regs */
1046                 dev_priv->fence_reg_start = param->value;
1047                 break;
1048         default:
1049                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1050                                         param->param);
1051                 return -EINVAL;
1052         }
1053
1054         return 0;
1055 }
1056
1057 static int i915_set_status_page(struct drm_device *dev, void *data,
1058                                 struct drm_file *file_priv)
1059 {
1060 #if 0   /* We don't care about dri1 */
1061         struct drm_i915_private *dev_priv = dev->dev_private;
1062         drm_i915_hws_addr_t *hws = data;
1063         struct intel_engine_cs *ring;
1064
1065         if (drm_core_check_feature(dev, DRIVER_MODESET))
1066                 return -ENODEV;
1067
1068         if (!I915_NEED_GFX_HWS(dev))
1069                 return -EINVAL;
1070
1071         if (!dev_priv) {
1072                 DRM_ERROR("called with no initialization\n");
1073                 return -EINVAL;
1074         }
1075
1076         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1077                 WARN(1, "tried to set status page when mode setting active\n");
1078                 return 0;
1079         }
1080
1081         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1082
1083         ring = LP_RING(dev_priv);
1084         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1085
1086         dev_priv->dri1.gfx_hws_cpu_addr =
1087                 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1088         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1089                 i915_dma_cleanup(dev);
1090                 ring->status_page.gfx_addr = 0;
1091                 DRM_ERROR("can not ioremap virtual address for"
1092                                 " G33 hw status page\n");
1093                 return -ENOMEM;
1094         }
1095
1096         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1097         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1098
1099         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1100                          ring->status_page.gfx_addr);
1101         DRM_DEBUG_DRIVER("load hws at %p\n",
1102                          ring->status_page.page_addr);
1103         return 0;
1104 #endif
1105         return -EINVAL;
1106 }
1107
1108 static int i915_get_bridge_dev(struct drm_device *dev)
1109 {
1110         struct drm_i915_private *dev_priv = dev->dev_private;
1111         static struct pci_dev i915_bridge_dev;
1112
1113         i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
1114         if (!i915_bridge_dev.dev) {
1115                 DRM_ERROR("bridge device not found\n");
1116                 return -1;
1117         }
1118
1119         dev_priv->bridge_dev = &i915_bridge_dev;
1120         return 0;
1121 }
1122
1123 #define MCHBAR_I915 0x44
1124 #define MCHBAR_I965 0x48
1125 #define MCHBAR_SIZE (4*4096)
1126
1127 #define DEVEN_REG 0x54
1128 #define   DEVEN_MCHBAR_EN (1 << 28)
1129
1130 /* Allocate space for the MCH regs if needed, return nonzero on error */
1131 static int
1132 intel_alloc_mchbar_resource(struct drm_device *dev)
1133 {
1134         struct drm_i915_private *dev_priv = dev->dev_private;
1135         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1136         device_t vga;
1137         u32 temp_lo, temp_hi = 0;
1138         u64 mchbar_addr;
1139
1140         if (INTEL_INFO(dev)->gen >= 4)
1141                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1142         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1143         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1144
1145         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1146 #ifdef CONFIG_PNP
1147         if (mchbar_addr &&
1148             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1149                 return 0;
1150 #endif
1151
1152         /* Get some space for it */
1153         vga = device_get_parent(dev->dev);
1154         dev_priv->mch_res_rid = 0x100;
1155         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1156             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1157             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1158         if (dev_priv->mch_res == NULL) {
1159                 DRM_ERROR("failed mchbar resource alloc\n");
1160                 return (-ENOMEM);
1161         }
1162
1163         if (INTEL_INFO(dev)->gen >= 4)
1164                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1165                                        upper_32_bits(rman_get_start(dev_priv->mch_res)));
1166
1167         pci_write_config_dword(dev_priv->bridge_dev, reg,
1168                                lower_32_bits(rman_get_start(dev_priv->mch_res)));
1169         return 0;
1170 }
1171
1172 /* Setup MCHBAR if possible, return true if we should disable it again */
1173 static void
1174 intel_setup_mchbar(struct drm_device *dev)
1175 {
1176         struct drm_i915_private *dev_priv = dev->dev_private;
1177         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1178         u32 temp;
1179         bool enabled;
1180
1181         if (IS_VALLEYVIEW(dev))
1182                 return;
1183
1184         dev_priv->mchbar_need_disable = false;
1185
1186         if (IS_I915G(dev) || IS_I915GM(dev)) {
1187                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1188                 enabled = !!(temp & DEVEN_MCHBAR_EN);
1189         } else {
1190                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1191                 enabled = temp & 1;
1192         }
1193
1194         /* If it's already enabled, don't have to do anything */
1195         if (enabled)
1196                 return;
1197
1198         if (intel_alloc_mchbar_resource(dev))
1199                 return;
1200
1201         dev_priv->mchbar_need_disable = true;
1202
1203         /* Space is allocated or reserved, so enable it. */
1204         if (IS_I915G(dev) || IS_I915GM(dev)) {
1205                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1206                                        temp | DEVEN_MCHBAR_EN);
1207         } else {
1208                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1209                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1210         }
1211 }
1212
1213 static void
1214 intel_teardown_mchbar(struct drm_device *dev)
1215 {
1216         struct drm_i915_private *dev_priv = dev->dev_private;
1217         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1218         device_t vga;
1219         u32 temp;
1220
1221         if (dev_priv->mchbar_need_disable) {
1222                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1223                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1224                         temp &= ~DEVEN_MCHBAR_EN;
1225                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1226                 } else {
1227                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1228                         temp &= ~1;
1229                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1230                 }
1231         }
1232
1233         if (dev_priv->mch_res != NULL) {
1234                 vga = device_get_parent(dev->dev);
1235                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1236                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1237                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1238                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1239                 dev_priv->mch_res = NULL;
1240         }
1241 }
1242
1243 #if 0
1244 /* true = enable decode, false = disable decoder */
1245 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1246 {
1247         struct drm_device *dev = cookie;
1248
1249         intel_modeset_vga_set_state(dev, state);
1250         if (state)
1251                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1252                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1253         else
1254                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1255 }
1256
1257 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1258 {
1259         struct drm_device *dev = pci_get_drvdata(pdev);
1260         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1261
1262         if (state == VGA_SWITCHEROO_ON) {
1263                 pr_info("switched on\n");
1264                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1265                 /* i915 resume handler doesn't set to D0 */
1266                 pci_set_power_state(dev->pdev, PCI_D0);
1267                 i915_resume(dev);
1268                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1269         } else {
1270                 pr_err("switched off\n");
1271                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1272                 i915_suspend(dev, pmm);
1273                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1274         }
1275 }
1276
1277 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1278 {
1279         struct drm_device *dev = pci_get_drvdata(pdev);
1280
1281         /*
1282          * FIXME: open_count is protected by drm_global_mutex but that would lead to
1283          * locking inversion with the driver load path. And the access here is
1284          * completely racy anyway. So don't bother with locking for now.
1285          */
1286         return dev->open_count == 0;
1287 }
1288
1289 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1290         .set_gpu_state = i915_switcheroo_set_state,
1291         .reprobe = NULL,
1292         .can_switch = i915_switcheroo_can_switch,
1293 };
1294 #endif
1295
1296 static int i915_load_modeset_init(struct drm_device *dev)
1297 {
1298         struct drm_i915_private *dev_priv = dev->dev_private;
1299         int ret;
1300
1301         ret = intel_parse_bios(dev);
1302         if (ret)
1303                 DRM_INFO("failed to find VBIOS tables\n");
1304
1305 #if 0
1306         /* If we have > 1 VGA cards, then we need to arbitrate access
1307          * to the common VGA resources.
1308          *
1309          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1310          * then we do not take part in VGA arbitration and the
1311          * vga_client_register() fails with -ENODEV.
1312          */
1313         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1314         if (ret && ret != -ENODEV)
1315                 goto out;
1316
1317         intel_register_dsm_handler();
1318
1319         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1320         if (ret)
1321                 goto cleanup_vga_client;
1322
1323         /* Initialise stolen first so that we may reserve preallocated
1324          * objects for the BIOS to KMS transition.
1325          */
1326         ret = i915_gem_init_stolen(dev);
1327         if (ret)
1328                 goto cleanup_vga_switcheroo;
1329 #endif
1330
1331         intel_power_domains_init_hw(dev_priv);
1332
1333         /*
1334          * We enable some interrupt sources in our postinstall hooks, so mark
1335          * interrupts as enabled _before_ actually enabling them to avoid
1336          * special cases in our ordering checks.
1337          */
1338         dev_priv->pm._irqs_disabled = false;
1339
1340         ret = drm_irq_install(dev, dev->irq);
1341         if (ret)
1342                 goto cleanup_gem_stolen;
1343
1344         /* Important: The output setup functions called by modeset_init need
1345          * working irqs for e.g. gmbus and dp aux transfers. */
1346         intel_modeset_init(dev);
1347
1348         ret = i915_gem_init(dev);
1349         if (ret)
1350                 goto cleanup_irq;
1351
1352 #if 0
1353         INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1354 #endif
1355
1356         intel_modeset_gem_init(dev);
1357
1358         /* Always safe in the mode setting case. */
1359         /* FIXME: do pre/post-mode set stuff in core KMS code */
1360         dev->vblank_disable_allowed = 1;
1361         if (INTEL_INFO(dev)->num_pipes == 0) {
1362                 return 0;
1363         }
1364
1365         ret = intel_fbdev_init(dev);
1366         if (ret)
1367                 goto cleanup_gem;
1368
1369         /* Only enable hotplug handling once the fbdev is fully set up. */
1370         intel_hpd_init(dev);
1371
1372         /*
1373          * Some ports require correctly set-up hpd registers for detection to
1374          * work properly (leading to ghost connected connector status), e.g. VGA
1375          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1376          * irqs are fully enabled. Now we should scan for the initial config
1377          * only once hotplug handling is enabled, but due to screwed-up locking
1378          * around kms/fbdev init we can't protect the fdbev initial config
1379          * scanning against hotplug events. Hence do this first and ignore the
1380          * tiny window where we will loose hotplug notifactions.
1381          */
1382         intel_fbdev_initial_config(dev);
1383
1384         drm_kms_helper_poll_init(dev);
1385
1386         return 0;
1387
1388 cleanup_gem:
1389         mutex_lock(&dev->struct_mutex);
1390         i915_gem_cleanup_ringbuffer(dev);
1391         i915_gem_context_fini(dev);
1392         mutex_unlock(&dev->struct_mutex);
1393         WARN_ON(dev_priv->mm.aliasing_ppgtt);
1394 cleanup_irq:
1395         drm_irq_uninstall(dev);
1396 cleanup_gem_stolen:
1397 #if 0
1398         i915_gem_cleanup_stolen(dev);
1399 cleanup_vga_switcheroo:
1400         vga_switcheroo_unregister_client(dev->pdev);
1401 cleanup_vga_client:
1402         vga_client_register(dev->pdev, NULL, NULL, NULL);
1403 out:
1404 #endif
1405         return ret;
1406 }
1407
1408 #if 0
1409 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1410 {
1411         struct drm_i915_master_private *master_priv;
1412
1413         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1414         if (!master_priv)
1415                 return -ENOMEM;
1416
1417         master->driver_priv = master_priv;
1418         return 0;
1419 }
1420
1421 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1422 {
1423         struct drm_i915_master_private *master_priv = master->driver_priv;
1424
1425         if (!master_priv)
1426                 return;
1427
1428         kfree(master_priv);
1429
1430         master->driver_priv = NULL;
1431 }
1432 #endif
1433
1434 #if IS_ENABLED(CONFIG_FB)
1435 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1436 {
1437         struct apertures_struct *ap;
1438         struct pci_dev *pdev = dev_priv->dev->pdev;
1439         bool primary;
1440         int ret;
1441
1442         ap = alloc_apertures(1);
1443         if (!ap)
1444                 return -ENOMEM;
1445
1446         ap->ranges[0].base = dev_priv->gtt.mappable_base;
1447         ap->ranges[0].size = dev_priv->gtt.mappable_end;
1448
1449         primary =
1450                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1451
1452         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1453
1454         kfree(ap);
1455
1456         return ret;
1457 }
1458 #else
1459 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1460 {
1461         return 0;
1462 }
1463 #endif
1464
1465 #if !defined(CONFIG_VGA_CONSOLE)
1466 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1467 {
1468         return 0;
1469 }
1470 #elif !defined(CONFIG_DUMMY_CONSOLE)
1471 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1472 {
1473         return -ENODEV;
1474 }
1475 #else
1476 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1477 {
1478         int ret = 0;
1479
1480         DRM_INFO("Replacing VGA console driver\n");
1481
1482         console_lock();
1483         if (con_is_bound(&vga_con))
1484                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
1485         if (ret == 0) {
1486                 ret = do_unregister_con_driver(&vga_con);
1487
1488                 /* Ignore "already unregistered". */
1489                 if (ret == -ENODEV)
1490                         ret = 0;
1491         }
1492         console_unlock();
1493
1494         return ret;
1495 }
1496 #endif
1497
1498 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1499 {
1500 #if 0
1501         const struct intel_device_info *info = &dev_priv->info;
1502
1503 #define PRINT_S(name) "%s"
1504 #define SEP_EMPTY
1505 #define PRINT_FLAG(name) info->name ? #name "," : ""
1506 #define SEP_COMMA ,
1507         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
1508                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1509                          info->gen,
1510                          dev_priv->dev->pdev->device,
1511                          dev_priv->dev->pdev->revision,
1512                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1513 #undef PRINT_S
1514 #undef SEP_EMPTY
1515 #undef PRINT_FLAG
1516 #undef SEP_COMMA
1517 #endif
1518 }
1519
1520 /*
1521  * Determine various intel_device_info fields at runtime.
1522  *
1523  * Use it when either:
1524  *   - it's judged too laborious to fill n static structures with the limit
1525  *     when a simple if statement does the job,
1526  *   - run-time checks (eg read fuse/strap registers) are needed.
1527  *
1528  * This function needs to be called:
1529  *   - after the MMIO has been setup as we are reading registers,
1530  *   - after the PCH has been detected,
1531  *   - before the first usage of the fields it can tweak.
1532  */
1533 static void intel_device_info_runtime_init(struct drm_device *dev)
1534 {
1535         struct drm_i915_private *dev_priv = dev->dev_private;
1536         struct intel_device_info *info;
1537         enum i915_pipe pipe;
1538
1539         info = (struct intel_device_info *)&dev_priv->info;
1540
1541         if (IS_VALLEYVIEW(dev))
1542                 for_each_pipe(pipe)
1543                         info->num_sprites[pipe] = 2;
1544         else
1545                 for_each_pipe(pipe)
1546                         info->num_sprites[pipe] = 1;
1547
1548         if (i915.disable_display) {
1549                 DRM_INFO("Display disabled (module parameter)\n");
1550                 info->num_pipes = 0;
1551         } else if (info->num_pipes > 0 &&
1552                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
1553                    !IS_VALLEYVIEW(dev)) {
1554                 u32 fuse_strap = I915_READ(FUSE_STRAP);
1555                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
1556
1557                 /*
1558                  * SFUSE_STRAP is supposed to have a bit signalling the display
1559                  * is fused off. Unfortunately it seems that, at least in
1560                  * certain cases, fused off display means that PCH display
1561                  * reads don't land anywhere. In that case, we read 0s.
1562                  *
1563                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1564                  * should be set when taking over after the firmware.
1565                  */
1566                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1567                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1568                     (dev_priv->pch_type == PCH_CPT &&
1569                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1570                         DRM_INFO("Display fused off, disabling\n");
1571                         info->num_pipes = 0;
1572                 }
1573         }
1574 }
1575
1576 /**
1577  * i915_driver_load - setup chip and create an initial config
1578  * @dev: DRM device
1579  * @flags: startup flags
1580  *
1581  * The driver load routine has to do several things:
1582  *   - drive output discovery via intel_modeset_init()
1583  *   - initialize the memory manager
1584  *   - allocate initial config memory
1585  *   - setup the DRM framebuffer with the allocated memory
1586  */
1587 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1588 {
1589         struct drm_i915_private *dev_priv = dev->dev_private;
1590         struct intel_device_info *info, *device_info;
1591         unsigned long base, size;
1592         int ret = 0, mmio_bar, mmio_size;
1593         uint32_t aperture_size;
1594         static struct pci_dev i915_pdev;
1595
1596         /* XXX: dev->pci_device not present in Linux drm */
1597         info = i915_get_device_id(dev->pci_device);
1598
1599         /* XXX: struct pci_dev */
1600         i915_pdev.dev = dev->dev;
1601         dev->pdev = &i915_pdev;
1602         dev->pdev->device = dev->pci_device;
1603
1604         /* Refuse to load on gen6+ without kms enabled. */
1605         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1606                 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1607                 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1608                 return -ENODEV;
1609         }
1610
1611         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1612         if (dev_priv == NULL)
1613                 return -ENOMEM;
1614
1615         dev->dev_private = dev_priv;
1616         dev_priv->dev = dev;
1617
1618         /* copy initial configuration to dev_priv->info */
1619         device_info = (struct intel_device_info *)&dev_priv->info;
1620         *device_info = *info;
1621
1622         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1623         lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
1624         spin_init(&dev_priv->backlight_lock, "i915bl");
1625         lockinit(&dev_priv->uncore.lock, "915gt", 0, LK_CANRECURSE);
1626         spin_init(&dev_priv->mm.object_stat_lock, "i915osl");
1627         spin_init(&dev_priv->mmio_flip_lock, "i915mfl");
1628         lockinit(&dev_priv->dpio_lock, "i915dpio", 0, LK_CANRECURSE);
1629         lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
1630
1631         intel_pm_setup(dev);
1632
1633         intel_display_crc_init(dev);
1634
1635         i915_dump_device_info(dev_priv);
1636
1637         /* Not all pre-production machines fall into this category, only the
1638          * very first ones. Almost everything should work, except for maybe
1639          * suspend/resume. And we don't implement workarounds that affect only
1640          * pre-production machines. */
1641         if (IS_HSW_EARLY_SDV(dev))
1642                 DRM_INFO("This is an early pre-production Haswell machine. "
1643                          "It may not be fully functional.\n");
1644
1645         if (i915_get_bridge_dev(dev)) {
1646                 ret = -EIO;
1647                 goto free_priv;
1648         }
1649
1650         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1651         /* Before gen4, the registers and the GTT are behind different BARs.
1652          * However, from gen4 onwards, the registers and the GTT are shared
1653          * in the same BAR, so we want to restrict this ioremap from
1654          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1655          * the register BAR remains the same size for all the earlier
1656          * generations up to Ironlake.
1657          */
1658         if (info->gen < 5)
1659                 mmio_size = 512*1024;
1660         else
1661                 mmio_size = 2*1024*1024;
1662
1663 #if 0
1664         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1665         if (!dev_priv->regs) {
1666                 DRM_ERROR("failed to map registers\n");
1667                 ret = -EIO;
1668                 goto put_bridge;
1669         }
1670 #else
1671         base = drm_get_resource_start(dev, mmio_bar);
1672         size = drm_get_resource_len(dev, mmio_bar);
1673
1674         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1675             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1676 #endif
1677
1678         /* This must be called before any calls to HAS_PCH_* */
1679         intel_detect_pch(dev);
1680
1681         intel_uncore_init(dev);
1682
1683         ret = i915_gem_gtt_init(dev);
1684         if (ret)
1685                 goto out_regs;
1686
1687         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1688                 ret = i915_kick_out_vgacon(dev_priv);
1689                 if (ret) {
1690                         DRM_ERROR("failed to remove conflicting VGA console\n");
1691                         goto out_gtt;
1692                 }
1693
1694                 ret = i915_kick_out_firmware_fb(dev_priv);
1695                 if (ret) {
1696                         DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1697                         goto out_gtt;
1698                 }
1699         }
1700
1701 #if 0
1702         pci_set_master(dev->pdev);
1703
1704         /* overlay on gen2 is broken and can't address above 1G */
1705         if (IS_GEN2(dev))
1706                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1707
1708         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1709          * using 32bit addressing, overwriting memory if HWS is located
1710          * above 4GB.
1711          *
1712          * The documentation also mentions an issue with undefined
1713          * behaviour if any general state is accessed within a page above 4GB,
1714          * which also needs to be handled carefully.
1715          */
1716         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1717                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1718 #endif
1719
1720         aperture_size = dev_priv->gtt.mappable_end;
1721
1722         dev_priv->gtt.mappable =
1723                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1724                                      aperture_size);
1725         if (dev_priv->gtt.mappable == NULL) {
1726                 ret = -EIO;
1727                 goto out_gtt;
1728         }
1729
1730         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1731                                               aperture_size);
1732
1733         /* The i915 workqueue is primarily used for batched retirement of
1734          * requests (and thus managing bo) once the task has been completed
1735          * by the GPU. i915_gem_retire_requests() is called directly when we
1736          * need high-priority retirement, such as waiting for an explicit
1737          * bo.
1738          *
1739          * It is also used for periodic low-priority events, such as
1740          * idle-timers and recording error state.
1741          *
1742          * All tasks on the workqueue are expected to acquire the dev mutex
1743          * so there is no point in running more than one instance of the
1744          * workqueue at any time.  Use an ordered one.
1745          */
1746         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1747         if (dev_priv->wq == NULL) {
1748                 DRM_ERROR("Failed to create our workqueue.\n");
1749                 ret = -ENOMEM;
1750                 goto out_mtrrfree;
1751         }
1752
1753         dev_priv->dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1754         if (dev_priv->dp_wq == NULL) {
1755                 DRM_ERROR("Failed to create our dp workqueue.\n");
1756                 ret = -ENOMEM;
1757                 goto out_freewq;
1758         }
1759
1760         intel_irq_init(dev);
1761         intel_uncore_sanitize(dev);
1762
1763         /* Try to make sure MCHBAR is enabled before poking at it */
1764         intel_setup_mchbar(dev);
1765         intel_setup_gmbus(dev);
1766         intel_opregion_setup(dev);
1767
1768         intel_setup_bios(dev);
1769
1770         i915_gem_load(dev);
1771
1772         /* On the 945G/GM, the chipset reports the MSI capability on the
1773          * integrated graphics even though the support isn't actually there
1774          * according to the published specs.  It doesn't appear to function
1775          * correctly in testing on 945G.
1776          * This may be a side effect of MSI having been made available for PEG
1777          * and the registers being closely associated.
1778          *
1779          * According to chipset errata, on the 965GM, MSI interrupts may
1780          * be lost or delayed, but we use them anyways to avoid
1781          * stuck interrupts on some machines.
1782          */
1783 #if 0
1784         if (!IS_I945G(dev) && !IS_I945GM(dev))
1785                 pci_enable_msi(dev->pdev);
1786 #endif
1787
1788         intel_device_info_runtime_init(dev);
1789
1790         if (INTEL_INFO(dev)->num_pipes) {
1791                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1792                 if (ret)
1793                         goto out_gem_unload;
1794         }
1795
1796         intel_power_domains_init(dev_priv);
1797
1798         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1799                 ret = i915_load_modeset_init(dev);
1800                 if (ret < 0) {
1801                         DRM_ERROR("failed to init modeset\n");
1802                         goto out_power_well;
1803                 }
1804         } else {
1805                 /* Start out suspended in ums mode. */
1806                 dev_priv->ums.mm_suspended = 1;
1807         }
1808
1809 #if 0
1810         i915_setup_sysfs(dev);
1811 #endif
1812
1813         if (INTEL_INFO(dev)->num_pipes) {
1814                 /* Must be done after probing outputs */
1815                 intel_opregion_init(dev);
1816 #if 0
1817                 acpi_video_register();
1818 #endif
1819         }
1820
1821         if (IS_GEN5(dev))
1822                 intel_gpu_ips_init(dev_priv);
1823
1824         intel_init_runtime_pm(dev_priv);
1825
1826         return 0;
1827
1828 out_power_well:
1829         intel_power_domains_remove(dev_priv);
1830         drm_vblank_cleanup(dev);
1831 out_gem_unload:
1832
1833         intel_teardown_gmbus(dev);
1834         intel_teardown_mchbar(dev);
1835         pm_qos_remove_request(&dev_priv->pm_qos);
1836         destroy_workqueue(dev_priv->dp_wq);
1837 out_freewq:
1838         destroy_workqueue(dev_priv->wq);
1839 out_mtrrfree:
1840         arch_phys_wc_del(dev_priv->gtt.mtrr);
1841 #if 0
1842         io_mapping_free(dev_priv->gtt.mappable);
1843 #endif
1844 out_gtt:
1845         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1846 out_regs:
1847         intel_uncore_fini(dev);
1848 free_priv:
1849         kfree(dev_priv);
1850         return ret;
1851 }
1852
1853 int i915_driver_unload(struct drm_device *dev)
1854 {
1855         struct drm_i915_private *dev_priv = dev->dev_private;
1856         int ret;
1857
1858         ret = i915_gem_suspend(dev);
1859         if (ret) {
1860                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1861                 return ret;
1862         }
1863
1864         intel_fini_runtime_pm(dev_priv);
1865
1866         intel_gpu_ips_teardown();
1867
1868         /* The i915.ko module is still not prepared to be loaded when
1869          * the power well is not enabled, so just enable it in case
1870          * we're going to unload/reload. */
1871         intel_display_set_init_power(dev_priv, true);
1872         intel_power_domains_remove(dev_priv);
1873
1874 #if 0
1875         i915_teardown_sysfs(dev);
1876
1877         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1878         unregister_shrinker(&dev_priv->mm.shrinker);
1879
1880         io_mapping_free(dev_priv->gtt.mappable);
1881 #endif
1882         arch_phys_wc_del(dev_priv->gtt.mtrr);
1883
1884 #if 0
1885         acpi_video_unregister();
1886 #endif
1887
1888         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1889                 intel_fbdev_fini(dev);
1890                 intel_modeset_cleanup(dev);
1891 #if 0
1892                 cancel_work_sync(&dev_priv->console_resume_work);
1893 #endif
1894
1895                 /*
1896                  * free the memory space allocated for the child device
1897                  * config parsed from VBT
1898                  */
1899                 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1900                         kfree(dev_priv->vbt.child_dev);
1901                         dev_priv->vbt.child_dev = NULL;
1902                         dev_priv->vbt.child_dev_num = 0;
1903                 }
1904
1905         }
1906
1907         /* Free error state after interrupts are fully disabled. */
1908         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1909         cancel_work_sync(&dev_priv->gpu_error.work);
1910 #if 0
1911         i915_destroy_error_state(dev);
1912 #endif
1913
1914         intel_opregion_fini(dev);
1915
1916         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1917                 /* Flush any outstanding unpin_work. */
1918                 flush_workqueue(dev_priv->wq);
1919
1920                 mutex_lock(&dev->struct_mutex);
1921                 i915_gem_cleanup_ringbuffer(dev);
1922                 i915_gem_context_fini(dev);
1923                 WARN_ON(dev_priv->mm.aliasing_ppgtt);
1924                 mutex_unlock(&dev->struct_mutex);
1925 #if 0
1926                 i915_gem_cleanup_stolen(dev);
1927 #endif
1928
1929                 if (!I915_NEED_GFX_HWS(dev))
1930                         i915_free_hws(dev);
1931         }
1932
1933         WARN_ON(!list_empty(&dev_priv->vm_list));
1934
1935         drm_vblank_cleanup(dev);
1936
1937         intel_teardown_gmbus(dev);
1938         intel_teardown_mchbar(dev);
1939
1940         bus_generic_detach(dev->dev);
1941         drm_rmmap(dev, dev_priv->mmio_map);
1942
1943         destroy_workqueue(dev_priv->dp_wq);
1944         destroy_workqueue(dev_priv->wq);
1945         pm_qos_remove_request(&dev_priv->pm_qos);
1946
1947         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
1948
1949         intel_uncore_fini(dev);
1950 #if 0
1951         if (dev_priv->regs != NULL)
1952                 pci_iounmap(dev->pdev, dev_priv->regs);
1953 #endif
1954
1955         pci_dev_put(dev_priv->bridge_dev);
1956         kfree(dev_priv);
1957
1958         return 0;
1959 }
1960
1961 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1962 {
1963         int ret;
1964
1965         ret = i915_gem_open(dev, file);
1966         if (ret)
1967                 return ret;
1968
1969         return 0;
1970 }
1971
1972 /**
1973  * i915_driver_lastclose - clean up after all DRM clients have exited
1974  * @dev: DRM device
1975  *
1976  * Take care of cleaning up after all DRM clients have exited.  In the
1977  * mode setting case, we want to restore the kernel's initial mode (just
1978  * in case the last client left us in a bad state).
1979  *
1980  * Additionally, in the non-mode setting case, we'll tear down the GTT
1981  * and DMA structures, since the kernel won't be using them, and clea
1982  * up any GEM state.
1983  */
1984 void i915_driver_lastclose(struct drm_device *dev)
1985 {
1986         struct drm_i915_private *dev_priv = dev->dev_private;
1987
1988         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1989          * goes right around and calls lastclose. Check for this and don't clean
1990          * up anything. */
1991         if (!dev_priv)
1992                 return;
1993
1994         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1995 #if 0
1996                 intel_fbdev_restore_mode(dev);
1997                 vga_switcheroo_process_delayed_switch();
1998 #endif
1999                 return;
2000         }
2001
2002         i915_gem_lastclose(dev);
2003
2004         i915_dma_cleanup(dev);
2005 }
2006
2007 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
2008 {
2009         mutex_lock(&dev->struct_mutex);
2010         i915_gem_context_close(dev, file);
2011         i915_gem_release(dev, file);
2012         mutex_unlock(&dev->struct_mutex);
2013 }
2014
2015 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2016 {
2017         struct drm_i915_file_private *file_priv = file->driver_priv;
2018
2019         if (file_priv && file_priv->bsd_ring)
2020                 file_priv->bsd_ring = NULL;
2021         kfree(file_priv);
2022 }
2023
2024 const struct drm_ioctl_desc i915_ioctls[] = {
2025         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2026         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2027         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2028         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2029         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2030         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2031         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2032         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2033         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2034         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2035         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2036         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2037         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2038         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2039         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2040         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2041         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2042         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2043         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2044         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2045         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2046         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2047         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2048         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
2049         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
2050         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2051         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2052         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2053         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2054         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2055         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2056         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2057         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2058         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2059         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2060         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2061         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2062         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2063         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2064         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2065         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2066         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2067         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2068         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2069         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
2070         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
2071         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
2072         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2073         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2074 #if 0
2075         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2076 #endif
2077 };
2078
2079 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
2080
2081 /*
2082  * This is really ugly: Because old userspace abused the linux agp interface to
2083  * manage the gtt, we need to claim that all intel devices are agp.  For
2084  * otherwise the drm core refuses to initialize the agp support code.
2085  */
2086 int i915_driver_device_is_agp(struct drm_device *dev)
2087 {
2088         return 1;
2089 }