sys/dev/netif/wx/if_wx.c

   1 /* $FreeBSD: src/sys/pci/if_wx.c,v 1.5.2.12 2003/03/05 18:42:34 njl Exp $ */
   2 /* $DragonFly: src/sys/dev/netif/wx/Attic/if_wx.c,v 1.10 2004/07/02 17:42:20 joerg Exp $ */
   3 /*
   4  * Principal Author: Matthew Jacob <mjacob@feral.com>
   5  * Copyright (c) 1999, 2001 by Traakan Software
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice unmodified, this list of conditions, and the following
  13  *    disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * Additional Copyright (c) 2001 by Parag Patel
  31  * under same licence for MII PHY code.
  32  */
  33
  34 /*
  35  * Intel Gigabit Ethernet (82452/82453) Driver.
  36  * Inspired by fxp driver by David Greenman for FreeBSD, and by
  37  * Bill Paul's work in other FreeBSD network drivers.
  38  */
  39
  40 /*
  41  * Many bug fixes gratefully acknowledged from:
  42  *
  43  *      The folks at Sitara Networks
  44  */
  45
  46 /*
  47  * Options
  48  */
  49
  50 /*
  51  * Use only every other 16 byte receive descriptor, leaving the ones
  52  * in between empty. This card is most efficient at reading/writing
  53  * 32 byte cache lines, so avoid all the (not working for early rev
  54  * cards) MWI and/or READ/MODIFY/WRITE cycles updating one descriptor
  55  * would have you do.
  56  *
  57  * This isn't debugged yet.
  58  */
  59 /* #define      PADDED_CELL     1 */
  60
  61 /*
  62  * Since the includes are a mess, they'll all be in if_wxvar.h
  63  */
  64
  65 #include "if_wxvar.h"
  66
  67 #ifdef __alpha__
  68 #undef vtophys
  69 #define vtophys(va)     alpha_XXX_dmamap((vm_offset_t)(va))
  70 #endif /* __alpha__ */
  71
  72 /*
  73  * Function Prototpes, yadda yadda...
  74  */
  75
  76 static int wx_intr(void *);
  77 static void wx_handle_link_intr(wx_softc_t *);
  78 static void wx_check_link(wx_softc_t *);
  79 static void wx_handle_rxint(wx_softc_t *);
  80 static void wx_gc(wx_softc_t *);
  81 static void wx_start(struct ifnet *);
  82 static int wx_ioctl(struct ifnet *, IOCTL_CMD_TYPE, caddr_t, struct ucred *);
  83 static int wx_ifmedia_upd(struct ifnet *);
  84 static void wx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  85 static int wx_init(void *);
  86 static void wx_hw_stop(wx_softc_t *);
  87 static void wx_set_addr(wx_softc_t *, int, u_int8_t *);
  88 static int wx_hw_initialize(wx_softc_t *);
  89 static void wx_stop(wx_softc_t *);
  90 static void wx_txwatchdog(struct ifnet *);
  91 static int wx_get_rbuf(wx_softc_t *, rxpkt_t *);
  92 static void wx_rxdma_map(wx_softc_t *, rxpkt_t *, struct mbuf *);
  93
  94 static INLINE void wx_eeprom_raise_clk(wx_softc_t *, u_int32_t);
  95 static INLINE void wx_eeprom_lower_clk(wx_softc_t *, u_int32_t);
  96 static INLINE void wx_eeprom_sobits(wx_softc_t *, u_int16_t, u_int16_t);
  97 static INLINE u_int16_t wx_eeprom_sibits(wx_softc_t *);
  98 static INLINE void wx_eeprom_cleanup(wx_softc_t *);
  99 static INLINE u_int16_t wx_read_eeprom_word(wx_softc_t *, int);
 100 static void wx_read_eeprom(wx_softc_t *, u_int16_t *, int, int);
 101
 102 static int wx_attach_common(wx_softc_t *);
 103 static void wx_watchdog(void *);
 104
 105 static INLINE void wx_mwi_whackon(wx_softc_t *);
 106 static INLINE void wx_mwi_unwhack(wx_softc_t *);
 107 static int wx_dring_setup(wx_softc_t *);
 108 static void wx_dring_teardown(wx_softc_t *);
 109
 110 static int wx_attach_phy(wx_softc_t *);
 111 static int wx_miibus_readreg(void *, int, int);
 112 static int wx_miibus_writereg(void *, int, int, int);
 113 static void wx_miibus_statchg(void *);
 114 static void wx_miibus_mediainit(void *);
 115
 116 static u_int32_t wx_mii_shift_in(wx_softc_t *);
 117 static void wx_mii_shift_out(wx_softc_t *, u_int32_t, u_int32_t);
 118
 119 #define WX_DISABLE_INT(sc)      WRITE_CSR(sc, WXREG_IMCLR, WXDISABLE)
 120 #define WX_ENABLE_INT(sc)       WRITE_CSR(sc, WXREG_IMASK, sc->wx_ienable)
 121
 122 /*
 123  * Until we do a bit more work, we can get no bigger than MCLBYTES
 124  */
 125 #if     0
 126 #define WX_MAXMTU       (WX_MAX_PKT_SIZE_JUMBO - sizeof (struct ether_header))
 127 #else
 128 #define WX_MAXMTU       (MCLBYTES - sizeof (struct ether_header))
 129 #endif
 130
 131 #define DPRINTF(sc, x)  if (sc->wx_debug) printf x
 132 #define IPRINTF(sc, x)  if (sc->wx_verbose) printf x
 133
 134 static const char ldn[] = "%s: link down\n";
 135 static const char lup[] = "%s: link up\n";
 136 static const char sqe[] = "%s: receive sequence error\n";
 137 static const char ane[] = "%s: /C/ ordered sets seen- enabling ANE\n";
 138 static const char inane[] = "%s: no /C/ ordered sets seen- disabling ANE\n";
 139
 140 static int wx_txint_delay = 5000;       /* ~5ms */
 141 TUNABLE_INT("hw.wx.txint_delay", &wx_txint_delay);
 142
 143 SYSCTL_NODE(_hw, OID_AUTO, wx, CTLFLAG_RD, 0, "WX driver parameters");
 144 SYSCTL_INT(_hw_wx, OID_AUTO, txint_delay, CTLFLAG_RW,
 145         &wx_txint_delay, 0, "");
 146 static int wx_dump_stats = -1;
 147 SYSCTL_INT(_hw_wx, OID_AUTO, dump_stats, CTLFLAG_RW,
 148         &wx_dump_stats, 0, "");
 149 static int wx_clr_stats = -1;
 150 SYSCTL_INT(_hw_wx, OID_AUTO, clear_stats, CTLFLAG_RW,
 151         &wx_clr_stats, 0, "");
 152
 153 /*
 154  * Program multicast addresses.
 155  *
 156  * This function must be called at splimp, but it may sleep.
 157  */
 158 static int
 159 wx_mc_setup(wx_softc_t *sc)
 160 {
 161         struct ifnet *ifp = &sc->wx_if;
 162         struct ifmultiaddr *ifma;
 163
 164         /*
 165          * XXX: drain TX queue
 166          */
 167         if (sc->tactive) {
 168                 return (EBUSY);
 169         }
 170
 171         wx_stop(sc);
 172
 173         if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) {
 174                 sc->all_mcasts = 1;
 175                 return (wx_init(sc));
 176         }
 177
 178         sc->wx_nmca = 0;
 179         for (ifma = ifp->if_multiaddrs.lh_first, sc->wx_nmca = 0;
 180             ifma != NULL; ifma = ifma->ifma_link.le_next) {
 181
 182                 if (ifma->ifma_addr->sa_family != AF_LINK) {
 183                         continue;
 184                 }
 185                 if (sc->wx_nmca >= WX_RAL_TAB_SIZE-1) {
 186                         sc->wx_nmca = 0;
 187                         sc->all_mcasts = 1;
 188                         break;
 189                 }
 190                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 191                     (void *) &sc->wx_mcaddr[sc->wx_nmca++][0], 6);
 192         }
 193         return (wx_init(sc));
 194 }
 195
 196 /*
 197  * Return identification string if this is device is ours.
 198  */
 199 static int
 200 wx_probe(device_t dev)
 201 {
 202         if (pci_get_vendor(dev) != WX_VENDOR_INTEL) {
 203                 return (ENXIO);
 204         }
 205         switch (pci_get_device(dev)) {
 206         case WX_PRODUCT_82452:
 207                 device_set_desc(dev, "Intel PRO/1000 Gigabit (WISEMAN)");
 208                 break;
 209         case WX_PRODUCT_LIVENGOOD:
 210                 device_set_desc(dev, "Intel PRO/1000 (LIVENGOOD)");
 211                 break;
 212         case WX_PRODUCT_82452_SC:
 213                 device_set_desc(dev, "Intel PRO/1000 F Gigabit Ethernet");
 214                 break;
 215         case WX_PRODUCT_82543:
 216                 device_set_desc(dev, "Intel PRO/1000 T Gigabit Ethernet");
 217                 break;
 218         default:
 219                 return (ENXIO);
 220         }
 221         return (0);
 222 }
 223
 224 static int
 225 wx_attach(device_t dev)
 226 {
 227         int error = 0;
 228         wx_softc_t *sc = device_get_softc(dev);
 229         struct ifnet *ifp;
 230         u_int32_t val;
 231         int rid;
 232
 233         bzero(sc, sizeof (wx_softc_t));
 234
 235         callout_handle_init(&sc->w.sch);
 236         sc->w.dev = dev;
 237
 238         if (bootverbose)
 239                 sc->wx_verbose = 1;
 240
 241         if (getenv_int ("wx_debug", &rid)) {
 242                 if (rid & (1 << device_get_unit(dev))) {
 243                         sc->wx_debug = 1;
 244                 }
 245         }
 246
 247         if (getenv_int("wx_no_ilos", &rid)) {
 248                 if (rid & (1 << device_get_unit(dev))) {
 249                         sc->wx_no_ilos = 1;
 250                 }
 251         }
 252
 253         if (getenv_int("wx_ilos", &rid)) {
 254                 if (rid & (1 << device_get_unit(dev))) {
 255                         sc->wx_ilos = 1;
 256                 }
 257         }
 258
 259         if (getenv_int("wx_no_flow", &rid)) {
 260                 if (rid & (1 << device_get_unit(dev))) {
 261                         sc->wx_no_flow = 1;
 262                 }
 263         }
 264
 265 #ifdef  SMPNG
 266         mtx_init(&sc->wx_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
 267 #endif
 268         WX_LOCK(sc);
 269         /*
 270          * get revision && id...
 271          */
 272         sc->wx_idnrev = (pci_get_device(dev) << 16) | (pci_get_revid(dev));
 273
 274         /*
 275          * Enable bus mastering, make sure that the cache line size is right.
 276          */
 277         pci_enable_busmaster(dev);
 278         pci_enable_io(dev, SYS_RES_MEMORY);
 279         val = pci_read_config(dev, PCIR_COMMAND, 4);
 280         if ((val & PCIM_CMD_MEMEN) == 0) {
 281                 device_printf(dev, "failed to enable memory mapping\n");
 282                 error = ENXIO;
 283                 goto out;
 284         }
 285
 286         /*
 287          * Let the BIOS do it's job- but check for sanity.
 288          */
 289         val = pci_read_config(dev, PCIR_CACHELNSZ, 1);
 290         if (val < 4 || val > 32) {
 291                 pci_write_config(dev, PCIR_CACHELNSZ, 8, 1);
 292         }
 293
 294         /*
 295          * Map control/status registers.
 296          */
 297         rid = WX_MMBA;
 298         sc->w.mem = bus_alloc_resource(dev, SYS_RES_MEMORY,
 299             &rid, 0, ~0, 1, RF_ACTIVE);
 300         if (!sc->w.mem) {
 301                 device_printf(dev, "could not map memory\n");
 302                 error = ENXIO;
 303                 goto out;
 304         }
 305         sc->w.st = rman_get_bustag(sc->w.mem);
 306         sc->w.sh = rman_get_bushandle(sc->w.mem);
 307
 308         rid = 0;
 309         sc->w.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 310             &rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 311         if (sc->w.irq == NULL) {
 312                 device_printf(dev, "could not map interrupt\n");
 313                 error = ENXIO;
 314                 goto out;
 315         }
 316         error = bus_setup_intr(dev, sc->w.irq, INTR_TYPE_NET,
 317             (void (*)(void *))wx_intr, sc, &sc->w.ih);
 318         if (error) {
 319                 device_printf(dev, "could not setup irq\n");
 320                 goto out;
 321         }
 322         (void) snprintf(sc->wx_name, sizeof (sc->wx_name) - 1, "wx%d",
 323             device_get_unit(dev));
 324         if (wx_attach_common(sc)) {
 325                 bus_teardown_intr(dev, sc->w.irq, sc->w.ih);
 326                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->w.irq);
 327                 bus_release_resource(dev, SYS_RES_MEMORY, WX_MMBA, sc->w.mem);
 328                 error = ENXIO;
 329                 goto out;
 330         }
 331
 332         ifp = &sc->w.arpcom.ac_if;
 333         if_initname(ifp, "wx", device_get_unit(dev));
 334         ifp->if_mtu = ETHERMTU; /* we always start at ETHERMTU size */
 335         ifp->if_output = ether_output;
 336         ifp->if_baudrate = 1000000000;
 337         ifp->if_init = (void (*)(void *))wx_init;
 338         ifp->if_softc = sc;
 339         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 340         ifp->if_ioctl = wx_ioctl;
 341         ifp->if_start = wx_start;
 342         ifp->if_watchdog = wx_txwatchdog;
 343         ifp->if_snd.ifq_maxlen = WX_MAX_TDESC - 1;
 344         ether_ifattach(ifp, sc->w.arpcom.ac_enaddr);
 345 out:
 346         WX_UNLOCK(sc);
 347         return (error);
 348 }
 349
 350 static int
 351 wx_attach_phy(wx_softc_t *sc)
 352 {
 353         if (mii_phy_probe(sc->w.dev, &sc->w.miibus, wx_ifmedia_upd,
 354             wx_ifmedia_sts)) {
 355                 printf("%s: no PHY probed!\n", sc->wx_name);
 356                 return (-1);
 357         }
 358         sc->wx_mii = 1;
 359         return 0;
 360 }
 361
 362 static int
 363 wx_detach(device_t dev)
 364 {
 365         wx_softc_t *sc = device_get_softc(dev);
 366
 367         WX_LOCK(sc);
 368         wx_stop(sc);
 369
 370         ether_ifdetach(&sc->w.arpcom.ac_if);
 371         if (sc->w.miibus) {
 372                 bus_generic_detach(dev);
 373                 device_delete_child(dev, sc->w.miibus);
 374         } else {
 375                 ifmedia_removeall(&sc->wx_media);
 376         }
 377         bus_teardown_intr(dev, sc->w.irq, sc->w.ih);
 378         bus_release_resource(dev, SYS_RES_IRQ, 0, sc->w.irq);
 379         bus_release_resource(dev, SYS_RES_MEMORY, WX_MMBA, sc->w.mem);
 380
 381         wx_dring_teardown(sc);
 382         if (sc->rbase) {
 383                 WXFREE(sc->rbase);
 384                 sc->rbase = NULL;
 385         }
 386         if (sc->tbase) {
 387                 WXFREE(sc->tbase);
 388                 sc->tbase = NULL;
 389         }
 390         WX_UNLOCK(sc);
 391 #ifdef  SMPNG
 392         mtx_destroy(&sc->wx_mtx);
 393 #endif
 394         return (0);
 395 }
 396
 397 static int
 398 wx_shutdown(device_t dev)
 399 {
 400         wx_hw_stop((wx_softc_t *) device_get_softc(dev));
 401         return (0);
 402 }
 403
 404 static INLINE void
 405 wx_mwi_whackon(wx_softc_t *sc)
 406 {
 407         sc->wx_cmdw = pci_read_config(sc->w.dev, PCIR_COMMAND, 2);
 408         pci_write_config(sc->w.dev, PCIR_COMMAND, sc->wx_cmdw & ~MWI, 2);
 409 }
 410
 411 static INLINE void
 412 wx_mwi_unwhack(wx_softc_t *sc)
 413 {
 414         if (sc->wx_cmdw & MWI) {
 415                 pci_write_config(sc->w.dev, PCIR_COMMAND, sc->wx_cmdw, 2);
 416         }
 417 }
 418
 419 static int
 420 wx_dring_setup(wx_softc_t *sc)
 421 {
 422         size_t len;
 423
 424         len = sizeof (wxrd_t) * WX_MAX_RDESC;
 425         sc->rdescriptors = (wxrd_t *)
 426             contigmalloc(len, M_DEVBUF, M_NOWAIT, 0, ~0, 4096, 0);
 427         if (sc->rdescriptors == NULL) {
 428                 printf("%s: could not allocate rcv descriptors\n", sc->wx_name);
 429                 return (-1);
 430         }
 431         if (((intptr_t)sc->rdescriptors) & 0xfff) {
 432                 contigfree(sc->rdescriptors, len, M_DEVBUF);
 433                 sc->rdescriptors = NULL;
 434                 printf("%s: rcv descriptors not 4KB aligned\n", sc->wx_name);
 435                 return (-1);
 436         }
 437         bzero(sc->rdescriptors, len);
 438
 439         len = sizeof (wxtd_t) * WX_MAX_TDESC;
 440         sc->tdescriptors = (wxtd_t *)
 441             contigmalloc(len, M_DEVBUF, M_NOWAIT, 0, ~0, 4096, 0);
 442         if (sc->tdescriptors == NULL) {
 443                 contigfree(sc->rdescriptors,
 444                     sizeof (wxrd_t) * WX_MAX_RDESC, M_DEVBUF);
 445                 sc->rdescriptors = NULL;
 446                 printf("%s: could not allocate xmt descriptors\n", sc->wx_name);
 447                 return (-1);
 448         }
 449         if (((intptr_t)sc->tdescriptors) & 0xfff) {
 450                 contigfree(sc->rdescriptors,
 451                     sizeof (wxrd_t) * WX_MAX_RDESC, M_DEVBUF);
 452                 contigfree(sc->tdescriptors, len, M_DEVBUF);
 453                 sc->rdescriptors = NULL;
 454                 sc->tdescriptors = NULL;
 455                 printf("%s: xmt descriptors not 4KB aligned\n", sc->wx_name);
 456                 return (-1);
 457         }
 458         bzero(sc->tdescriptors, len);
 459         return (0);
 460 }
 461
 462 static void
 463 wx_dring_teardown(wx_softc_t *sc)
 464 {
 465         if (sc->rdescriptors) {
 466                 contigfree(sc->rdescriptors,
 467                     sizeof (wxrd_t) * WX_MAX_RDESC, M_DEVBUF);
 468                 sc->rdescriptors = NULL;
 469         }
 470         if (sc->tdescriptors) {
 471                 contigfree(sc->tdescriptors,
 472                     sizeof (wxtd_t) * WX_MAX_TDESC, M_DEVBUF);
 473                 sc->tdescriptors = NULL;
 474         }
 475 }
 476
 477 static device_method_t wx_methods[] = {
 478         /* Device interface */
 479         DEVMETHOD(device_probe,         wx_probe),
 480         DEVMETHOD(device_attach,        wx_attach),
 481         DEVMETHOD(device_detach,        wx_detach),
 482         DEVMETHOD(device_shutdown,      wx_shutdown),
 483
 484         /* bus interface */
 485         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 486         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 487
 488         /* MII interface */
 489         DEVMETHOD(miibus_readreg,       wx_miibus_readreg),
 490         DEVMETHOD(miibus_writereg,      wx_miibus_writereg),
 491         DEVMETHOD(miibus_statchg,       wx_miibus_statchg),
 492         DEVMETHOD(miibus_mediainit,     wx_miibus_mediainit),
 493
 494         { 0, 0 }
 495 };
 496
 497 static driver_t wx_driver = {
 498         "wx", wx_methods, sizeof(wx_softc_t),
 499 };
 500 static devclass_t wx_devclass;
 501
 502 DECLARE_DUMMY_MODULE(if_wx);
 503 MODULE_DEPEND(if_wx, miibus, 1, 1, 1);
 504 DRIVER_MODULE(if_wx, pci, wx_driver, wx_devclass, 0, 0);
 505 DRIVER_MODULE(miibus, wx, miibus_driver, miibus_devclass, 0, 0);
 506
 507 /*
 508  * Do generic parts of attach. Our registers have been mapped
 509  * and our interrupt registered.
 510  */
 511 static int
 512 wx_attach_common(wx_softc_t *sc)
 513 {
 514         size_t len;
 515         u_int32_t tmp;
 516         int ll = 0;
 517
 518         /*
 519          * First, check for revision support.
 520          */
 521         if (sc->wx_idnrev < WX_WISEMAN_2_0) {
 522                 printf("%s: cannot support ID 0x%x, revision %d chips\n",
 523                     sc->wx_name, sc->wx_idnrev >> 16, sc->wx_idnrev & 0xffff);
 524                 return (ENXIO);
 525         }
 526
 527         /*
 528          * Second, reset the chip.
 529          */
 530         wx_hw_stop(sc);
 531
 532         /*
 533          * Third, validate our EEPROM.
 534          */
 535
 536         /* TBD */
 537
 538         /*
 539          * Fourth, read eeprom for our MAC address and other things.
 540          */
 541         wx_read_eeprom(sc, (u_int16_t *)sc->wx_enaddr, WX_EEPROM_MAC_OFF, 3);
 542
 543         /*
 544          * Fifth, establish some adapter parameters.
 545          */
 546         sc->wx_dcr = 0;
 547
 548         if (IS_LIVENGOOD_CU(sc)) {
 549
 550                 /* settings to talk to PHY */
 551                 sc->wx_dcr |= WXDCR_FRCSPD | WXDCR_FRCDPX | WXDCR_SLU;
 552                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
 553
 554                 /*
 555                  * Raise the PHY's reset line to make it operational.
 556                  */
 557                 tmp = READ_CSR(sc, WXREG_EXCT);
 558                 tmp |= WXPHY_RESET_DIR4;
 559                 WRITE_CSR(sc, WXREG_EXCT, tmp);
 560                 DELAY(20*1000);
 561
 562                 tmp = READ_CSR(sc, WXREG_EXCT);
 563                 tmp &= ~WXPHY_RESET4;
 564                 WRITE_CSR(sc, WXREG_EXCT, tmp);
 565                 DELAY(20*1000);
 566
 567                 tmp = READ_CSR(sc, WXREG_EXCT);
 568                 tmp |= WXPHY_RESET4;
 569                 WRITE_CSR(sc, WXREG_EXCT, tmp);
 570                 DELAY(20*1000);
 571
 572                 if (wx_attach_phy(sc)) {
 573                         goto fail;
 574                 }
 575         } else {
 576                 ifmedia_init(&sc->wx_media, IFM_IMASK,
 577                     wx_ifmedia_upd, wx_ifmedia_sts);
 578
 579                 ifmedia_add(&sc->wx_media, IFM_ETHER|IFM_1000_SX, 0, NULL);
 580                 ifmedia_add(&sc->wx_media,
 581                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
 582                 ifmedia_set(&sc->wx_media, IFM_ETHER|IFM_1000_SX|IFM_FDX);
 583
 584                 sc->wx_media.ifm_media = sc->wx_media.ifm_cur->ifm_media;
 585         }
 586
 587         /*
 588          * Sixth, establish a default device control register word.
 589          */
 590         ll += 1;
 591         if (sc->wx_cfg1 & WX_EEPROM_CTLR1_FD)
 592                 sc->wx_dcr |= WXDCR_FD;
 593         if (sc->wx_cfg1 & WX_EEPROM_CTLR1_ILOS)
 594                 sc->wx_dcr |= WXDCR_ILOS;
 595
 596         tmp = (sc->wx_cfg1 >> WX_EEPROM_CTLR1_SWDPIO_SHIFT) & WXDCR_SWDPIO_MASK;
 597         sc->wx_dcr |= (tmp << WXDCR_SWDPIO_SHIFT);
 598
 599         if (sc->wx_no_ilos)
 600                 sc->wx_dcr &= ~WXDCR_ILOS;
 601         if (sc->wx_ilos)
 602                 sc->wx_dcr |= WXDCR_ILOS;
 603         if (sc->wx_no_flow == 0)
 604                 sc->wx_dcr |= WXDCR_RFCE | WXDCR_TFCE;
 605
 606         /*
 607          * Seventh, allocate various sw structures...
 608          */
 609         len = sizeof (rxpkt_t) * WX_MAX_RDESC;
 610         sc->rbase = (rxpkt_t *) WXMALLOC(len);
 611         if (sc->rbase == NULL) {
 612                 goto fail;
 613         }
 614         bzero(sc->rbase, len);
 615         ll += 1;
 616
 617         len = sizeof (txpkt_t) * WX_MAX_TDESC;
 618         sc->tbase = (txpkt_t *) WXMALLOC(len);
 619         if (sc->tbase == NULL) {
 620                 goto fail;
 621         }
 622         bzero(sc->tbase, len);
 623         ll += 1;
 624
 625         /*
 626          * Eighth, allocate and dma map (platform dependent) descriptor rings.
 627          * They have to be aligned on a 4KB boundary.
 628          */
 629         if (wx_dring_setup(sc) == 0) {
 630                 return (0);
 631         }
 632
 633 fail:
 634         printf("%s: failed to do common attach (%d)\n", sc->wx_name, ll);
 635         wx_dring_teardown(sc);
 636         if (sc->rbase) {
 637                 WXFREE(sc->rbase);
 638                 sc->rbase = NULL;
 639         }
 640         if (sc->tbase) {
 641                 WXFREE(sc->tbase);
 642                 sc->tbase = NULL;
 643         }
 644         return (ENOMEM);
 645 }
 646
 647 /*
 648  * EEPROM functions.
 649  */
 650
 651 static INLINE void
 652 wx_eeprom_raise_clk(wx_softc_t *sc, u_int32_t regval)
 653 {
 654         WRITE_CSR(sc, WXREG_EECDR, regval | WXEECD_SK);
 655         DELAY(50);
 656 }
 657
 658 static INLINE void
 659 wx_eeprom_lower_clk(wx_softc_t *sc, u_int32_t regval)
 660 {
 661         WRITE_CSR(sc, WXREG_EECDR, regval & ~WXEECD_SK);
 662         DELAY(50);
 663 }
 664
 665 static INLINE void
 666 wx_eeprom_sobits(wx_softc_t *sc, u_int16_t data, u_int16_t count)
 667 {
 668         u_int32_t regval, mask;
 669
 670         mask = 1 << (count - 1);
 671         regval = READ_CSR(sc, WXREG_EECDR) & ~(WXEECD_DI|WXEECD_DO);
 672
 673         do {
 674                 if (data & mask)
 675                         regval |= WXEECD_DI;
 676                 else
 677                         regval &= ~WXEECD_DI;
 678                 WRITE_CSR(sc, WXREG_EECDR, regval); DELAY(50);
 679                 wx_eeprom_raise_clk(sc, regval);
 680                 wx_eeprom_lower_clk(sc, regval);
 681                 mask >>= 1;
 682         } while (mask != 0);
 683         WRITE_CSR(sc, WXREG_EECDR, regval & ~WXEECD_DI);
 684 }
 685
 686 static INLINE u_int16_t
 687 wx_eeprom_sibits(wx_softc_t *sc)
 688 {
 689         unsigned int regval, i;
 690         u_int16_t data;
 691
 692         data = 0;
 693         regval = READ_CSR(sc, WXREG_EECDR) & ~(WXEECD_DI|WXEECD_DO);
 694         for (i = 0; i != 16; i++) {
 695                 data <<= 1;
 696                 wx_eeprom_raise_clk(sc, regval);
 697                 regval = READ_CSR(sc, WXREG_EECDR) & ~WXEECD_DI;
 698                 if (regval & WXEECD_DO) {
 699                         data |= 1;
 700                 }
 701                 wx_eeprom_lower_clk(sc, regval);
 702         }
 703         return (data);
 704 }
 705
 706 static INLINE void
 707 wx_eeprom_cleanup(wx_softc_t *sc)
 708 {
 709         u_int32_t regval;
 710         regval = READ_CSR(sc, WXREG_EECDR) & ~(WXEECD_DI|WXEECD_CS);
 711         WRITE_CSR(sc, WXREG_EECDR, regval); DELAY(50);
 712         wx_eeprom_raise_clk(sc, regval);
 713         wx_eeprom_lower_clk(sc, regval);
 714 }
 715
 716 static u_int16_t INLINE
 717 wx_read_eeprom_word(wx_softc_t *sc, int offset)
 718 {
 719         u_int16_t       data;
 720         WRITE_CSR(sc, WXREG_EECDR, WXEECD_CS);
 721         wx_eeprom_sobits(sc, EEPROM_READ_OPCODE, 3);
 722         wx_eeprom_sobits(sc, offset, 6);
 723         data = wx_eeprom_sibits(sc);
 724         wx_eeprom_cleanup(sc);
 725         return (data);
 726 }
 727
 728 static void
 729 wx_read_eeprom(wx_softc_t *sc, u_int16_t *data, int offset, int words)
 730 {
 731         int i;
 732         for (i = 0; i < words; i++) {
 733                 *data++ = wx_read_eeprom_word(sc, offset++);
 734         }
 735         sc->wx_cfg1 = wx_read_eeprom_word(sc, WX_EEPROM_CTLR1_OFF);
 736 }
 737
 738 /*
 739  * Start packet transmission on the interface.
 740  */
 741
 742 static void
 743 wx_start(struct ifnet *ifp)
 744 {
 745         wx_softc_t *sc = SOFTC_IFP(ifp);
 746         u_int16_t widx = WX_MAX_TDESC, cidx, nactv;
 747
 748         WX_LOCK(sc);
 749         DPRINTF(sc, ("%s: wx_start\n", sc->wx_name));
 750         nactv = sc->tactive;
 751         while (nactv < WX_MAX_TDESC - 1) {
 752                 int ndesc, plen;
 753                 int gctried = 0;
 754                 struct mbuf *m, *mb_head;
 755
 756                 IF_DEQUEUE(&ifp->if_snd, mb_head);
 757                 if (mb_head == NULL) {
 758                         break;
 759                 }
 760                 sc->wx_xmitwanted++;
 761
 762                 /*
 763                  * If we have a packet less than ethermin, pad it out.
 764                  */
 765                 if (mb_head->m_pkthdr.len < WX_MIN_RPKT_SIZE) {
 766                         if (mb_head->m_next == NULL) {
 767                                 mb_head->m_len = WX_MIN_RPKT_SIZE;
 768                         } else {
 769                                 MGETHDR(m, MB_DONTWAIT, MT_DATA);
 770                                 if (m == NULL) {
 771                                         m_freem(mb_head);
 772                                         break;
 773                                 }
 774                                 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
 775                                     mtod(m, caddr_t));
 776                                 m->m_pkthdr.len = m->m_len = WX_MIN_RPKT_SIZE;
 777                                 bzero(mtod(m, char *) + mb_head->m_pkthdr.len,
 778                                      WX_MIN_RPKT_SIZE - mb_head->m_pkthdr.len);
 779                                 sc->wx_xmitpullup++;
 780                                 m_freem(mb_head);
 781                                 mb_head = m;
 782                         }
 783                 }
 784         again:
 785                 cidx = sc->tnxtfree;
 786                 nactv = sc->tactive;
 787
 788
 789                 /*
 790                  * Go through each of the mbufs in the chain and initialize
 791                  * the transmit buffer descriptors with the physical address
 792                  * and size of that mbuf. If we have a length less than our
 793                  * minimum transmit size, we bail (to do a pullup). If we run
 794                  * out of descriptors, we also bail and try and do a pullup.
 795                  */
 796                 for (plen = ndesc = 0, m = mb_head; m != NULL; m = m->m_next) {
 797                         vm_offset_t vptr;
 798                         wxtd_t *td;
 799
 800                         /*
 801                          * If this mbuf has no data, skip it.
 802                          */
 803                         if (m->m_len == 0) {
 804                                 continue;
 805                         }
 806
 807                         /*
 808                          * This appears to be a bogus check the PRO1000T.
 809                          * I think they meant that the minimum packet size
 810                          * is in fact WX_MIN_XPKT_SIZE (all data loaded)
 811                          */
 812 #if     0
 813                         /*
 814                          * If this mbuf is too small for the chip's minimum,
 815                          * break out to cluster it.
 816                          */
 817                         if (m->m_len < WX_MIN_XPKT_SIZE) {
 818                                 sc->wx_xmitrunt++;
 819                                 break;
 820                         }
 821 #endif
 822
 823                         /*
 824                          * Do we have a descriptor available for this mbuf?
 825                          */
 826                         if (++nactv == WX_MAX_TDESC) {
 827                                 if (gctried++ == 0) {
 828                                         sc->wx_xmitgc++;
 829                                         wx_gc(sc);
 830                                         goto again;
 831                                 }
 832                                 break;
 833                         }
 834                         sc->tbase[cidx].dptr = m;
 835                         td = &sc->tdescriptors[cidx];
 836                         td->length = m->m_len;
 837                         plen += m->m_len;
 838
 839                         vptr = mtod(m, vm_offset_t);
 840                         td->address.highpart = 0;
 841                         td->address.lowpart = vtophys(vptr);
 842
 843                         td->cso = 0;
 844                         td->status = 0;
 845                         td->special = 0;
 846                         td->cmd = 0;
 847                         td->css = 0;
 848
 849                         if (sc->wx_debug) {
 850                                 printf("%s: XMIT[%d] %p vptr %lx (length %d "
 851                                     "DMA addr %x) idx %d\n", sc->wx_name,
 852                                     ndesc, m, (long) vptr, td->length,
 853                                     td->address.lowpart, cidx);
 854                         }
 855                         ndesc++;
 856                         cidx = T_NXT_IDX(cidx);
 857                 }
 858
 859                 /*
 860                  * If we get here and m is NULL, we can send
 861                  * the the packet chain described by mb_head.
 862                  */
 863                 if (m == NULL) {
 864                         /*
 865                          * Mark the last descriptor with EOP and tell the
 866                          * chip to insert a final checksum.
 867                          */
 868                         wxtd_t *td = &sc->tdescriptors[T_PREV_IDX(cidx)];
 869                         td->cmd = TXCMD_EOP|TXCMD_IFCS;
 870                         /*
 871                          * Set up a delayed interrupt when this packet
 872                          * is sent and the descriptor written back.
 873                          * Additional packets completing will cause
 874                          * interrupt to be delayed further. Therefore,
 875                          * after the *last* packet is sent, after the delay
 876                          * period in TIDV, an interrupt will be generated
 877                          * which will cause us to garbage collect.
 878                          */
 879                         td->cmd |= TXCMD_IDE|TXCMD_RPS;
 880
 881                         /*
 882                          * Don't xmit odd length packets.
 883                          * We're okay with bumping things
 884                          * up as long as our mbuf allocation
 885                          * is always larger than our MTU
 886                          * by a comfortable amount.
 887                          *
 888                          * Yes, it's a hole to run past the end
 889                          * of a packet.
 890                          */
 891                         if (plen & 0x1) {
 892                                 sc->wx_oddpkt++;
 893                                 td->length++;
 894                         }
 895
 896                         sc->tbase[sc->tnxtfree].sidx = sc->tnxtfree;
 897                         sc->tbase[sc->tnxtfree].eidx = cidx;
 898                         sc->tbase[sc->tnxtfree].next = NULL;
 899                         if (sc->tbsyf) {
 900                                 sc->tbsyl->next = &sc->tbase[sc->tnxtfree];
 901                         } else {
 902                                 sc->tbsyf = &sc->tbase[sc->tnxtfree];
 903                         }
 904                         sc->tbsyl = &sc->tbase[sc->tnxtfree];
 905                         sc->tnxtfree = cidx;
 906                         sc->tactive = nactv;
 907                         ifp->if_timer = 10;
 908                         if (ifp->if_bpf)
 909                                 bpf_mtap(WX_BPFTAP_ARG(ifp), mb_head);
 910                         /* defer xmit until we've got them all */
 911                         widx = cidx;
 912                         continue;
 913                 }
 914
 915                 /*
 916                  * Otherwise, we couldn't send this packet for some reason.
 917                  *
 918                  * If don't have a descriptor available, and this is a
 919                  * single mbuf packet, freeze output so that later we
 920                  * can restart when we have more room. Otherwise, we'll
 921                  * try and cluster the request. We've already tried to
 922                  * garbage collect completed descriptors.
 923                  */
 924                 if (nactv == WX_MAX_TDESC && mb_head->m_next == NULL) {
 925                         sc->wx_xmitputback++;
 926                         ifp->if_flags |= IFF_OACTIVE;
 927                         IF_PREPEND(&ifp->if_snd, mb_head);
 928                         break;
 929                 }
 930
 931                 /*
 932                  * Otherwise, it's either a fragment length somewhere in the
 933                  * chain that isn't at least WX_MIN_XPKT_SIZE in length or
 934                  * the number of fragments exceeds the number of descriptors
 935                  * available.
 936                  *
 937                  * We could try a variety of strategies here- if this is
 938                  * a length problem for single mbuf packet or a length problem
 939                  * for the last mbuf in a chain (we could just try and adjust
 940                  * it), but it's just simpler to try and cluster it.
 941                  */
 942                 MGETHDR(m, MB_DONTWAIT, MT_DATA);
 943                 if (m == NULL) {
 944                         m_freem(mb_head);
 945                         break;
 946                 }
 947                 MCLGET(m, MB_DONTWAIT);
 948                 if ((m->m_flags & M_EXT) == 0) {
 949                         m_freem(m);
 950                         m_freem(mb_head);
 951                         break;
 952                 }
 953                 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, mtod(m, caddr_t));
 954                 m->m_pkthdr.len = m->m_len = mb_head->m_pkthdr.len;
 955                 m_freem(mb_head);
 956                 mb_head = m;
 957                 sc->wx_xmitcluster++;
 958                 goto again;
 959         }
 960
 961         if (widx < WX_MAX_TDESC) {
 962                 if (IS_WISEMAN(sc)) {
 963                         WRITE_CSR(sc, WXREG_TDT, widx);
 964                 } else {
 965                         WRITE_CSR(sc, WXREG_TDT_LIVENGOOD, widx);
 966                 }
 967         }
 968
 969         if (sc->tactive == WX_MAX_TDESC - 1) {
 970                 sc->wx_xmitgc++;
 971                 wx_gc(sc);
 972                 if (sc->tactive >= WX_MAX_TDESC - 1) {
 973                         sc->wx_xmitblocked++;
 974                         ifp->if_flags |= IFF_OACTIVE;
 975                 }
 976         }
 977
 978         /* used SW LED to indicate transmission active */
 979         if (sc->tactive > 0 && sc->wx_mii) {
 980                 WRITE_CSR(sc, WXREG_DCR,
 981                     READ_CSR(sc, WXREG_DCR) | (WXDCR_SWDPIO0|WXDCR_SWDPIN0));
 982         }
 983         WX_UNLOCK(sc);
 984 }
 985
 986 /*
 987  * Process interface interrupts.
 988  */
 989 static int
 990 wx_intr(void *arg)
 991 {
 992         wx_softc_t *sc = arg;
 993         int claimed = 0;
 994
 995         WX_ILOCK(sc);
 996         /*
 997          * Read interrupt cause register. Reading it clears bits.
 998          */
 999         sc->wx_icr = READ_CSR(sc, WXREG_ICR);
1000         if (sc->wx_icr) {
1001                 claimed++;
1002                 WX_DISABLE_INT(sc);
1003                 sc->wx_intr++;
1004                 if (sc->wx_icr & (WXISR_LSC|WXISR_RXSEQ|WXISR_GPI_EN1)) {
1005                         sc->wx_linkintr++;
1006                         wx_handle_link_intr(sc);
1007                 }
1008                 wx_handle_rxint(sc);
1009                 if (sc->wx_icr & WXISR_TXDW) {
1010                         sc->wx_txqe++;
1011                         wx_gc(sc);
1012                 }
1013 #if     0
1014                 if (sc->wx_icr & WXISR_TXQE) {
1015                         sc->wx_txqe++;
1016                         wx_gc(sc);
1017                 }
1018 #endif
1019                 if (sc->wx_if.if_snd.ifq_head != NULL) {
1020                         wx_start(&sc->wx_if);
1021                 }
1022                 WX_ENABLE_INT(sc);
1023         }
1024         WX_IUNLK(sc);
1025         return (claimed);
1026 }
1027
1028 static void
1029 wx_handle_link_intr(wx_softc_t *sc)
1030 {
1031         u_int32_t txcw, rxcw, dcr, dsr;
1032
1033
1034         dcr = READ_CSR(sc, WXREG_DCR);
1035         DPRINTF(sc, ("%s: handle_link_intr: icr=%#x dcr=%#x\n",
1036             sc->wx_name, sc->wx_icr, dcr));
1037         if (sc->wx_mii) {
1038                 mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
1039                 mii_pollstat(mii);
1040                 if (mii->mii_media_status & IFM_ACTIVE) {
1041                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE) {
1042                                 IPRINTF(sc, (ldn, sc->wx_name));
1043                                 sc->linkup = 0;
1044                         } else {
1045                                 IPRINTF(sc, (lup, sc->wx_name));
1046                                 sc->linkup = 1;
1047                         }
1048                         WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1049                 } else if (sc->wx_icr & WXISR_RXSEQ) {
1050                         DPRINTF(sc, (sqe, sc->wx_name));
1051                 }
1052                 return;
1053         }
1054
1055         txcw = READ_CSR(sc, WXREG_XMIT_CFGW);
1056         rxcw = READ_CSR(sc, WXREG_RECV_CFGW);
1057         dsr = READ_CSR(sc, WXREG_DSR);
1058
1059         /*
1060          * If we have LOS or are now receiving Ordered Sets and are not
1061          * doing auto-negotiation, restore autonegotiation.
1062          */
1063
1064         if (((dcr & WXDCR_SWDPIN1) || (rxcw & WXRXCW_C)) &&
1065             ((txcw & WXTXCW_ANE) == 0)) {
1066                 DPRINTF(sc, (ane, sc->wx_name));
1067                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT);
1068                 sc->wx_dcr &= ~WXDCR_SLU;
1069                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1070                 sc->ane_failed = 0;
1071         }
1072
1073         if (sc->wx_icr & WXISR_LSC) {
1074                 if (READ_CSR(sc, WXREG_DSR) & WXDSR_LU) {
1075                         IPRINTF(sc, (lup, sc->wx_name));
1076                         sc->linkup = 1;
1077                         sc->wx_dcr |= (WXDCR_SWDPIO0|WXDCR_SWDPIN0);
1078                 } else {
1079                         IPRINTF(sc, (ldn, sc->wx_name));
1080                         sc->linkup = 0;
1081                         sc->wx_dcr &= ~(WXDCR_SWDPIO0|WXDCR_SWDPIN0);
1082                 }
1083                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1084         } else {
1085                 DPRINTF(sc, (sqe, sc->wx_name));
1086         }
1087 }
1088
1089 static void
1090 wx_check_link(wx_softc_t *sc)
1091 {
1092         u_int32_t rxcw, dcr, dsr;
1093
1094         if (sc->wx_mii) {
1095                 mii_pollstat(WX_MII_FROM_SOFTC(sc));
1096                 return;
1097         }
1098
1099         rxcw = READ_CSR(sc, WXREG_RECV_CFGW);
1100         dcr = READ_CSR(sc, WXREG_DCR);
1101         dsr = READ_CSR(sc, WXREG_DSR);
1102
1103         if ((dsr & WXDSR_LU) == 0 && (dcr & WXDCR_SWDPIN1) == 0 &&
1104             (rxcw & WXRXCW_C) == 0) {
1105                 if (sc->ane_failed == 0) {
1106                         sc->ane_failed = 1;
1107                         return;
1108                 }
1109                 DPRINTF(sc, (inane, sc->wx_name));
1110                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT & ~WXTXCW_ANE);
1111                 if (sc->wx_idnrev < WX_WISEMAN_2_1)
1112                         sc->wx_dcr &= ~WXDCR_TFCE;
1113                 sc->wx_dcr |= WXDCR_SLU;
1114                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1115         } else if ((rxcw & WXRXCW_C) != 0 && (dcr & WXDCR_SLU) != 0) {
1116                 DPRINTF(sc, (ane, sc->wx_name));
1117                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT);
1118                 sc->wx_dcr &= ~WXDCR_SLU;
1119                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1120         }
1121 }
1122
1123 static void
1124 wx_handle_rxint(wx_softc_t *sc)
1125 {
1126         struct ether_header *eh;
1127         struct mbuf *m0, *mb, *pending[WX_MAX_RDESC];
1128         struct ifnet *ifp = &sc->wx_if;
1129         int npkts, ndesc, lidx, idx, tlen;
1130
1131         DPRINTF(sc, ("%s: wx_handle_rxint\n", sc->wx_name));
1132
1133         for (m0 = sc->rpending, tlen = ndesc = npkts = 0, idx = sc->rnxt,
1134             lidx = R_PREV_IDX(idx); ndesc < WX_MAX_RDESC;
1135             ndesc++, lidx = idx, idx = R_NXT_IDX(idx)) {
1136                 wxrd_t *rd;
1137                 rxpkt_t *rxpkt;
1138                 int length, offset, lastframe;
1139
1140                 rd = &sc->rdescriptors[idx];
1141                 /*
1142                  * XXX: DMA Flush descriptor
1143                  */
1144                 if ((rd->status & RDSTAT_DD) == 0) {
1145                         if (m0) {
1146                                 if (sc->rpending == NULL) {
1147                                         m0->m_pkthdr.len = tlen;
1148                                         sc->rpending = m0;
1149                                 } else {
1150                                         m_freem(m0);
1151                                 }
1152                                 m0 = NULL;
1153                         }
1154                         DPRINTF(sc, ("%s: WXRX: ndesc %d idx %d lidx %d\n",
1155                             sc->wx_name, ndesc, idx, lidx));
1156                         break;
1157                 }
1158
1159                 if (rd->errors != 0) {
1160                         printf("%s: packet with errors (%x)\n",
1161                             sc->wx_name, rd->errors);
1162                         rd->status = 0;
1163                         ifp->if_ierrors++;
1164                         if (m0) {
1165                                 m_freem(m0);
1166                                 m0 = NULL;
1167                                 if (sc->rpending) {
1168                                         m_freem(sc->rpending);
1169                                         sc->rpending = NULL;
1170                                 }
1171                         }
1172                         continue;
1173                 }
1174
1175
1176                 rxpkt = &sc->rbase[idx];
1177                 mb = rxpkt->dptr;
1178                 if (mb == NULL) {
1179                         printf("%s: receive descriptor with no mbuf\n",
1180                             sc->wx_name);
1181                         (void) wx_get_rbuf(sc, rxpkt);
1182                         rd->status = 0;
1183                         ifp->if_ierrors++;
1184                         if (m0) {
1185                                 m_freem(m0);
1186                                 m0 = NULL;
1187                                 if (sc->rpending) {
1188                                         m_freem(sc->rpending);
1189                                         sc->rpending = NULL;
1190                                 }
1191                         }
1192                         continue;
1193                 }
1194
1195                 /* XXX: Flush DMA for rxpkt */
1196
1197                 if (wx_get_rbuf(sc, rxpkt)) {
1198                         sc->wx_rxnobuf++;
1199                         wx_rxdma_map(sc, rxpkt, mb);
1200                         ifp->if_ierrors++;
1201                         rd->status = 0;
1202                         if (m0) {
1203                                 m_freem(m0);
1204                                 m0 = NULL;
1205                                 if (sc->rpending) {
1206                                         m_freem(sc->rpending);
1207                                         sc->rpending = NULL;
1208                                 }
1209                         }
1210                         continue;
1211                 }
1212
1213                 /*
1214                  * Save the completing packet's offset value and length
1215                  * and install the new one into the descriptor.
1216                  */
1217                 lastframe = (rd->status & RDSTAT_EOP) != 0;
1218                 length = rd->length;
1219                 offset = rd->address.lowpart & 0xff;
1220                 bzero (rd, sizeof (*rd));
1221                 rd->address.lowpart = rxpkt->dma_addr + WX_RX_OFFSET_VALUE;
1222
1223                 mb->m_len = length;
1224                 mb->m_data += offset;
1225                 mb->m_next = NULL;
1226                 if (m0 == NULL) {
1227                         m0 = mb;
1228                         tlen = length;
1229                 } else if (m0 == sc->rpending) {
1230                         /*
1231                          * Pick up where we left off before. If
1232                          * we have an offset (we're assuming the
1233                          * first frame has an offset), then we've
1234                          * lost sync somewhere along the line.
1235                          */
1236                         if (offset) {
1237                                 printf("%s: lost sync with partial packet\n",
1238                                     sc->wx_name);
1239                                 m_freem(sc->rpending);
1240                                 sc->rpending = NULL;
1241                                 m0 = mb;
1242                                 tlen = length;
1243                         } else {
1244                                 sc->rpending = NULL;
1245                                 tlen = m0->m_pkthdr.len;
1246                         }
1247                 } else {
1248                         tlen += length;
1249                 }
1250
1251                 DPRINTF(sc, ("%s: RDESC[%d] len %d off %d lastframe %d\n",
1252                     sc->wx_name, idx, mb->m_len, offset, lastframe));
1253                 if (m0 != mb)
1254                         m_cat(m0, mb);
1255                 if (lastframe == 0) {
1256                         continue;
1257                 }
1258                 m0->m_pkthdr.rcvif = ifp;
1259                 m0->m_pkthdr.len = tlen - WX_CRC_LENGTH;
1260                 mb->m_len -= WX_CRC_LENGTH;
1261
1262                 eh = mtod(m0, struct ether_header *);
1263                 /*
1264                  * No need to check for promiscous mode since
1265                  * the decision to keep or drop the packet is
1266                  * handled by ether_input()
1267                  */
1268                 pending[npkts++] = m0;
1269                 m0 = NULL;
1270                 tlen = 0;
1271         }
1272
1273         if (ndesc) {
1274                 if (IS_WISEMAN(sc)) {
1275                         WRITE_CSR(sc, WXREG_RDT0, lidx);
1276                 } else {
1277                         WRITE_CSR(sc, WXREG_RDT0_LIVENGOOD, lidx);
1278                 }
1279                 sc->rnxt = idx;
1280         }
1281
1282         if (npkts) {
1283                 sc->wx_rxintr++;
1284         }
1285
1286         for (idx = 0; idx < npkts; idx++) {
1287                 mb = pending[idx];
1288                 if (ifp->if_bpf) {
1289                         bpf_mtap(WX_BPFTAP_ARG(ifp), mb);
1290                 }
1291                 ifp->if_ipackets++;
1292                 DPRINTF(sc, ("%s: RECV packet length %d\n",
1293                     sc->wx_name, mb->m_pkthdr.len));
1294                 eh = mtod(mb, struct ether_header *);
1295                 m_adj(mb, sizeof (struct ether_header));
1296                 ether_input(ifp, eh, mb);
1297         }
1298 }
1299
1300 static void
1301 wx_gc(wx_softc_t *sc)
1302 {
1303         struct ifnet *ifp = &sc->wx_if;
1304         txpkt_t *txpkt;
1305         u_int32_t tdh;
1306
1307         WX_LOCK(sc);
1308         txpkt = sc->tbsyf;
1309         if (IS_WISEMAN(sc)) {
1310                 tdh = READ_CSR(sc, WXREG_TDH);
1311         } else {
1312                 tdh = READ_CSR(sc, WXREG_TDH_LIVENGOOD);
1313         }
1314         while (txpkt != NULL) {
1315                 u_int32_t end = txpkt->eidx, cidx = tdh;
1316
1317                 /*
1318                  * Normalize start..end indices to 2 *
1319                  * WX_MAX_TDESC range to eliminate wrap.
1320                  */
1321                 if (txpkt->eidx < txpkt->sidx) {
1322                         end += WX_MAX_TDESC;
1323                 }
1324
1325                 /*
1326                  * Normalize current chip index to 2 *
1327                  * WX_MAX_TDESC range to eliminate wrap.
1328                  */
1329                 if (cidx < txpkt->sidx) {
1330                         cidx += WX_MAX_TDESC;
1331                 }
1332
1333                 /*
1334                  * If the current chip index is between low and
1335                  * high indices for this packet, it's not finished
1336                  * transmitting yet. Because transmits are done FIFO,
1337                  * this means we're done garbage collecting too.
1338                  */
1339
1340                 if (txpkt->sidx <= cidx && cidx < txpkt->eidx) {
1341                         DPRINTF(sc, ("%s: TXGC %d..%d TDH %d\n", sc->wx_name,
1342                             txpkt->sidx, txpkt->eidx, tdh));
1343                         break;
1344                 }
1345                 ifp->if_opackets++;
1346
1347                 if (txpkt->dptr) {
1348                         (void) m_freem(txpkt->dptr);
1349                 } else {
1350                         printf("%s: null mbuf in gc\n", sc->wx_name);
1351                 }
1352
1353                 for (cidx = txpkt->sidx; cidx != txpkt->eidx;
1354                     cidx = T_NXT_IDX(cidx)) {
1355                         txpkt_t *tmp;
1356                         wxtd_t *td;
1357
1358                         td = &sc->tdescriptors[cidx];
1359                         if (td->status & TXSTS_EC) {
1360                                 IPRINTF(sc, ("%s: excess collisions\n",
1361                                     sc->wx_name));
1362                                 ifp->if_collisions++;
1363                                 ifp->if_oerrors++;
1364                         }
1365                         if (td->status & TXSTS_LC) {
1366                                 IPRINTF(sc,
1367                                     ("%s: lost carrier\n", sc->wx_name));
1368                                 ifp->if_oerrors++;
1369                         }
1370                         tmp = &sc->tbase[cidx];
1371                         DPRINTF(sc, ("%s: TXGC[%d] %p %d..%d done nact %d "
1372                             "TDH %d\n", sc->wx_name, cidx, tmp->dptr,
1373                             txpkt->sidx, txpkt->eidx, sc->tactive, tdh));
1374                         tmp->dptr = NULL;
1375                         if (sc->tactive == 0) {
1376                                 printf("%s: nactive < 0?\n", sc->wx_name);
1377                         } else {
1378                                 sc->tactive -= 1;
1379                         }
1380                         bzero(td, sizeof (*td));
1381                 }
1382                 sc->tbsyf = txpkt->next;
1383                 txpkt = sc->tbsyf;
1384         }
1385         if (sc->tactive < WX_MAX_TDESC - 1) {
1386                 ifp->if_timer = 0;
1387                 ifp->if_flags &= ~IFF_OACTIVE;
1388         }
1389
1390         /* used SW LED to indicate transmission not active */
1391         if (sc->tactive == 0 && sc->wx_mii) {
1392                 WRITE_CSR(sc, WXREG_DCR,
1393                     READ_CSR(sc, WXREG_DCR) & ~(WXDCR_SWDPIO0|WXDCR_SWDPIN0));
1394         }
1395         WX_UNLOCK(sc);
1396 }
1397
1398 /*
1399  * Periodic timer to update packet in/out/collision statistics,
1400  * and, more importantly, garbage collect completed transmissions
1401  * and to handle link status changes.
1402  */
1403 #define WX_PRT_STATS(sc, y)     printf("\t" # y " = %u\n", ((sc)->y))
1404 #define WX_CLR_STATS(sc, y)     ((sc)->y  = 0)
1405
1406 static void
1407 wx_watchdog(void *arg)
1408 {
1409         wx_softc_t *sc = arg;
1410
1411         WX_LOCK(sc);
1412         if (sc->wx_needreinit) {
1413                 WX_UNLOCK(sc);
1414                 if (wx_init(sc) == 0) {
1415                         WX_LOCK(sc);
1416                         sc->wx_needreinit = 0;
1417                 } else {
1418                         WX_LOCK(sc);
1419                 }
1420         } else {
1421                 wx_gc(sc);
1422                 wx_check_link(sc);
1423         }
1424         if (wx_dump_stats == device_get_unit(sc->w.dev)) {
1425                 printf("%s: current statistics\n", sc->wx_name);
1426                 WX_PRT_STATS(sc, wx_intr);
1427                 WX_PRT_STATS(sc, wx_linkintr);
1428                 WX_PRT_STATS(sc, wx_rxintr);
1429                 WX_PRT_STATS(sc, wx_txqe);
1430                 WX_PRT_STATS(sc, wx_xmitgc);
1431                 WX_PRT_STATS(sc, wx_xmitpullup);
1432                 WX_PRT_STATS(sc, wx_xmitcluster);
1433                 WX_PRT_STATS(sc, wx_xmitputback);
1434                 WX_PRT_STATS(sc, wx_xmitwanted);
1435                 WX_PRT_STATS(sc, wx_xmitblocked);
1436                 WX_PRT_STATS(sc, wx_xmitrunt);
1437                 WX_PRT_STATS(sc, wx_rxnobuf);
1438                 WX_PRT_STATS(sc, wx_oddpkt);
1439                 wx_dump_stats = -1;
1440         }
1441         if (wx_clr_stats == device_get_unit(sc->w.dev)) {
1442                 printf("%s: statistics cleared\n", sc->wx_name);
1443                 WX_CLR_STATS(sc, wx_intr);
1444                 WX_CLR_STATS(sc, wx_linkintr);
1445                 WX_CLR_STATS(sc, wx_rxintr);
1446                 WX_CLR_STATS(sc, wx_txqe);
1447                 WX_CLR_STATS(sc, wx_xmitgc);
1448                 WX_CLR_STATS(sc, wx_xmitpullup);
1449                 WX_CLR_STATS(sc, wx_xmitcluster);
1450                 WX_CLR_STATS(sc, wx_xmitputback);
1451                 WX_CLR_STATS(sc, wx_xmitwanted);
1452                 WX_CLR_STATS(sc, wx_xmitblocked);
1453                 WX_CLR_STATS(sc, wx_xmitrunt);
1454                 WX_CLR_STATS(sc, wx_rxnobuf);
1455                 WX_CLR_STATS(sc, wx_oddpkt);
1456                 wx_clr_stats = -1;
1457         }
1458         WX_UNLOCK(sc);
1459
1460         /*
1461          * Schedule another timeout one second from now.
1462          */
1463         TIMEOUT(sc, wx_watchdog, sc, hz);
1464 }
1465
1466 /*
1467  * Stop and reinitialize the hardware
1468  */
1469 static void
1470 wx_hw_stop(wx_softc_t *sc)
1471 {
1472         u_int32_t icr;
1473         DPRINTF(sc, ("%s: wx_hw_stop\n", sc->wx_name));
1474         WX_DISABLE_INT(sc);
1475         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1476                 wx_mwi_whackon(sc);
1477         }
1478         WRITE_CSR(sc, WXREG_DCR, WXDCR_RST);
1479         DELAY(20 * 1000);
1480         icr = READ_CSR(sc, WXREG_ICR);
1481         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1482                 wx_mwi_unwhack(sc);
1483         }
1484 }
1485
1486 static void
1487 wx_set_addr(wx_softc_t *sc, int idx, u_int8_t *mac)
1488 {
1489         u_int32_t t0, t1;
1490         DPRINTF(sc, ("%s: wx_set_addr\n", sc->wx_name));
1491         t0 = (mac[0]) | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
1492         t1 = (mac[4] << 0) | (mac[5] << 8);
1493         t1 |= WX_RAL_AV;
1494         WRITE_CSR(sc, WXREG_RAL_LO(idx), t0);
1495         WRITE_CSR(sc, WXREG_RAL_HI(idx), t1);
1496 }
1497
1498 static int
1499 wx_hw_initialize(wx_softc_t *sc)
1500 {
1501         int i;
1502
1503         DPRINTF(sc, ("%s: wx_hw_initialize\n", sc->wx_name));
1504
1505         WRITE_CSR(sc, WXREG_VET, 0);
1506         for (i = 0; i < (WX_VLAN_TAB_SIZE << 2); i += 4) {
1507                 WRITE_CSR(sc, (WXREG_VFTA + i), 0);
1508         }
1509         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1510                 wx_mwi_whackon(sc);
1511                 WRITE_CSR(sc, WXREG_RCTL, WXRCTL_RST);
1512                 DELAY(5 * 1000);
1513         }
1514         /*
1515          * Load the first receiver address with our MAC address,
1516          * and load as many multicast addresses as can fit into
1517          * the receive address array.
1518          */
1519         wx_set_addr(sc, 0, sc->wx_enaddr);
1520         for (i = 1; i <= sc->wx_nmca; i++) {
1521                 if (i >= WX_RAL_TAB_SIZE) {
1522                         break;
1523                 } else {
1524                         wx_set_addr(sc, i, sc->wx_mcaddr[i-1]);
1525                 }
1526         }
1527
1528         while (i < WX_RAL_TAB_SIZE) {
1529                 WRITE_CSR(sc, WXREG_RAL_LO(i), 0);
1530                 WRITE_CSR(sc, WXREG_RAL_HI(i), 0);
1531                 i++;
1532         }
1533
1534         if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1535                 WRITE_CSR(sc, WXREG_RCTL, 0);
1536                 DELAY(1 * 1000);
1537                 wx_mwi_unwhack(sc);
1538         }
1539
1540         /*
1541          * Clear out the hashed multicast table array.
1542          */
1543         for (i = 0; i < WX_MC_TAB_SIZE; i++) {
1544                 WRITE_CSR(sc, WXREG_MTA + (sizeof (u_int32_t) * 4), 0);
1545         }
1546
1547         if (IS_LIVENGOOD_CU(sc)) {
1548                 /*
1549                  * has a PHY - raise its reset line to make it operational
1550                  */
1551                 u_int32_t tmp = READ_CSR(sc, WXREG_EXCT);
1552                 tmp |= WXPHY_RESET_DIR4;
1553                 WRITE_CSR(sc, WXREG_EXCT, tmp);
1554                 DELAY(20*1000);
1555
1556                 tmp = READ_CSR(sc, WXREG_EXCT);
1557                 tmp &= ~WXPHY_RESET4;
1558                 WRITE_CSR(sc, WXREG_EXCT, tmp);
1559                 DELAY(20*1000);
1560
1561                 tmp = READ_CSR(sc, WXREG_EXCT);
1562                 tmp |= WXPHY_RESET4;
1563                 WRITE_CSR(sc, WXREG_EXCT, tmp);
1564                 DELAY(20*1000);
1565         } else if (IS_LIVENGOOD(sc)) {
1566                 u_int16_t tew;
1567
1568                 /*
1569                  * Handle link control
1570                  */
1571                 WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr | WXDCR_LRST);
1572                 DELAY(50 * 1000);
1573
1574                 wx_read_eeprom(sc, &tew, WX_EEPROM_CTLR2_OFF, 1);
1575                 tew = (tew & WX_EEPROM_CTLR2_SWDPIO) << WX_EEPROM_EXT_SHIFT;
1576                 WRITE_CSR(sc, WXREG_EXCT, (u_int32_t)tew);
1577         }
1578
1579         if (sc->wx_dcr & (WXDCR_RFCE|WXDCR_TFCE)) {
1580                 WRITE_CSR(sc, WXREG_FCAL, FC_FRM_CONST_LO);
1581                 WRITE_CSR(sc, WXREG_FCAH, FC_FRM_CONST_HI);
1582                 WRITE_CSR(sc, WXREG_FCT, FC_TYP_CONST);
1583         } else {
1584                 WRITE_CSR(sc, WXREG_FCAL, 0);
1585                 WRITE_CSR(sc, WXREG_FCAH, 0);
1586                 WRITE_CSR(sc, WXREG_FCT, 0);
1587         }
1588         WRITE_CSR(sc, WXREG_FLOW_XTIMER, WX_XTIMER_DFLT);
1589
1590         if (IS_WISEMAN(sc)) {
1591                 if (sc->wx_idnrev < WX_WISEMAN_2_1) {
1592                         WRITE_CSR(sc, WXREG_FLOW_RCV_HI, 0);
1593                         WRITE_CSR(sc, WXREG_FLOW_RCV_LO, 0);
1594                         sc->wx_dcr &= ~(WXDCR_RFCE|WXDCR_TFCE);
1595                 } else {
1596                         WRITE_CSR(sc, WXREG_FLOW_RCV_HI, WX_RCV_FLOW_HI_DFLT);
1597                         WRITE_CSR(sc, WXREG_FLOW_RCV_LO, WX_RCV_FLOW_LO_DFLT);
1598                 }
1599         } else {
1600                 WRITE_CSR(sc, WXREG_FLOW_RCV_HI_LIVENGOOD, WX_RCV_FLOW_HI_DFLT);
1601                 WRITE_CSR(sc, WXREG_FLOW_RCV_LO_LIVENGOOD, WX_RCV_FLOW_LO_DFLT);
1602         }
1603
1604         if (!IS_LIVENGOOD_CU(sc))
1605                 WRITE_CSR(sc, WXREG_XMIT_CFGW, WXTXCW_DEFAULT);
1606
1607         WRITE_CSR(sc, WXREG_DCR, sc->wx_dcr);
1608         DELAY(50 * 1000);
1609
1610         if (!IS_LIVENGOOD_CU(sc)) {
1611                 /*
1612                  * The pin stuff is all FM from the Linux driver.
1613                  */
1614                 if ((READ_CSR(sc, WXREG_DCR) & WXDCR_SWDPIN1) == 0) {
1615                         for (i = 0; i < (WX_LINK_UP_TIMEOUT/10); i++) {
1616                                 DELAY(10 * 1000);
1617                                 if (READ_CSR(sc, WXREG_DSR) & WXDSR_LU) {
1618                                         sc->linkup = 1;
1619                                         break;
1620                                 }
1621                         }
1622                         if (sc->linkup == 0) {
1623                                 sc->ane_failed = 1;
1624                                 wx_check_link(sc);
1625                         }
1626                         sc->ane_failed = 0;
1627                 } else {
1628                         printf("%s: SWDPIO1 did not clear- check for reversed "
1629                                 "or disconnected cable\n", sc->wx_name);
1630                         /* but return okay anyway */
1631                 }
1632         }
1633
1634         sc->wx_ienable = WXIENABLE_DEFAULT;
1635         return (0);
1636 }
1637
1638 /*
1639  * Stop the interface. Cancels the statistics updater and resets the interface.
1640  */
1641 static void
1642 wx_stop(wx_softc_t *sc)
1643 {
1644         txpkt_t *txp;
1645         rxpkt_t *rxp;
1646         struct ifnet *ifp = &sc->wx_if;
1647
1648         DPRINTF(sc, ("%s: wx_stop\n", sc->wx_name));
1649         /*
1650          * Cancel stats updater.
1651          */
1652         UNTIMEOUT(wx_watchdog, sc, sc);
1653
1654         /*
1655          * Reset the chip
1656          */
1657         wx_hw_stop(sc);
1658
1659         /*
1660          * Release any xmit buffers.
1661          */
1662         for (txp = sc->tbase; txp && txp < &sc->tbase[WX_MAX_TDESC]; txp++) {
1663                 if (txp->dptr) {
1664                         m_free(txp->dptr);
1665                         txp->dptr = NULL;
1666                 }
1667         }
1668
1669         /*
1670          * Free all the receive buffers.
1671          */
1672         for (rxp = sc->rbase; rxp && rxp < &sc->rbase[WX_MAX_RDESC]; rxp++) {
1673                 if (rxp->dptr) {
1674                         m_free(rxp->dptr);
1675                         rxp->dptr = NULL;
1676                 }
1677         }
1678
1679         if (sc->rpending) {
1680                 m_freem(sc->rpending);
1681                 sc->rpending = NULL;
1682         }
1683
1684         /*
1685          * And we're outta here...
1686          */
1687
1688         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1689         ifp->if_timer = 0;
1690 }
1691
1692 /*
1693  * Transmit Watchdog
1694  */
1695 static void
1696 wx_txwatchdog(struct ifnet *ifp)
1697 {
1698         wx_softc_t *sc = SOFTC_IFP(ifp);
1699         printf("%s: device timeout\n", sc->wx_name);
1700         ifp->if_oerrors++;
1701         if (wx_init(sc)) {
1702                 printf("%s: could not re-init device\n", sc->wx_name);
1703                 sc->wx_needreinit = 1;
1704         }
1705 }
1706
1707 static int
1708 wx_init(void *xsc)
1709 {
1710         struct ifmedia *ifm;
1711         wx_softc_t *sc = xsc;
1712         struct ifnet *ifp = &sc->wx_if;
1713         rxpkt_t *rxpkt;
1714         wxrd_t *rd;
1715         size_t len;
1716         int i, bflags;
1717
1718         DPRINTF(sc, ("%s: wx_init\n", sc->wx_name));
1719         WX_LOCK(sc);
1720
1721         /*
1722          * Cancel any pending I/O by resetting things.
1723          * wx_stop will free any allocated mbufs.
1724          */
1725         wx_stop(sc);
1726
1727         /*
1728          * Reset the hardware. All network addresses loaded here, but
1729          * neither the receiver nor the transmitter are enabled.
1730          */
1731
1732         if (wx_hw_initialize(sc)) {
1733                 DPRINTF(sc, ("%s: wx_hw_initialize failed\n", sc->wx_name));
1734                 WX_UNLOCK(sc);
1735                 return (EIO);
1736         }
1737
1738         /*
1739          * Set up the receive ring stuff.
1740          */
1741         len = sizeof (wxrd_t) * WX_MAX_RDESC;
1742         bzero(sc->rdescriptors, len);
1743         for (rxpkt = sc->rbase, i = 0; rxpkt != NULL && i < WX_MAX_RDESC;
1744             i += RXINCR, rxpkt++) {
1745                 rd = &sc->rdescriptors[i];
1746                 if (wx_get_rbuf(sc, rxpkt)) {
1747                         break;
1748                 }
1749                 rd->address.lowpart = rxpkt->dma_addr + WX_RX_OFFSET_VALUE;
1750         }
1751         if (i != WX_MAX_RDESC) {
1752                 printf("%s: could not set up rbufs\n", sc->wx_name);
1753                 wx_stop(sc);
1754                 WX_UNLOCK(sc);
1755                 return (ENOMEM);
1756         }
1757
1758         /*
1759          * Set up transmit parameters and enable the transmitter.
1760          */
1761         sc->tnxtfree = sc->tactive = 0;
1762         sc->tbsyf = sc->tbsyl = NULL;
1763         WRITE_CSR(sc, WXREG_TCTL, 0);
1764         DELAY(5 * 1000);
1765         if (IS_WISEMAN(sc)) {
1766                 WRITE_CSR(sc, WXREG_TDBA_LO,
1767                         vtophys((vm_offset_t)&sc->tdescriptors[0]));
1768                 WRITE_CSR(sc, WXREG_TDBA_HI, 0);
1769                 WRITE_CSR(sc, WXREG_TDLEN, WX_MAX_TDESC * sizeof (wxtd_t));
1770                 WRITE_CSR(sc, WXREG_TDH, 0);
1771                 WRITE_CSR(sc, WXREG_TDT, 0);
1772                 WRITE_CSR(sc, WXREG_TQSA_HI, 0);
1773                 WRITE_CSR(sc, WXREG_TQSA_LO, 0);
1774                 WRITE_CSR(sc, WXREG_TIPG, WX_WISEMAN_TIPG_DFLT);
1775                 WRITE_CSR(sc, WXREG_TIDV, wx_txint_delay);
1776         } else {
1777                 WRITE_CSR(sc, WXREG_TDBA_LO_LIVENGOOD,
1778                         vtophys((vm_offset_t)&sc->tdescriptors[0]));
1779                 WRITE_CSR(sc, WXREG_TDBA_HI_LIVENGOOD, 0);
1780                 WRITE_CSR(sc, WXREG_TDLEN_LIVENGOOD,
1781                         WX_MAX_TDESC * sizeof (wxtd_t));
1782                 WRITE_CSR(sc, WXREG_TDH_LIVENGOOD, 0);
1783                 WRITE_CSR(sc, WXREG_TDT_LIVENGOOD, 0);
1784                 WRITE_CSR(sc, WXREG_TQSA_HI, 0);
1785                 WRITE_CSR(sc, WXREG_TQSA_LO, 0);
1786                 WRITE_CSR(sc, WXREG_TIPG, WX_LIVENGOOD_TIPG_DFLT);
1787                 WRITE_CSR(sc, WXREG_TIDV_LIVENGOOD, wx_txint_delay);
1788         }
1789         WRITE_CSR(sc, WXREG_TCTL, (WXTCTL_CT(WX_COLLISION_THRESHOLD) |
1790             WXTCTL_COLD(WX_FDX_COLLISION_DX) | WXTCTL_EN));
1791         /*
1792          * Set up receive parameters and enable the receiver.
1793          */
1794
1795         sc->rnxt = 0;
1796         WRITE_CSR(sc, WXREG_RCTL, 0);
1797         DELAY(5 * 1000);
1798         if (IS_WISEMAN(sc)) {
1799                 WRITE_CSR(sc, WXREG_RDTR0, WXRDTR_FPD);
1800                 WRITE_CSR(sc, WXREG_RDBA0_LO,
1801                     vtophys((vm_offset_t)&sc->rdescriptors[0]));
1802                 WRITE_CSR(sc, WXREG_RDBA0_HI, 0);
1803                 WRITE_CSR(sc, WXREG_RDLEN0, WX_MAX_RDESC * sizeof (wxrd_t));
1804                 WRITE_CSR(sc, WXREG_RDH0, 0);
1805                 WRITE_CSR(sc, WXREG_RDT0, (WX_MAX_RDESC - RXINCR));
1806         } else {
1807                 /*
1808                  * The delay should yield ~10us receive interrupt delay
1809                  */
1810                 WRITE_CSR(sc, WXREG_RDTR0_LIVENGOOD, WXRDTR_FPD | 0x40);
1811                 WRITE_CSR(sc, WXREG_RDBA0_LO_LIVENGOOD,
1812                     vtophys((vm_offset_t)&sc->rdescriptors[0]));
1813                 WRITE_CSR(sc, WXREG_RDBA0_HI_LIVENGOOD, 0);
1814                 WRITE_CSR(sc, WXREG_RDLEN0_LIVENGOOD,
1815                     WX_MAX_RDESC * sizeof (wxrd_t));
1816                 WRITE_CSR(sc, WXREG_RDH0_LIVENGOOD, 0);
1817                 WRITE_CSR(sc, WXREG_RDT0_LIVENGOOD, (WX_MAX_RDESC - RXINCR));
1818         }
1819         WRITE_CSR(sc, WXREG_RDTR1, 0);
1820         WRITE_CSR(sc, WXREG_RDBA1_LO, 0);
1821         WRITE_CSR(sc, WXREG_RDBA1_HI, 0);
1822         WRITE_CSR(sc, WXREG_RDLEN1, 0);
1823         WRITE_CSR(sc, WXREG_RDH1, 0);
1824         WRITE_CSR(sc, WXREG_RDT1, 0);
1825
1826         if (ifp->if_mtu > ETHERMTU) {
1827                 bflags = WXRCTL_EN | WXRCTL_LPE | WXRCTL_2KRBUF;
1828         } else {
1829                 bflags = WXRCTL_EN | WXRCTL_2KRBUF;
1830         }
1831
1832         WRITE_CSR(sc, WXREG_RCTL, bflags |
1833             ((ifp->if_flags & IFF_BROADCAST) ? WXRCTL_BAM : 0) |
1834             ((ifp->if_flags & IFF_PROMISC) ? WXRCTL_UPE : 0) |
1835             ((sc->all_mcasts) ? WXRCTL_MPE : 0));
1836
1837         /*
1838          * Enable Interrupts
1839          */
1840         WX_ENABLE_INT(sc);
1841
1842         if (sc->wx_mii) {
1843                 mii_mediachg(WX_MII_FROM_SOFTC(sc));
1844         } else {
1845                 ifm = &sc->wx_media;
1846                 i = ifm->ifm_media;
1847                 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1848                 wx_ifmedia_upd(ifp);
1849                 ifm->ifm_media = i;
1850         }
1851
1852         /*
1853          * Mark that we're up and running...
1854          */
1855         ifp->if_flags |= IFF_RUNNING;
1856         ifp->if_flags &= ~IFF_OACTIVE;
1857
1858
1859         /*
1860          * Start stats updater.
1861          */
1862         TIMEOUT(sc, wx_watchdog, sc, hz);
1863
1864         WX_UNLOCK(sc);
1865         /*
1866          * And we're outta here...
1867          */
1868         return (0);
1869 }
1870
1871 /*
1872  * Get a receive buffer for our use (and dma map the data area).
1873  *
1874  * The Wiseman chip can have buffers be 256, 512, 1024 or 2048 bytes in size.
1875  * The LIVENGOOD chip can go higher (up to 16K), but what's the point as
1876  * we aren't doing non-MCLGET memory management.
1877  *
1878  * It wants them aligned on 256 byte boundaries, but can actually cope
1879  * with an offset in the first 255 bytes of the head of a receive frame.
1880  *
1881  * We'll allocate a MCLBYTE sized cluster but *not* adjust the data pointer
1882  * by any alignment value. Instead, we'll tell the chip to offset by any
1883  * alignment and we'll catch the alignment on the backend at interrupt time.
1884  */
1885 static void
1886 wx_rxdma_map(wx_softc_t *sc, rxpkt_t *rxpkt, struct mbuf *mb)
1887 {
1888         rxpkt->dptr = mb;
1889         rxpkt->dma_addr = vtophys(mtod(mb, vm_offset_t));
1890 }
1891
1892 static int
1893 wx_get_rbuf(wx_softc_t *sc, rxpkt_t *rxpkt)
1894 {
1895         struct mbuf *mb;
1896         MGETHDR(mb, MB_DONTWAIT, MT_DATA);
1897         if (mb == NULL) {
1898                 rxpkt->dptr = NULL;
1899                 return (-1);
1900         }
1901         MCLGET(mb, MB_DONTWAIT);
1902         if ((mb->m_flags & M_EXT) == 0) {
1903                 m_freem(mb);
1904                 rxpkt->dptr = NULL;
1905                 return (-1);
1906         }
1907         wx_rxdma_map(sc, rxpkt, mb);
1908         return (0);
1909 }
1910
1911 static int
1912 wx_ioctl(struct ifnet *ifp, IOCTL_CMD_TYPE command, caddr_t data,
1913     struct ucred *cr)
1914 {
1915         wx_softc_t *sc = SOFTC_IFP(ifp);
1916         struct ifreq *ifr = (struct ifreq *) data;
1917         int error = 0;
1918
1919         WX_LOCK(sc);
1920         switch (command) {
1921         case SIOCSIFADDR:
1922         case SIOCGIFADDR:
1923                 error = ether_ioctl(ifp, command, data);
1924                 break;
1925         case SIOCSIFMTU:
1926                 if (ifr->ifr_mtu > WX_MAXMTU || ifr->ifr_mtu < ETHERMIN) {
1927                         error = EINVAL;
1928                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
1929                         ifp->if_mtu = ifr->ifr_mtu;
1930                         error = wx_init(sc);
1931                 }
1932                 break;
1933         case SIOCSIFFLAGS:
1934                 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1935
1936                 /*
1937                  * If interface is marked up and not running, then start it.
1938                  * If it is marked down and running, stop it.
1939                  * If it's up then re-initialize it. This is so flags
1940                  * such as IFF_PROMISC are handled.
1941                  */
1942                 if (ifp->if_flags & IFF_UP) {
1943                         if ((ifp->if_flags & IFF_RUNNING) == 0) {
1944                                 error = wx_init(sc);
1945                         }
1946                 } else {
1947                         if (ifp->if_flags & IFF_RUNNING) {
1948                                 wx_stop(sc);
1949                         }
1950                 }
1951                 break;
1952
1953         case SIOCADDMULTI:
1954         case SIOCDELMULTI:
1955                 sc->all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0;
1956                 error = wx_mc_setup(sc);
1957                 break;
1958         case SIOCGIFMEDIA:
1959         case SIOCSIFMEDIA:
1960                 DPRINTF(sc, ("%s: ioctl SIOC[GS]IFMEDIA: command=%#lx\n",
1961                     sc->wx_name, command));
1962                 if (sc->wx_mii) {
1963                         mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
1964                         error = ifmedia_ioctl(ifp, ifr,
1965                             &mii->mii_media, command);
1966                 } else {
1967                         error = ifmedia_ioctl(ifp, ifr, &sc->wx_media, command);
1968                 }
1969
1970                 break;
1971         default:
1972                 error = EINVAL;
1973         }
1974
1975         WX_UNLOCK(sc);
1976         return (error);
1977 }
1978
1979 static int
1980 wx_ifmedia_upd(struct ifnet *ifp)
1981 {
1982         struct wx_softc *sc = SOFTC_IFP(ifp);
1983         struct ifmedia *ifm;
1984
1985         DPRINTF(sc, ("%s: ifmedia_upd\n", sc->wx_name));
1986
1987         if (sc->wx_mii) {
1988                 mii_mediachg(WX_MII_FROM_SOFTC(sc));
1989                 return 0;
1990         }
1991
1992         ifm = &sc->wx_media;
1993
1994         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1995                 return (EINVAL);
1996         }
1997
1998         return (0);
1999 }
2000
2001 static void
2002 wx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2003 {
2004         u_int32_t dsr;
2005         struct wx_softc *sc = SOFTC_IFP(ifp);
2006
2007         DPRINTF(sc, ("%s: ifmedia_sts: ", sc->wx_name));
2008
2009         if (sc->wx_mii) {
2010                 mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
2011                 mii_pollstat(mii);
2012                 ifmr->ifm_active = mii->mii_media_active;
2013                 ifmr->ifm_status = mii->mii_media_status;
2014                 DPRINTF(sc, ("active=%#x status=%#x\n",
2015                     ifmr->ifm_active, ifmr->ifm_status));
2016                 return;
2017         }
2018
2019         DPRINTF(sc, ("\n"));
2020         ifmr->ifm_status = IFM_AVALID;
2021         ifmr->ifm_active = IFM_ETHER;
2022
2023         if (sc->linkup == 0)
2024                 return;
2025
2026         ifmr->ifm_status |= IFM_ACTIVE;
2027         dsr = READ_CSR(sc, WXREG_DSR);
2028         if (IS_LIVENGOOD(sc)) {
2029                 if (dsr &  WXDSR_1000BT) {
2030                         if (IS_LIVENGOOD_CU(sc)) {
2031                                 ifmr->ifm_status |= IFM_1000_TX;
2032                         }
2033                         else {
2034                                 ifmr->ifm_status |= IFM_1000_SX;
2035                         }
2036                 } else if (dsr & WXDSR_100BT) {
2037                         ifmr->ifm_status |= IFM_100_FX; /* ?? */
2038                 } else {
2039                         ifmr->ifm_status |= IFM_10_T;   /* ?? */
2040                 }
2041         } else {
2042                 ifmr->ifm_status |= IFM_1000_SX;
2043         }
2044         if (dsr & WXDSR_FD) {
2045                 ifmr->ifm_active |= IFM_FDX;
2046         }
2047 }
2048
2049
2050 #define RAISE_CLOCK(sc, dcr)    \
2051                 WRITE_CSR(sc, WXREG_DCR, (dcr) | WXPHY_MDC), DELAY(2)
2052
2053 #define LOWER_CLOCK(sc, dcr)    \
2054                 WRITE_CSR(sc, WXREG_DCR, (dcr) & ~WXPHY_MDC), DELAY(2)
2055
2056 static u_int32_t
2057 wx_mii_shift_in(wx_softc_t *sc)
2058 {
2059         u_int32_t dcr, i;
2060         u_int32_t data = 0;
2061
2062         dcr = READ_CSR(sc, WXREG_DCR);
2063         dcr &= ~(WXPHY_MDIO_DIR | WXPHY_MDIO);
2064         WRITE_CSR(sc, WXREG_DCR, dcr);
2065         RAISE_CLOCK(sc, dcr);
2066         LOWER_CLOCK(sc, dcr);
2067
2068         for (i = 0; i < 16; i++) {
2069                 data <<= 1;
2070                 RAISE_CLOCK(sc, dcr);
2071                 dcr = READ_CSR(sc, WXREG_DCR);
2072
2073                 if (dcr & WXPHY_MDIO)
2074                         data |= 1;
2075
2076                 LOWER_CLOCK(sc, dcr);
2077         }
2078
2079         RAISE_CLOCK(sc, dcr);
2080         LOWER_CLOCK(sc, dcr);
2081         return (data);
2082 }
2083
2084 static void
2085 wx_mii_shift_out(wx_softc_t *sc, u_int32_t data, u_int32_t count)
2086 {
2087         u_int32_t dcr, mask;
2088
2089         dcr = READ_CSR(sc, WXREG_DCR);
2090         dcr |= WXPHY_MDIO_DIR | WXPHY_MDC_DIR;
2091
2092         for (mask = (1 << (count - 1)); mask; mask >>= 1) {
2093                 if (data & mask)
2094                         dcr |= WXPHY_MDIO;
2095                 else
2096                         dcr &= ~WXPHY_MDIO;
2097
2098                 WRITE_CSR(sc, WXREG_DCR, dcr);
2099                 DELAY(2);
2100                 RAISE_CLOCK(sc, dcr);
2101                 LOWER_CLOCK(sc, dcr);
2102         }
2103 }
2104
2105 static int
2106 wx_miibus_readreg(void *arg, int phy, int reg)
2107 {
2108         wx_softc_t *sc = WX_SOFTC_FROM_MII_ARG(arg);
2109         unsigned int data = 0;
2110
2111         if (!IS_LIVENGOOD_CU(sc)) {
2112                 return 0;
2113         }
2114         wx_mii_shift_out(sc, WXPHYC_PREAMBLE, WXPHYC_PREAMBLE_LEN);
2115         wx_mii_shift_out(sc, reg | (phy << 5) | (WXPHYC_READ << 10) |
2116             (WXPHYC_SOF << 12), 14);
2117         data = wx_mii_shift_in(sc);
2118         return (data & WXMDIC_DATA_MASK);
2119 }
2120
2121 static int
2122 wx_miibus_writereg(void *arg, int phy, int reg, int data)
2123 {
2124         wx_softc_t *sc = WX_SOFTC_FROM_MII_ARG(arg);
2125         if (!IS_LIVENGOOD_CU(sc)) {
2126                 return 0;
2127         }
2128         wx_mii_shift_out(sc, WXPHYC_PREAMBLE, WXPHYC_PREAMBLE_LEN);
2129         wx_mii_shift_out(sc, (u_int32_t)data | (WXPHYC_TURNAROUND << 16) |
2130             (reg << 18) | (phy << 23) | (WXPHYC_WRITE << 28) |
2131             (WXPHYC_SOF << 30), 32);
2132         return (0);
2133 }
2134
2135 static void
2136 wx_miibus_statchg(void *arg)
2137 {
2138         wx_softc_t *sc = WX_SOFTC_FROM_MII_ARG(arg);
2139         mii_data_t *mii = WX_MII_FROM_SOFTC(sc);
2140         u_int32_t dcr, tctl;
2141
2142         if (mii == NULL)
2143                 return;
2144
2145         dcr = sc->wx_dcr;
2146         tctl = READ_CSR(sc, WXREG_TCTL);
2147         DPRINTF(sc, ("%s: statchg dcr=%#x tctl=%#x", sc->wx_name, dcr, tctl));
2148
2149         dcr |= WXDCR_FRCSPD | WXDCR_FRCDPX | WXDCR_SLU;
2150         dcr &= ~(WXDCR_SPEED_MASK | WXDCR_ASDE /* | WXDCR_ILOS */);
2151
2152         if (mii->mii_media_status & IFM_ACTIVE) {
2153                 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE) {
2154                         DPRINTF(sc, (" link-down\n"));
2155                         sc->linkup = 0;
2156                         return;
2157                 }
2158
2159                 sc->linkup = 1;
2160         }
2161
2162         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) {
2163                 DPRINTF(sc, (" 1000TX"));
2164                 dcr |= WXDCR_1000BT;
2165         } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2166                 DPRINTF(sc, (" 100TX"));
2167                 dcr |= WXDCR_100BT;
2168         } else  /* assume IFM_10_TX */ {
2169                 DPRINTF(sc, (" 10TX"));
2170                 dcr |= WXDCR_10BT;
2171         }
2172
2173         if (mii->mii_media_active & IFM_FDX) {
2174                 DPRINTF(sc, ("-FD"));
2175                 tctl = WXTCTL_CT(WX_COLLISION_THRESHOLD) |
2176                     WXTCTL_COLD(WX_FDX_COLLISION_DX) | WXTCTL_EN;
2177                 dcr |= WXDCR_FD;
2178         } else {
2179                 DPRINTF(sc, ("-HD"));
2180                 tctl = WXTCTL_CT(WX_COLLISION_THRESHOLD) |
2181                     WXTCTL_COLD(WX_HDX_COLLISION_DX) | WXTCTL_EN;
2182                 dcr &= ~WXDCR_FD;
2183         }
2184
2185         /* FLAG0==rx-flow-control FLAG1==tx-flow-control */
2186         if (mii->mii_media_active & IFM_FLAG0) {
2187                 dcr |= WXDCR_RFCE;
2188         } else {
2189                 dcr &= ~WXDCR_RFCE;
2190         }
2191
2192         if (mii->mii_media_active & IFM_FLAG1) {
2193                 dcr |= WXDCR_TFCE;
2194         } else {
2195                 dcr &= ~WXDCR_TFCE;
2196         }
2197
2198         if (dcr & (WXDCR_RFCE|WXDCR_TFCE)) {
2199                 WRITE_CSR(sc, WXREG_FCAL, FC_FRM_CONST_LO);
2200                 WRITE_CSR(sc, WXREG_FCAH, FC_FRM_CONST_HI);
2201                 WRITE_CSR(sc, WXREG_FCT, FC_TYP_CONST);
2202         } else {
2203                 WRITE_CSR(sc, WXREG_FCAL, 0);
2204                 WRITE_CSR(sc, WXREG_FCAH, 0);
2205                 WRITE_CSR(sc, WXREG_FCT, 0);
2206         }
2207
2208         DPRINTF(sc, (" dcr=%#x tctl=%#x\n", dcr, tctl));
2209         WRITE_CSR(sc, WXREG_TCTL, tctl);
2210         sc->wx_dcr = dcr;
2211         WRITE_CSR(sc, WXREG_DCR, dcr);
2212 }
2213
2214 static void
2215 wx_miibus_mediainit(void *arg)
2216 {
2217 }