2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $
34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.42 2007/03/26 12:13:58 sephe Exp $
38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
39 * for FreeBSD. Datasheets are available from:
41 * http://www.national.com/ds/DP/DP83820.pdf
42 * http://www.national.com/ds/DP/DP83821.pdf
44 * These chips are used on several low cost gigabit ethernet NICs
45 * sold by D-Link, Addtron, SMC and Asante. Both parts are
46 * virtually the same, except the 83820 is a 64-bit/32-bit part,
47 * while the 83821 is 32-bit only.
49 * Many cards also use National gigE transceivers, such as the
50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
51 * contains a full register description that applies to all of these
54 * http://www.national.com/ds/DP/DP83861.pdf
56 * Written by Bill Paul <wpaul@bsdi.com>
57 * BSDi Open Source Solutions
61 * The NatSemi DP83820 and 83821 controllers are enhanced versions
62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
67 * matching buffers, one perfect address filter buffer and interrupt
68 * moderation. The 83820 supports both 64-bit and 32-bit addressing
69 * and data transfers: the 64-bit support can be toggled on or off
70 * via software. This affects the size of certain fields in the DMA
73 * There are two bugs/misfeatures in the 83820/83821 that I have
76 * - Receive buffers must be aligned on 64-bit boundaries, which means
77 * you must resort to copying data in order to fix up the payload
80 * - In order to transmit jumbo frames larger than 8170 bytes, you have
81 * to turn off transmit checksum offloading, because the chip can't
82 * compute the checksum on an outgoing frame unless it fits entirely
83 * within the TX FIFO, which is only 8192 bytes in size. If you have
84 * TX checksum offload enabled and you transmit attempt to transmit a
85 * frame larger than 8170 bytes, the transmitter will wedge.
87 * To work around the latter problem, TX checksum offload is disabled
88 * if the user selects an MTU larger than 8152 (8170 - 18).
91 #include "opt_polling.h"
93 #include <sys/param.h>
94 #include <sys/systm.h>
95 #include <sys/sockio.h>
97 #include <sys/malloc.h>
98 #include <sys/kernel.h>
99 #include <sys/socket.h>
100 #include <sys/serialize.h>
102 #include <sys/rman.h>
103 #include <sys/thread2.h>
106 #include <net/ifq_var.h>
107 #include <net/if_arp.h>
108 #include <net/ethernet.h>
109 #include <net/if_dl.h>
110 #include <net/if_media.h>
111 #include <net/if_types.h>
112 #include <net/vlan/if_vlan_var.h>
116 #include <vm/vm.h> /* for vtophys */
117 #include <vm/pmap.h> /* for vtophys */
119 #include <dev/netif/mii_layer/mii.h>
120 #include <dev/netif/mii_layer/miivar.h>
122 #include <bus/pci/pcidevs.h>
123 #include <bus/pci/pcireg.h>
124 #include <bus/pci/pcivar.h>
126 #define NGE_USEIOSPACE
128 #include "if_ngereg.h"
131 /* "controller miibus0" required. See GENERIC if you get errors here. */
132 #include "miibus_if.h"
134 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
137 * Various supported device vendors/types and their names.
139 static struct nge_type nge_devs[] = {
140 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820,
141 "National Semiconductor Gigabit Ethernet" },
145 static int nge_probe(device_t);
146 static int nge_attach(device_t);
147 static int nge_detach(device_t);
149 static int nge_alloc_jumbo_mem(struct nge_softc *);
150 static struct nge_jslot
151 *nge_jalloc(struct nge_softc *);
152 static void nge_jfree(void *);
153 static void nge_jref(void *);
155 static int nge_newbuf(struct nge_softc *, struct nge_desc *,
157 static int nge_encap(struct nge_softc *, struct mbuf *, uint32_t *);
158 static void nge_rxeof(struct nge_softc *);
159 static void nge_txeof(struct nge_softc *);
160 static void nge_intr(void *);
161 static void nge_tick(void *);
162 static void nge_start(struct ifnet *);
163 static int nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
164 static void nge_init(void *);
165 static void nge_stop(struct nge_softc *);
166 static void nge_watchdog(struct ifnet *);
167 static void nge_shutdown(device_t);
168 static int nge_ifmedia_upd(struct ifnet *);
169 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
171 static void nge_delay(struct nge_softc *);
172 static void nge_eeprom_idle(struct nge_softc *);
173 static void nge_eeprom_putbyte(struct nge_softc *, int);
174 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *);
175 static void nge_read_eeprom(struct nge_softc *, void *, int, int);
177 static void nge_mii_sync(struct nge_softc *);
178 static void nge_mii_send(struct nge_softc *, uint32_t, int);
179 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
180 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
182 static int nge_miibus_readreg(device_t, int, int);
183 static int nge_miibus_writereg(device_t, int, int, int);
184 static void nge_miibus_statchg(device_t);
186 static void nge_setmulti(struct nge_softc *);
187 static void nge_reset(struct nge_softc *);
188 static int nge_list_rx_init(struct nge_softc *);
189 static int nge_list_tx_init(struct nge_softc *);
190 #ifdef DEVICE_POLLING
191 static void nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
194 #ifdef NGE_USEIOSPACE
195 #define NGE_RES SYS_RES_IOPORT
196 #define NGE_RID NGE_PCI_LOIO
198 #define NGE_RES SYS_RES_MEMORY
199 #define NGE_RID NGE_PCI_LOMEM
202 static device_method_t nge_methods[] = {
203 /* Device interface */
204 DEVMETHOD(device_probe, nge_probe),
205 DEVMETHOD(device_attach, nge_attach),
206 DEVMETHOD(device_detach, nge_detach),
207 DEVMETHOD(device_shutdown, nge_shutdown),
210 DEVMETHOD(bus_print_child, bus_generic_print_child),
211 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
214 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
215 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
216 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
221 static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc));
222 static devclass_t nge_devclass;
224 DECLARE_DUMMY_MODULE(if_nge);
225 MODULE_DEPEND(if_nge, miibus, 1, 1, 1);
226 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0);
227 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
229 #define NGE_SETBIT(sc, reg, x) \
230 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
232 #define NGE_CLRBIT(sc, reg, x) \
233 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
236 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
239 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
242 nge_delay(struct nge_softc *sc)
246 for (idx = (300 / 33) + 1; idx > 0; idx--)
247 CSR_READ_4(sc, NGE_CSR);
251 nge_eeprom_idle(struct nge_softc *sc)
255 SIO_SET(NGE_MEAR_EE_CSEL);
257 SIO_SET(NGE_MEAR_EE_CLK);
260 for (i = 0; i < 25; i++) {
261 SIO_CLR(NGE_MEAR_EE_CLK);
263 SIO_SET(NGE_MEAR_EE_CLK);
267 SIO_CLR(NGE_MEAR_EE_CLK);
269 SIO_CLR(NGE_MEAR_EE_CSEL);
271 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
275 * Send a read command and address to the EEPROM, check for ACK.
278 nge_eeprom_putbyte(struct nge_softc *sc, int addr)
282 d = addr | NGE_EECMD_READ;
285 * Feed in each bit and stobe the clock.
287 for (i = 0x400; i; i >>= 1) {
289 SIO_SET(NGE_MEAR_EE_DIN);
291 SIO_CLR(NGE_MEAR_EE_DIN);
293 SIO_SET(NGE_MEAR_EE_CLK);
295 SIO_CLR(NGE_MEAR_EE_CLK);
301 * Read a word of data stored in the EEPROM at address 'addr.'
304 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest)
309 /* Force EEPROM to idle state. */
312 /* Enter EEPROM access mode. */
314 SIO_CLR(NGE_MEAR_EE_CLK);
316 SIO_SET(NGE_MEAR_EE_CSEL);
320 * Send address of word we want to read.
322 nge_eeprom_putbyte(sc, addr);
325 * Start reading bits from EEPROM.
327 for (i = 0x8000; i; i >>= 1) {
328 SIO_SET(NGE_MEAR_EE_CLK);
330 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
333 SIO_CLR(NGE_MEAR_EE_CLK);
337 /* Turn off EEPROM access mode. */
344 * Read a sequence of words from the EEPROM.
347 nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt)
350 uint16_t word = 0, *ptr;
352 for (i = 0; i < cnt; i++) {
353 nge_eeprom_getword(sc, off + i, &word);
354 ptr = (uint16_t *)((uint8_t *)dest + (i * 2));
360 * Sync the PHYs by setting data bit and strobing the clock 32 times.
363 nge_mii_sync(struct nge_softc *sc)
367 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA);
369 for (i = 0; i < 32; i++) {
370 SIO_SET(NGE_MEAR_MII_CLK);
372 SIO_CLR(NGE_MEAR_MII_CLK);
378 * Clock a series of bits through the MII.
381 nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt)
385 SIO_CLR(NGE_MEAR_MII_CLK);
387 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
389 SIO_SET(NGE_MEAR_MII_DATA);
391 SIO_CLR(NGE_MEAR_MII_DATA);
393 SIO_CLR(NGE_MEAR_MII_CLK);
395 SIO_SET(NGE_MEAR_MII_CLK);
400 * Read an PHY register through the MII.
403 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame)
408 * Set up frame for RX.
410 frame->mii_stdelim = NGE_MII_STARTDELIM;
411 frame->mii_opcode = NGE_MII_READOP;
412 frame->mii_turnaround = 0;
415 CSR_WRITE_4(sc, NGE_MEAR, 0);
420 SIO_SET(NGE_MEAR_MII_DIR);
425 * Send command/address info.
427 nge_mii_send(sc, frame->mii_stdelim, 2);
428 nge_mii_send(sc, frame->mii_opcode, 2);
429 nge_mii_send(sc, frame->mii_phyaddr, 5);
430 nge_mii_send(sc, frame->mii_regaddr, 5);
433 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA));
435 SIO_SET(NGE_MEAR_MII_CLK);
439 SIO_CLR(NGE_MEAR_MII_DIR);
441 SIO_CLR(NGE_MEAR_MII_CLK);
443 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
444 SIO_SET(NGE_MEAR_MII_CLK);
448 * Now try reading data bits. If the ack failed, we still
449 * need to clock through 16 cycles to keep the PHY(s) in sync.
452 for(i = 0; i < 16; i++) {
453 SIO_CLR(NGE_MEAR_MII_CLK);
455 SIO_SET(NGE_MEAR_MII_CLK);
461 for (i = 0x8000; i; i >>= 1) {
462 SIO_CLR(NGE_MEAR_MII_CLK);
465 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
466 frame->mii_data |= i;
469 SIO_SET(NGE_MEAR_MII_CLK);
474 SIO_CLR(NGE_MEAR_MII_CLK);
476 SIO_SET(NGE_MEAR_MII_CLK);
485 * Write to a PHY register through the MII.
488 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame)
491 * Set up frame for TX.
494 frame->mii_stdelim = NGE_MII_STARTDELIM;
495 frame->mii_opcode = NGE_MII_WRITEOP;
496 frame->mii_turnaround = NGE_MII_TURNAROUND;
499 * Turn on data output.
501 SIO_SET(NGE_MEAR_MII_DIR);
505 nge_mii_send(sc, frame->mii_stdelim, 2);
506 nge_mii_send(sc, frame->mii_opcode, 2);
507 nge_mii_send(sc, frame->mii_phyaddr, 5);
508 nge_mii_send(sc, frame->mii_regaddr, 5);
509 nge_mii_send(sc, frame->mii_turnaround, 2);
510 nge_mii_send(sc, frame->mii_data, 16);
513 SIO_SET(NGE_MEAR_MII_CLK);
515 SIO_CLR(NGE_MEAR_MII_CLK);
521 SIO_CLR(NGE_MEAR_MII_DIR);
527 nge_miibus_readreg(device_t dev, int phy, int reg)
529 struct nge_softc *sc = device_get_softc(dev);
530 struct nge_mii_frame frame;
532 bzero((char *)&frame, sizeof(frame));
534 frame.mii_phyaddr = phy;
535 frame.mii_regaddr = reg;
536 nge_mii_readreg(sc, &frame);
538 return(frame.mii_data);
542 nge_miibus_writereg(device_t dev, int phy, int reg, int data)
544 struct nge_softc *sc = device_get_softc(dev);
545 struct nge_mii_frame frame;
547 bzero((char *)&frame, sizeof(frame));
549 frame.mii_phyaddr = phy;
550 frame.mii_regaddr = reg;
551 frame.mii_data = data;
552 nge_mii_writereg(sc, &frame);
558 nge_miibus_statchg(device_t dev)
560 struct nge_softc *sc = device_get_softc(dev);
561 struct mii_data *mii;
565 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
567 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
568 if (status == 0 || status & NGE_TBIANAR_FDX) {
569 NGE_SETBIT(sc, NGE_TX_CFG,
570 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
571 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
573 NGE_CLRBIT(sc, NGE_TX_CFG,
574 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
575 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
577 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
579 NGE_CLRBIT(sc, NGE_TX_CFG,
580 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
581 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
583 NGE_SETBIT(sc, NGE_TX_CFG,
584 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
585 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
588 mii = device_get_softc(sc->nge_miibus);
590 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
591 NGE_SETBIT(sc, NGE_TX_CFG,
592 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
593 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
595 NGE_CLRBIT(sc, NGE_TX_CFG,
596 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
597 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
600 /* If we have a 1000Mbps link, set the mode_1000 bit. */
601 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
602 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
603 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
605 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
611 nge_setmulti(struct nge_softc *sc)
613 struct ifnet *ifp = &sc->arpcom.ac_if;
614 struct ifmultiaddr *ifma;
615 uint32_t filtsave, h = 0, i;
618 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
619 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
620 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH);
621 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
626 * We have to explicitly enable the multicast hash table
627 * on the NatSemi chip if we want to use it, which we do.
628 * We also have to tell it that we don't want to use the
629 * hash table for matching unicast addresses.
631 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
632 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
633 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH);
635 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
637 /* first, zot all the existing hash bits */
638 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
639 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
640 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
644 * From the 11 bits returned by the crc routine, the top 7
645 * bits represent the 16-bit word in the mcast hash table
646 * that needs to be updated, and the lower 4 bits represent
647 * which bit within that byte needs to be set.
649 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
650 if (ifma->ifma_addr->sa_family != AF_LINK)
652 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
653 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
654 index = (h >> 4) & 0x7F;
656 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
657 NGE_FILTADDR_MCAST_LO + (index * 2));
658 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
661 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
665 nge_reset(struct nge_softc *sc)
669 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
671 for (i = 0; i < NGE_TIMEOUT; i++) {
672 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0)
676 if (i == NGE_TIMEOUT)
677 kprintf("nge%d: reset never completed\n", sc->nge_unit);
679 /* Wait a little while for the chip to get its brains in order. */
683 * If this is a NetSemi chip, make sure to clear
686 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
687 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
691 * Probe for an NatSemi chip. Check the PCI vendor and device
692 * IDs against our list and return a device name if we find a match.
695 nge_probe(device_t dev)
698 uint16_t vendor, product;
700 vendor = pci_get_vendor(dev);
701 product = pci_get_device(dev);
703 for (t = nge_devs; t->nge_name != NULL; t++) {
704 if (vendor == t->nge_vid && product == t->nge_did) {
705 device_set_desc(dev, t->nge_name);
714 * Attach the interface. Allocate softc structures, do ifmedia
715 * setup and ethernet/BPF attach.
718 nge_attach(device_t dev)
720 struct nge_softc *sc;
722 uint8_t eaddr[ETHER_ADDR_LEN];
724 int error = 0, rid, unit;
725 const char *sep = "";
727 sc = device_get_softc(dev);
728 unit = device_get_unit(dev);
729 callout_init(&sc->nge_stat_timer);
730 lwkt_serialize_init(&sc->nge_jslot_serializer);
733 * Handle power management nonsense.
735 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF;
736 if (command == 0x01) {
737 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4);
738 if (command & NGE_PSTATE_MASK) {
739 uint32_t iobase, membase, irq;
741 /* Save important PCI config data. */
742 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
743 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
744 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
746 /* Reset the power state. */
747 kprintf("nge%d: chip is in D%d power mode "
748 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK);
749 command &= 0xFFFFFFFC;
750 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4);
752 /* Restore PCI config data. */
753 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
754 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
755 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
760 * Map control/status registers.
762 command = pci_read_config(dev, PCIR_COMMAND, 4);
763 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
764 pci_write_config(dev, PCIR_COMMAND, command, 4);
765 command = pci_read_config(dev, PCIR_COMMAND, 4);
767 #ifdef NGE_USEIOSPACE
768 if (!(command & PCIM_CMD_PORTEN)) {
769 kprintf("nge%d: failed to enable I/O ports!\n", unit);
774 if (!(command & PCIM_CMD_MEMEN)) {
775 kprintf("nge%d: failed to enable memory mapping!\n", unit);
782 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
784 if (sc->nge_res == NULL) {
785 kprintf("nge%d: couldn't map ports/memory\n", unit);
790 sc->nge_btag = rman_get_bustag(sc->nge_res);
791 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
793 /* Allocate interrupt */
795 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
796 RF_SHAREABLE | RF_ACTIVE);
798 if (sc->nge_irq == NULL) {
799 kprintf("nge%d: couldn't map interrupt\n", unit);
804 /* Reset the adapter. */
808 * Get station address from the EEPROM.
810 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1);
811 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1);
812 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1);
816 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
817 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
819 if (sc->nge_ldata == NULL) {
820 kprintf("nge%d: no memory for list buffers!\n", unit);
824 bzero(sc->nge_ldata, sizeof(struct nge_list_data));
826 /* Try to allocate memory for jumbo buffers. */
827 if (nge_alloc_jumbo_mem(sc)) {
828 kprintf("nge%d: jumbo buffer allocation failed\n",
834 ifp = &sc->arpcom.ac_if;
836 if_initname(ifp, "nge", unit);
837 ifp->if_mtu = ETHERMTU;
838 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
839 ifp->if_ioctl = nge_ioctl;
840 ifp->if_start = nge_start;
841 #ifdef DEVICE_POLLING
842 ifp->if_poll = nge_poll;
844 ifp->if_watchdog = nge_watchdog;
845 ifp->if_init = nge_init;
846 ifp->if_baudrate = 1000000000;
847 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1);
848 ifq_set_ready(&ifp->if_snd);
849 ifp->if_hwassist = NGE_CSUM_FEATURES;
850 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING;
851 ifp->if_capenable = ifp->if_capabilities;
856 if (mii_phy_probe(dev, &sc->nge_miibus,
857 nge_ifmedia_upd, nge_ifmedia_sts)) {
858 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
860 device_printf(dev, "Using TBI\n");
862 sc->nge_miibus = dev;
864 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
866 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
867 #define PRINT(s) kprintf("%s%s", sep, s); sep = ", "
868 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
869 device_printf(dev, " ");
870 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
872 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
873 PRINT("1000baseSX-FDX");
874 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
880 ifmedia_set(&sc->nge_ifmedia,
881 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
883 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
885 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
886 | NGE_GPIO_GP3_OUTENB
887 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
890 kprintf("nge%d: MII without any PHY!\n", sc->nge_unit);
897 * Call MI attach routine.
899 ether_ifattach(ifp, eaddr, NULL);
901 error = bus_setup_intr(dev, sc->nge_irq, INTR_NETSAFE,
902 nge_intr, sc, &sc->nge_intrhand,
906 device_printf(dev, "couldn't set up irq\n");
917 nge_detach(device_t dev)
919 struct nge_softc *sc = device_get_softc(dev);
920 struct ifnet *ifp = &sc->arpcom.ac_if;
922 if (device_is_attached(dev)) {
923 lwkt_serialize_enter(ifp->if_serializer);
926 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
927 lwkt_serialize_exit(ifp->if_serializer);
933 device_delete_child(dev, sc->nge_miibus);
934 bus_generic_detach(dev);
937 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
939 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
941 contigfree(sc->nge_ldata, sizeof(struct nge_list_data),
944 if (sc->nge_cdata.nge_jumbo_buf)
945 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
951 * Initialize the transmit descriptors.
954 nge_list_tx_init(struct nge_softc *sc)
956 struct nge_list_data *ld;
957 struct nge_ring_data *cd;
963 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
964 if (i == (NGE_TX_LIST_CNT - 1)) {
965 ld->nge_tx_list[i].nge_nextdesc =
967 ld->nge_tx_list[i].nge_next =
968 vtophys(&ld->nge_tx_list[0]);
970 ld->nge_tx_list[i].nge_nextdesc =
971 &ld->nge_tx_list[i + 1];
972 ld->nge_tx_list[i].nge_next =
973 vtophys(&ld->nge_tx_list[i + 1]);
975 ld->nge_tx_list[i].nge_mbuf = NULL;
976 ld->nge_tx_list[i].nge_ptr = 0;
977 ld->nge_tx_list[i].nge_ctl = 0;
980 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
987 * Initialize the RX descriptors and allocate mbufs for them. Note that
988 * we arrange the descriptors in a closed ring, so that the last descriptor
989 * points back to the first.
992 nge_list_rx_init(struct nge_softc *sc)
994 struct nge_list_data *ld;
995 struct nge_ring_data *cd;
1001 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1002 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1004 if (i == (NGE_RX_LIST_CNT - 1)) {
1005 ld->nge_rx_list[i].nge_nextdesc =
1006 &ld->nge_rx_list[0];
1007 ld->nge_rx_list[i].nge_next =
1008 vtophys(&ld->nge_rx_list[0]);
1010 ld->nge_rx_list[i].nge_nextdesc =
1011 &ld->nge_rx_list[i + 1];
1012 ld->nge_rx_list[i].nge_next =
1013 vtophys(&ld->nge_rx_list[i + 1]);
1017 cd->nge_rx_prod = 0;
1023 * Initialize an RX descriptor and attach an MBUF cluster.
1026 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m)
1028 struct mbuf *m_new = NULL;
1029 struct nge_jslot *buf;
1032 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1033 if (m_new == NULL) {
1034 kprintf("nge%d: no memory for rx list "
1035 "-- packet dropped!\n", sc->nge_unit);
1039 /* Allocate the jumbo buffer */
1040 buf = nge_jalloc(sc);
1043 kprintf("nge%d: jumbo allocation failed "
1044 "-- packet dropped!\n", sc->nge_unit);
1049 /* Attach the buffer to the mbuf */
1050 m_new->m_ext.ext_arg = buf;
1051 m_new->m_ext.ext_buf = buf->nge_buf;
1052 m_new->m_ext.ext_free = nge_jfree;
1053 m_new->m_ext.ext_ref = nge_jref;
1054 m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN;
1056 m_new->m_data = m_new->m_ext.ext_buf;
1057 m_new->m_flags |= M_EXT;
1058 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1061 m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN;
1062 m_new->m_data = m_new->m_ext.ext_buf;
1065 m_adj(m_new, sizeof(uint64_t));
1067 c->nge_mbuf = m_new;
1068 c->nge_ptr = vtophys(mtod(m_new, caddr_t));
1069 c->nge_ctl = m_new->m_len;
1076 nge_alloc_jumbo_mem(struct nge_softc *sc)
1080 struct nge_jslot *entry;
1082 /* Grab a big chunk o' storage. */
1083 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
1084 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1086 if (sc->nge_cdata.nge_jumbo_buf == NULL) {
1087 kprintf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
1091 SLIST_INIT(&sc->nge_jfree_listhead);
1094 * Now divide it up into 9K pieces and save the addresses
1097 ptr = sc->nge_cdata.nge_jumbo_buf;
1098 for (i = 0; i < NGE_JSLOTS; i++) {
1099 entry = &sc->nge_cdata.nge_jslots[i];
1101 entry->nge_buf = ptr;
1102 entry->nge_inuse = 0;
1103 entry->nge_slot = i;
1104 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link);
1113 * Allocate a jumbo buffer.
1115 static struct nge_jslot *
1116 nge_jalloc(struct nge_softc *sc)
1118 struct nge_jslot *entry;
1120 lwkt_serialize_enter(&sc->nge_jslot_serializer);
1121 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1123 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link);
1124 entry->nge_inuse = 1;
1127 kprintf("nge%d: no free jumbo buffers\n", sc->nge_unit);
1130 lwkt_serialize_exit(&sc->nge_jslot_serializer);
1135 * Adjust usage count on a jumbo buffer. In general this doesn't
1136 * get used much because our jumbo buffers don't get passed around
1137 * a lot, but it's implemented for correctness.
1142 struct nge_jslot *entry = (struct nge_jslot *)arg;
1143 struct nge_softc *sc = entry->nge_sc;
1146 panic("nge_jref: can't find softc pointer!");
1148 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry)
1149 panic("nge_jref: asked to reference buffer "
1150 "that we don't manage!");
1151 else if (entry->nge_inuse == 0)
1152 panic("nge_jref: buffer already free!");
1154 atomic_add_int(&entry->nge_inuse, 1);
1158 * Release a jumbo buffer.
1161 nge_jfree(void *arg)
1163 struct nge_jslot *entry = (struct nge_jslot *)arg;
1164 struct nge_softc *sc = entry->nge_sc;
1167 panic("nge_jref: can't find softc pointer!");
1169 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) {
1170 panic("nge_jref: asked to reference buffer "
1171 "that we don't manage!");
1172 } else if (entry->nge_inuse == 0) {
1173 panic("nge_jref: buffer already free!");
1175 lwkt_serialize_enter(&sc->nge_jslot_serializer);
1176 atomic_subtract_int(&entry->nge_inuse, 1);
1177 if (entry->nge_inuse == 0) {
1178 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
1181 lwkt_serialize_exit(&sc->nge_jslot_serializer);
1185 * A frame has been uploaded: pass the resulting mbuf chain up to
1186 * the higher level protocols.
1189 nge_rxeof(struct nge_softc *sc)
1192 struct ifnet *ifp = &sc->arpcom.ac_if;
1193 struct nge_desc *cur_rx;
1194 int i, total_len = 0;
1197 i = sc->nge_cdata.nge_rx_prod;
1199 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1200 struct mbuf *m0 = NULL;
1203 #ifdef DEVICE_POLLING
1204 if (ifp->if_flags & IFF_POLLING) {
1205 if (sc->rxcycles <= 0)
1209 #endif /* DEVICE_POLLING */
1211 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1212 rxstat = cur_rx->nge_rxstat;
1213 extsts = cur_rx->nge_extsts;
1214 m = cur_rx->nge_mbuf;
1215 cur_rx->nge_mbuf = NULL;
1216 total_len = NGE_RXBYTES(cur_rx);
1217 NGE_INC(i, NGE_RX_LIST_CNT);
1219 * If an error occurs, update stats, clear the
1220 * status word and leave the mbuf cluster in place:
1221 * it should simply get re-used next time this descriptor
1222 * comes up in the ring.
1224 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) {
1226 nge_newbuf(sc, cur_rx, m);
1231 * Ok. NatSemi really screwed up here. This is the
1232 * only gigE chip I know of with alignment constraints
1233 * on receive buffers. RX buffers must be 64-bit aligned.
1237 * By popular demand, ignore the alignment problems
1238 * on the Intel x86 platform. The performance hit
1239 * incurred due to unaligned accesses is much smaller
1240 * than the hit produced by forcing buffer copies all
1241 * the time, especially with jumbo frames. We still
1242 * need to fix up the alignment everywhere else though.
1244 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
1246 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1247 total_len + ETHER_ALIGN, 0, ifp, NULL);
1248 nge_newbuf(sc, cur_rx, m);
1250 kprintf("nge%d: no receive buffers "
1251 "available -- packet dropped!\n",
1256 m_adj(m0, ETHER_ALIGN);
1260 m->m_pkthdr.rcvif = ifp;
1261 m->m_pkthdr.len = m->m_len = total_len;
1267 /* Do IP checksum checking. */
1268 if (extsts & NGE_RXEXTSTS_IPPKT)
1269 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1270 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1271 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1272 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1273 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) ||
1274 (extsts & NGE_RXEXTSTS_UDPPKT &&
1275 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) {
1276 m->m_pkthdr.csum_flags |=
1277 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1278 m->m_pkthdr.csum_data = 0xffff;
1282 * If we received a packet with a vlan tag, pass it
1283 * to vlan_input() instead of ether_input().
1285 if (extsts & NGE_RXEXTSTS_VLANPKT)
1286 VLAN_INPUT_TAG(m, extsts & NGE_RXEXTSTS_VTCI);
1288 ifp->if_input(ifp, m);
1291 sc->nge_cdata.nge_rx_prod = i;
1295 * A frame was downloaded to the chip. It's safe for us to clean up
1299 nge_txeof(struct nge_softc *sc)
1301 struct ifnet *ifp = &sc->arpcom.ac_if;
1302 struct nge_desc *cur_tx = NULL;
1305 /* Clear the timeout timer. */
1309 * Go through our tx list and free mbufs for those
1310 * frames that have been transmitted.
1312 idx = sc->nge_cdata.nge_tx_cons;
1313 while (idx != sc->nge_cdata.nge_tx_prod) {
1314 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1316 if (NGE_OWNDESC(cur_tx))
1319 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1320 sc->nge_cdata.nge_tx_cnt--;
1321 NGE_INC(idx, NGE_TX_LIST_CNT);
1325 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1327 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1328 ifp->if_collisions++;
1329 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1330 ifp->if_collisions++;
1333 ifp->if_collisions +=
1334 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1337 if (cur_tx->nge_mbuf != NULL) {
1338 m_freem(cur_tx->nge_mbuf);
1339 cur_tx->nge_mbuf = NULL;
1342 sc->nge_cdata.nge_tx_cnt--;
1343 NGE_INC(idx, NGE_TX_LIST_CNT);
1347 sc->nge_cdata.nge_tx_cons = idx;
1350 ifp->if_flags &= ~IFF_OACTIVE;
1356 struct nge_softc *sc = xsc;
1357 struct ifnet *ifp = &sc->arpcom.ac_if;
1358 struct mii_data *mii;
1360 lwkt_serialize_enter(ifp->if_serializer);
1363 if (sc->nge_link == 0) {
1364 if (CSR_READ_4(sc, NGE_TBI_BMSR)
1365 & NGE_TBIBMSR_ANEG_DONE) {
1366 kprintf("nge%d: gigabit link up\n",
1368 nge_miibus_statchg(sc->nge_miibus);
1370 if (!ifq_is_empty(&ifp->if_snd))
1375 mii = device_get_softc(sc->nge_miibus);
1378 if (sc->nge_link == 0) {
1379 if (mii->mii_media_status & IFM_ACTIVE &&
1380 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1382 if (IFM_SUBTYPE(mii->mii_media_active)
1384 kprintf("nge%d: gigabit link up\n",
1386 if (!ifq_is_empty(&ifp->if_snd))
1391 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1393 lwkt_serialize_exit(ifp->if_serializer);
1396 #ifdef DEVICE_POLLING
1399 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1401 struct nge_softc *sc = ifp->if_softc;
1405 /* disable interrupts */
1406 CSR_WRITE_4(sc, NGE_IER, 0);
1408 case POLL_DEREGISTER:
1409 /* enable interrupts */
1410 CSR_WRITE_4(sc, NGE_IER, 1);
1414 * On the nge, reading the status register also clears it.
1415 * So before returning to intr mode we must make sure that all
1416 * possible pending sources of interrupts have been served.
1417 * In practice this means run to completion the *eof routines,
1418 * and then call the interrupt routine
1420 sc->rxcycles = count;
1423 if (!ifq_is_empty(&ifp->if_snd))
1426 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1429 /* Reading the ISR register clears all interrupts. */
1430 status = CSR_READ_4(sc, NGE_ISR);
1432 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1435 if (status & (NGE_ISR_RX_IDLE))
1436 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1438 if (status & NGE_ISR_SYSERR) {
1447 #endif /* DEVICE_POLLING */
1452 struct nge_softc *sc = arg;
1453 struct ifnet *ifp = &sc->arpcom.ac_if;
1456 /* Supress unwanted interrupts */
1457 if (!(ifp->if_flags & IFF_UP)) {
1462 /* Disable interrupts. */
1463 CSR_WRITE_4(sc, NGE_IER, 0);
1465 /* Data LED on for TBI mode */
1467 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1468 | NGE_GPIO_GP3_OUT);
1471 /* Reading the ISR register clears all interrupts. */
1472 status = CSR_READ_4(sc, NGE_ISR);
1474 if ((status & NGE_INTRS) == 0)
1477 if ((status & NGE_ISR_TX_DESC_OK) ||
1478 (status & NGE_ISR_TX_ERR) ||
1479 (status & NGE_ISR_TX_OK) ||
1480 (status & NGE_ISR_TX_IDLE))
1483 if ((status & NGE_ISR_RX_DESC_OK) ||
1484 (status & NGE_ISR_RX_ERR) ||
1485 (status & NGE_ISR_RX_OFLOW) ||
1486 (status & NGE_ISR_RX_FIFO_OFLOW) ||
1487 (status & NGE_ISR_RX_IDLE) ||
1488 (status & NGE_ISR_RX_OK))
1491 if ((status & NGE_ISR_RX_IDLE))
1492 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1494 if (status & NGE_ISR_SYSERR) {
1496 ifp->if_flags &= ~IFF_RUNNING;
1501 /* mii_tick should only be called once per second */
1502 if (status & NGE_ISR_PHY_INTR) {
1504 nge_tick_serialized(sc);
1509 /* Re-enable interrupts. */
1510 CSR_WRITE_4(sc, NGE_IER, 1);
1512 if (!ifq_is_empty(&ifp->if_snd))
1515 /* Data LED off for TBI mode */
1518 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1519 & ~NGE_GPIO_GP3_OUT);
1523 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1524 * pointers to the fragment pointers.
1527 nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1529 struct nge_desc *f = NULL;
1531 int frag, cur, cnt = 0;
1532 struct ifvlan *ifv = NULL;
1534 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1535 m_head->m_pkthdr.rcvif != NULL &&
1536 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1537 ifv = m_head->m_pkthdr.rcvif->if_softc;
1540 * Start packing the mbufs in this chain into
1541 * the fragment pointers. Stop when we run out
1542 * of fragments or hit the end of the mbuf chain.
1545 cur = frag = *txidx;
1547 for (m = m_head; m != NULL; m = m->m_next) {
1548 if (m->m_len != 0) {
1549 if ((NGE_TX_LIST_CNT -
1550 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1552 f = &sc->nge_ldata->nge_tx_list[frag];
1553 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1554 f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1556 f->nge_ctl |= NGE_CMDSTS_OWN;
1558 NGE_INC(frag, NGE_TX_LIST_CNT);
1566 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1567 if (m_head->m_pkthdr.csum_flags) {
1568 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1569 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1570 NGE_TXEXTSTS_IPCSUM;
1571 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1572 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1573 NGE_TXEXTSTS_TCPCSUM;
1574 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1575 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1576 NGE_TXEXTSTS_UDPCSUM;
1580 sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1581 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag);
1584 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1585 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1586 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1587 sc->nge_cdata.nge_tx_cnt += cnt;
1594 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1595 * to the mbuf data regions directly in the transmit lists. We also save a
1596 * copy of the pointers since the transmit list fragment pointers are
1597 * physical addresses.
1601 nge_start(struct ifnet *ifp)
1603 struct nge_softc *sc = ifp->if_softc;
1604 struct mbuf *m_head = NULL;
1611 idx = sc->nge_cdata.nge_tx_prod;
1613 if (ifp->if_flags & IFF_OACTIVE)
1617 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1618 m_head = ifq_poll(&ifp->if_snd);
1622 if (nge_encap(sc, m_head, &idx)) {
1623 ifp->if_flags |= IFF_OACTIVE;
1626 ifq_dequeue(&ifp->if_snd, m_head);
1629 BPF_MTAP(ifp, m_head);
1636 sc->nge_cdata.nge_tx_prod = idx;
1637 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1640 * Set a timeout in case the chip goes out to lunch.
1648 struct nge_softc *sc = xsc;
1649 struct ifnet *ifp = &sc->arpcom.ac_if;
1650 struct mii_data *mii;
1652 if (ifp->if_flags & IFF_RUNNING) {
1657 * Cancel pending I/O and free all RX/TX buffers.
1660 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1665 mii = device_get_softc(sc->nge_miibus);
1667 /* Set MAC address */
1668 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1669 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1670 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1671 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1672 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1673 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1674 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1675 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1676 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1678 /* Init circular RX list. */
1679 if (nge_list_rx_init(sc) == ENOBUFS) {
1680 kprintf("nge%d: initialization failed: no "
1681 "memory for rx buffers\n", sc->nge_unit);
1687 * Init tx descriptors.
1689 nge_list_tx_init(sc);
1692 * For the NatSemi chip, we have to explicitly enable the
1693 * reception of ARP frames, as well as turn on the 'perfect
1694 * match' filter where we store the station address, otherwise
1695 * we won't receive unicasts meant for this host.
1697 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1698 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1700 /* If we want promiscuous mode, set the allframes bit. */
1701 if (ifp->if_flags & IFF_PROMISC)
1702 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1704 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1707 * Set the capture broadcast bit to capture broadcast frames.
1709 if (ifp->if_flags & IFF_BROADCAST)
1710 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1712 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1715 * Load the multicast filter.
1719 /* Turn the receive filter on */
1720 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1723 * Load the address of the RX and TX lists.
1725 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1726 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1727 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1728 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1730 /* Set RX configuration */
1731 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1733 * Enable hardware checksum validation for all IPv4
1734 * packets, do not reject packets with bad checksums.
1736 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1739 * Tell the chip to detect and strip VLAN tag info from
1740 * received frames. The tag will be provided in the extsts
1741 * field in the RX descriptors.
1743 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1744 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1746 /* Set TX configuration */
1747 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1750 * Enable TX IPv4 checksumming on a per-packet basis.
1752 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1755 * Tell the chip to insert VLAN tags on a per-packet basis as
1756 * dictated by the code in the frame encapsulation routine.
1758 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1760 /* Set full/half duplex mode. */
1762 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1764 NGE_SETBIT(sc, NGE_TX_CFG,
1765 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1766 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1768 NGE_CLRBIT(sc, NGE_TX_CFG,
1769 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1770 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1773 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1774 NGE_SETBIT(sc, NGE_TX_CFG,
1775 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1776 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1778 NGE_CLRBIT(sc, NGE_TX_CFG,
1779 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1780 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1785 * Enable the delivery of PHY interrupts based on
1786 * link/speed/duplex status changes. Also enable the
1787 * extsts field in the DMA descriptors (needed for
1788 * TCP/IP checksum offload on transmit).
1790 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD |
1791 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB);
1794 * Configure interrupt holdoff (moderation). We can
1795 * have the chip delay interrupt delivery for a certain
1796 * period. Units are in 100us, and the max setting
1797 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1799 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1802 * Enable interrupts.
1804 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1805 #ifdef DEVICE_POLLING
1807 * ... only enable interrupts if we are not polling, make sure
1808 * they are off otherwise.
1810 if (ifp->if_flags & IFF_POLLING)
1811 CSR_WRITE_4(sc, NGE_IER, 0);
1813 #endif /* DEVICE_POLLING */
1814 CSR_WRITE_4(sc, NGE_IER, 1);
1816 /* Enable receiver and transmitter. */
1817 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE);
1818 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1820 nge_ifmedia_upd(ifp);
1822 ifp->if_flags |= IFF_RUNNING;
1823 ifp->if_flags &= ~IFF_OACTIVE;
1827 * Set media options.
1830 nge_ifmedia_upd(struct ifnet *ifp)
1832 struct nge_softc *sc = ifp->if_softc;
1833 struct mii_data *mii;
1836 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1838 CSR_WRITE_4(sc, NGE_TBI_ANAR,
1839 CSR_READ_4(sc, NGE_TBI_ANAR)
1840 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1841 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1842 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1843 | NGE_TBIBMCR_RESTART_ANEG);
1844 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1845 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1846 & IFM_GMASK) == IFM_FDX) {
1847 NGE_SETBIT(sc, NGE_TX_CFG,
1848 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1849 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1851 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1852 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1854 NGE_CLRBIT(sc, NGE_TX_CFG,
1855 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1856 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1858 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1859 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1862 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1863 & ~NGE_GPIO_GP3_OUT);
1865 mii = device_get_softc(sc->nge_miibus);
1867 if (mii->mii_instance) {
1868 struct mii_softc *miisc;
1869 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1870 miisc = LIST_NEXT(miisc, mii_list))
1871 mii_phy_reset(miisc);
1880 * Report current media status.
1883 nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1885 struct nge_softc *sc = ifp->if_softc;
1886 struct mii_data *mii;
1889 ifmr->ifm_status = IFM_AVALID;
1890 ifmr->ifm_active = IFM_ETHER;
1892 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)
1893 ifmr->ifm_status |= IFM_ACTIVE;
1894 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1895 ifmr->ifm_active |= IFM_LOOP;
1896 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
1897 ifmr->ifm_active |= IFM_NONE;
1898 ifmr->ifm_status = 0;
1901 ifmr->ifm_active |= IFM_1000_SX;
1902 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1904 ifmr->ifm_active |= IFM_AUTO;
1905 if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1906 & NGE_TBIANAR_FDX) {
1907 ifmr->ifm_active |= IFM_FDX;
1908 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1909 & NGE_TBIANAR_HDX) {
1910 ifmr->ifm_active |= IFM_HDX;
1912 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1914 ifmr->ifm_active |= IFM_FDX;
1916 ifmr->ifm_active |= IFM_HDX;
1919 mii = device_get_softc(sc->nge_miibus);
1921 ifmr->ifm_active = mii->mii_media_active;
1922 ifmr->ifm_status = mii->mii_media_status;
1927 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1929 struct nge_softc *sc = ifp->if_softc;
1930 struct ifreq *ifr = (struct ifreq *) data;
1931 struct mii_data *mii;
1936 if (ifr->ifr_mtu > NGE_JUMBO_MTU) {
1939 ifp->if_mtu = ifr->ifr_mtu;
1941 * Workaround: if the MTU is larger than
1942 * 8152 (TX FIFO size minus 64 minus 18), turn off
1943 * TX checksum offloading.
1945 if (ifr->ifr_mtu >= 8152)
1946 ifp->if_hwassist = 0;
1948 ifp->if_hwassist = NGE_CSUM_FEATURES;
1952 if (ifp->if_flags & IFF_UP) {
1953 if (ifp->if_flags & IFF_RUNNING &&
1954 ifp->if_flags & IFF_PROMISC &&
1955 !(sc->nge_if_flags & IFF_PROMISC)) {
1956 NGE_SETBIT(sc, NGE_RXFILT_CTL,
1957 NGE_RXFILTCTL_ALLPHYS|
1958 NGE_RXFILTCTL_ALLMULTI);
1959 } else if (ifp->if_flags & IFF_RUNNING &&
1960 !(ifp->if_flags & IFF_PROMISC) &&
1961 sc->nge_if_flags & IFF_PROMISC) {
1962 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
1963 NGE_RXFILTCTL_ALLPHYS);
1964 if (!(ifp->if_flags & IFF_ALLMULTI))
1965 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
1966 NGE_RXFILTCTL_ALLMULTI);
1968 ifp->if_flags &= ~IFF_RUNNING;
1972 if (ifp->if_flags & IFF_RUNNING)
1975 sc->nge_if_flags = ifp->if_flags;
1986 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
1989 mii = device_get_softc(sc->nge_miibus);
1990 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1995 error = ether_ioctl(ifp, command, data);
2002 nge_watchdog(struct ifnet *ifp)
2004 struct nge_softc *sc = ifp->if_softc;
2007 kprintf("nge%d: watchdog timeout\n", sc->nge_unit);
2011 ifp->if_flags &= ~IFF_RUNNING;
2014 if (!ifq_is_empty(&ifp->if_snd))
2019 * Stop the adapter and free any mbufs allocated to the
2023 nge_stop(struct nge_softc *sc)
2025 struct ifnet *ifp = &sc->arpcom.ac_if;
2026 struct ifmedia_entry *ifm;
2027 struct mii_data *mii;
2028 int i, itmp, mtmp, dtmp;
2034 mii = device_get_softc(sc->nge_miibus);
2036 callout_stop(&sc->nge_stat_timer);
2037 CSR_WRITE_4(sc, NGE_IER, 0);
2038 CSR_WRITE_4(sc, NGE_IMR, 0);
2039 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2041 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2042 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2045 * Isolate/power down the PHY, but leave the media selection
2046 * unchanged so that things will be put back to normal when
2047 * we bring the interface back up.
2049 itmp = ifp->if_flags;
2050 ifp->if_flags |= IFF_UP;
2053 ifm = sc->nge_ifmedia.ifm_cur;
2055 ifm = mii->mii_media.ifm_cur;
2057 mtmp = ifm->ifm_media;
2058 dtmp = ifm->ifm_data;
2059 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2060 ifm->ifm_data = MII_MEDIA_NONE;
2064 ifm->ifm_media = mtmp;
2065 ifm->ifm_data = dtmp;
2066 ifp->if_flags = itmp;
2071 * Free data in the RX lists.
2073 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2074 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2075 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2076 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2079 bzero(&sc->nge_ldata->nge_rx_list,
2080 sizeof(sc->nge_ldata->nge_rx_list));
2083 * Free the TX list buffers.
2085 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2086 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2087 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2088 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2092 bzero(&sc->nge_ldata->nge_tx_list,
2093 sizeof(sc->nge_ldata->nge_tx_list));
2095 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2099 * Stop all chip I/O so that the kernel's probe routines don't
2100 * get confused by errant DMAs when rebooting.
2103 nge_shutdown(device_t dev)
2105 struct nge_softc *sc = device_get_softc(dev);
2106 struct ifnet *ifp = &sc->arpcom.ac_if;
2108 lwkt_serialize_enter(ifp->if_serializer);
2111 lwkt_serialize_exit(ifp->if_serializer);