2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
28 * $DragonFly: src/sys/dev/netif/jme/if_jme.c,v 1.12 2008/11/26 11:55:18 sephe Exp $
31 #include "opt_polling.h"
35 #include <sys/param.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
39 #include <sys/interrupt.h>
40 #include <sys/malloc.h>
43 #include <sys/serialize.h>
44 #include <sys/socket.h>
45 #include <sys/sockio.h>
46 #include <sys/sysctl.h>
48 #include <net/ethernet.h>
51 #include <net/if_arp.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/ifq_var.h>
55 #include <net/toeplitz.h>
56 #include <net/toeplitz2.h>
57 #include <net/vlan/if_vlan_var.h>
58 #include <net/vlan/if_vlan_ether.h>
60 #include <netinet/in.h>
62 #include <dev/netif/mii_layer/miivar.h>
63 #include <dev/netif/mii_layer/jmphyreg.h>
65 #include <bus/pci/pcireg.h>
66 #include <bus/pci/pcivar.h>
67 #include <bus/pci/pcidevs.h>
69 #include <dev/netif/jme/if_jmereg.h>
70 #include <dev/netif/jme/if_jmevar.h>
72 #include "miibus_if.h"
74 /* Define the following to disable printing Rx errors. */
75 #undef JME_SHOW_ERRORS
77 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
80 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
82 if ((sc)->jme_rss_debug >= (lvl)) \
83 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
85 #else /* !JME_RSS_DEBUG */
86 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
87 #endif /* JME_RSS_DEBUG */
89 static int jme_probe(device_t);
90 static int jme_attach(device_t);
91 static int jme_detach(device_t);
92 static int jme_shutdown(device_t);
93 static int jme_suspend(device_t);
94 static int jme_resume(device_t);
96 static int jme_miibus_readreg(device_t, int, int);
97 static int jme_miibus_writereg(device_t, int, int, int);
98 static void jme_miibus_statchg(device_t);
100 static void jme_init(void *);
101 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
102 static void jme_start(struct ifnet *);
103 static void jme_watchdog(struct ifnet *);
104 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
105 static int jme_mediachange(struct ifnet *);
106 #ifdef DEVICE_POLLING
107 static void jme_poll(struct ifnet *, enum poll_cmd, int);
110 static void jme_intr(void *);
111 static void jme_txeof(struct jme_softc *);
112 static void jme_rxeof(struct jme_softc *, int);
113 static int jme_rxeof_chain(struct jme_softc *, int,
114 struct mbuf_chain *, int);
115 static void jme_rx_intr(struct jme_softc *, uint32_t);
117 static int jme_dma_alloc(struct jme_softc *);
118 static void jme_dma_free(struct jme_softc *);
119 static int jme_init_rx_ring(struct jme_softc *, int);
120 static void jme_init_tx_ring(struct jme_softc *);
121 static void jme_init_ssb(struct jme_softc *);
122 static int jme_newbuf(struct jme_softc *, int, struct jme_rxdesc *, int);
123 static int jme_encap(struct jme_softc *, struct mbuf **);
124 static void jme_rxpkt(struct jme_softc *, int, struct mbuf_chain *);
125 static int jme_rxring_dma_alloc(struct jme_softc *, int);
126 static int jme_rxbuf_dma_alloc(struct jme_softc *, int);
128 static void jme_tick(void *);
129 static void jme_stop(struct jme_softc *);
130 static void jme_reset(struct jme_softc *);
131 static void jme_set_vlan(struct jme_softc *);
132 static void jme_set_filter(struct jme_softc *);
133 static void jme_stop_tx(struct jme_softc *);
134 static void jme_stop_rx(struct jme_softc *);
135 static void jme_mac_config(struct jme_softc *);
136 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
137 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
138 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
140 static void jme_setwol(struct jme_softc *);
141 static void jme_setlinkspeed(struct jme_softc *);
143 static void jme_set_tx_coal(struct jme_softc *);
144 static void jme_set_rx_coal(struct jme_softc *);
145 static void jme_enable_rss(struct jme_softc *);
146 static void jme_disable_rss(struct jme_softc *);
148 static void jme_sysctl_node(struct jme_softc *);
149 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
150 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
151 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
152 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
155 * Devices supported by this driver.
157 static const struct jme_dev {
158 uint16_t jme_vendorid;
159 uint16_t jme_deviceid;
161 const char *jme_name;
163 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
165 "JMicron Inc, JMC250 Gigabit Ethernet" },
166 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
168 "JMicron Inc, JMC260 Fast Ethernet" },
172 static device_method_t jme_methods[] = {
173 /* Device interface. */
174 DEVMETHOD(device_probe, jme_probe),
175 DEVMETHOD(device_attach, jme_attach),
176 DEVMETHOD(device_detach, jme_detach),
177 DEVMETHOD(device_shutdown, jme_shutdown),
178 DEVMETHOD(device_suspend, jme_suspend),
179 DEVMETHOD(device_resume, jme_resume),
182 DEVMETHOD(bus_print_child, bus_generic_print_child),
183 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
186 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
187 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
188 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
193 static driver_t jme_driver = {
196 sizeof(struct jme_softc)
199 static devclass_t jme_devclass;
201 DECLARE_DUMMY_MODULE(if_jme);
202 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
203 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, 0, 0);
204 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0);
206 static const struct {
209 } jme_rx_status[JME_NRXRING_MAX] = {
210 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP },
211 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP },
212 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP },
213 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP }
216 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
217 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
218 static int jme_rx_ring_count = JME_NRXRING_DEF;
220 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
221 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
222 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
225 * Read a PHY register on the MII of the JMC250.
228 jme_miibus_readreg(device_t dev, int phy, int reg)
230 struct jme_softc *sc = device_get_softc(dev);
234 /* For FPGA version, PHY address 0 should be ignored. */
235 if (sc->jme_caps & JME_CAP_FPGA) {
239 if (sc->jme_phyaddr != phy)
243 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
244 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
246 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
248 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
252 device_printf(sc->jme_dev, "phy read timeout: "
253 "phy %d, reg %d\n", phy, reg);
257 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
261 * Write a PHY register on the MII of the JMC250.
264 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
266 struct jme_softc *sc = device_get_softc(dev);
269 /* For FPGA version, PHY address 0 should be ignored. */
270 if (sc->jme_caps & JME_CAP_FPGA) {
274 if (sc->jme_phyaddr != phy)
278 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
279 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
280 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
282 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
284 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
288 device_printf(sc->jme_dev, "phy write timeout: "
289 "phy %d, reg %d\n", phy, reg);
296 * Callback from MII layer when media changes.
299 jme_miibus_statchg(device_t dev)
301 struct jme_softc *sc = device_get_softc(dev);
302 struct ifnet *ifp = &sc->arpcom.ac_if;
303 struct mii_data *mii;
304 struct jme_txdesc *txd;
308 ASSERT_SERIALIZED(ifp->if_serializer);
310 if ((ifp->if_flags & IFF_RUNNING) == 0)
313 mii = device_get_softc(sc->jme_miibus);
315 sc->jme_flags &= ~JME_FLAG_LINK;
316 if ((mii->mii_media_status & IFM_AVALID) != 0) {
317 switch (IFM_SUBTYPE(mii->mii_media_active)) {
320 sc->jme_flags |= JME_FLAG_LINK;
323 if (sc->jme_caps & JME_CAP_FASTETH)
325 sc->jme_flags |= JME_FLAG_LINK;
333 * Disabling Rx/Tx MACs have a side-effect of resetting
334 * JME_TXNDA/JME_RXNDA register to the first address of
335 * Tx/Rx descriptor address. So driver should reset its
336 * internal procucer/consumer pointer and reclaim any
337 * allocated resources. Note, just saving the value of
338 * JME_TXNDA and JME_RXNDA registers before stopping MAC
339 * and restoring JME_TXNDA/JME_RXNDA register is not
340 * sufficient to make sure correct MAC state because
341 * stopping MAC operation can take a while and hardware
342 * might have updated JME_TXNDA/JME_RXNDA registers
343 * during the stop operation.
346 /* Disable interrupts */
347 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
350 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
352 callout_stop(&sc->jme_tick_ch);
354 /* Stop receiver/transmitter. */
358 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
359 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
362 if (rdata->jme_rxhead != NULL)
363 m_freem(rdata->jme_rxhead);
364 JME_RXCHAIN_RESET(sc, r);
367 * Reuse configured Rx descriptors and reset
368 * procuder/consumer index.
370 rdata->jme_rx_cons = 0;
374 if (sc->jme_cdata.jme_tx_cnt != 0) {
375 /* Remove queued packets for transmit. */
376 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
377 txd = &sc->jme_cdata.jme_txdesc[i];
378 if (txd->tx_m != NULL) {
380 sc->jme_cdata.jme_tx_tag,
389 jme_init_tx_ring(sc);
391 /* Initialize shadow status block. */
394 /* Program MAC with resolved speed/duplex/flow-control. */
395 if (sc->jme_flags & JME_FLAG_LINK) {
398 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
400 /* Set Tx ring address to the hardware. */
401 paddr = sc->jme_cdata.jme_tx_ring_paddr;
402 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
403 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
405 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
406 CSR_WRITE_4(sc, JME_RXCSR,
407 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
409 /* Set Rx ring address to the hardware. */
410 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
411 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
412 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
415 /* Restart receiver/transmitter. */
416 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
418 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
421 ifp->if_flags |= IFF_RUNNING;
422 ifp->if_flags &= ~IFF_OACTIVE;
423 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
425 #ifdef DEVICE_POLLING
426 if (!(ifp->if_flags & IFF_POLLING))
428 /* Reenable interrupts. */
429 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
433 * Get the current interface media status.
436 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
438 struct jme_softc *sc = ifp->if_softc;
439 struct mii_data *mii = device_get_softc(sc->jme_miibus);
441 ASSERT_SERIALIZED(ifp->if_serializer);
444 ifmr->ifm_status = mii->mii_media_status;
445 ifmr->ifm_active = mii->mii_media_active;
449 * Set hardware to newly-selected media.
452 jme_mediachange(struct ifnet *ifp)
454 struct jme_softc *sc = ifp->if_softc;
455 struct mii_data *mii = device_get_softc(sc->jme_miibus);
458 ASSERT_SERIALIZED(ifp->if_serializer);
460 if (mii->mii_instance != 0) {
461 struct mii_softc *miisc;
463 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
464 mii_phy_reset(miisc);
466 error = mii_mediachg(mii);
472 jme_probe(device_t dev)
474 const struct jme_dev *sp;
477 vid = pci_get_vendor(dev);
478 did = pci_get_device(dev);
479 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
480 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
481 struct jme_softc *sc = device_get_softc(dev);
483 sc->jme_caps = sp->jme_caps;
484 device_set_desc(dev, sp->jme_name);
492 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
498 for (i = JME_TIMEOUT; i > 0; i--) {
499 reg = CSR_READ_4(sc, JME_SMBCSR);
500 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
506 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
510 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
511 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
512 for (i = JME_TIMEOUT; i > 0; i--) {
514 reg = CSR_READ_4(sc, JME_SMBINTF);
515 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
520 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
524 reg = CSR_READ_4(sc, JME_SMBINTF);
525 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
531 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
533 uint8_t fup, reg, val;
538 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
539 fup != JME_EEPROM_SIG0)
541 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
542 fup != JME_EEPROM_SIG1)
546 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
548 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
549 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
550 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
552 if (reg >= JME_PAR0 &&
553 reg < JME_PAR0 + ETHER_ADDR_LEN) {
554 if (jme_eeprom_read_byte(sc, offset + 2,
557 eaddr[reg - JME_PAR0] = val;
561 /* Check for the end of EEPROM descriptor. */
562 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
564 /* Try next eeprom descriptor. */
565 offset += JME_EEPROM_DESC_BYTES;
566 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
568 if (match == ETHER_ADDR_LEN)
575 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
579 /* Read station address. */
580 par0 = CSR_READ_4(sc, JME_PAR0);
581 par1 = CSR_READ_4(sc, JME_PAR1);
583 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
584 device_printf(sc->jme_dev,
585 "generating fake ethernet address.\n");
586 par0 = karc4random();
587 /* Set OUI to JMicron. */
591 eaddr[3] = (par0 >> 16) & 0xff;
592 eaddr[4] = (par0 >> 8) & 0xff;
593 eaddr[5] = par0 & 0xff;
595 eaddr[0] = (par0 >> 0) & 0xFF;
596 eaddr[1] = (par0 >> 8) & 0xFF;
597 eaddr[2] = (par0 >> 16) & 0xFF;
598 eaddr[3] = (par0 >> 24) & 0xFF;
599 eaddr[4] = (par1 >> 0) & 0xFF;
600 eaddr[5] = (par1 >> 8) & 0xFF;
605 jme_attach(device_t dev)
607 struct jme_softc *sc = device_get_softc(dev);
608 struct ifnet *ifp = &sc->arpcom.ac_if;
611 uint8_t pcie_ptr, rev;
613 uint8_t eaddr[ETHER_ADDR_LEN];
615 sc->jme_rx_desc_cnt = roundup(jme_rx_desc_count, JME_NDESC_ALIGN);
616 if (sc->jme_rx_desc_cnt > JME_NDESC_MAX)
617 sc->jme_rx_desc_cnt = JME_NDESC_MAX;
619 sc->jme_tx_desc_cnt = roundup(jme_tx_desc_count, JME_NDESC_ALIGN);
620 if (sc->jme_tx_desc_cnt > JME_NDESC_MAX)
621 sc->jme_tx_desc_cnt = JME_NDESC_MAX;
624 * Calculate rx rings based on ncpus2
626 sc->jme_rx_ring_cnt = jme_rx_ring_count;
627 if (sc->jme_rx_ring_cnt <= 0)
628 sc->jme_rx_ring_cnt = JME_NRXRING_1;
629 if (sc->jme_rx_ring_cnt > ncpus2)
630 sc->jme_rx_ring_cnt = ncpus2;
632 if (sc->jme_rx_ring_cnt >= JME_NRXRING_4)
633 sc->jme_rx_ring_cnt = JME_NRXRING_4;
634 else if (sc->jme_rx_ring_cnt >= JME_NRXRING_2)
635 sc->jme_rx_ring_cnt = JME_NRXRING_2;
636 sc->jme_rx_ring_inuse = sc->jme_rx_ring_cnt;
639 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
641 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
643 callout_init(&sc->jme_tick_ch);
646 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
649 irq = pci_read_config(dev, PCIR_INTLINE, 4);
650 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
652 device_printf(dev, "chip is in D%d power mode "
653 "-- setting to D0\n", pci_get_powerstate(dev));
655 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
657 pci_write_config(dev, PCIR_INTLINE, irq, 4);
658 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
660 #endif /* !BURN_BRIDGE */
662 /* Enable bus mastering */
663 pci_enable_busmaster(dev);
668 * JMC250 supports both memory mapped and I/O register space
669 * access. Because I/O register access should use different
670 * BARs to access registers it's waste of time to use I/O
671 * register spce access. JMC250 uses 16K to map entire memory
674 sc->jme_mem_rid = JME_PCIR_BAR;
675 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
676 &sc->jme_mem_rid, RF_ACTIVE);
677 if (sc->jme_mem_res == NULL) {
678 device_printf(dev, "can't allocate IO memory\n");
681 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
682 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
688 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
690 RF_SHAREABLE | RF_ACTIVE);
691 if (sc->jme_irq_res == NULL) {
692 device_printf(dev, "can't allocate irq\n");
700 reg = CSR_READ_4(sc, JME_CHIPMODE);
701 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
703 sc->jme_caps |= JME_CAP_FPGA;
705 device_printf(dev, "FPGA revision: 0x%04x\n",
706 (reg & CHIPMODE_FPGA_REV_MASK) >>
707 CHIPMODE_FPGA_REV_SHIFT);
711 /* NOTE: FM revision is put in the upper 4 bits */
712 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
713 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
715 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
717 did = pci_get_device(dev);
719 case PCI_PRODUCT_JMICRON_JMC250:
720 if (rev == JME_REV1_A2)
721 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
724 case PCI_PRODUCT_JMICRON_JMC260:
726 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
730 panic("unknown device id 0x%04x\n", did);
732 if (rev >= JME_REV2) {
733 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
734 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
735 GHC_TXMAC_CLKSRC_1000;
738 /* Reset the ethernet controller. */
741 /* Get station address. */
742 reg = CSR_READ_4(sc, JME_SMBCSR);
743 if (reg & SMBCSR_EEPROM_PRESENT)
744 error = jme_eeprom_macaddr(sc, eaddr);
745 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
746 if (error != 0 && (bootverbose)) {
747 device_printf(dev, "ethernet hardware address "
748 "not found in EEPROM.\n");
750 jme_reg_macaddr(sc, eaddr);
755 * Integrated JR0211 has fixed PHY address whereas FPGA version
756 * requires PHY probing to get correct PHY address.
758 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
759 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
760 GPREG0_PHY_ADDR_MASK;
762 device_printf(dev, "PHY is at address %d.\n",
769 /* Set max allowable DMA size. */
770 pcie_ptr = pci_get_pciecap_ptr(dev);
774 sc->jme_caps |= JME_CAP_PCIE;
775 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
777 device_printf(dev, "Read request size : %d bytes.\n",
778 128 << ((ctrl >> 12) & 0x07));
779 device_printf(dev, "TLP payload size : %d bytes.\n",
780 128 << ((ctrl >> 5) & 0x07));
782 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
783 case PCIEM_DEVCTL_MAX_READRQ_128:
784 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
786 case PCIEM_DEVCTL_MAX_READRQ_256:
787 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
790 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
793 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
795 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
796 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
800 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
801 sc->jme_caps |= JME_CAP_PMCAP;
809 /* Allocate DMA stuffs */
810 error = jme_dma_alloc(sc);
815 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
816 ifp->if_init = jme_init;
817 ifp->if_ioctl = jme_ioctl;
818 ifp->if_start = jme_start;
819 #ifdef DEVICE_POLLING
820 ifp->if_poll = jme_poll;
822 ifp->if_watchdog = jme_watchdog;
823 ifq_set_maxlen(&ifp->if_snd, sc->jme_tx_desc_cnt - JME_TXD_RSVD);
824 ifq_set_ready(&ifp->if_snd);
826 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
827 ifp->if_capabilities = IFCAP_HWCSUM |
829 IFCAP_VLAN_HWTAGGING;
830 if (sc->jme_rx_ring_cnt > JME_NRXRING_MIN)
831 ifp->if_capabilities |= IFCAP_RSS;
832 ifp->if_capenable = ifp->if_capabilities;
835 * Disable TXCSUM by default to improve bulk data
836 * transmit performance (+20Mbps improvement).
838 ifp->if_capenable &= ~IFCAP_TXCSUM;
840 if (ifp->if_capenable & IFCAP_TXCSUM)
841 ifp->if_hwassist = JME_CSUM_FEATURES;
843 /* Set up MII bus. */
844 error = mii_phy_probe(dev, &sc->jme_miibus,
845 jme_mediachange, jme_mediastatus);
847 device_printf(dev, "no PHY found!\n");
852 * Save PHYADDR for FPGA mode PHY.
854 if (sc->jme_caps & JME_CAP_FPGA) {
855 struct mii_data *mii = device_get_softc(sc->jme_miibus);
857 if (mii->mii_instance != 0) {
858 struct mii_softc *miisc;
860 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
861 if (miisc->mii_phy != 0) {
862 sc->jme_phyaddr = miisc->mii_phy;
866 if (sc->jme_phyaddr != 0) {
867 device_printf(sc->jme_dev,
868 "FPGA PHY is at %d\n", sc->jme_phyaddr);
870 jme_miibus_writereg(dev, sc->jme_phyaddr,
871 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
873 /* XXX should we clear JME_WA_EXTFIFO */
878 ether_ifattach(ifp, eaddr, NULL);
880 /* Tell the upper layer(s) we support long frames. */
881 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
883 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE, jme_intr, sc,
884 &sc->jme_irq_handle, ifp->if_serializer);
886 device_printf(dev, "could not set up interrupt handler.\n");
891 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->jme_irq_res));
892 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
900 jme_detach(device_t dev)
902 struct jme_softc *sc = device_get_softc(dev);
904 if (device_is_attached(dev)) {
905 struct ifnet *ifp = &sc->arpcom.ac_if;
907 lwkt_serialize_enter(ifp->if_serializer);
909 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
910 lwkt_serialize_exit(ifp->if_serializer);
915 if (sc->jme_sysctl_tree != NULL)
916 sysctl_ctx_free(&sc->jme_sysctl_ctx);
918 if (sc->jme_miibus != NULL)
919 device_delete_child(dev, sc->jme_miibus);
920 bus_generic_detach(dev);
922 if (sc->jme_irq_res != NULL) {
923 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
927 if (sc->jme_mem_res != NULL) {
928 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
938 jme_sysctl_node(struct jme_softc *sc)
942 char rx_ring_pkt[32];
946 sysctl_ctx_init(&sc->jme_sysctl_ctx);
947 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
948 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
949 device_get_nameunit(sc->jme_dev),
951 if (sc->jme_sysctl_tree == NULL) {
952 device_printf(sc->jme_dev, "can't add sysctl node\n");
956 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
957 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
958 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
959 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
961 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
962 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
963 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
964 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
966 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
967 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
968 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
969 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
971 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
972 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
973 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
974 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
976 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
977 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
978 "rx_desc_count", CTLFLAG_RD, &sc->jme_rx_desc_cnt,
980 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
981 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
982 "tx_desc_count", CTLFLAG_RD, &sc->jme_tx_desc_cnt,
984 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
985 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
986 "rx_ring_count", CTLFLAG_RD, &sc->jme_rx_ring_cnt,
988 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
989 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
990 "rx_ring_inuse", CTLFLAG_RD, &sc->jme_rx_ring_inuse,
991 0, "RX ring in use");
993 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
994 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
995 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
996 0, "RSS debug level");
997 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
998 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
999 SYSCTL_ADD_UINT(&sc->jme_sysctl_ctx,
1000 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1001 rx_ring_pkt, CTLFLAG_RW,
1002 &sc->jme_rx_ring_pkt[r],
1008 * Set default coalesce valves
1010 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1011 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1012 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1013 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1016 * Adjust coalesce valves, in case that the number of TX/RX
1017 * descs are set to small values by users.
1019 * NOTE: coal_max will not be zero, since number of descs
1020 * must aligned by JME_NDESC_ALIGN (16 currently)
1022 coal_max = sc->jme_tx_desc_cnt / 6;
1023 if (coal_max < sc->jme_tx_coal_pkt)
1024 sc->jme_tx_coal_pkt = coal_max;
1026 coal_max = sc->jme_rx_desc_cnt / 4;
1027 if (coal_max < sc->jme_rx_coal_pkt)
1028 sc->jme_rx_coal_pkt = coal_max;
1032 jme_dma_alloc(struct jme_softc *sc)
1034 struct jme_txdesc *txd;
1038 sc->jme_cdata.jme_txdesc =
1039 kmalloc(sc->jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1040 M_DEVBUF, M_WAITOK | M_ZERO);
1041 for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1042 sc->jme_cdata.jme_rx_data[i].jme_rxdesc =
1043 kmalloc(sc->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1044 M_DEVBUF, M_WAITOK | M_ZERO);
1047 /* Create parent ring tag. */
1048 error = bus_dma_tag_create(NULL,/* parent */
1049 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1050 sc->jme_lowaddr, /* lowaddr */
1051 BUS_SPACE_MAXADDR, /* highaddr */
1052 NULL, NULL, /* filter, filterarg */
1053 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1055 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1057 &sc->jme_cdata.jme_ring_tag);
1059 device_printf(sc->jme_dev,
1060 "could not create parent ring DMA tag.\n");
1065 * Create DMA stuffs for TX ring
1067 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1068 JME_TX_RING_ALIGN, 0,
1069 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1070 JME_TX_RING_SIZE(sc),
1071 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1073 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1076 sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1077 sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1078 sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1079 sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1082 * Create DMA stuffs for RX rings
1084 for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1085 error = jme_rxring_dma_alloc(sc, i);
1090 /* Create parent buffer tag. */
1091 error = bus_dma_tag_create(NULL,/* parent */
1092 1, 0, /* algnmnt, boundary */
1093 sc->jme_lowaddr, /* lowaddr */
1094 BUS_SPACE_MAXADDR, /* highaddr */
1095 NULL, NULL, /* filter, filterarg */
1096 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1098 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1100 &sc->jme_cdata.jme_buffer_tag);
1102 device_printf(sc->jme_dev,
1103 "could not create parent buffer DMA tag.\n");
1108 * Create DMA stuffs for shadow status block
1110 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1111 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1112 JME_SSB_SIZE, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1114 device_printf(sc->jme_dev,
1115 "could not create shadow status block.\n");
1118 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1119 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1120 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1121 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1124 * Create DMA stuffs for TX buffers
1127 /* Create tag for Tx buffers. */
1128 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1129 1, 0, /* algnmnt, boundary */
1130 BUS_SPACE_MAXADDR, /* lowaddr */
1131 BUS_SPACE_MAXADDR, /* highaddr */
1132 NULL, NULL, /* filter, filterarg */
1133 JME_JUMBO_FRAMELEN, /* maxsize */
1134 JME_MAXTXSEGS, /* nsegments */
1135 JME_MAXSEGSIZE, /* maxsegsize */
1136 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1137 &sc->jme_cdata.jme_tx_tag);
1139 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1143 /* Create DMA maps for Tx buffers. */
1144 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1145 txd = &sc->jme_cdata.jme_txdesc[i];
1146 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1147 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1152 device_printf(sc->jme_dev,
1153 "could not create %dth Tx dmamap.\n", i);
1155 for (j = 0; j < i; ++j) {
1156 txd = &sc->jme_cdata.jme_txdesc[j];
1157 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1160 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1161 sc->jme_cdata.jme_tx_tag = NULL;
1167 * Create DMA stuffs for RX buffers
1169 for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1170 error = jme_rxbuf_dma_alloc(sc, i);
1178 jme_dma_free(struct jme_softc *sc)
1180 struct jme_txdesc *txd;
1181 struct jme_rxdesc *rxd;
1182 struct jme_rxdata *rdata;
1186 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1187 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1188 sc->jme_cdata.jme_tx_ring_map);
1189 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1190 sc->jme_cdata.jme_tx_ring,
1191 sc->jme_cdata.jme_tx_ring_map);
1192 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1193 sc->jme_cdata.jme_tx_ring_tag = NULL;
1197 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1198 rdata = &sc->jme_cdata.jme_rx_data[r];
1199 if (rdata->jme_rx_ring_tag != NULL) {
1200 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1201 rdata->jme_rx_ring_map);
1202 bus_dmamem_free(rdata->jme_rx_ring_tag,
1204 rdata->jme_rx_ring_map);
1205 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1206 rdata->jme_rx_ring_tag = NULL;
1211 if (sc->jme_cdata.jme_tx_tag != NULL) {
1212 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1213 txd = &sc->jme_cdata.jme_txdesc[i];
1214 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1217 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1218 sc->jme_cdata.jme_tx_tag = NULL;
1222 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1223 rdata = &sc->jme_cdata.jme_rx_data[r];
1224 if (rdata->jme_rx_tag != NULL) {
1225 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
1226 rxd = &rdata->jme_rxdesc[i];
1227 bus_dmamap_destroy(rdata->jme_rx_tag,
1230 bus_dmamap_destroy(rdata->jme_rx_tag,
1231 rdata->jme_rx_sparemap);
1232 bus_dma_tag_destroy(rdata->jme_rx_tag);
1233 rdata->jme_rx_tag = NULL;
1237 /* Shadow status block. */
1238 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1239 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1240 sc->jme_cdata.jme_ssb_map);
1241 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1242 sc->jme_cdata.jme_ssb_block,
1243 sc->jme_cdata.jme_ssb_map);
1244 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1245 sc->jme_cdata.jme_ssb_tag = NULL;
1248 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1249 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1250 sc->jme_cdata.jme_buffer_tag = NULL;
1252 if (sc->jme_cdata.jme_ring_tag != NULL) {
1253 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1254 sc->jme_cdata.jme_ring_tag = NULL;
1257 if (sc->jme_cdata.jme_txdesc != NULL) {
1258 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1259 sc->jme_cdata.jme_txdesc = NULL;
1261 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1262 rdata = &sc->jme_cdata.jme_rx_data[r];
1263 if (rdata->jme_rxdesc != NULL) {
1264 kfree(rdata->jme_rxdesc, M_DEVBUF);
1265 rdata->jme_rxdesc = NULL;
1271 * Make sure the interface is stopped at reboot time.
1274 jme_shutdown(device_t dev)
1276 return jme_suspend(dev);
1281 * Unlike other ethernet controllers, JMC250 requires
1282 * explicit resetting link speed to 10/100Mbps as gigabit
1283 * link will cunsume more power than 375mA.
1284 * Note, we reset the link speed to 10/100Mbps with
1285 * auto-negotiation but we don't know whether that operation
1286 * would succeed or not as we have no control after powering
1287 * off. If the renegotiation fail WOL may not work. Running
1288 * at 1Gbps draws more power than 375mA at 3.3V which is
1289 * specified in PCI specification and that would result in
1290 * complete shutdowning power to ethernet controller.
1293 * Save current negotiated media speed/duplex/flow-control
1294 * to softc and restore the same link again after resuming.
1295 * PHY handling such as power down/resetting to 100Mbps
1296 * may be better handled in suspend method in phy driver.
1299 jme_setlinkspeed(struct jme_softc *sc)
1301 struct mii_data *mii;
1304 JME_LOCK_ASSERT(sc);
1306 mii = device_get_softc(sc->jme_miibus);
1309 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1310 switch IFM_SUBTYPE(mii->mii_media_active) {
1320 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1321 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1322 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1323 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1324 BMCR_AUTOEN | BMCR_STARTNEG);
1327 /* Poll link state until jme(4) get a 10/100 link. */
1328 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1330 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1331 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1341 pause("jmelnk", hz);
1344 if (i == MII_ANEGTICKS_GIGE)
1345 device_printf(sc->jme_dev, "establishing link failed, "
1346 "WOL may not work!");
1349 * No link, force MAC to have 100Mbps, full-duplex link.
1350 * This is the last resort and may/may not work.
1352 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1353 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1358 jme_setwol(struct jme_softc *sc)
1360 struct ifnet *ifp = &sc->arpcom.ac_if;
1365 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1366 /* No PME capability, PHY power down. */
1367 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1368 MII_BMCR, BMCR_PDOWN);
1372 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1373 pmcs = CSR_READ_4(sc, JME_PMCS);
1374 pmcs &= ~PMCS_WOL_ENB_MASK;
1375 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1376 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1377 /* Enable PME message. */
1378 gpr |= GPREG0_PME_ENB;
1379 /* For gigabit controllers, reset link speed to 10/100. */
1380 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1381 jme_setlinkspeed(sc);
1384 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1385 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1388 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1389 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1390 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1391 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1392 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1393 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1394 /* No WOL, PHY power down. */
1395 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1396 MII_BMCR, BMCR_PDOWN);
1402 jme_suspend(device_t dev)
1404 struct jme_softc *sc = device_get_softc(dev);
1405 struct ifnet *ifp = &sc->arpcom.ac_if;
1407 lwkt_serialize_enter(ifp->if_serializer);
1412 lwkt_serialize_exit(ifp->if_serializer);
1418 jme_resume(device_t dev)
1420 struct jme_softc *sc = device_get_softc(dev);
1421 struct ifnet *ifp = &sc->arpcom.ac_if;
1426 lwkt_serialize_enter(ifp->if_serializer);
1429 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1432 pmstat = pci_read_config(sc->jme_dev,
1433 pmc + PCIR_POWER_STATUS, 2);
1434 /* Disable PME clear PME status. */
1435 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1436 pci_write_config(sc->jme_dev,
1437 pmc + PCIR_POWER_STATUS, pmstat, 2);
1441 if (ifp->if_flags & IFF_UP)
1444 lwkt_serialize_exit(ifp->if_serializer);
1450 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1452 struct jme_txdesc *txd;
1453 struct jme_desc *desc;
1455 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1457 int error, i, prod, symbol_desc;
1458 uint32_t cflags, flag64;
1460 M_ASSERTPKTHDR((*m_head));
1462 prod = sc->jme_cdata.jme_tx_prod;
1463 txd = &sc->jme_cdata.jme_txdesc[prod];
1465 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1470 maxsegs = (sc->jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1471 (JME_TXD_RSVD + symbol_desc);
1472 if (maxsegs > JME_MAXTXSEGS)
1473 maxsegs = JME_MAXTXSEGS;
1474 KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
1475 ("not enough segments %d\n", maxsegs));
1477 error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1478 txd->tx_dmamap, m_head,
1479 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1483 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1484 BUS_DMASYNC_PREWRITE);
1489 /* Configure checksum offload. */
1490 if (m->m_pkthdr.csum_flags & CSUM_IP)
1491 cflags |= JME_TD_IPCSUM;
1492 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1493 cflags |= JME_TD_TCPCSUM;
1494 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1495 cflags |= JME_TD_UDPCSUM;
1497 /* Configure VLAN. */
1498 if (m->m_flags & M_VLANTAG) {
1499 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1500 cflags |= JME_TD_VLAN_TAG;
1503 desc = &sc->jme_cdata.jme_tx_ring[prod];
1504 desc->flags = htole32(cflags);
1505 desc->addr_hi = htole32(m->m_pkthdr.len);
1506 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1508 * Use 64bits TX desc chain format.
1510 * The first TX desc of the chain, which is setup here,
1511 * is just a symbol TX desc carrying no payload.
1513 flag64 = JME_TD_64BIT;
1517 /* No effective TX desc is consumed */
1521 * Use 32bits TX desc chain format.
1523 * The first TX desc of the chain, which is setup here,
1524 * is an effective TX desc carrying the first segment of
1528 desc->buflen = htole32(txsegs[0].ds_len);
1529 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1531 /* One effective TX desc is consumed */
1534 sc->jme_cdata.jme_tx_cnt++;
1535 KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1536 sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1537 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1539 txd->tx_ndesc = 1 - i;
1540 for (; i < nsegs; i++) {
1541 desc = &sc->jme_cdata.jme_tx_ring[prod];
1542 desc->flags = htole32(JME_TD_OWN | flag64);
1543 desc->buflen = htole32(txsegs[i].ds_len);
1544 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1545 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1547 sc->jme_cdata.jme_tx_cnt++;
1548 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1549 sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1550 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1553 /* Update producer index. */
1554 sc->jme_cdata.jme_tx_prod = prod;
1556 * Finally request interrupt and give the first descriptor
1557 * owenership to hardware.
1559 desc = txd->tx_desc;
1560 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1563 txd->tx_ndesc += nsegs;
1573 jme_start(struct ifnet *ifp)
1575 struct jme_softc *sc = ifp->if_softc;
1576 struct mbuf *m_head;
1579 ASSERT_SERIALIZED(ifp->if_serializer);
1581 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1582 ifq_purge(&ifp->if_snd);
1586 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1589 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1592 while (!ifq_is_empty(&ifp->if_snd)) {
1594 * Check number of available TX descs, always
1595 * leave JME_TXD_RSVD free TX descs.
1597 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1598 sc->jme_tx_desc_cnt - JME_TXD_RSVD) {
1599 ifp->if_flags |= IFF_OACTIVE;
1603 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1608 * Pack the data into the transmit ring. If we
1609 * don't have room, set the OACTIVE flag and wait
1610 * for the NIC to drain the ring.
1612 if (jme_encap(sc, &m_head)) {
1613 KKASSERT(m_head == NULL);
1615 ifp->if_flags |= IFF_OACTIVE;
1621 * If there's a BPF listener, bounce a copy of this frame
1624 ETHER_BPF_MTAP(ifp, m_head);
1629 * Reading TXCSR takes very long time under heavy load
1630 * so cache TXCSR value and writes the ORed value with
1631 * the kick command to the TXCSR. This saves one register
1634 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1635 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1636 /* Set a timeout in case the chip goes out to lunch. */
1637 ifp->if_timer = JME_TX_TIMEOUT;
1642 jme_watchdog(struct ifnet *ifp)
1644 struct jme_softc *sc = ifp->if_softc;
1646 ASSERT_SERIALIZED(ifp->if_serializer);
1648 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1649 if_printf(ifp, "watchdog timeout (missed link)\n");
1656 if (sc->jme_cdata.jme_tx_cnt == 0) {
1657 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1659 if (!ifq_is_empty(&ifp->if_snd))
1664 if_printf(ifp, "watchdog timeout\n");
1667 if (!ifq_is_empty(&ifp->if_snd))
1672 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1674 struct jme_softc *sc = ifp->if_softc;
1675 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1676 struct ifreq *ifr = (struct ifreq *)data;
1677 int error = 0, mask;
1679 ASSERT_SERIALIZED(ifp->if_serializer);
1683 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1684 (!(sc->jme_caps & JME_CAP_JUMBO) &&
1685 ifr->ifr_mtu > JME_MAX_MTU)) {
1690 if (ifp->if_mtu != ifr->ifr_mtu) {
1692 * No special configuration is required when interface
1693 * MTU is changed but availability of Tx checksum
1694 * offload should be chcked against new MTU size as
1695 * FIFO size is just 2K.
1697 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1698 ifp->if_capenable &= ~IFCAP_TXCSUM;
1699 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1701 ifp->if_mtu = ifr->ifr_mtu;
1702 if (ifp->if_flags & IFF_RUNNING)
1708 if (ifp->if_flags & IFF_UP) {
1709 if (ifp->if_flags & IFF_RUNNING) {
1710 if ((ifp->if_flags ^ sc->jme_if_flags) &
1711 (IFF_PROMISC | IFF_ALLMULTI))
1717 if (ifp->if_flags & IFF_RUNNING)
1720 sc->jme_if_flags = ifp->if_flags;
1725 if (ifp->if_flags & IFF_RUNNING)
1731 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1735 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1737 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1738 ifp->if_capenable ^= IFCAP_TXCSUM;
1739 if (IFCAP_TXCSUM & ifp->if_capenable)
1740 ifp->if_hwassist |= JME_CSUM_FEATURES;
1742 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1744 if (mask & IFCAP_RXCSUM) {
1747 ifp->if_capenable ^= IFCAP_RXCSUM;
1748 reg = CSR_READ_4(sc, JME_RXMAC);
1749 reg &= ~RXMAC_CSUM_ENB;
1750 if (ifp->if_capenable & IFCAP_RXCSUM)
1751 reg |= RXMAC_CSUM_ENB;
1752 CSR_WRITE_4(sc, JME_RXMAC, reg);
1755 if (mask & IFCAP_VLAN_HWTAGGING) {
1756 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1760 if (mask & IFCAP_RSS) {
1761 ifp->if_capenable ^= IFCAP_RSS;
1762 if (ifp->if_flags & IFF_RUNNING)
1768 error = ether_ioctl(ifp, cmd, data);
1775 jme_mac_config(struct jme_softc *sc)
1777 struct mii_data *mii;
1778 uint32_t ghc, rxmac, txmac, txpause, gp1;
1779 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1781 mii = device_get_softc(sc->jme_miibus);
1783 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1785 CSR_WRITE_4(sc, JME_GHC, 0);
1787 rxmac = CSR_READ_4(sc, JME_RXMAC);
1788 rxmac &= ~RXMAC_FC_ENB;
1789 txmac = CSR_READ_4(sc, JME_TXMAC);
1790 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1791 txpause = CSR_READ_4(sc, JME_TXPFC);
1792 txpause &= ~TXPFC_PAUSE_ENB;
1793 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1794 ghc |= GHC_FULL_DUPLEX;
1795 rxmac &= ~RXMAC_COLL_DET_ENB;
1796 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1797 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1800 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1801 txpause |= TXPFC_PAUSE_ENB;
1802 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1803 rxmac |= RXMAC_FC_ENB;
1805 /* Disable retry transmit timer/retry limit. */
1806 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1807 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1809 rxmac |= RXMAC_COLL_DET_ENB;
1810 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1811 /* Enable retry transmit timer/retry limit. */
1812 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1813 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1817 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1819 gp1 = CSR_READ_4(sc, JME_GPREG1);
1820 gp1 &= ~GPREG1_WA_HDX;
1822 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1825 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1827 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1829 gp1 |= GPREG1_WA_HDX;
1833 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1835 gp1 |= GPREG1_WA_HDX;
1838 * Use extended FIFO depth to workaround CRC errors
1839 * emitted by chips before JMC250B
1841 phyconf = JMPHY_CONF_EXTFIFO;
1845 if (sc->jme_caps & JME_CAP_FASTETH)
1848 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1850 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1856 CSR_WRITE_4(sc, JME_GHC, ghc);
1857 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1858 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1859 CSR_WRITE_4(sc, JME_TXPFC, txpause);
1861 if (sc->jme_workaround & JME_WA_EXTFIFO) {
1862 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1863 JMPHY_CONF, phyconf);
1865 if (sc->jme_workaround & JME_WA_HDX)
1866 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1872 struct jme_softc *sc = xsc;
1873 struct ifnet *ifp = &sc->arpcom.ac_if;
1877 ASSERT_SERIALIZED(ifp->if_serializer);
1879 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1880 if (status == 0 || status == 0xFFFFFFFF)
1883 /* Disable interrupts. */
1884 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1886 status = CSR_READ_4(sc, JME_INTR_STATUS);
1887 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1890 /* Reset PCC counter/timer and Ack interrupts. */
1891 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1893 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1894 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1896 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
1897 if (status & jme_rx_status[r].jme_coal) {
1898 status |= jme_rx_status[r].jme_coal |
1899 jme_rx_status[r].jme_comp;
1903 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1905 if (ifp->if_flags & IFF_RUNNING) {
1906 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1907 jme_rx_intr(sc, status);
1909 if (status & INTR_RXQ_DESC_EMPTY) {
1911 * Notify hardware availability of new Rx buffers.
1912 * Reading RXCSR takes very long time under heavy
1913 * load so cache RXCSR value and writes the ORed
1914 * value with the kick command to the RXCSR. This
1915 * saves one register access cycle.
1917 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1918 RXCSR_RX_ENB | RXCSR_RXQ_START);
1921 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
1923 if (!ifq_is_empty(&ifp->if_snd))
1928 /* Reenable interrupts. */
1929 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
1933 jme_txeof(struct jme_softc *sc)
1935 struct ifnet *ifp = &sc->arpcom.ac_if;
1936 struct jme_txdesc *txd;
1940 cons = sc->jme_cdata.jme_tx_cons;
1941 if (cons == sc->jme_cdata.jme_tx_prod)
1945 * Go through our Tx list and free mbufs for those
1946 * frames which have been transmitted.
1948 while (cons != sc->jme_cdata.jme_tx_prod) {
1949 txd = &sc->jme_cdata.jme_txdesc[cons];
1950 KASSERT(txd->tx_m != NULL,
1951 ("%s: freeing NULL mbuf!\n", __func__));
1953 status = le32toh(txd->tx_desc->flags);
1954 if ((status & JME_TD_OWN) == JME_TD_OWN)
1957 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
1961 if (status & JME_TD_COLLISION) {
1962 ifp->if_collisions +=
1963 le32toh(txd->tx_desc->buflen) &
1964 JME_TD_BUF_LEN_MASK;
1969 * Only the first descriptor of multi-descriptor
1970 * transmission is updated so driver have to skip entire
1971 * chained buffers for the transmiited frame. In other
1972 * words, JME_TD_OWN bit is valid only at the first
1973 * descriptor of a multi-descriptor transmission.
1975 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
1976 sc->jme_cdata.jme_tx_ring[cons].flags = 0;
1977 JME_DESC_INC(cons, sc->jme_tx_desc_cnt);
1980 /* Reclaim transferred mbufs. */
1981 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
1984 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
1985 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
1986 ("%s: Active Tx desc counter was garbled\n", __func__));
1989 sc->jme_cdata.jme_tx_cons = cons;
1991 if (sc->jme_cdata.jme_tx_cnt == 0)
1994 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
1995 sc->jme_tx_desc_cnt - JME_TXD_RSVD)
1996 ifp->if_flags &= ~IFF_OACTIVE;
1999 static __inline void
2000 jme_discard_rxbufs(struct jme_softc *sc, int ring, int cons, int count)
2002 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2005 for (i = 0; i < count; ++i) {
2006 struct jme_desc *desc = &rdata->jme_rx_ring[cons];
2008 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2009 desc->buflen = htole32(MCLBYTES);
2010 JME_DESC_INC(cons, sc->jme_rx_desc_cnt);
2014 static __inline struct pktinfo *
2015 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2017 if (flags & JME_RD_IPV4)
2018 pi->pi_netisr = NETISR_IP;
2019 else if (flags & JME_RD_IPV6)
2020 pi->pi_netisr = NETISR_IPV6;
2025 pi->pi_l3proto = IPPROTO_UNKNOWN;
2027 if (flags & JME_RD_MORE_FRAG)
2028 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2029 else if (flags & JME_RD_TCP)
2030 pi->pi_l3proto = IPPROTO_TCP;
2031 else if (flags & JME_RD_UDP)
2032 pi->pi_l3proto = IPPROTO_UDP;
2038 /* Receive a frame. */
2040 jme_rxpkt(struct jme_softc *sc, int ring, struct mbuf_chain *chain)
2042 struct ifnet *ifp = &sc->arpcom.ac_if;
2043 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2044 struct jme_desc *desc;
2045 struct jme_rxdesc *rxd;
2046 struct mbuf *mp, *m;
2047 uint32_t flags, status, hash, hashinfo;
2048 int cons, count, nsegs;
2050 cons = rdata->jme_rx_cons;
2051 desc = &rdata->jme_rx_ring[cons];
2052 flags = le32toh(desc->flags);
2053 status = le32toh(desc->buflen);
2054 hash = le32toh(desc->addr_hi);
2055 hashinfo = le32toh(desc->addr_lo);
2056 nsegs = JME_RX_NSEGS(status);
2058 JME_RSS_DPRINTF(sc, 15, "ring%d, flags 0x%08x, "
2059 "hash 0x%08x, hash info 0x%08x\n",
2060 ring, flags, hash, hashinfo);
2062 if (status & JME_RX_ERR_STAT) {
2064 jme_discard_rxbufs(sc, ring, cons, nsegs);
2065 #ifdef JME_SHOW_ERRORS
2066 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2067 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2069 rdata->jme_rx_cons += nsegs;
2070 rdata->jme_rx_cons %= sc->jme_rx_desc_cnt;
2074 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2075 for (count = 0; count < nsegs; count++,
2076 JME_DESC_INC(cons, sc->jme_rx_desc_cnt)) {
2077 rxd = &rdata->jme_rxdesc[cons];
2080 /* Add a new receive buffer to the ring. */
2081 if (jme_newbuf(sc, ring, rxd, 0) != 0) {
2084 jme_discard_rxbufs(sc, ring, cons, nsegs - count);
2085 if (rdata->jme_rxhead != NULL) {
2086 m_freem(rdata->jme_rxhead);
2087 JME_RXCHAIN_RESET(sc, ring);
2093 * Assume we've received a full sized frame.
2094 * Actual size is fixed when we encounter the end of
2095 * multi-segmented frame.
2097 mp->m_len = MCLBYTES;
2099 /* Chain received mbufs. */
2100 if (rdata->jme_rxhead == NULL) {
2101 rdata->jme_rxhead = mp;
2102 rdata->jme_rxtail = mp;
2105 * Receive processor can receive a maximum frame
2106 * size of 65535 bytes.
2108 rdata->jme_rxtail->m_next = mp;
2109 rdata->jme_rxtail = mp;
2112 if (count == nsegs - 1) {
2113 struct pktinfo pi0, *pi;
2115 /* Last desc. for this frame. */
2116 m = rdata->jme_rxhead;
2117 m->m_pkthdr.len = rdata->jme_rxlen;
2119 /* Set first mbuf size. */
2120 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2121 /* Set last mbuf size. */
2122 mp->m_len = rdata->jme_rxlen -
2123 ((MCLBYTES - JME_RX_PAD_BYTES) +
2124 (MCLBYTES * (nsegs - 2)));
2126 m->m_len = rdata->jme_rxlen;
2128 m->m_pkthdr.rcvif = ifp;
2131 * Account for 10bytes auto padding which is used
2132 * to align IP header on 32bit boundary. Also note,
2133 * CRC bytes is automatically removed by the
2136 m->m_data += JME_RX_PAD_BYTES;
2138 /* Set checksum information. */
2139 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2140 (flags & JME_RD_IPV4)) {
2141 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2142 if (flags & JME_RD_IPCSUM)
2143 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2144 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2145 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2146 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2147 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2148 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2149 m->m_pkthdr.csum_flags |=
2150 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2151 m->m_pkthdr.csum_data = 0xffff;
2155 /* Check for VLAN tagged packets. */
2156 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2157 (flags & JME_RD_VLAN_TAG)) {
2158 m->m_pkthdr.ether_vlantag =
2159 flags & JME_RD_VLAN_MASK;
2160 m->m_flags |= M_VLANTAG;
2165 if (ifp->if_capenable & IFCAP_RSS)
2166 pi = jme_pktinfo(&pi0, flags);
2171 (hashinfo & JME_RD_HASH_FN_MASK) != 0) {
2172 m->m_flags |= M_HASH;
2173 m->m_pkthdr.hash = toeplitz_hash(hash);
2176 #ifdef JME_RSS_DEBUG
2178 JME_RSS_DPRINTF(sc, 10,
2179 "isr %d flags %08x, l3 %d %s\n",
2180 pi->pi_netisr, pi->pi_flags,
2182 (m->m_flags & M_HASH) ? "hash" : "");
2187 ether_input_chain(ifp, m, pi, chain);
2189 /* Reset mbuf chains. */
2190 JME_RXCHAIN_RESET(sc, ring);
2191 #ifdef JME_RSS_DEBUG
2192 sc->jme_rx_ring_pkt[ring]++;
2197 rdata->jme_rx_cons += nsegs;
2198 rdata->jme_rx_cons %= sc->jme_rx_desc_cnt;
2202 jme_rxeof_chain(struct jme_softc *sc, int ring, struct mbuf_chain *chain,
2205 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2206 struct jme_desc *desc;
2207 int nsegs, prog, pktlen;
2211 #ifdef DEVICE_POLLING
2212 if (count >= 0 && count-- == 0)
2215 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2216 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2218 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2222 * Check number of segments against received bytes.
2223 * Non-matching value would indicate that hardware
2224 * is still trying to update Rx descriptors. I'm not
2225 * sure whether this check is needed.
2227 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2228 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2229 if (nsegs != howmany(pktlen, MCLBYTES)) {
2230 if_printf(&sc->arpcom.ac_if, "RX fragment count(%d) "
2231 "and packet size(%d) mismach\n",
2236 /* Received a frame. */
2237 jme_rxpkt(sc, ring, chain);
2244 jme_rxeof(struct jme_softc *sc, int ring)
2246 struct mbuf_chain chain[MAXCPU];
2248 ether_input_chain_init(chain);
2249 if (jme_rxeof_chain(sc, ring, chain, -1))
2250 ether_input_dispatch(chain);
2256 struct jme_softc *sc = xsc;
2257 struct ifnet *ifp = &sc->arpcom.ac_if;
2258 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2260 lwkt_serialize_enter(ifp->if_serializer);
2263 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2265 lwkt_serialize_exit(ifp->if_serializer);
2269 jme_reset(struct jme_softc *sc)
2273 /* Make sure that TX and RX are stopped */
2278 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2282 * Hold reset bit before stop reset
2285 /* Disable TXMAC and TXOFL clock sources */
2286 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2287 /* Disable RXMAC clock source */
2288 val = CSR_READ_4(sc, JME_GPREG1);
2289 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2291 CSR_READ_4(sc, JME_GHC);
2294 CSR_WRITE_4(sc, JME_GHC, 0);
2296 CSR_READ_4(sc, JME_GHC);
2299 * Clear reset bit after stop reset
2302 /* Enable TXMAC and TXOFL clock sources */
2303 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2304 /* Enable RXMAC clock source */
2305 val = CSR_READ_4(sc, JME_GPREG1);
2306 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2308 CSR_READ_4(sc, JME_GHC);
2310 /* Disable TXMAC and TXOFL clock sources */
2311 CSR_WRITE_4(sc, JME_GHC, 0);
2312 /* Disable RXMAC clock source */
2313 val = CSR_READ_4(sc, JME_GPREG1);
2314 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2316 CSR_READ_4(sc, JME_GHC);
2318 /* Enable TX and RX */
2319 val = CSR_READ_4(sc, JME_TXCSR);
2320 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2321 val = CSR_READ_4(sc, JME_RXCSR);
2322 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2324 CSR_READ_4(sc, JME_TXCSR);
2325 CSR_READ_4(sc, JME_RXCSR);
2327 /* Enable TXMAC and TXOFL clock sources */
2328 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2329 /* Eisable RXMAC clock source */
2330 val = CSR_READ_4(sc, JME_GPREG1);
2331 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2333 CSR_READ_4(sc, JME_GHC);
2335 /* Stop TX and RX */
2343 struct jme_softc *sc = xsc;
2344 struct ifnet *ifp = &sc->arpcom.ac_if;
2345 struct mii_data *mii;
2346 uint8_t eaddr[ETHER_ADDR_LEN];
2351 ASSERT_SERIALIZED(ifp->if_serializer);
2354 * Cancel any pending I/O.
2359 * Reset the chip to a known state.
2364 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2365 KKASSERT(sc->jme_txd_spare >= 1);
2368 * If we use 64bit address mode for transmitting, each Tx request
2369 * needs one more symbol descriptor.
2371 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2372 sc->jme_txd_spare += 1;
2374 if (ifp->if_capenable & IFCAP_RSS)
2377 jme_disable_rss(sc);
2379 /* Init RX descriptors */
2380 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2381 error = jme_init_rx_ring(sc, r);
2383 if_printf(ifp, "initialization failed: "
2384 "no memory for %dth RX ring.\n", r);
2390 /* Init TX descriptors */
2391 jme_init_tx_ring(sc);
2393 /* Initialize shadow status block. */
2396 /* Reprogram the station address. */
2397 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2398 CSR_WRITE_4(sc, JME_PAR0,
2399 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2400 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2403 * Configure Tx queue.
2404 * Tx priority queue weight value : 0
2405 * Tx FIFO threshold for processing next packet : 16QW
2406 * Maximum Tx DMA length : 512
2407 * Allow Tx DMA burst.
2409 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2410 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2411 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2412 sc->jme_txcsr |= sc->jme_tx_dma_size;
2413 sc->jme_txcsr |= TXCSR_DMA_BURST;
2414 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2416 /* Set Tx descriptor counter. */
2417 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_tx_desc_cnt);
2419 /* Set Tx ring address to the hardware. */
2420 paddr = sc->jme_cdata.jme_tx_ring_paddr;
2421 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2422 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2424 /* Configure TxMAC parameters. */
2425 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2426 reg |= TXMAC_THRESH_1_PKT;
2427 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2428 CSR_WRITE_4(sc, JME_TXMAC, reg);
2431 * Configure Rx queue.
2432 * FIFO full threshold for transmitting Tx pause packet : 128T
2433 * FIFO threshold for processing next packet : 128QW
2435 * Max Rx DMA length : 128
2436 * Rx descriptor retry : 32
2437 * Rx descriptor retry time gap : 256ns
2438 * Don't receive runt/bad frame.
2440 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2443 * Since Rx FIFO size is 4K bytes, receiving frames larger
2444 * than 4K bytes will suffer from Rx FIFO overruns. So
2445 * decrease FIFO threshold to reduce the FIFO overruns for
2446 * frames larger than 4000 bytes.
2447 * For best performance of standard MTU sized frames use
2448 * maximum allowable FIFO threshold, 128QW.
2450 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2452 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2454 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2456 /* Improve PCI Express compatibility */
2457 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2459 sc->jme_rxcsr |= sc->jme_rx_dma_size;
2460 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2461 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2462 /* XXX TODO DROP_BAD */
2464 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2465 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2467 /* Set Rx descriptor counter. */
2468 CSR_WRITE_4(sc, JME_RXQDC, sc->jme_rx_desc_cnt);
2470 /* Set Rx ring address to the hardware. */
2471 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
2472 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2473 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2476 /* Clear receive filter. */
2477 CSR_WRITE_4(sc, JME_RXMAC, 0);
2479 /* Set up the receive filter. */
2484 * Disable all WOL bits as WOL can interfere normal Rx
2485 * operation. Also clear WOL detection status bits.
2487 reg = CSR_READ_4(sc, JME_PMCS);
2488 reg &= ~PMCS_WOL_ENB_MASK;
2489 CSR_WRITE_4(sc, JME_PMCS, reg);
2492 * Pad 10bytes right before received frame. This will greatly
2493 * help Rx performance on strict-alignment architectures as
2494 * it does not need to copy the frame to align the payload.
2496 reg = CSR_READ_4(sc, JME_RXMAC);
2497 reg |= RXMAC_PAD_10BYTES;
2499 if (ifp->if_capenable & IFCAP_RXCSUM)
2500 reg |= RXMAC_CSUM_ENB;
2501 CSR_WRITE_4(sc, JME_RXMAC, reg);
2503 /* Configure general purpose reg0 */
2504 reg = CSR_READ_4(sc, JME_GPREG0);
2505 reg &= ~GPREG0_PCC_UNIT_MASK;
2506 /* Set PCC timer resolution to micro-seconds unit. */
2507 reg |= GPREG0_PCC_UNIT_US;
2509 * Disable all shadow register posting as we have to read
2510 * JME_INTR_STATUS register in jme_intr. Also it seems
2511 * that it's hard to synchronize interrupt status between
2512 * hardware and software with shadow posting due to
2513 * requirements of bus_dmamap_sync(9).
2515 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2516 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2517 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2518 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2519 /* Disable posting of DW0. */
2520 reg &= ~GPREG0_POST_DW0_ENB;
2521 /* Clear PME message. */
2522 reg &= ~GPREG0_PME_ENB;
2523 /* Set PHY address. */
2524 reg &= ~GPREG0_PHY_ADDR_MASK;
2525 reg |= sc->jme_phyaddr;
2526 CSR_WRITE_4(sc, JME_GPREG0, reg);
2528 /* Configure Tx queue 0 packet completion coalescing. */
2529 jme_set_tx_coal(sc);
2531 /* Configure Rx queue 0 packet completion coalescing. */
2532 jme_set_rx_coal(sc);
2534 /* Configure shadow status block but don't enable posting. */
2535 paddr = sc->jme_cdata.jme_ssb_block_paddr;
2536 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2537 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2539 /* Disable Timer 1 and Timer 2. */
2540 CSR_WRITE_4(sc, JME_TIMER1, 0);
2541 CSR_WRITE_4(sc, JME_TIMER2, 0);
2543 /* Configure retry transmit period, retry limit value. */
2544 CSR_WRITE_4(sc, JME_TXTRHD,
2545 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2546 TXTRHD_RT_PERIOD_MASK) |
2547 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2548 TXTRHD_RT_LIMIT_SHIFT));
2550 #ifdef DEVICE_POLLING
2551 if (!(ifp->if_flags & IFF_POLLING))
2553 /* Initialize the interrupt mask. */
2554 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2555 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2558 * Enabling Tx/Rx DMA engines and Rx queue processing is
2559 * done after detection of valid link in jme_miibus_statchg.
2561 sc->jme_flags &= ~JME_FLAG_LINK;
2563 /* Set the current media. */
2564 mii = device_get_softc(sc->jme_miibus);
2567 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2569 ifp->if_flags |= IFF_RUNNING;
2570 ifp->if_flags &= ~IFF_OACTIVE;
2574 jme_stop(struct jme_softc *sc)
2576 struct ifnet *ifp = &sc->arpcom.ac_if;
2577 struct jme_txdesc *txd;
2578 struct jme_rxdesc *rxd;
2579 struct jme_rxdata *rdata;
2582 ASSERT_SERIALIZED(ifp->if_serializer);
2585 * Mark the interface down and cancel the watchdog timer.
2587 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2590 callout_stop(&sc->jme_tick_ch);
2591 sc->jme_flags &= ~JME_FLAG_LINK;
2594 * Disable interrupts.
2596 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2597 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2599 /* Disable updating shadow status block. */
2600 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2601 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2603 /* Stop receiver, transmitter. */
2608 * Free partial finished RX segments
2610 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2611 rdata = &sc->jme_cdata.jme_rx_data[r];
2612 if (rdata->jme_rxhead != NULL)
2613 m_freem(rdata->jme_rxhead);
2614 JME_RXCHAIN_RESET(sc, r);
2618 * Free RX and TX mbufs still in the queues.
2620 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2621 rdata = &sc->jme_cdata.jme_rx_data[r];
2622 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2623 rxd = &rdata->jme_rxdesc[i];
2624 if (rxd->rx_m != NULL) {
2625 bus_dmamap_unload(rdata->jme_rx_tag,
2632 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2633 txd = &sc->jme_cdata.jme_txdesc[i];
2634 if (txd->tx_m != NULL) {
2635 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2645 jme_stop_tx(struct jme_softc *sc)
2650 reg = CSR_READ_4(sc, JME_TXCSR);
2651 if ((reg & TXCSR_TX_ENB) == 0)
2653 reg &= ~TXCSR_TX_ENB;
2654 CSR_WRITE_4(sc, JME_TXCSR, reg);
2655 for (i = JME_TIMEOUT; i > 0; i--) {
2657 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2661 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2665 jme_stop_rx(struct jme_softc *sc)
2670 reg = CSR_READ_4(sc, JME_RXCSR);
2671 if ((reg & RXCSR_RX_ENB) == 0)
2673 reg &= ~RXCSR_RX_ENB;
2674 CSR_WRITE_4(sc, JME_RXCSR, reg);
2675 for (i = JME_TIMEOUT; i > 0; i--) {
2677 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2681 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2685 jme_init_tx_ring(struct jme_softc *sc)
2687 struct jme_chain_data *cd;
2688 struct jme_txdesc *txd;
2691 sc->jme_cdata.jme_tx_prod = 0;
2692 sc->jme_cdata.jme_tx_cons = 0;
2693 sc->jme_cdata.jme_tx_cnt = 0;
2695 cd = &sc->jme_cdata;
2696 bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2697 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2698 txd = &sc->jme_cdata.jme_txdesc[i];
2700 txd->tx_desc = &cd->jme_tx_ring[i];
2706 jme_init_ssb(struct jme_softc *sc)
2708 struct jme_chain_data *cd;
2710 cd = &sc->jme_cdata;
2711 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2715 jme_init_rx_ring(struct jme_softc *sc, int ring)
2717 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2718 struct jme_rxdesc *rxd;
2721 KKASSERT(rdata->jme_rxhead == NULL &&
2722 rdata->jme_rxtail == NULL &&
2723 rdata->jme_rxlen == 0);
2724 rdata->jme_rx_cons = 0;
2726 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(sc));
2727 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2730 rxd = &rdata->jme_rxdesc[i];
2732 rxd->rx_desc = &rdata->jme_rx_ring[i];
2733 error = jme_newbuf(sc, ring, rxd, 1);
2741 jme_newbuf(struct jme_softc *sc, int ring, struct jme_rxdesc *rxd, int init)
2743 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2744 struct jme_desc *desc;
2746 bus_dma_segment_t segs;
2750 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2754 * JMC250 has 64bit boundary alignment limitation so jme(4)
2755 * takes advantage of 10 bytes padding feature of hardware
2756 * in order not to copy entire frame to align IP header on
2759 m->m_len = m->m_pkthdr.len = MCLBYTES;
2761 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2762 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2767 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
2771 if (rxd->rx_m != NULL) {
2772 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2773 BUS_DMASYNC_POSTREAD);
2774 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2776 map = rxd->rx_dmamap;
2777 rxd->rx_dmamap = rdata->jme_rx_sparemap;
2778 rdata->jme_rx_sparemap = map;
2781 desc = rxd->rx_desc;
2782 desc->buflen = htole32(segs.ds_len);
2783 desc->addr_lo = htole32(JME_ADDR_LO(segs.ds_addr));
2784 desc->addr_hi = htole32(JME_ADDR_HI(segs.ds_addr));
2785 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2791 jme_set_vlan(struct jme_softc *sc)
2793 struct ifnet *ifp = &sc->arpcom.ac_if;
2796 ASSERT_SERIALIZED(ifp->if_serializer);
2798 reg = CSR_READ_4(sc, JME_RXMAC);
2799 reg &= ~RXMAC_VLAN_ENB;
2800 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2801 reg |= RXMAC_VLAN_ENB;
2802 CSR_WRITE_4(sc, JME_RXMAC, reg);
2806 jme_set_filter(struct jme_softc *sc)
2808 struct ifnet *ifp = &sc->arpcom.ac_if;
2809 struct ifmultiaddr *ifma;
2814 ASSERT_SERIALIZED(ifp->if_serializer);
2816 rxcfg = CSR_READ_4(sc, JME_RXMAC);
2817 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2821 * Always accept frames destined to our station address.
2822 * Always accept broadcast frames.
2824 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2826 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2827 if (ifp->if_flags & IFF_PROMISC)
2828 rxcfg |= RXMAC_PROMISC;
2829 if (ifp->if_flags & IFF_ALLMULTI)
2830 rxcfg |= RXMAC_ALLMULTI;
2831 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2832 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2833 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2838 * Set up the multicast address filter by passing all multicast
2839 * addresses through a CRC generator, and then using the low-order
2840 * 6 bits as an index into the 64 bit multicast hash table. The
2841 * high order bits select the register, while the rest of the bits
2842 * select the bit within the register.
2844 rxcfg |= RXMAC_MULTICAST;
2845 bzero(mchash, sizeof(mchash));
2847 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2848 if (ifma->ifma_addr->sa_family != AF_LINK)
2850 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2851 ifma->ifma_addr), ETHER_ADDR_LEN);
2853 /* Just want the 6 least significant bits. */
2856 /* Set the corresponding bit in the hash table. */
2857 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2860 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2861 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2862 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2866 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
2868 struct jme_softc *sc = arg1;
2869 struct ifnet *ifp = &sc->arpcom.ac_if;
2872 lwkt_serialize_enter(ifp->if_serializer);
2874 v = sc->jme_tx_coal_to;
2875 error = sysctl_handle_int(oidp, &v, 0, req);
2876 if (error || req->newptr == NULL)
2879 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
2884 if (v != sc->jme_tx_coal_to) {
2885 sc->jme_tx_coal_to = v;
2886 if (ifp->if_flags & IFF_RUNNING)
2887 jme_set_tx_coal(sc);
2890 lwkt_serialize_exit(ifp->if_serializer);
2895 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
2897 struct jme_softc *sc = arg1;
2898 struct ifnet *ifp = &sc->arpcom.ac_if;
2901 lwkt_serialize_enter(ifp->if_serializer);
2903 v = sc->jme_tx_coal_pkt;
2904 error = sysctl_handle_int(oidp, &v, 0, req);
2905 if (error || req->newptr == NULL)
2908 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
2913 if (v != sc->jme_tx_coal_pkt) {
2914 sc->jme_tx_coal_pkt = v;
2915 if (ifp->if_flags & IFF_RUNNING)
2916 jme_set_tx_coal(sc);
2919 lwkt_serialize_exit(ifp->if_serializer);
2924 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
2926 struct jme_softc *sc = arg1;
2927 struct ifnet *ifp = &sc->arpcom.ac_if;
2930 lwkt_serialize_enter(ifp->if_serializer);
2932 v = sc->jme_rx_coal_to;
2933 error = sysctl_handle_int(oidp, &v, 0, req);
2934 if (error || req->newptr == NULL)
2937 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
2942 if (v != sc->jme_rx_coal_to) {
2943 sc->jme_rx_coal_to = v;
2944 if (ifp->if_flags & IFF_RUNNING)
2945 jme_set_rx_coal(sc);
2948 lwkt_serialize_exit(ifp->if_serializer);
2953 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
2955 struct jme_softc *sc = arg1;
2956 struct ifnet *ifp = &sc->arpcom.ac_if;
2959 lwkt_serialize_enter(ifp->if_serializer);
2961 v = sc->jme_rx_coal_pkt;
2962 error = sysctl_handle_int(oidp, &v, 0, req);
2963 if (error || req->newptr == NULL)
2966 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
2971 if (v != sc->jme_rx_coal_pkt) {
2972 sc->jme_rx_coal_pkt = v;
2973 if (ifp->if_flags & IFF_RUNNING)
2974 jme_set_rx_coal(sc);
2977 lwkt_serialize_exit(ifp->if_serializer);
2982 jme_set_tx_coal(struct jme_softc *sc)
2986 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
2988 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
2989 PCCTX_COAL_PKT_MASK;
2990 reg |= PCCTX_COAL_TXQ0;
2991 CSR_WRITE_4(sc, JME_PCCTX, reg);
2995 jme_set_rx_coal(struct jme_softc *sc)
3000 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3002 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3003 PCCRX_COAL_PKT_MASK;
3004 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
3005 if (r < sc->jme_rx_ring_inuse)
3006 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3008 CSR_WRITE_4(sc, JME_PCCRX(r), 0);
3012 #ifdef DEVICE_POLLING
3015 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3017 struct jme_softc *sc = ifp->if_softc;
3018 struct mbuf_chain chain[MAXCPU];
3022 ASSERT_SERIALIZED(ifp->if_serializer);
3026 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3029 case POLL_DEREGISTER:
3030 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3033 case POLL_AND_CHECK_STATUS:
3035 status = CSR_READ_4(sc, JME_INTR_STATUS);
3037 ether_input_chain_init(chain);
3038 for (r = 0; r < sc->jme_rx_ring_inuse; ++r)
3039 prog += jme_rxeof_chain(sc, r, chain, count);
3041 ether_input_dispatch(chain);
3043 if (status & INTR_RXQ_DESC_EMPTY) {
3044 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3045 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3046 RXCSR_RX_ENB | RXCSR_RXQ_START);
3050 if (!ifq_is_empty(&ifp->if_snd))
3056 #endif /* DEVICE_POLLING */
3059 jme_rxring_dma_alloc(struct jme_softc *sc, int ring)
3061 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
3065 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
3066 JME_RX_RING_ALIGN, 0,
3067 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3068 JME_RX_RING_SIZE(sc),
3069 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3071 device_printf(sc->jme_dev,
3072 "could not allocate %dth Rx ring.\n", ring);
3075 rdata->jme_rx_ring_tag = dmem.dmem_tag;
3076 rdata->jme_rx_ring_map = dmem.dmem_map;
3077 rdata->jme_rx_ring = dmem.dmem_addr;
3078 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3084 jme_rxbuf_dma_alloc(struct jme_softc *sc, int ring)
3086 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
3089 /* Create tag for Rx buffers. */
3090 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
3091 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
3092 BUS_SPACE_MAXADDR, /* lowaddr */
3093 BUS_SPACE_MAXADDR, /* highaddr */
3094 NULL, NULL, /* filter, filterarg */
3095 MCLBYTES, /* maxsize */
3097 MCLBYTES, /* maxsegsize */
3098 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3099 &rdata->jme_rx_tag);
3101 device_printf(sc->jme_dev,
3102 "could not create %dth Rx DMA tag.\n", ring);
3106 /* Create DMA maps for Rx buffers. */
3107 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3108 &rdata->jme_rx_sparemap);
3110 device_printf(sc->jme_dev,
3111 "could not create %dth spare Rx dmamap.\n", ring);
3112 bus_dma_tag_destroy(rdata->jme_rx_tag);
3113 rdata->jme_rx_tag = NULL;
3116 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
3117 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3119 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3124 device_printf(sc->jme_dev,
3125 "could not create %dth Rx dmamap "
3126 "for %dth RX ring.\n", i, ring);
3128 for (j = 0; j < i; ++j) {
3129 rxd = &rdata->jme_rxdesc[j];
3130 bus_dmamap_destroy(rdata->jme_rx_tag,
3133 bus_dmamap_destroy(rdata->jme_rx_tag,
3134 rdata->jme_rx_sparemap);
3135 bus_dma_tag_destroy(rdata->jme_rx_tag);
3136 rdata->jme_rx_tag = NULL;
3144 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3146 struct mbuf_chain chain[MAXCPU];
3149 ether_input_chain_init(chain);
3150 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
3151 if (status & jme_rx_status[r].jme_coal)
3152 prog += jme_rxeof_chain(sc, r, chain, -1);
3155 ether_input_dispatch(chain);
3159 jme_enable_rss(struct jme_softc *sc)
3162 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3165 sc->jme_rx_ring_inuse = sc->jme_rx_ring_cnt;
3167 KASSERT(sc->jme_rx_ring_inuse == JME_NRXRING_2 ||
3168 sc->jme_rx_ring_inuse == JME_NRXRING_4,
3169 ("%s: invalid # of RX rings (%d)\n",
3170 sc->arpcom.ac_if.if_xname, sc->jme_rx_ring_inuse));
3172 rssc = RSSC_HASH_64_ENTRY;
3173 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3174 rssc |= sc->jme_rx_ring_inuse >> 1;
3175 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3176 CSR_WRITE_4(sc, JME_RSSC, rssc);
3178 toeplitz_get_key(key, sizeof(key));
3179 for (i = 0; i < RSSKEY_NREGS; ++i) {
3182 keyreg = RSSKEY_REGVAL(key, i);
3183 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3185 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3189 * Create redirect table in following fashion:
3190 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3193 for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3196 q = i % sc->jme_rx_ring_inuse;
3197 ind |= q << (i * 8);
3199 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3201 for (i = 0; i < RSSTBL_NREGS; ++i)
3202 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3206 jme_disable_rss(struct jme_softc *sc)
3208 sc->jme_rx_ring_inuse = JME_NRXRING_1;
3209 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);