2 * Copyright (c) 2001-2011, Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 #include "opt_polling.h"
34 #include <sys/param.h>
36 #include <sys/endian.h>
37 #include <sys/interrupt.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
43 #include <sys/serialize.h>
44 #include <sys/serialize2.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
48 #include <sys/systm.h>
51 #include <net/ethernet.h>
53 #include <net/if_arp.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
56 #include <net/ifq_var.h>
57 #include <net/toeplitz.h>
58 #include <net/toeplitz2.h>
59 #include <net/vlan/if_vlan_var.h>
60 #include <net/vlan/if_vlan_ether.h>
61 #include <net/if_poll.h>
63 #include <netinet/in_systm.h>
64 #include <netinet/in.h>
65 #include <netinet/ip.h>
66 #include <netinet/tcp.h>
67 #include <netinet/udp.h>
69 #include <bus/pci/pcivar.h>
70 #include <bus/pci/pcireg.h>
72 #include <dev/netif/ig_hal/e1000_api.h>
73 #include <dev/netif/ig_hal/e1000_82575.h>
74 #include <dev/netif/igb/if_igb.h>
76 #define IGB_NAME "Intel(R) PRO/1000 "
77 #define IGB_DEVICE(id) \
78 { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
79 #define IGB_DEVICE_NULL { 0, 0, NULL }
81 static struct igb_device {
86 IGB_DEVICE(82575EB_COPPER),
87 IGB_DEVICE(82575EB_FIBER_SERDES),
88 IGB_DEVICE(82575GB_QUAD_COPPER),
91 IGB_DEVICE(82576_NS_SERDES),
92 IGB_DEVICE(82576_FIBER),
93 IGB_DEVICE(82576_SERDES),
94 IGB_DEVICE(82576_SERDES_QUAD),
95 IGB_DEVICE(82576_QUAD_COPPER),
96 IGB_DEVICE(82576_QUAD_COPPER_ET2),
98 IGB_DEVICE(82580_COPPER),
99 IGB_DEVICE(82580_FIBER),
100 IGB_DEVICE(82580_SERDES),
101 IGB_DEVICE(82580_SGMII),
102 IGB_DEVICE(82580_COPPER_DUAL),
103 IGB_DEVICE(82580_QUAD_FIBER),
104 IGB_DEVICE(DH89XXCC_SERDES),
105 IGB_DEVICE(DH89XXCC_SGMII),
106 IGB_DEVICE(DH89XXCC_SFP),
107 IGB_DEVICE(DH89XXCC_BACKPLANE),
108 IGB_DEVICE(I350_COPPER),
109 IGB_DEVICE(I350_FIBER),
110 IGB_DEVICE(I350_SERDES),
111 IGB_DEVICE(I350_SGMII),
114 /* required last entry */
118 static int igb_probe(device_t);
119 static int igb_attach(device_t);
120 static int igb_detach(device_t);
121 static int igb_shutdown(device_t);
122 static int igb_suspend(device_t);
123 static int igb_resume(device_t);
125 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
126 static void igb_setup_ifp(struct igb_softc *);
127 static int igb_txctx_pullup(struct igb_tx_ring *, struct mbuf **);
128 static boolean_t igb_txctx(struct igb_tx_ring *, struct mbuf *);
129 static void igb_add_sysctl(struct igb_softc *);
130 static int igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
131 static int igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
133 static void igb_vf_init_stats(struct igb_softc *);
134 static void igb_reset(struct igb_softc *);
135 static void igb_update_stats_counters(struct igb_softc *);
136 static void igb_update_vf_stats_counters(struct igb_softc *);
137 static void igb_update_link_status(struct igb_softc *);
138 static void igb_init_tx_unit(struct igb_softc *);
139 static void igb_init_rx_unit(struct igb_softc *);
141 static void igb_set_vlan(struct igb_softc *);
142 static void igb_set_multi(struct igb_softc *);
143 static void igb_set_promisc(struct igb_softc *);
144 static void igb_disable_promisc(struct igb_softc *);
146 static int igb_dma_alloc(struct igb_softc *);
147 static void igb_dma_free(struct igb_softc *);
148 static int igb_create_tx_ring(struct igb_tx_ring *);
149 static int igb_create_rx_ring(struct igb_rx_ring *);
150 static void igb_free_tx_ring(struct igb_tx_ring *);
151 static void igb_free_rx_ring(struct igb_rx_ring *);
152 static void igb_destroy_tx_ring(struct igb_tx_ring *, int);
153 static void igb_destroy_rx_ring(struct igb_rx_ring *, int);
154 static void igb_init_tx_ring(struct igb_tx_ring *);
155 static int igb_init_rx_ring(struct igb_rx_ring *);
156 static int igb_newbuf(struct igb_rx_ring *, int, boolean_t);
157 static int igb_encap(struct igb_tx_ring *, struct mbuf **);
159 static void igb_stop(struct igb_softc *);
160 static void igb_init(void *);
161 static int igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
162 static void igb_media_status(struct ifnet *, struct ifmediareq *);
163 static int igb_media_change(struct ifnet *);
164 static void igb_timer(void *);
165 static void igb_watchdog(struct ifnet *);
166 static void igb_start(struct ifnet *);
167 #ifdef DEVICE_POLLING
168 static void igb_poll(struct ifnet *, enum poll_cmd, int);
171 static void igb_intr(void *);
172 static void igb_shared_intr(void *);
173 static void igb_rxeof(struct igb_rx_ring *, int);
174 static void igb_txeof(struct igb_tx_ring *);
175 static void igb_set_eitr(struct igb_softc *);
176 static void igb_enable_intr(struct igb_softc *);
177 static void igb_disable_intr(struct igb_softc *);
178 static void igb_init_unshared_intr(struct igb_softc *);
179 static void igb_init_intr(struct igb_softc *);
180 static int igb_setup_intr(struct igb_softc *);
181 static void igb_setup_tx_intr(struct igb_tx_ring *);
182 static void igb_setup_rx_intr(struct igb_rx_ring *);
184 /* Management and WOL Support */
185 static void igb_get_mgmt(struct igb_softc *);
186 static void igb_rel_mgmt(struct igb_softc *);
187 static void igb_get_hw_control(struct igb_softc *);
188 static void igb_rel_hw_control(struct igb_softc *);
189 static void igb_enable_wol(device_t);
191 static device_method_t igb_methods[] = {
192 /* Device interface */
193 DEVMETHOD(device_probe, igb_probe),
194 DEVMETHOD(device_attach, igb_attach),
195 DEVMETHOD(device_detach, igb_detach),
196 DEVMETHOD(device_shutdown, igb_shutdown),
197 DEVMETHOD(device_suspend, igb_suspend),
198 DEVMETHOD(device_resume, igb_resume),
202 static driver_t igb_driver = {
205 sizeof(struct igb_softc),
208 static devclass_t igb_devclass;
210 DECLARE_DUMMY_MODULE(if_igb);
211 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
212 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
214 static int igb_rxd = IGB_DEFAULT_RXD;
215 static int igb_txd = IGB_DEFAULT_TXD;
216 static int igb_msi_enable = 1;
217 static int igb_msix_enable = 1;
218 static int igb_eee_disabled = 1; /* Energy Efficient Ethernet */
219 static int igb_fc_setting = e1000_fc_full;
222 * DMA Coalescing, only for i350 - default to off,
223 * this feature is for power savings
225 static int igb_dma_coalesce = 0;
227 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
228 TUNABLE_INT("hw.igb.txd", &igb_txd);
229 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
230 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
231 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
234 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
235 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
238 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
240 /* Ignore Checksum bit is set */
241 if (staterr & E1000_RXD_STAT_IXSM)
244 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
246 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
248 if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
249 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
250 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
251 CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
252 mp->m_pkthdr.csum_data = htons(0xffff);
258 igb_probe(device_t dev)
260 const struct igb_device *d;
263 vid = pci_get_vendor(dev);
264 did = pci_get_device(dev);
266 for (d = igb_devices; d->desc != NULL; ++d) {
267 if (vid == d->vid && did == d->did) {
268 device_set_desc(dev, d->desc);
276 igb_attach(device_t dev)
278 struct igb_softc *sc = device_get_softc(dev);
279 uint16_t eeprom_data;
285 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
286 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
287 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
288 igb_sysctl_nvm_info, "I", "NVM Information");
290 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
291 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
292 OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
293 &igb_enable_aim, 1, "Interrupt Moderation");
295 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
296 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
297 OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
298 adapter, 0, igb_set_flowcntl, "I", "Flow Control");
301 callout_init_mp(&sc->timer);
303 sc->dev = sc->osdep.dev = dev;
306 * Determine hardware and mac type
308 sc->hw.vendor_id = pci_get_vendor(dev);
309 sc->hw.device_id = pci_get_device(dev);
310 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
311 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
312 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
314 if (e1000_set_mac_type(&sc->hw))
317 /* Are we a VF device? */
318 if (sc->hw.mac.type == e1000_vfadapt ||
319 sc->hw.mac.type == e1000_vfadapt_i350)
324 /* Enable bus mastering */
325 pci_enable_busmaster(dev);
330 sc->mem_rid = PCIR_BAR(0);
331 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
333 if (sc->mem_res == NULL) {
334 device_printf(dev, "Unable to allocate bus resource: memory\n");
338 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
339 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
341 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
346 sc->intr_type = pci_alloc_1intr(dev, igb_msi_enable,
347 &sc->intr_rid, &intr_flags);
349 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
351 if (sc->intr_res == NULL) {
352 device_printf(dev, "Unable to allocate bus resource: "
358 /* Save PCI command register for Shared Code */
359 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
360 sc->hw.back = &sc->osdep;
362 sc->tx_ring_cnt = 1; /* XXX */
363 sc->rx_ring_cnt = 1; /* XXX */
364 sc->intr_rate = IGB_INTR_RATE;
366 /* Do Shared Code initialization */
367 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
368 device_printf(dev, "Setup of Shared code failed\n");
373 e1000_get_bus_info(&sc->hw);
375 sc->hw.mac.autoneg = DO_AUTO_NEG;
376 sc->hw.phy.autoneg_wait_to_complete = FALSE;
377 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
380 if (sc->hw.phy.media_type == e1000_media_type_copper) {
381 sc->hw.phy.mdix = AUTO_ALL_MODES;
382 sc->hw.phy.disable_polarity_correction = FALSE;
383 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
386 /* Set the frame limits assuming standard ethernet sized frames. */
387 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
388 sc->min_frame_size = ETHER_MIN_LEN;
390 /* Allocate RX/TX rings' busdma(9) stuffs */
391 error = igb_dma_alloc(sc);
395 /* Allocate the appropriate stats memory */
397 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
399 igb_vf_init_stats(sc);
401 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
405 /* Allocate multicast array memory. */
406 sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
409 /* Some adapter-specific advanced features */
410 if (sc->hw.mac.type >= e1000_i350) {
412 igb_set_sysctl_value(adapter, "dma_coalesce",
413 "configure dma coalesce",
414 &adapter->dma_coalesce, igb_dma_coalesce);
415 igb_set_sysctl_value(adapter, "eee_disabled",
416 "enable Energy Efficient Ethernet",
417 &adapter->hw.dev_spec._82575.eee_disable,
420 sc->dma_coalesce = igb_dma_coalesce;
421 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
423 e1000_set_eee_i350(&sc->hw);
427 * Start from a known state, this is important in reading the nvm and
430 e1000_reset_hw(&sc->hw);
432 /* Make sure we have a good EEPROM before we read from it */
433 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
435 * Some PCI-E parts fail the first check due to
436 * the link being in sleep state, call it again,
437 * if it fails a second time its a real issue.
439 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
441 "The EEPROM Checksum Is Not Valid\n");
447 /* Copy the permanent MAC address out of the EEPROM */
448 if (e1000_read_mac_addr(&sc->hw) < 0) {
449 device_printf(dev, "EEPROM read error while reading MAC"
454 if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
455 device_printf(dev, "Invalid MAC address\n");
462 ** Configure Interrupts
464 if ((adapter->msix > 1) && (igb_enable_msix))
465 error = igb_allocate_msix(adapter);
466 else /* MSI or Legacy */
467 error = igb_allocate_legacy(adapter);
472 /* Setup OS specific network interface */
475 /* Add sysctl tree, must after igb_setup_ifp() */
478 /* Now get a good starting state */
481 /* Initialize statistics */
482 igb_update_stats_counters(sc);
484 sc->hw.mac.get_link_status = 1;
485 igb_update_link_status(sc);
487 /* Indicate SOL/IDER usage */
488 if (e1000_check_reset_block(&sc->hw)) {
490 "PHY reset is blocked due to SOL/IDER session.\n");
493 /* Determine if we have to control management hardware */
494 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
499 /* APME bit in EEPROM is mapped to WUC.APME */
500 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
502 sc->wol = E1000_WUFC_MAG;
503 /* XXX disable WOL */
507 /* Register for VLAN events */
508 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
509 igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
510 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
511 igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
515 igb_add_hw_stats(adapter);
518 error = igb_setup_intr(sc);
520 ether_ifdetach(&sc->arpcom.ac_if);
531 igb_detach(device_t dev)
533 struct igb_softc *sc = device_get_softc(dev);
535 if (device_is_attached(dev)) {
536 struct ifnet *ifp = &sc->arpcom.ac_if;
538 ifnet_serialize_all(ifp);
542 e1000_phy_hw_reset(&sc->hw);
544 /* Give control back to firmware */
546 igb_rel_hw_control(sc);
549 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
550 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
554 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
556 ifnet_deserialize_all(ifp);
559 } else if (sc->mem_res != NULL) {
560 igb_rel_hw_control(sc);
562 bus_generic_detach(dev);
564 if (sc->intr_res != NULL) {
565 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
568 if (sc->intr_type == PCI_INTR_TYPE_MSI)
569 pci_release_msi(dev);
571 if (sc->mem_res != NULL) {
572 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
579 kfree(sc->mta, M_DEVBUF);
580 if (sc->stats != NULL)
581 kfree(sc->stats, M_DEVBUF);
583 if (sc->sysctl_tree != NULL)
584 sysctl_ctx_free(&sc->sysctl_ctx);
590 igb_shutdown(device_t dev)
592 return igb_suspend(dev);
596 igb_suspend(device_t dev)
598 struct igb_softc *sc = device_get_softc(dev);
599 struct ifnet *ifp = &sc->arpcom.ac_if;
601 ifnet_serialize_all(ifp);
606 igb_rel_hw_control(sc);
609 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
610 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
614 ifnet_deserialize_all(ifp);
616 return bus_generic_suspend(dev);
620 igb_resume(device_t dev)
622 struct igb_softc *sc = device_get_softc(dev);
623 struct ifnet *ifp = &sc->arpcom.ac_if;
625 ifnet_serialize_all(ifp);
632 ifnet_deserialize_all(ifp);
634 return bus_generic_resume(dev);
638 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
640 struct igb_softc *sc = ifp->if_softc;
641 struct ifreq *ifr = (struct ifreq *)data;
642 int max_frame_size, mask, reinit;
645 ASSERT_IFNET_SERIALIZED_ALL(ifp);
649 max_frame_size = 9234;
650 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
656 ifp->if_mtu = ifr->ifr_mtu;
657 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
660 if (ifp->if_flags & IFF_RUNNING)
665 if (ifp->if_flags & IFF_UP) {
666 if (ifp->if_flags & IFF_RUNNING) {
667 if ((ifp->if_flags ^ sc->if_flags) &
668 (IFF_PROMISC | IFF_ALLMULTI)) {
669 igb_disable_promisc(sc);
675 } else if (ifp->if_flags & IFF_RUNNING) {
678 sc->if_flags = ifp->if_flags;
683 if (ifp->if_flags & IFF_RUNNING) {
684 igb_disable_intr(sc);
686 #ifdef DEVICE_POLLING
687 if (!(ifp->if_flags & IFF_POLLING))
695 * As the speed/duplex settings are being
696 * changed, we need toreset the PHY.
698 sc->hw.phy.reset_disable = FALSE;
700 /* Check SOL/IDER usage */
701 if (e1000_check_reset_block(&sc->hw)) {
702 if_printf(ifp, "Media change is "
703 "blocked due to SOL/IDER session.\n");
709 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
714 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
715 if (mask & IFCAP_HWCSUM) {
716 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
719 if (mask & IFCAP_VLAN_HWTAGGING) {
720 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
723 if (reinit && (ifp->if_flags & IFF_RUNNING))
728 error = ether_ioctl(ifp, command, data);
737 struct igb_softc *sc = xsc;
738 struct ifnet *ifp = &sc->arpcom.ac_if;
741 ASSERT_IFNET_SERIALIZED_ALL(ifp);
745 /* Get the latest mac address, User can use a LAA */
746 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
748 /* Put the address into the Receive Address Array */
749 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
752 igb_update_link_status(sc);
754 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
756 /* Set hardware offload abilities */
757 if (ifp->if_capenable & IFCAP_TXCSUM)
758 ifp->if_hwassist = IGB_CSUM_FEATURES;
760 ifp->if_hwassist = 0;
762 /* Configure for OS presence */
765 /* Prepare transmit descriptors and buffers */
766 for (i = 0; i < sc->tx_ring_cnt; ++i)
767 igb_init_tx_ring(&sc->tx_rings[i]);
768 igb_init_tx_unit(sc);
770 /* Setup Multicast table */
775 * Figure out the desired mbuf pool
776 * for doing jumbo/packetsplit
778 if (adapter->max_frame_size <= 2048)
779 adapter->rx_mbuf_sz = MCLBYTES;
780 else if (adapter->max_frame_size <= 4096)
781 adapter->rx_mbuf_sz = MJUMPAGESIZE;
783 adapter->rx_mbuf_sz = MJUM9BYTES;
785 sc->rx_mbuf_sz = MCLBYTES;
788 /* Initialize interrupt */
791 /* Prepare receive descriptors and buffers */
792 for (i = 0; i < sc->rx_ring_cnt; ++i) {
795 error = igb_init_rx_ring(&sc->rx_rings[i]);
797 if_printf(ifp, "Could not setup receive structures\n");
802 igb_init_rx_unit(sc);
804 /* Enable VLAN support */
805 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
808 /* Don't lose promiscuous settings */
811 ifp->if_flags |= IFF_RUNNING;
812 ifp->if_flags &= ~IFF_OACTIVE;
814 callout_reset(&sc->timer, hz, igb_timer, sc);
815 e1000_clear_hw_cntrs_base_generic(&sc->hw);
818 if (adapter->msix > 1) /* Set up queue routing */
819 igb_configure_queues(adapter);
822 /* this clears any pending interrupts */
823 E1000_READ_REG(&sc->hw, E1000_ICR);
824 #ifdef DEVICE_POLLING
826 * Only enable interrupts if we are not polling, make sure
827 * they are off otherwise.
829 if (ifp->if_flags & IFF_POLLING)
830 igb_disable_intr(sc);
832 #endif /* DEVICE_POLLING */
835 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
838 /* Set Energy Efficient Ethernet */
839 e1000_set_eee_i350(&sc->hw);
841 /* Don't reset the phy next time init gets called */
842 sc->hw.phy.reset_disable = TRUE;
846 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
848 struct igb_softc *sc = ifp->if_softc;
849 u_char fiber_type = IFM_1000_SX;
851 ASSERT_IFNET_SERIALIZED_ALL(ifp);
853 igb_update_link_status(sc);
855 ifmr->ifm_status = IFM_AVALID;
856 ifmr->ifm_active = IFM_ETHER;
858 if (!sc->link_active)
861 ifmr->ifm_status |= IFM_ACTIVE;
863 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
864 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
865 ifmr->ifm_active |= fiber_type | IFM_FDX;
867 switch (sc->link_speed) {
869 ifmr->ifm_active |= IFM_10_T;
873 ifmr->ifm_active |= IFM_100_TX;
877 ifmr->ifm_active |= IFM_1000_T;
880 if (sc->link_duplex == FULL_DUPLEX)
881 ifmr->ifm_active |= IFM_FDX;
883 ifmr->ifm_active |= IFM_HDX;
888 igb_media_change(struct ifnet *ifp)
890 struct igb_softc *sc = ifp->if_softc;
891 struct ifmedia *ifm = &sc->media;
893 ASSERT_IFNET_SERIALIZED_ALL(ifp);
895 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
898 switch (IFM_SUBTYPE(ifm->ifm_media)) {
900 sc->hw.mac.autoneg = DO_AUTO_NEG;
901 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
907 sc->hw.mac.autoneg = DO_AUTO_NEG;
908 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
912 sc->hw.mac.autoneg = FALSE;
913 sc->hw.phy.autoneg_advertised = 0;
914 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
915 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
917 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
921 sc->hw.mac.autoneg = FALSE;
922 sc->hw.phy.autoneg_advertised = 0;
923 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
924 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
926 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
930 if_printf(ifp, "Unsupported media type\n");
940 igb_set_promisc(struct igb_softc *sc)
942 struct ifnet *ifp = &sc->arpcom.ac_if;
943 struct e1000_hw *hw = &sc->hw;
947 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
951 reg = E1000_READ_REG(hw, E1000_RCTL);
952 if (ifp->if_flags & IFF_PROMISC) {
953 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
954 E1000_WRITE_REG(hw, E1000_RCTL, reg);
955 } else if (ifp->if_flags & IFF_ALLMULTI) {
956 reg |= E1000_RCTL_MPE;
957 reg &= ~E1000_RCTL_UPE;
958 E1000_WRITE_REG(hw, E1000_RCTL, reg);
963 igb_disable_promisc(struct igb_softc *sc)
965 struct e1000_hw *hw = &sc->hw;
969 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
972 reg = E1000_READ_REG(hw, E1000_RCTL);
973 reg &= ~E1000_RCTL_UPE;
974 reg &= ~E1000_RCTL_MPE;
975 E1000_WRITE_REG(hw, E1000_RCTL, reg);
979 igb_set_multi(struct igb_softc *sc)
981 struct ifnet *ifp = &sc->arpcom.ac_if;
982 struct ifmultiaddr *ifma;
983 uint32_t reg_rctl = 0;
988 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
990 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
991 if (ifma->ifma_addr->sa_family != AF_LINK)
994 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
997 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
998 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1002 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1003 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1004 reg_rctl |= E1000_RCTL_MPE;
1005 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1007 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1012 igb_timer(void *xsc)
1014 struct igb_softc *sc = xsc;
1015 struct ifnet *ifp = &sc->arpcom.ac_if;
1017 ifnet_serialize_all(ifp);
1019 igb_update_link_status(sc);
1020 igb_update_stats_counters(sc);
1022 callout_reset(&sc->timer, hz, igb_timer, sc);
1024 ifnet_deserialize_all(ifp);
1028 igb_update_link_status(struct igb_softc *sc)
1030 struct ifnet *ifp = &sc->arpcom.ac_if;
1031 struct e1000_hw *hw = &sc->hw;
1032 uint32_t link_check, thstat, ctrl;
1034 link_check = thstat = ctrl = 0;
1036 /* Get the cached link value or read for real */
1037 switch (hw->phy.media_type) {
1038 case e1000_media_type_copper:
1039 if (hw->mac.get_link_status) {
1040 /* Do the work to read phy */
1041 e1000_check_for_link(hw);
1042 link_check = !hw->mac.get_link_status;
1048 case e1000_media_type_fiber:
1049 e1000_check_for_link(hw);
1050 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1053 case e1000_media_type_internal_serdes:
1054 e1000_check_for_link(hw);
1055 link_check = hw->mac.serdes_has_link;
1058 /* VF device is type_unknown */
1059 case e1000_media_type_unknown:
1060 e1000_check_for_link(hw);
1061 link_check = !hw->mac.get_link_status;
1067 /* Check for thermal downshift or shutdown */
1068 if (hw->mac.type == e1000_i350) {
1069 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1070 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1073 /* Now we check if a transition has happened */
1074 if (link_check && sc->link_active == 0) {
1075 e1000_get_speed_and_duplex(hw,
1076 &sc->link_speed, &sc->link_duplex);
1078 if_printf(ifp, "Link is up %d Mbps %s\n",
1080 sc->link_duplex == FULL_DUPLEX ?
1081 "Full Duplex" : "Half Duplex");
1083 sc->link_active = 1;
1085 ifp->if_baudrate = sc->link_speed * 1000000;
1086 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1087 (thstat & E1000_THSTAT_LINK_THROTTLE))
1088 if_printf(ifp, "Link: thermal downshift\n");
1089 /* This can sleep */
1090 ifp->if_link_state = LINK_STATE_UP;
1091 if_link_state_change(ifp);
1092 } else if (!link_check && sc->link_active == 1) {
1093 ifp->if_baudrate = sc->link_speed = 0;
1094 sc->link_duplex = 0;
1096 if_printf(ifp, "Link is Down\n");
1097 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1098 (thstat & E1000_THSTAT_PWR_DOWN))
1099 if_printf(ifp, "Link: thermal shutdown\n");
1100 sc->link_active = 0;
1101 /* This can sleep */
1102 ifp->if_link_state = LINK_STATE_DOWN;
1103 if_link_state_change(ifp);
1108 igb_stop(struct igb_softc *sc)
1110 struct ifnet *ifp = &sc->arpcom.ac_if;
1113 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1115 igb_disable_intr(sc);
1117 callout_stop(&sc->timer);
1119 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1122 e1000_reset_hw(&sc->hw);
1123 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1125 e1000_led_off(&sc->hw);
1126 e1000_cleanup_led(&sc->hw);
1128 for (i = 0; i < sc->tx_ring_cnt; ++i)
1129 igb_free_tx_ring(&sc->tx_rings[i]);
1130 for (i = 0; i < sc->rx_ring_cnt; ++i)
1131 igb_free_rx_ring(&sc->rx_rings[i]);
1135 igb_reset(struct igb_softc *sc)
1137 struct ifnet *ifp = &sc->arpcom.ac_if;
1138 struct e1000_hw *hw = &sc->hw;
1139 struct e1000_fc_info *fc = &hw->fc;
1143 /* Let the firmware know the OS is in control */
1144 igb_get_hw_control(sc);
1147 * Packet Buffer Allocation (PBA)
1148 * Writing PBA sets the receive portion of the buffer
1149 * the remainder is used for the transmit buffer.
1151 switch (hw->mac.type) {
1153 pba = E1000_PBA_32K;
1158 pba = E1000_READ_REG(hw, E1000_RXPBS);
1159 pba &= E1000_RXPBS_SIZE_MASK_82576;
1164 case e1000_vfadapt_i350:
1165 pba = E1000_READ_REG(hw, E1000_RXPBS);
1166 pba = e1000_rxpbs_adjust_82580(pba);
1168 /* XXX pba = E1000_PBA_35K; */
1174 /* Special needs in case of Jumbo frames */
1175 if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1176 uint32_t tx_space, min_tx, min_rx;
1178 pba = E1000_READ_REG(hw, E1000_PBA);
1179 tx_space = pba >> 16;
1182 min_tx = (sc->max_frame_size +
1183 sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1184 min_tx = roundup2(min_tx, 1024);
1186 min_rx = sc->max_frame_size;
1187 min_rx = roundup2(min_rx, 1024);
1189 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1190 pba = pba - (min_tx - tx_space);
1192 * if short on rx space, rx wins
1193 * and must trump tx adjustment
1198 E1000_WRITE_REG(hw, E1000_PBA, pba);
1202 * These parameters control the automatic generation (Tx) and
1203 * response (Rx) to Ethernet PAUSE frames.
1204 * - High water mark should allow for at least two frames to be
1205 * received after sending an XOFF.
1206 * - Low water mark works best when it is very near the high water mark.
1207 * This allows the receiver to restart by sending XON when it has
1210 hwm = min(((pba << 10) * 9 / 10),
1211 ((pba << 10) - 2 * sc->max_frame_size));
1213 if (hw->mac.type < e1000_82576) {
1214 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1215 fc->low_water = fc->high_water - 8;
1217 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1218 fc->low_water = fc->high_water - 16;
1220 fc->pause_time = IGB_FC_PAUSE_TIME;
1221 fc->send_xon = TRUE;
1223 /* Issue a global reset */
1225 E1000_WRITE_REG(hw, E1000_WUC, 0);
1227 if (e1000_init_hw(hw) < 0)
1228 if_printf(ifp, "Hardware Initialization Failed\n");
1230 /* Setup DMA Coalescing */
1231 if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1234 hwm = (pba - 4) << 10;
1235 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1236 & E1000_DMACR_DMACTHR_MASK;
1238 /* transition to L0x or L1 if available..*/
1239 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1241 /* timer = +-1000 usec in 32usec intervals */
1243 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1245 /* No lower threshold */
1246 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1248 /* set hwm to PBA - 2 * max frame size */
1249 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1251 /* Set the interval before transition */
1252 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1253 reg |= 0x800000FF; /* 255 usec */
1254 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1256 /* free space in tx packet buffer to wake from DMA coal */
1257 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1258 (20480 - (2 * sc->max_frame_size)) >> 6);
1260 /* make low power state decision controlled by DMA coal */
1261 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1262 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1263 reg | E1000_PCIEMISC_LX_DECISION);
1264 if_printf(ifp, "DMA Coalescing enabled\n");
1267 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1268 e1000_get_phy_info(hw);
1269 e1000_check_for_link(hw);
1273 igb_setup_ifp(struct igb_softc *sc)
1275 struct ifnet *ifp = &sc->arpcom.ac_if;
1277 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1279 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1280 ifp->if_init = igb_init;
1281 ifp->if_ioctl = igb_ioctl;
1282 ifp->if_start = igb_start;
1283 #ifdef DEVICE_POLLING
1284 ifp->if_poll = igb_poll;
1286 ifp->if_watchdog = igb_watchdog;
1288 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1289 ifq_set_ready(&ifp->if_snd);
1291 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1293 ifp->if_capabilities =
1294 IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1295 ifp->if_capenable = ifp->if_capabilities;
1296 ifp->if_hwassist = IGB_CSUM_FEATURES;
1299 * Tell the upper layer(s) we support long frames
1301 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1304 * Specify the media types supported by this adapter and register
1305 * callbacks to update media and link information
1307 ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1308 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1309 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1310 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1312 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1314 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1315 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1317 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1318 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1320 if (sc->hw.phy.type != e1000_phy_ife) {
1321 ifmedia_add(&sc->media,
1322 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1323 ifmedia_add(&sc->media,
1324 IFM_ETHER | IFM_1000_T, 0, NULL);
1327 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1328 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1332 igb_add_sysctl(struct igb_softc *sc)
1334 sysctl_ctx_init(&sc->sysctl_ctx);
1335 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1336 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1337 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1338 if (sc->sysctl_tree == NULL) {
1339 device_printf(sc->dev, "can't add sysctl node\n");
1343 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1344 OID_AUTO, "rxd", CTLFLAG_RD, &sc->num_rx_desc, 0, NULL);
1345 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1346 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
1348 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1349 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1350 sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1352 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1353 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1354 sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1355 "# segments per TX interrupt");
1359 igb_dma_alloc(struct igb_softc *sc)
1364 * Create top level busdma tag
1366 error = bus_dma_tag_create(NULL, 1, 0,
1367 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1368 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1371 device_printf(sc->dev, "could not create top level DMA tag\n");
1376 * Allocate TX descriptor rings and buffers
1378 sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1379 M_DEVBUF, M_WAITOK | M_ZERO);
1380 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1381 struct igb_tx_ring *txr = &sc->tx_rings[i];
1383 /* Set up some basics */
1387 error = igb_create_tx_ring(txr);
1393 * Allocate RX descriptor rings and buffers
1395 sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1396 M_DEVBUF, M_WAITOK | M_ZERO);
1397 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1398 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1400 /* Set up some basics */
1404 error = igb_create_rx_ring(rxr);
1413 igb_dma_free(struct igb_softc *sc)
1417 if (sc->tx_rings != NULL) {
1418 for (i = 0; i < sc->tx_ring_cnt; ++i)
1419 igb_destroy_tx_ring(&sc->tx_rings[i], sc->num_tx_desc);
1420 kfree(sc->tx_rings, M_DEVBUF);
1423 if (sc->rx_rings != NULL) {
1424 for (i = 0; i < sc->rx_ring_cnt; ++i)
1425 igb_destroy_rx_ring(&sc->rx_rings[i], sc->num_rx_desc);
1426 kfree(sc->rx_rings, M_DEVBUF);
1431 igb_create_tx_ring(struct igb_tx_ring *txr)
1433 int tsize, error, i;
1436 * Validate number of transmit descriptors. It must not exceed
1437 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1439 if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1440 (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1441 device_printf(txr->sc->dev,
1442 "Using %d TX descriptors instead of %d!\n",
1443 IGB_DEFAULT_TXD, igb_txd);
1444 txr->sc->num_tx_desc = IGB_DEFAULT_TXD;
1446 txr->sc->num_tx_desc = igb_txd;
1450 * Allocate TX descriptor ring
1452 tsize = roundup2(txr->sc->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1454 txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1455 IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1456 &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1457 if (txr->txdma.dma_vaddr == NULL) {
1458 device_printf(txr->sc->dev,
1459 "Unable to allocate TX Descriptor memory\n");
1462 txr->tx_base = txr->txdma.dma_vaddr;
1463 bzero(txr->tx_base, tsize);
1465 txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->sc->num_tx_desc,
1466 M_DEVBUF, M_WAITOK | M_ZERO);
1469 * Allocate TX head write-back buffer
1471 txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1472 __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1473 &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1474 if (txr->tx_hdr == NULL) {
1475 device_printf(txr->sc->dev,
1476 "Unable to allocate TX head write-back buffer\n");
1481 * Create DMA tag for TX buffers
1483 error = bus_dma_tag_create(txr->sc->parent_tag,
1484 1, 0, /* alignment, bounds */
1485 BUS_SPACE_MAXADDR, /* lowaddr */
1486 BUS_SPACE_MAXADDR, /* highaddr */
1487 NULL, NULL, /* filter, filterarg */
1488 IGB_TSO_SIZE, /* maxsize */
1489 IGB_MAX_SCATTER, /* nsegments */
1490 PAGE_SIZE, /* maxsegsize */
1491 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1492 BUS_DMA_ONEBPAGE, /* flags */
1495 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1496 kfree(txr->tx_buf, M_DEVBUF);
1502 * Create DMA maps for TX buffers
1504 for (i = 0; i < txr->sc->num_tx_desc; ++i) {
1505 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1507 error = bus_dmamap_create(txr->tx_tag,
1508 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1510 device_printf(txr->sc->dev,
1511 "Unable to create TX DMA map\n");
1512 igb_destroy_tx_ring(txr, i);
1518 * Initialize various watermark
1520 txr->spare_desc = IGB_TX_SPARE;
1521 txr->intr_nsegs = txr->sc->num_tx_desc / 16;
1522 txr->oact_hi_desc = txr->sc->num_tx_desc / 2;
1523 txr->oact_lo_desc = txr->sc->num_tx_desc / 8;
1524 if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1525 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1526 if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1527 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1533 igb_free_tx_ring(struct igb_tx_ring *txr)
1537 for (i = 0; i < txr->sc->num_tx_desc; ++i) {
1538 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1540 if (txbuf->m_head != NULL) {
1541 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1542 m_freem(txbuf->m_head);
1543 txbuf->m_head = NULL;
1549 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1553 if (txr->txdma.dma_vaddr != NULL) {
1554 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1555 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1556 txr->txdma.dma_map);
1557 bus_dma_tag_destroy(txr->txdma.dma_tag);
1558 txr->txdma.dma_vaddr = NULL;
1561 if (txr->tx_hdr != NULL) {
1562 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1563 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1565 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1569 if (txr->tx_buf == NULL)
1572 for (i = 0; i < ndesc; ++i) {
1573 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1575 KKASSERT(txbuf->m_head == NULL);
1576 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1578 bus_dma_tag_destroy(txr->tx_tag);
1580 kfree(txr->tx_buf, M_DEVBUF);
1585 igb_init_tx_ring(struct igb_tx_ring *txr)
1587 /* Clear the old descriptor contents */
1589 sizeof(union e1000_adv_tx_desc) * txr->sc->num_tx_desc);
1591 /* Clear TX head write-back buffer */
1595 txr->next_avail_desc = 0;
1596 txr->next_to_clean = 0;
1599 /* Set number of descriptors available */
1600 txr->tx_avail = txr->sc->num_tx_desc;
1604 igb_init_tx_unit(struct igb_softc *sc)
1606 struct e1000_hw *hw = &sc->hw;
1610 /* Setup the Tx Descriptor Rings */
1611 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1612 struct igb_tx_ring *txr = &sc->tx_rings[i];
1613 uint64_t bus_addr = txr->txdma.dma_paddr;
1614 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1615 uint32_t txdctl = 0;
1616 uint32_t dca_txctrl;
1618 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1619 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
1620 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1621 (uint32_t)(bus_addr >> 32));
1622 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1623 (uint32_t)bus_addr);
1625 /* Setup the HW Tx Head and Tail descriptor pointers */
1626 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1627 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1629 txdctl |= IGB_TX_PTHRESH;
1630 txdctl |= IGB_TX_HTHRESH << 8;
1631 txdctl |= IGB_TX_WTHRESH << 16;
1632 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1633 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1635 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1636 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1637 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1639 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1640 (uint32_t)(hdr_paddr >> 32));
1641 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1642 ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1648 e1000_config_collision_dist(hw);
1650 /* Program the Transmit Control Register */
1651 tctl = E1000_READ_REG(hw, E1000_TCTL);
1652 tctl &= ~E1000_TCTL_CT;
1653 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1654 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1656 /* This write will effectively turn on the transmit unit. */
1657 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1661 igb_txctx(struct igb_tx_ring *txr, struct mbuf *mp)
1663 struct e1000_adv_tx_context_desc *TXD;
1664 struct igb_tx_buf *txbuf;
1665 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1666 struct ether_vlan_header *eh;
1667 struct ip *ip = NULL;
1668 int ehdrlen, ctxd, ip_hlen = 0;
1669 uint16_t etype, vlantag = 0;
1670 boolean_t offload = TRUE;
1672 if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1675 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1676 ctxd = txr->next_avail_desc;
1677 txbuf = &txr->tx_buf[ctxd];
1678 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1681 * In advanced descriptors the vlan tag must
1682 * be placed into the context descriptor, thus
1683 * we need to be here just for that setup.
1685 if (mp->m_flags & M_VLANTAG) {
1686 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1687 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1688 } else if (!offload) {
1693 * Determine where frame payload starts.
1694 * Jump over vlan headers if already present,
1695 * helpful for QinQ too.
1697 KASSERT(mp->m_len >= ETHER_HDR_LEN,
1698 ("igb_txctx_pullup is not called (eh)?\n"));
1699 eh = mtod(mp, struct ether_vlan_header *);
1700 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1701 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
1702 ("igb_txctx_pullup is not called (evh)?\n"));
1703 etype = ntohs(eh->evl_proto);
1704 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
1706 etype = ntohs(eh->evl_encap_proto);
1707 ehdrlen = ETHER_HDR_LEN;
1710 /* Set the ether header length */
1711 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1715 KASSERT(mp->m_len >= ehdrlen + IGB_IPVHL_SIZE,
1716 ("igb_txctx_pullup is not called (eh+ip_vhl)?\n"));
1718 /* NOTE: We could only safely access ip.ip_vhl part */
1719 ip = (struct ip *)(mp->m_data + ehdrlen);
1720 ip_hlen = ip->ip_hl << 2;
1722 if (mp->m_pkthdr.csum_flags & CSUM_IP)
1723 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1727 case ETHERTYPE_IPV6:
1728 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1729 ip_hlen = sizeof(struct ip6_hdr);
1730 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
1739 vlan_macip_lens |= ip_hlen;
1740 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1742 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1743 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1744 else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1745 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1747 /* 82575 needs the queue index added */
1748 if (txr->sc->hw.mac.type == e1000_82575)
1749 mss_l4len_idx = txr->me << 4;
1751 /* Now copy bits into descriptor */
1752 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1753 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1754 TXD->seqnum_seed = htole32(0);
1755 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1757 txbuf->m_head = NULL;
1759 /* We've consumed the first desc, adjust counters */
1760 if (++ctxd == txr->sc->num_tx_desc)
1762 txr->next_avail_desc = ctxd;
1769 igb_txeof(struct igb_tx_ring *txr)
1771 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1772 int first, hdr, avail;
1774 if (txr->tx_avail == txr->sc->num_tx_desc)
1777 first = txr->next_to_clean;
1778 hdr = *(txr->tx_hdr);
1783 avail = txr->tx_avail;
1784 while (first != hdr) {
1785 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1788 if (txbuf->m_head) {
1789 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1790 m_freem(txbuf->m_head);
1791 txbuf->m_head = NULL;
1794 if (++first == txr->sc->num_tx_desc)
1797 txr->next_to_clean = first;
1798 txr->tx_avail = avail;
1801 * If we have a minimum free, clear IFF_OACTIVE
1802 * to tell the stack that it is OK to send packets.
1804 if (IGB_IS_NOT_OACTIVE(txr)) {
1805 ifp->if_flags &= ~IFF_OACTIVE;
1808 * We have enough TX descriptors, turn off
1809 * the watchdog. We allow small amount of
1810 * packets (roughly intr_nsegs) pending on
1811 * the transmit ring.
1818 igb_create_rx_ring(struct igb_rx_ring *rxr)
1820 int rsize, i, error;
1823 * Validate number of receive descriptors. It must not exceed
1824 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1826 if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1827 (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1828 device_printf(rxr->sc->dev,
1829 "Using %d RX descriptors instead of %d!\n",
1830 IGB_DEFAULT_RXD, igb_rxd);
1831 rxr->sc->num_rx_desc = IGB_DEFAULT_RXD;
1833 rxr->sc->num_rx_desc = igb_rxd;
1837 * Allocate RX descriptor ring
1839 rsize = roundup2(rxr->sc->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1841 rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1842 IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1843 &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1844 &rxr->rxdma.dma_paddr);
1845 if (rxr->rxdma.dma_vaddr == NULL) {
1846 device_printf(rxr->sc->dev,
1847 "Unable to allocate RxDescriptor memory\n");
1850 rxr->rx_base = rxr->rxdma.dma_vaddr;
1851 bzero(rxr->rx_base, rsize);
1853 rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->sc->num_rx_desc,
1854 M_DEVBUF, M_WAITOK | M_ZERO);
1857 * Create DMA tag for RX buffers
1859 error = bus_dma_tag_create(rxr->sc->parent_tag,
1860 1, 0, /* alignment, bounds */
1861 BUS_SPACE_MAXADDR, /* lowaddr */
1862 BUS_SPACE_MAXADDR, /* highaddr */
1863 NULL, NULL, /* filter, filterarg */
1864 MCLBYTES, /* maxsize */
1866 MCLBYTES, /* maxsegsize */
1867 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
1870 device_printf(rxr->sc->dev,
1871 "Unable to create RX payload DMA tag\n");
1872 kfree(rxr->rx_buf, M_DEVBUF);
1878 * Create spare DMA map for RX buffers
1880 error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
1883 device_printf(rxr->sc->dev,
1884 "Unable to create spare RX DMA maps\n");
1885 bus_dma_tag_destroy(rxr->rx_tag);
1886 kfree(rxr->rx_buf, M_DEVBUF);
1892 * Create DMA maps for RX buffers
1894 for (i = 0; i < rxr->sc->num_rx_desc; i++) {
1895 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1897 error = bus_dmamap_create(rxr->rx_tag,
1898 BUS_DMA_WAITOK, &rxbuf->map);
1900 device_printf(rxr->sc->dev,
1901 "Unable to create RX DMA maps\n");
1902 igb_destroy_rx_ring(rxr, i);
1910 igb_free_rx_ring(struct igb_rx_ring *rxr)
1914 for (i = 0; i < rxr->sc->num_rx_desc; ++i) {
1915 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1917 if (rxbuf->m_head != NULL) {
1918 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
1919 m_freem(rxbuf->m_head);
1920 rxbuf->m_head = NULL;
1924 if (rxr->fmp != NULL)
1931 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
1935 if (rxr->rxdma.dma_vaddr != NULL) {
1936 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
1937 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
1938 rxr->rxdma.dma_map);
1939 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
1940 rxr->rxdma.dma_vaddr = NULL;
1943 if (rxr->rx_buf == NULL)
1946 for (i = 0; i < ndesc; ++i) {
1947 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1949 KKASSERT(rxbuf->m_head == NULL);
1950 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
1952 bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
1953 bus_dma_tag_destroy(rxr->rx_tag);
1955 kfree(rxr->rx_buf, M_DEVBUF);
1960 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
1962 rxd->read.pkt_addr = htole64(rxbuf->paddr);
1963 rxd->wb.upper.status_error = 0;
1967 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
1970 bus_dma_segment_t seg;
1972 struct igb_rx_buf *rxbuf;
1975 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1978 if_printf(&rxr->sc->arpcom.ac_if,
1979 "Unable to allocate RX mbuf\n");
1983 m->m_len = m->m_pkthdr.len = MCLBYTES;
1985 if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
1986 m_adj(m, ETHER_ALIGN);
1988 error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
1989 rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
1993 if_printf(&rxr->sc->arpcom.ac_if,
1994 "Unable to load RX mbuf\n");
1999 rxbuf = &rxr->rx_buf[i];
2000 if (rxbuf->m_head != NULL)
2001 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2004 rxbuf->map = rxr->rx_sparemap;
2005 rxr->rx_sparemap = map;
2008 rxbuf->paddr = seg.ds_addr;
2010 igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2015 igb_init_rx_ring(struct igb_rx_ring *rxr)
2019 /* Clear the ring contents */
2021 rxr->sc->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2023 /* Now replenish the ring mbufs */
2024 for (i = 0; i < rxr->sc->num_rx_desc; ++i) {
2027 error = igb_newbuf(rxr, i, TRUE);
2032 /* Setup our descriptor indices */
2033 rxr->next_to_check = 0;
2037 rxr->discard = FALSE;
2043 igb_init_rx_unit(struct igb_softc *sc)
2045 struct ifnet *ifp = &sc->arpcom.ac_if;
2046 struct e1000_hw *hw = &sc->hw;
2047 uint32_t rctl, rxcsum, srrctl = 0;
2051 * Make sure receives are disabled while setting
2052 * up the descriptor ring
2054 rctl = E1000_READ_REG(hw, E1000_RCTL);
2055 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2059 ** Set up for header split
2061 if (igb_header_split) {
2062 /* Use a standard mbuf for the header */
2063 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2064 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2067 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2070 ** Set up for jumbo frames
2072 if (ifp->if_mtu > ETHERMTU) {
2073 rctl |= E1000_RCTL_LPE;
2075 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2076 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2077 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2078 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2079 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2080 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2082 /* Set maximum packet len */
2083 psize = adapter->max_frame_size;
2084 /* are we on a vlan? */
2085 if (adapter->ifp->if_vlantrunk != NULL)
2086 psize += VLAN_TAG_SIZE;
2087 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2089 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2090 rctl |= E1000_RCTL_SZ_2048;
2093 rctl &= ~E1000_RCTL_LPE;
2094 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2095 rctl |= E1000_RCTL_SZ_2048;
2098 /* Setup the Base and Length of the Rx Descriptor Rings */
2099 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2100 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2101 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2104 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2105 sc->num_rx_desc * sizeof(struct e1000_rx_desc));
2106 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2107 (uint32_t)(bus_addr >> 32));
2108 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2109 (uint32_t)bus_addr);
2110 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2111 /* Enable this Queue */
2112 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2113 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2114 rxdctl &= 0xFFF00000;
2115 rxdctl |= IGB_RX_PTHRESH;
2116 rxdctl |= IGB_RX_HTHRESH << 8;
2117 rxdctl |= IGB_RX_WTHRESH << 16;
2118 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2122 * Setup for RX MultiQueue
2124 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2126 if (sc->rx_ring_cnt >1) {
2127 u32 random[10], mrqc, shift = 0;
2133 arc4rand(&random, sizeof(random), 0);
2134 if (adapter->hw.mac.type == e1000_82575)
2136 /* Warning FM follows */
2137 for (int i = 0; i < 128; i++) {
2139 (i % sc->rx_ring_cnt) << shift;
2142 E1000_RETA(i >> 2), reta.dword);
2144 /* Now fill in hash table */
2145 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2146 for (int i = 0; i < 10; i++)
2147 E1000_WRITE_REG_ARRAY(hw,
2148 E1000_RSSRK(0), i, random[i]);
2150 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2151 E1000_MRQC_RSS_FIELD_IPV4_TCP);
2152 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2153 E1000_MRQC_RSS_FIELD_IPV6_TCP);
2154 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2155 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2156 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2157 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2159 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2162 ** NOTE: Receive Full-Packet Checksum Offload
2163 ** is mutually exclusive with Multiqueue. However
2164 ** this is not the same as TCP/IP checksums which
2167 rxcsum |= E1000_RXCSUM_PCSD;
2172 if (ifp->if_capenable & IFCAP_RXCSUM)
2173 rxcsum |= E1000_RXCSUM_IPPCSE;
2175 rxcsum &= ~E1000_RXCSUM_TUOFL;
2177 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2179 /* Setup the Receive Control Register */
2180 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2181 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2182 E1000_RCTL_RDMTS_HALF |
2183 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2184 /* Strip CRC bytes. */
2185 rctl |= E1000_RCTL_SECRC;
2186 /* Make sure VLAN Filters are off */
2187 rctl &= ~E1000_RCTL_VFE;
2188 /* Don't store bad packets */
2189 rctl &= ~E1000_RCTL_SBP;
2191 /* Enable Receives */
2192 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2195 * Setup the HW Rx Head and Tail Descriptor Pointers
2196 * - needs to be after enable
2198 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2199 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2201 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2202 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->sc->num_rx_desc - 1);
2207 igb_rxeof(struct igb_rx_ring *rxr, int count)
2209 struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2210 union e1000_adv_rx_desc *cur;
2214 i = rxr->next_to_check;
2215 cur = &rxr->rx_base[i];
2216 staterr = le32toh(cur->wb.upper.status_error);
2218 if ((staterr & E1000_RXD_STAT_DD) == 0)
2221 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2222 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2223 struct mbuf *m = NULL;
2226 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2230 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2232 struct mbuf *mp = rxbuf->m_head;
2236 len = le16toh(cur->wb.upper.length);
2237 if (rxr->sc->hw.mac.type == e1000_i350 &&
2238 (staterr & E1000_RXDEXT_STATERR_LB))
2239 vlan = be16toh(cur->wb.upper.vlan);
2241 vlan = le16toh(cur->wb.upper.vlan);
2243 bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2244 BUS_DMASYNC_POSTREAD);
2246 if (igb_newbuf(rxr, i, FALSE) != 0) {
2252 if (rxr->fmp == NULL) {
2253 mp->m_pkthdr.len = len;
2257 rxr->lmp->m_next = mp;
2258 rxr->lmp = rxr->lmp->m_next;
2259 rxr->fmp->m_pkthdr.len += len;
2267 m->m_pkthdr.rcvif = ifp;
2270 if (ifp->if_capenable & IFCAP_RXCSUM)
2271 igb_rxcsum(staterr, m);
2273 if (staterr & E1000_RXD_STAT_VP) {
2274 m->m_pkthdr.ether_vlantag = vlan;
2275 m->m_flags |= M_VLANTAG;
2279 if (ifp->if_capenable & IFCAP_RSS) {
2280 pi = emx_rssinfo(m, &pi0, mrq,
2288 igb_setup_rxdesc(cur, rxbuf);
2290 rxr->discard = TRUE;
2292 rxr->discard = FALSE;
2293 if (rxr->fmp != NULL) {
2302 ether_input_pkt(ifp, m, NULL);
2304 /* Advance our pointers to the next descriptor. */
2305 if (++i == rxr->sc->num_rx_desc)
2308 cur = &rxr->rx_base[i];
2309 staterr = le32toh(cur->wb.upper.status_error);
2311 rxr->next_to_check = i;
2314 i = rxr->sc->num_rx_desc - 1;
2315 E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2320 igb_set_vlan(struct igb_softc *sc)
2322 struct e1000_hw *hw = &sc->hw;
2325 struct ifnet *ifp = sc->arpcom.ac_if;
2329 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2333 reg = E1000_READ_REG(hw, E1000_CTRL);
2334 reg |= E1000_CTRL_VME;
2335 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2338 /* Enable the Filter Table */
2339 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2340 reg = E1000_READ_REG(hw, E1000_RCTL);
2341 reg &= ~E1000_RCTL_CFIEN;
2342 reg |= E1000_RCTL_VFE;
2343 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2347 /* Update the frame size */
2348 E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2349 sc->max_frame_size + VLAN_TAG_SIZE);
2352 /* Don't bother with table if no vlans */
2353 if ((adapter->num_vlans == 0) ||
2354 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2357 ** A soft reset zero's out the VFTA, so
2358 ** we need to repopulate it now.
2360 for (int i = 0; i < IGB_VFTA_SIZE; i++)
2361 if (adapter->shadow_vfta[i] != 0) {
2362 if (adapter->vf_ifp)
2363 e1000_vfta_set_vf(hw,
2364 adapter->shadow_vfta[i], TRUE);
2366 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2367 i, adapter->shadow_vfta[i]);
2373 igb_enable_intr(struct igb_softc *sc)
2375 lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
2377 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2378 /* XXX MSI-X should use sc->intr_mask */
2379 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2380 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2381 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2382 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2384 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2386 E1000_WRITE_FLUSH(&sc->hw);
2390 igb_disable_intr(struct igb_softc *sc)
2392 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2393 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2394 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2396 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2397 E1000_WRITE_FLUSH(&sc->hw);
2399 lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
2403 * Bit of a misnomer, what this really means is
2404 * to enable OS management of the system... aka
2405 * to disable special hardware management features
2408 igb_get_mgmt(struct igb_softc *sc)
2410 if (sc->has_manage) {
2411 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2412 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2414 /* disable hardware interception of ARP */
2415 manc &= ~E1000_MANC_ARP_EN;
2417 /* enable receiving management packets to the host */
2418 manc |= E1000_MANC_EN_MNG2HOST;
2419 manc2h |= 1 << 5; /* Mng Port 623 */
2420 manc2h |= 1 << 6; /* Mng Port 664 */
2421 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2422 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2427 * Give control back to hardware management controller
2431 igb_rel_mgmt(struct igb_softc *sc)
2433 if (sc->has_manage) {
2434 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2436 /* Re-enable hardware interception of ARP */
2437 manc |= E1000_MANC_ARP_EN;
2438 manc &= ~E1000_MANC_EN_MNG2HOST;
2440 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2445 * Sets CTRL_EXT:DRV_LOAD bit.
2447 * For ASF and Pass Through versions of f/w this means that
2448 * the driver is loaded.
2451 igb_get_hw_control(struct igb_softc *sc)
2458 /* Let firmware know the driver has taken over */
2459 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2460 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2461 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2465 * Resets CTRL_EXT:DRV_LOAD bit.
2467 * For ASF and Pass Through versions of f/w this means that the
2468 * driver is no longer loaded.
2471 igb_rel_hw_control(struct igb_softc *sc)
2478 /* Let firmware taken over control of h/w */
2479 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2480 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2481 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2485 igb_is_valid_ether_addr(const uint8_t *addr)
2487 uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2489 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2495 * Enable PCI Wake On Lan capability
2498 igb_enable_wol(device_t dev)
2500 uint16_t cap, status;
2503 /* First find the capabilities pointer*/
2504 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2506 /* Read the PM Capabilities */
2507 id = pci_read_config(dev, cap, 1);
2508 if (id != PCIY_PMG) /* Something wrong */
2512 * OK, we have the power capabilities,
2513 * so now get the status register
2515 cap += PCIR_POWER_STATUS;
2516 status = pci_read_config(dev, cap, 2);
2517 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2518 pci_write_config(dev, cap, status, 2);
2522 igb_update_stats_counters(struct igb_softc *sc)
2524 struct e1000_hw *hw = &sc->hw;
2525 struct e1000_hw_stats *stats;
2526 struct ifnet *ifp = &sc->arpcom.ac_if;
2529 * The virtual function adapter has only a
2530 * small controlled set of stats, do only
2534 igb_update_vf_stats_counters(sc);
2539 if (sc->hw.phy.media_type == e1000_media_type_copper ||
2540 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2542 E1000_READ_REG(hw,E1000_SYMERRS);
2543 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2546 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2547 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2548 stats->scc += E1000_READ_REG(hw, E1000_SCC);
2549 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2551 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2552 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2553 stats->colc += E1000_READ_REG(hw, E1000_COLC);
2554 stats->dc += E1000_READ_REG(hw, E1000_DC);
2555 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2556 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2557 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2560 * For watchdog management we need to know if we have been
2561 * paused during the last interval, so capture that here.
2563 sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2564 stats->xoffrxc += sc->pause_frames;
2565 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2566 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2567 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2568 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2569 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2570 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2571 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2572 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2573 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2574 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2575 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2576 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2578 /* For the 64-bit byte counters the low dword must be read first. */
2579 /* Both registers clear on the read of the high dword */
2581 stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2582 ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2583 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2584 ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2586 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2587 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2588 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2589 stats->roc += E1000_READ_REG(hw, E1000_ROC);
2590 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2592 stats->tor += E1000_READ_REG(hw, E1000_TORH);
2593 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2595 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2596 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2597 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2598 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2599 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2600 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2601 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2602 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2603 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2604 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2606 /* Interrupt Counts */
2608 stats->iac += E1000_READ_REG(hw, E1000_IAC);
2609 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2610 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2611 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2612 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2613 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2614 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2615 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2616 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2618 /* Host to Card Statistics */
2620 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2621 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2622 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2623 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2624 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2625 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2626 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2627 stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2628 ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2629 stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2630 ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2631 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2632 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2633 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2635 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2636 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2637 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2638 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2639 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2640 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2642 ifp->if_collisions = stats->colc;
2645 ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2646 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2649 ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2651 /* Driver specific counters */
2652 sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2653 sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2654 sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2655 sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2656 sc->packet_buf_alloc_tx =
2657 ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2658 sc->packet_buf_alloc_rx =
2659 (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2663 igb_vf_init_stats(struct igb_softc *sc)
2665 struct e1000_hw *hw = &sc->hw;
2666 struct e1000_vf_stats *stats;
2669 stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2670 stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2671 stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2672 stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2673 stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2677 igb_update_vf_stats_counters(struct igb_softc *sc)
2679 struct e1000_hw *hw = &sc->hw;
2680 struct e1000_vf_stats *stats;
2682 if (sc->link_speed == 0)
2686 UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2687 UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2688 UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2689 UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2690 UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2693 #ifdef DEVICE_POLLING
2696 igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2698 struct igb_softc *sc = ifp->if_softc;
2701 ASSERT_SERIALIZED(ifp->if_serializer);
2705 igb_disable_intr(sc);
2708 case POLL_DEREGISTER:
2709 igb_enable_intr(sc);
2712 case POLL_AND_CHECK_STATUS:
2713 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2714 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2715 sc->hw.mac.get_link_status = 1;
2716 igb_update_link_status(sc);
2720 if (ifp->if_flags & IFF_RUNNING) {
2721 igb_rxeof(&sc->rx_rings[0], count);
2723 igb_txeof(&sc->tx_rings[0]);
2724 if (!ifq_is_empty(&ifp->if_snd))
2731 #endif /* DEVICE_POLLING */
2736 struct igb_softc *sc = xsc;
2737 struct ifnet *ifp = &sc->arpcom.ac_if;
2740 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2742 eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
2747 if (ifp->if_flags & IFF_RUNNING) {
2748 if (eicr & sc->rx_rings[0].rx_intr_mask)
2749 igb_rxeof(&sc->rx_rings[0], -1);
2751 if (eicr & sc->tx_rings[0].tx_intr_mask) {
2752 igb_txeof(&sc->tx_rings[0]);
2753 if (!ifq_is_empty(&ifp->if_snd))
2758 if (eicr & E1000_EICR_OTHER) {
2759 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2761 /* Link status change */
2762 if (icr & E1000_ICR_LSC) {
2763 sc->hw.mac.get_link_status = 1;
2764 igb_update_link_status(sc);
2769 * Reading EICR has the side effect to clear interrupt mask,
2770 * so all interrupts need to be enabled here.
2772 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2776 igb_shared_intr(void *xsc)
2778 struct igb_softc *sc = xsc;
2779 struct ifnet *ifp = &sc->arpcom.ac_if;
2782 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2784 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2787 if (reg_icr == 0xffffffff)
2790 /* Definitely not our interrupt. */
2794 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
2797 if (ifp->if_flags & IFF_RUNNING) {
2798 igb_rxeof(&sc->rx_rings[0], -1);
2800 igb_txeof(&sc->tx_rings[0]);
2801 if (!ifq_is_empty(&ifp->if_snd))
2805 /* Link status change */
2806 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2807 sc->hw.mac.get_link_status = 1;
2808 igb_update_link_status(sc);
2811 if (reg_icr & E1000_ICR_RXO)
2816 igb_txctx_pullup(struct igb_tx_ring *txr, struct mbuf **m0)
2818 struct mbuf *m = *m0;
2819 struct ether_header *eh;
2822 txr->ctx_try_pullup++;
2824 len = ETHER_HDR_LEN + IGB_IPVHL_SIZE;
2826 if (__predict_false(!M_WRITABLE(m))) {
2827 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2833 eh = mtod(m, struct ether_header *);
2835 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2836 len += EVL_ENCAPLEN;
2838 if (m->m_len < len) {
2847 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2849 m = m_pullup(m, ETHER_HDR_LEN);
2851 txr->ctx_pullup1_failed++;
2857 eh = mtod(m, struct ether_header *);
2859 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2860 len += EVL_ENCAPLEN;
2862 if (m->m_len < len) {
2864 m = m_pullup(m, len);
2866 txr->ctx_pullup2_failed++;
2876 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
2878 bus_dma_segment_t segs[IGB_MAX_SCATTER];
2880 struct igb_tx_buf *tx_buf, *tx_buf_mapped;
2881 union e1000_adv_tx_desc *txd = NULL;
2882 struct mbuf *m_head = *m_headp;
2883 uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
2884 int maxsegs, nsegs, i, j, error, last = 0;
2885 uint32_t hdrlen = 0;
2887 if (m_head->m_len < IGB_TXCSUM_MINHL &&
2888 ((m_head->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) ||
2889 (m_head->m_flags & M_VLANTAG))) {
2891 * Make sure that ethernet header and ip.ip_hl are in
2892 * contiguous memory, since if TXCSUM or VLANTAG is
2893 * enabled, later TX context descriptor's setup need
2894 * to access ip.ip_hl.
2896 error = igb_txctx_pullup(txr, m_headp);
2898 KKASSERT(*m_headp == NULL);
2904 /* Set basic descriptor constants */
2905 cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
2906 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
2907 if (m_head->m_flags & M_VLANTAG)
2908 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2911 * Map the packet for DMA.
2913 tx_buf = &txr->tx_buf[txr->next_avail_desc];
2914 tx_buf_mapped = tx_buf;
2917 maxsegs = txr->tx_avail - IGB_TX_RESERVED;
2918 KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
2919 if (maxsegs > IGB_MAX_SCATTER)
2920 maxsegs = IGB_MAX_SCATTER;
2922 error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
2923 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2925 if (error == ENOBUFS)
2926 txr->sc->mbuf_defrag_failed++;
2928 txr->sc->no_tx_dma_setup++;
2934 bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
2940 * Set up the context descriptor:
2941 * used when any hardware offload is done.
2942 * This includes CSUM, VLAN, and TSO. It
2943 * will use the first descriptor.
2945 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2946 if (igb_tso_setup(txr, m_head, &hdrlen)) {
2947 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2948 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2949 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2952 } else if (igb_tx_ctx_setup(txr, m_head))
2953 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2955 if (igb_txctx(txr, m_head)) {
2956 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
2957 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
2958 olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
2963 txr->tx_nsegs += nsegs;
2964 if (txr->tx_nsegs >= txr->intr_nsegs) {
2966 * Report Status (RS) is turned on every intr_nsegs
2967 * descriptors (roughly).
2970 cmd_rs = E1000_ADVTXD_DCMD_RS;
2973 /* Calculate payload length */
2974 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
2975 << E1000_ADVTXD_PAYLEN_SHIFT);
2977 /* 82575 needs the queue index added */
2978 if (txr->sc->hw.mac.type == e1000_82575)
2979 olinfo_status |= txr->me << 4;
2981 /* Set up our transmit descriptors */
2982 i = txr->next_avail_desc;
2983 for (j = 0; j < nsegs; j++) {
2985 bus_addr_t seg_addr;
2987 tx_buf = &txr->tx_buf[i];
2988 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
2989 seg_addr = segs[j].ds_addr;
2990 seg_len = segs[j].ds_len;
2992 txd->read.buffer_addr = htole64(seg_addr);
2993 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
2994 txd->read.olinfo_status = htole32(olinfo_status);
2996 if (++i == txr->sc->num_tx_desc)
2998 tx_buf->m_head = NULL;
3001 KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3002 txr->next_avail_desc = i;
3003 txr->tx_avail -= nsegs;
3005 tx_buf->m_head = m_head;
3006 tx_buf_mapped->map = tx_buf->map;
3010 * Last Descriptor of Packet needs End Of Packet (EOP)
3012 txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3015 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3016 * that this frame is available to transmit.
3018 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3025 igb_start(struct ifnet *ifp)
3027 struct igb_softc *sc = ifp->if_softc;
3028 struct igb_tx_ring *txr = &sc->tx_rings[0];
3029 struct mbuf *m_head;
3031 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3033 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
3036 if (!sc->link_active) {
3037 ifq_purge(&ifp->if_snd);
3041 if (!IGB_IS_NOT_OACTIVE(txr))
3044 while (!ifq_is_empty(&ifp->if_snd)) {
3045 if (IGB_IS_OACTIVE(txr)) {
3046 ifp->if_flags |= IFF_OACTIVE;
3047 /* Set watchdog on */
3052 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3056 if (igb_encap(txr, &m_head)) {
3061 /* Send a copy of the frame to the BPF listener */
3062 ETHER_BPF_MTAP(ifp, m_head);
3067 igb_watchdog(struct ifnet *ifp)
3069 struct igb_softc *sc = ifp->if_softc;
3070 struct igb_tx_ring *txr = &sc->tx_rings[0];
3072 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3075 * If flow control has paused us since last checking
3076 * it invalidates the watchdog timing, so dont run it.
3078 if (sc->pause_frames) {
3079 sc->pause_frames = 0;
3084 if_printf(ifp, "Watchdog timeout -- resetting\n");
3085 if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3086 E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3087 E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3088 if_printf(ifp, "TX(%d) desc avail = %d, "
3089 "Next TX to Clean = %d\n",
3090 txr->me, txr->tx_avail, txr->next_to_clean);
3093 sc->watchdog_events++;
3096 if (!ifq_is_empty(&ifp->if_snd))
3101 igb_set_eitr(struct igb_softc *sc)
3105 if (sc->intr_rate > 0) {
3106 if (sc->hw.mac.type == e1000_82575) {
3107 itr = 1000000000 / 256 / sc->intr_rate;
3110 * Document is wrong on the 2 bits left shift
3113 itr = 1000000 / sc->intr_rate;
3118 if (sc->hw.mac.type == e1000_82575)
3121 itr |= E1000_EITR_CNT_IGNR;
3122 E1000_WRITE_REG(&sc->hw, E1000_EITR(0), itr);
3126 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3128 struct igb_softc *sc = (void *)arg1;
3129 struct ifnet *ifp = &sc->arpcom.ac_if;
3130 int error, intr_rate;
3132 intr_rate = sc->intr_rate;
3133 error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3134 if (error || req->newptr == NULL)
3139 ifnet_serialize_all(ifp);
3141 sc->intr_rate = intr_rate;
3142 if (ifp->if_flags & IFF_RUNNING)
3145 ifnet_deserialize_all(ifp);
3148 if_printf(ifp, "Interrupt rate set to %d/sec\n", sc->intr_rate);
3153 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3155 struct igb_softc *sc = (void *)arg1;
3156 struct ifnet *ifp = &sc->arpcom.ac_if;
3157 struct igb_tx_ring *txr = &sc->tx_rings[0];
3160 nsegs = txr->intr_nsegs;
3161 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3162 if (error || req->newptr == NULL)
3167 ifnet_serialize_all(ifp);
3169 if (nsegs >= sc->num_tx_desc - txr->oact_lo_desc ||
3170 nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3174 txr->intr_nsegs = nsegs;
3177 ifnet_deserialize_all(ifp);
3183 igb_init_intr(struct igb_softc *sc)
3185 if (sc->flags & IGB_FLAG_SHARED_INTR)
3188 igb_init_unshared_intr(sc);
3192 igb_init_unshared_intr(struct igb_softc *sc)
3194 struct e1000_hw *hw = &sc->hw;
3195 const struct igb_rx_ring *rxr;
3196 const struct igb_tx_ring *txr;
3197 uint32_t ivar, index;
3201 * Enable extended mode
3203 if (sc->hw.mac.type != e1000_82575) {
3204 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_NSICR);
3208 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3209 tmp |= E1000_CTRL_EXT_IRCA;
3210 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3214 * Map TX/RX interrupts to EICR
3216 switch (sc->hw.mac.type) {
3220 case e1000_vfadapt_i350:
3222 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3223 rxr = &sc->rx_rings[i];
3226 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3231 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3235 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3237 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3240 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3241 txr = &sc->tx_rings[i];
3244 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3249 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3253 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3255 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3257 /* Clear unused IVAR_MISC */
3258 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3263 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3264 rxr = &sc->rx_rings[i];
3266 index = i & 0x7; /* Each IVAR has two entries */
3267 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3272 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3276 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3278 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3281 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3282 txr = &sc->tx_rings[i];
3284 index = i & 0x7; /* Each IVAR has two entries */
3285 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3290 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3294 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3296 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3298 /* Clear unused IVAR_MISC */
3299 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3304 * Enable necessary interrupt bits.
3306 * The name of the register is confusing; in addition to
3307 * configuring the first vector of MSI-X, it also configures
3308 * which bits of EICR could be set by the hardware even when
3309 * MSI or line interrupt is used; it thus controls interrupt
3310 * generation. It MUST be configured explicitly; the default
3311 * value mentioned in the datasheet is wrong: RX queue0 and
3312 * TX queue0 are NOT enabled by default.
3314 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3322 * Configure interrupt moderation
3328 igb_setup_intr(struct igb_softc *sc)
3330 struct ifnet *ifp = &sc->arpcom.ac_if;
3334 * Setup interrupt mask
3336 for (i = 0; i < sc->tx_ring_cnt; ++i)
3337 igb_setup_tx_intr(&sc->tx_rings[i]);
3338 for (i = 0; i < sc->rx_ring_cnt; ++i)
3339 igb_setup_rx_intr(&sc->rx_rings[i]);
3341 sc->intr_mask = E1000_EICR_OTHER;
3342 for (i = 0; i < sc->rx_ring_cnt; ++i)
3343 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3344 for (i = 0; i < sc->tx_ring_cnt; ++i)
3345 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3347 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3350 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3352 sc->flags |= IGB_FLAG_SHARED_INTR;
3354 device_printf(sc->dev, "IRQ shared\n");
3355 } else if (bootverbose) {
3356 device_printf(sc->dev, "IRQ unshared\n");
3360 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3361 (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_shared_intr : igb_intr,
3362 sc, &sc->intr_tag, ifp->if_serializer);
3364 device_printf(sc->dev, "Failed to register interrupt handler");
3368 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3369 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3375 igb_setup_tx_intr(struct igb_tx_ring *txr)
3377 if (txr->sc->hw.mac.type == e1000_82575) {
3378 txr->tx_intr_bit = 0; /* unused */
3381 txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3384 txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3387 txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3390 txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3393 panic("unsupported # of TX ring, %d\n", txr->me);
3396 txr->tx_intr_bit = 0; /* XXX */
3397 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3402 igb_setup_rx_intr(struct igb_rx_ring *rxr)
3404 if (rxr->sc->hw.mac.type == e1000_82575) {
3405 rxr->rx_intr_bit = 0; /* unused */
3408 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3411 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3414 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3417 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3420 panic("unsupported # of RX ring, %d\n", rxr->me);
3423 rxr->rx_intr_bit = 1; /* XXX */
3424 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;