igb: Main serializer should be enough to protect link status
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
1 /*
2  * Copyright (c) 2001-2011, Intel Corporation 
3  * All rights reserved.
4  * 
5  * Redistribution and use in source and binary forms, with or without 
6  * modification, are permitted provided that the following conditions are met:
7  * 
8  *  1. Redistributions of source code must retain the above copyright notice, 
9  *     this list of conditions and the following disclaimer.
10  * 
11  *  2. Redistributions in binary form must reproduce the above copyright 
12  *     notice, this list of conditions and the following disclaimer in the 
13  *     documentation and/or other materials provided with the distribution.
14  * 
15  *  3. Neither the name of the Intel Corporation nor the names of its 
16  *     contributors may be used to endorse or promote products derived from 
17  *     this software without specific prior written permission.
18  * 
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31
32 #include "opt_polling.h"
33 #include "opt_igb.h"
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/endian.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/mbuf.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/serialize.h>
45 #include <sys/serialize2.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
50
51 #include <net/bpf.h>
52 #include <net/ethernet.h>
53 #include <net/if.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
58 #include <net/toeplitz.h>
59 #include <net/toeplitz2.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 #include <net/if_poll.h>
63
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
69
70 #include <bus/pci/pcivar.h>
71 #include <bus/pci/pcireg.h>
72
73 #include <dev/netif/ig_hal/e1000_api.h>
74 #include <dev/netif/ig_hal/e1000_82575.h>
75 #include <dev/netif/igb/if_igb.h>
76
77 #ifdef IGB_RSS_DEBUG
78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
79 do { \
80         if (sc->rss_debug >= lvl) \
81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
82 } while (0)
83 #else   /* !IGB_RSS_DEBUG */
84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
85 #endif  /* IGB_RSS_DEBUG */
86
87 #define IGB_NAME        "Intel(R) PRO/1000 "
88 #define IGB_DEVICE(id)  \
89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90 #define IGB_DEVICE_NULL { 0, 0, NULL }
91
92 static struct igb_device {
93         uint16_t        vid;
94         uint16_t        did;
95         const char      *desc;
96 } igb_devices[] = {
97         IGB_DEVICE(82575EB_COPPER),
98         IGB_DEVICE(82575EB_FIBER_SERDES),
99         IGB_DEVICE(82575GB_QUAD_COPPER),
100         IGB_DEVICE(82576),
101         IGB_DEVICE(82576_NS),
102         IGB_DEVICE(82576_NS_SERDES),
103         IGB_DEVICE(82576_FIBER),
104         IGB_DEVICE(82576_SERDES),
105         IGB_DEVICE(82576_SERDES_QUAD),
106         IGB_DEVICE(82576_QUAD_COPPER),
107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
108         IGB_DEVICE(82576_VF),
109         IGB_DEVICE(82580_COPPER),
110         IGB_DEVICE(82580_FIBER),
111         IGB_DEVICE(82580_SERDES),
112         IGB_DEVICE(82580_SGMII),
113         IGB_DEVICE(82580_COPPER_DUAL),
114         IGB_DEVICE(82580_QUAD_FIBER),
115         IGB_DEVICE(DH89XXCC_SERDES),
116         IGB_DEVICE(DH89XXCC_SGMII),
117         IGB_DEVICE(DH89XXCC_SFP),
118         IGB_DEVICE(DH89XXCC_BACKPLANE),
119         IGB_DEVICE(I350_COPPER),
120         IGB_DEVICE(I350_FIBER),
121         IGB_DEVICE(I350_SERDES),
122         IGB_DEVICE(I350_SGMII),
123         IGB_DEVICE(I350_VF),
124
125         /* required last entry */
126         IGB_DEVICE_NULL
127 };
128
129 static int      igb_probe(device_t);
130 static int      igb_attach(device_t);
131 static int      igb_detach(device_t);
132 static int      igb_shutdown(device_t);
133 static int      igb_suspend(device_t);
134 static int      igb_resume(device_t);
135
136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137 static void     igb_setup_ifp(struct igb_softc *);
138 static int      igb_txctx_pullup(struct igb_tx_ring *, struct mbuf **);
139 static boolean_t igb_txctx(struct igb_tx_ring *, struct mbuf *);
140 static void     igb_add_sysctl(struct igb_softc *);
141 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
142 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
143
144 static void     igb_vf_init_stats(struct igb_softc *);
145 static void     igb_reset(struct igb_softc *);
146 static void     igb_update_stats_counters(struct igb_softc *);
147 static void     igb_update_vf_stats_counters(struct igb_softc *);
148 static void     igb_update_link_status(struct igb_softc *);
149 static void     igb_init_tx_unit(struct igb_softc *);
150 static void     igb_init_rx_unit(struct igb_softc *);
151
152 static void     igb_set_vlan(struct igb_softc *);
153 static void     igb_set_multi(struct igb_softc *);
154 static void     igb_set_promisc(struct igb_softc *);
155 static void     igb_disable_promisc(struct igb_softc *);
156
157 static int      igb_alloc_rings(struct igb_softc *);
158 static void     igb_free_rings(struct igb_softc *);
159 static int      igb_create_tx_ring(struct igb_tx_ring *);
160 static int      igb_create_rx_ring(struct igb_rx_ring *);
161 static void     igb_free_tx_ring(struct igb_tx_ring *);
162 static void     igb_free_rx_ring(struct igb_rx_ring *);
163 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
164 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
165 static void     igb_init_tx_ring(struct igb_tx_ring *);
166 static int      igb_init_rx_ring(struct igb_rx_ring *);
167 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
168 static int      igb_encap(struct igb_tx_ring *, struct mbuf **);
169
170 static void     igb_stop(struct igb_softc *);
171 static void     igb_init(void *);
172 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
173 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
174 static int      igb_media_change(struct ifnet *);
175 static void     igb_timer(void *);
176 static void     igb_watchdog(struct ifnet *);
177 static void     igb_start(struct ifnet *);
178 #ifdef DEVICE_POLLING
179 static void     igb_poll(struct ifnet *, enum poll_cmd, int);
180 #endif
181 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
182 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
183 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
184 #ifdef INVARIANTS
185 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
186                     boolean_t);
187 #endif
188
189 static void     igb_intr(void *);
190 static void     igb_shared_intr(void *);
191 static void     igb_rxeof(struct igb_rx_ring *, int);
192 static void     igb_txeof(struct igb_tx_ring *);
193 static void     igb_set_eitr(struct igb_softc *);
194 static void     igb_enable_intr(struct igb_softc *);
195 static void     igb_disable_intr(struct igb_softc *);
196 static void     igb_init_unshared_intr(struct igb_softc *);
197 static void     igb_init_intr(struct igb_softc *);
198 static int      igb_setup_intr(struct igb_softc *);
199 static void     igb_setup_tx_intr(struct igb_tx_ring *, int *, int);
200 static void     igb_setup_rx_intr(struct igb_rx_ring *, int *, int);
201
202 /* Management and WOL Support */
203 static void     igb_get_mgmt(struct igb_softc *);
204 static void     igb_rel_mgmt(struct igb_softc *);
205 static void     igb_get_hw_control(struct igb_softc *);
206 static void     igb_rel_hw_control(struct igb_softc *);
207 static void     igb_enable_wol(device_t);
208
209 static device_method_t igb_methods[] = {
210         /* Device interface */
211         DEVMETHOD(device_probe,         igb_probe),
212         DEVMETHOD(device_attach,        igb_attach),
213         DEVMETHOD(device_detach,        igb_detach),
214         DEVMETHOD(device_shutdown,      igb_shutdown),
215         DEVMETHOD(device_suspend,       igb_suspend),
216         DEVMETHOD(device_resume,        igb_resume),
217         { 0, 0 }
218 };
219
220 static driver_t igb_driver = {
221         "igb",
222         igb_methods,
223         sizeof(struct igb_softc),
224 };
225
226 static devclass_t igb_devclass;
227
228 DECLARE_DUMMY_MODULE(if_igb);
229 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
230 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
231
232 static int      igb_rxd = IGB_DEFAULT_RXD;
233 static int      igb_txd = IGB_DEFAULT_TXD;
234 static int      igb_rxr = 0;
235 static int      igb_msi_enable = 1;
236 static int      igb_msix_enable = 1;
237 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
238 static int      igb_fc_setting = e1000_fc_full;
239
240 /*
241  * DMA Coalescing, only for i350 - default to off,
242  * this feature is for power savings
243  */
244 static int      igb_dma_coalesce = 0;
245
246 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
247 TUNABLE_INT("hw.igb.txd", &igb_txd);
248 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
249 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
250 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
251 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
252
253 /* i350 specific */
254 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
255 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
256
257 static __inline void
258 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
259 {
260         /* Ignore Checksum bit is set */
261         if (staterr & E1000_RXD_STAT_IXSM)
262                 return;
263
264         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
265             E1000_RXD_STAT_IPCS)
266                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
267
268         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
269                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
270                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
271                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
272                         mp->m_pkthdr.csum_data = htons(0xffff);
273                 }
274         }
275 }
276
277 static __inline struct pktinfo *
278 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
279     uint32_t hash, uint32_t hashtype, uint32_t staterr)
280 {
281         switch (hashtype) {
282         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
283                 pi->pi_netisr = NETISR_IP;
284                 pi->pi_flags = 0;
285                 pi->pi_l3proto = IPPROTO_TCP;
286                 break;
287
288         case E1000_RXDADV_RSSTYPE_IPV4:
289                 if (staterr & E1000_RXD_STAT_IXSM)
290                         return NULL;
291
292                 if ((staterr &
293                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
294                     E1000_RXD_STAT_TCPCS) {
295                         pi->pi_netisr = NETISR_IP;
296                         pi->pi_flags = 0;
297                         pi->pi_l3proto = IPPROTO_UDP;
298                         break;
299                 }
300                 /* FALL THROUGH */
301         default:
302                 return NULL;
303         }
304
305         m->m_flags |= M_HASH;
306         m->m_pkthdr.hash = toeplitz_hash(hash);
307         return pi;
308 }
309
310 static int
311 igb_probe(device_t dev)
312 {
313         const struct igb_device *d;
314         uint16_t vid, did;
315
316         vid = pci_get_vendor(dev);
317         did = pci_get_device(dev);
318
319         for (d = igb_devices; d->desc != NULL; ++d) {
320                 if (vid == d->vid && did == d->did) {
321                         device_set_desc(dev, d->desc);
322                         return 0;
323                 }
324         }
325         return ENXIO;
326 }
327
328 static int
329 igb_attach(device_t dev)
330 {
331         struct igb_softc *sc = device_get_softc(dev);
332         uint16_t eeprom_data;
333         u_int intr_flags;
334         int error = 0, i, j, ring_max;
335
336 #ifdef notyet
337         /* SYSCTL stuff */
338         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
339             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
340             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
341             igb_sysctl_nvm_info, "I", "NVM Information");
342
343         SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
344             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
345             OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
346             &igb_enable_aim, 1, "Interrupt Moderation");
347
348         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
349             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
350             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
351             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
352 #endif
353
354         callout_init_mp(&sc->timer);
355
356         sc->dev = sc->osdep.dev = dev;
357
358         /*
359          * Determine hardware and mac type
360          */
361         sc->hw.vendor_id = pci_get_vendor(dev);
362         sc->hw.device_id = pci_get_device(dev);
363         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
364         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
365         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
366
367         if (e1000_set_mac_type(&sc->hw))
368                 return ENXIO;
369
370         /* Are we a VF device? */
371         if (sc->hw.mac.type == e1000_vfadapt ||
372             sc->hw.mac.type == e1000_vfadapt_i350)
373                 sc->vf_ifp = 1;
374         else
375                 sc->vf_ifp = 0;
376
377         /* Enable bus mastering */
378         pci_enable_busmaster(dev);
379
380         /*
381          * Allocate IO memory
382          */
383         sc->mem_rid = PCIR_BAR(0);
384         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
385             RF_ACTIVE);
386         if (sc->mem_res == NULL) {
387                 device_printf(dev, "Unable to allocate bus resource: memory\n");
388                 error = ENXIO;
389                 goto failed;
390         }
391         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
392         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
393
394         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
395
396         /*
397          * Allocate interrupt
398          */
399         sc->intr_type = pci_alloc_1intr(dev, igb_msi_enable,
400             &sc->intr_rid, &intr_flags);
401
402         sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
403             intr_flags);
404         if (sc->intr_res == NULL) {
405                 device_printf(dev, "Unable to allocate bus resource: "
406                     "interrupt\n");
407                 error = ENXIO;
408                 goto failed;
409         }
410
411         /* Save PCI command register for Shared Code */
412         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
413         sc->hw.back = &sc->osdep;
414
415         switch (sc->hw.mac.type) {
416         case e1000_82575:
417                 ring_max = IGB_MAX_RING_82575;
418                 break;
419         case e1000_82580:
420                 ring_max = IGB_MAX_RING_82580;
421                 break;
422         case e1000_i350:
423                 ring_max = IGB_MAX_RING_I350;
424                 break;
425         case e1000_82576:
426                 ring_max = IGB_MAX_RING_82576;
427                 break;
428         default:
429                 ring_max = IGB_MIN_RING;
430                 break;
431         }
432         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
433         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
434         sc->tx_ring_cnt = 1; /* XXX */
435
436         sc->intr_rate = IGB_INTR_RATE;
437
438         /* Do Shared Code initialization */
439         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
440                 device_printf(dev, "Setup of Shared code failed\n");
441                 error = ENXIO;
442                 goto failed;
443         }
444
445         e1000_get_bus_info(&sc->hw);
446
447         sc->hw.mac.autoneg = DO_AUTO_NEG;
448         sc->hw.phy.autoneg_wait_to_complete = FALSE;
449         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
450
451         /* Copper options */
452         if (sc->hw.phy.media_type == e1000_media_type_copper) {
453                 sc->hw.phy.mdix = AUTO_ALL_MODES;
454                 sc->hw.phy.disable_polarity_correction = FALSE;
455                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
456         }
457
458         /* Set the frame limits assuming  standard ethernet sized frames. */
459         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
460
461         /* Allocate RX/TX rings */
462         error = igb_alloc_rings(sc);
463         if (error)
464                 goto failed;
465
466         /*
467          * Setup serializers
468          */
469         lwkt_serialize_init(&sc->main_serialize);
470         i = 0;
471         sc->serializes[i++] = &sc->main_serialize;
472
473         sc->tx_serialize = i;
474         for (j = 0; j < sc->tx_ring_cnt; ++j)
475                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
476
477         sc->rx_serialize = i;
478         for (j = 0; j < sc->rx_ring_cnt; ++j)
479                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
480
481         sc->serialize_cnt = i;
482         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
483
484         /* Allocate the appropriate stats memory */
485         if (sc->vf_ifp) {
486                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
487                     M_WAITOK | M_ZERO);
488                 igb_vf_init_stats(sc);
489         } else {
490                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
491                     M_WAITOK | M_ZERO);
492         }
493
494         /* Allocate multicast array memory. */
495         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
496             M_DEVBUF, M_WAITOK);
497
498         /* Some adapter-specific advanced features */
499         if (sc->hw.mac.type >= e1000_i350) {
500 #ifdef notyet
501                 igb_set_sysctl_value(adapter, "dma_coalesce",
502                     "configure dma coalesce",
503                     &adapter->dma_coalesce, igb_dma_coalesce);
504                 igb_set_sysctl_value(adapter, "eee_disabled",
505                     "enable Energy Efficient Ethernet",
506                     &adapter->hw.dev_spec._82575.eee_disable,
507                     igb_eee_disabled);
508 #else
509                 sc->dma_coalesce = igb_dma_coalesce;
510                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
511 #endif
512                 e1000_set_eee_i350(&sc->hw);
513         }
514
515         /*
516          * Start from a known state, this is important in reading the nvm and
517          * mac from that.
518          */
519         e1000_reset_hw(&sc->hw);
520
521         /* Make sure we have a good EEPROM before we read from it */
522         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
523                 /*
524                  * Some PCI-E parts fail the first check due to
525                  * the link being in sleep state, call it again,
526                  * if it fails a second time its a real issue.
527                  */
528                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
529                         device_printf(dev,
530                             "The EEPROM Checksum Is Not Valid\n");
531                         error = EIO;
532                         goto failed;
533                 }
534         }
535
536         /* Copy the permanent MAC address out of the EEPROM */
537         if (e1000_read_mac_addr(&sc->hw) < 0) {
538                 device_printf(dev, "EEPROM read error while reading MAC"
539                     " address\n");
540                 error = EIO;
541                 goto failed;
542         }
543         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
544                 device_printf(dev, "Invalid MAC address\n");
545                 error = EIO;
546                 goto failed;
547         }
548
549 #ifdef notyet
550         /* 
551         ** Configure Interrupts
552         */
553         if ((adapter->msix > 1) && (igb_enable_msix))
554                 error = igb_allocate_msix(adapter);
555         else /* MSI or Legacy */
556                 error = igb_allocate_legacy(adapter);
557         if (error)
558                 goto err_late;
559 #endif
560
561         /* Setup OS specific network interface */
562         igb_setup_ifp(sc);
563
564         /* Add sysctl tree, must after igb_setup_ifp() */
565         igb_add_sysctl(sc);
566
567         /* Now get a good starting state */
568         igb_reset(sc);
569
570         /* Initialize statistics */
571         igb_update_stats_counters(sc);
572
573         sc->hw.mac.get_link_status = 1;
574         igb_update_link_status(sc);
575
576         /* Indicate SOL/IDER usage */
577         if (e1000_check_reset_block(&sc->hw)) {
578                 device_printf(dev,
579                     "PHY reset is blocked due to SOL/IDER session.\n");
580         }
581
582         /* Determine if we have to control management hardware */
583         if (e1000_enable_mng_pass_thru(&sc->hw))
584                 sc->flags |= IGB_FLAG_HAS_MGMT;
585
586         /*
587          * Setup Wake-on-Lan
588          */
589         /* APME bit in EEPROM is mapped to WUC.APME */
590         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
591         if (eeprom_data)
592                 sc->wol = E1000_WUFC_MAG;
593         /* XXX disable WOL */
594         sc->wol = 0; 
595
596 #ifdef notyet
597         /* Register for VLAN events */
598         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
599              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
600         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
601              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
602 #endif
603
604 #ifdef notyet
605         igb_add_hw_stats(adapter);
606 #endif
607
608         error = igb_setup_intr(sc);
609         if (error) {
610                 ether_ifdetach(&sc->arpcom.ac_if);
611                 goto failed;
612         }
613         return 0;
614
615 failed:
616         igb_detach(dev);
617         return error;
618 }
619
620 static int
621 igb_detach(device_t dev)
622 {
623         struct igb_softc *sc = device_get_softc(dev);
624
625         if (device_is_attached(dev)) {
626                 struct ifnet *ifp = &sc->arpcom.ac_if;
627
628                 ifnet_serialize_all(ifp);
629
630                 igb_stop(sc);
631
632                 e1000_phy_hw_reset(&sc->hw);
633
634                 /* Give control back to firmware */
635                 igb_rel_mgmt(sc);
636                 igb_rel_hw_control(sc);
637
638                 if (sc->wol) {
639                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
640                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
641                         igb_enable_wol(dev);
642                 }
643
644                 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
645
646                 ifnet_deserialize_all(ifp);
647
648                 ether_ifdetach(ifp);
649         } else if (sc->mem_res != NULL) {
650                 igb_rel_hw_control(sc);
651         }
652         bus_generic_detach(dev);
653
654         if (sc->intr_res != NULL) {
655                 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
656                     sc->intr_res);
657         }
658         if (sc->intr_type == PCI_INTR_TYPE_MSI)
659                 pci_release_msi(dev);
660
661         if (sc->mem_res != NULL) {
662                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
663                     sc->mem_res);
664         }
665
666         igb_free_rings(sc);
667
668         if (sc->mta != NULL)
669                 kfree(sc->mta, M_DEVBUF);
670         if (sc->stats != NULL)
671                 kfree(sc->stats, M_DEVBUF);
672
673         if (sc->sysctl_tree != NULL)
674                 sysctl_ctx_free(&sc->sysctl_ctx);
675
676         return 0;
677 }
678
679 static int
680 igb_shutdown(device_t dev)
681 {
682         return igb_suspend(dev);
683 }
684
685 static int
686 igb_suspend(device_t dev)
687 {
688         struct igb_softc *sc = device_get_softc(dev);
689         struct ifnet *ifp = &sc->arpcom.ac_if;
690
691         ifnet_serialize_all(ifp);
692
693         igb_stop(sc);
694
695         igb_rel_mgmt(sc);
696         igb_rel_hw_control(sc);
697
698         if (sc->wol) {
699                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
700                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
701                 igb_enable_wol(dev);
702         }
703
704         ifnet_deserialize_all(ifp);
705
706         return bus_generic_suspend(dev);
707 }
708
709 static int
710 igb_resume(device_t dev)
711 {
712         struct igb_softc *sc = device_get_softc(dev);
713         struct ifnet *ifp = &sc->arpcom.ac_if;
714
715         ifnet_serialize_all(ifp);
716
717         igb_init(sc);
718         igb_get_mgmt(sc);
719
720         if_devstart(ifp);
721
722         ifnet_deserialize_all(ifp);
723
724         return bus_generic_resume(dev);
725 }
726
727 static int
728 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
729 {
730         struct igb_softc *sc = ifp->if_softc;
731         struct ifreq *ifr = (struct ifreq *)data;
732         int max_frame_size, mask, reinit;
733         int error = 0;
734
735         ASSERT_IFNET_SERIALIZED_ALL(ifp);
736
737         switch (command) {
738         case SIOCSIFMTU:
739                 max_frame_size = 9234;
740                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
741                     ETHER_CRC_LEN) {
742                         error = EINVAL;
743                         break;
744                 }
745
746                 ifp->if_mtu = ifr->ifr_mtu;
747                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
748                     ETHER_CRC_LEN;
749
750                 if (ifp->if_flags & IFF_RUNNING)
751                         igb_init(sc);
752                 break;
753
754         case SIOCSIFFLAGS:
755                 if (ifp->if_flags & IFF_UP) {
756                         if (ifp->if_flags & IFF_RUNNING) {
757                                 if ((ifp->if_flags ^ sc->if_flags) &
758                                     (IFF_PROMISC | IFF_ALLMULTI)) {
759                                         igb_disable_promisc(sc);
760                                         igb_set_promisc(sc);
761                                 }
762                         } else {
763                                 igb_init(sc);
764                         }
765                 } else if (ifp->if_flags & IFF_RUNNING) {
766                         igb_stop(sc);
767                 }
768                 sc->if_flags = ifp->if_flags;
769                 break;
770
771         case SIOCADDMULTI:
772         case SIOCDELMULTI:
773                 if (ifp->if_flags & IFF_RUNNING) {
774                         igb_disable_intr(sc);
775                         igb_set_multi(sc);
776 #ifdef DEVICE_POLLING
777                         if (!(ifp->if_flags & IFF_POLLING))
778 #endif
779                                 igb_enable_intr(sc);
780                 }
781                 break;
782
783         case SIOCSIFMEDIA:
784                 /*
785                  * As the speed/duplex settings are being
786                  * changed, we need toreset the PHY.
787                  */
788                 sc->hw.phy.reset_disable = FALSE;
789
790                 /* Check SOL/IDER usage */
791                 if (e1000_check_reset_block(&sc->hw)) {
792                         if_printf(ifp, "Media change is "
793                             "blocked due to SOL/IDER session.\n");
794                         break;
795                 }
796                 /* FALL THROUGH */
797
798         case SIOCGIFMEDIA:
799                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
800                 break;
801
802         case SIOCSIFCAP:
803                 reinit = 0;
804                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
805                 if (mask & IFCAP_HWCSUM) {
806                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
807                         reinit = 1;
808                 }
809                 if (mask & IFCAP_VLAN_HWTAGGING) {
810                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
811                         reinit = 1;
812                 }
813                 if (mask & IFCAP_RSS)
814                         ifp->if_capenable ^= IFCAP_RSS;
815                 if (reinit && (ifp->if_flags & IFF_RUNNING))
816                         igb_init(sc);
817                 break;
818
819         default:
820                 error = ether_ioctl(ifp, command, data);
821                 break;
822         }
823         return error;
824 }
825
826 static void
827 igb_init(void *xsc)
828 {
829         struct igb_softc *sc = xsc;
830         struct ifnet *ifp = &sc->arpcom.ac_if;
831         int i;
832
833         ASSERT_IFNET_SERIALIZED_ALL(ifp);
834
835         igb_stop(sc);
836
837         /* Get the latest mac address, User can use a LAA */
838         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
839
840         /* Put the address into the Receive Address Array */
841         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
842
843         igb_reset(sc);
844         igb_update_link_status(sc);
845
846         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
847
848         /* Set hardware offload abilities */
849         if (ifp->if_capenable & IFCAP_TXCSUM)
850                 ifp->if_hwassist = IGB_CSUM_FEATURES;
851         else
852                 ifp->if_hwassist = 0;
853
854         /* Configure for OS presence */
855         igb_get_mgmt(sc);
856
857         /* Prepare transmit descriptors and buffers */
858         for (i = 0; i < sc->tx_ring_cnt; ++i)
859                 igb_init_tx_ring(&sc->tx_rings[i]);
860         igb_init_tx_unit(sc);
861
862         /* Setup Multicast table */
863         igb_set_multi(sc);
864
865 #if 0
866         /*
867          * Figure out the desired mbuf pool
868          * for doing jumbo/packetsplit
869          */
870         if (adapter->max_frame_size <= 2048)
871                 adapter->rx_mbuf_sz = MCLBYTES;
872         else if (adapter->max_frame_size <= 4096)
873                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
874         else
875                 adapter->rx_mbuf_sz = MJUM9BYTES;
876 #endif
877
878         /* Initialize interrupt */
879         igb_init_intr(sc);
880
881         /* Prepare receive descriptors and buffers */
882         for (i = 0; i < sc->rx_ring_cnt; ++i) {
883                 int error;
884
885                 error = igb_init_rx_ring(&sc->rx_rings[i]);
886                 if (error) {
887                         if_printf(ifp, "Could not setup receive structures\n");
888                         igb_stop(sc);
889                         return;
890                 }
891         }
892         igb_init_rx_unit(sc);
893
894         /* Enable VLAN support */
895         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
896                 igb_set_vlan(sc);
897
898         /* Don't lose promiscuous settings */
899         igb_set_promisc(sc);
900
901         ifp->if_flags |= IFF_RUNNING;
902         ifp->if_flags &= ~IFF_OACTIVE;
903
904         callout_reset(&sc->timer, hz, igb_timer, sc);
905         e1000_clear_hw_cntrs_base_generic(&sc->hw);
906
907 #if 0
908         if (adapter->msix > 1) /* Set up queue routing */
909                 igb_configure_queues(adapter);
910 #endif
911
912         /* this clears any pending interrupts */
913         E1000_READ_REG(&sc->hw, E1000_ICR);
914 #ifdef DEVICE_POLLING
915         /*
916          * Only enable interrupts if we are not polling, make sure
917          * they are off otherwise.
918          */
919         if (ifp->if_flags & IFF_POLLING)
920                 igb_disable_intr(sc);
921         else
922 #endif /* DEVICE_POLLING */
923         {
924                 igb_enable_intr(sc);
925                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
926         }
927
928         /* Set Energy Efficient Ethernet */
929         e1000_set_eee_i350(&sc->hw);
930
931         /* Don't reset the phy next time init gets called */
932         sc->hw.phy.reset_disable = TRUE;
933 }
934
935 static void
936 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
937 {
938         struct igb_softc *sc = ifp->if_softc;
939         u_char fiber_type = IFM_1000_SX;
940
941         ASSERT_IFNET_SERIALIZED_ALL(ifp);
942
943         igb_update_link_status(sc);
944
945         ifmr->ifm_status = IFM_AVALID;
946         ifmr->ifm_active = IFM_ETHER;
947
948         if (!sc->link_active)
949                 return;
950
951         ifmr->ifm_status |= IFM_ACTIVE;
952
953         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
954             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
955                 ifmr->ifm_active |= fiber_type | IFM_FDX;
956         } else {
957                 switch (sc->link_speed) {
958                 case 10:
959                         ifmr->ifm_active |= IFM_10_T;
960                         break;
961
962                 case 100:
963                         ifmr->ifm_active |= IFM_100_TX;
964                         break;
965
966                 case 1000:
967                         ifmr->ifm_active |= IFM_1000_T;
968                         break;
969                 }
970                 if (sc->link_duplex == FULL_DUPLEX)
971                         ifmr->ifm_active |= IFM_FDX;
972                 else
973                         ifmr->ifm_active |= IFM_HDX;
974         }
975 }
976
977 static int
978 igb_media_change(struct ifnet *ifp)
979 {
980         struct igb_softc *sc = ifp->if_softc;
981         struct ifmedia *ifm = &sc->media;
982
983         ASSERT_IFNET_SERIALIZED_ALL(ifp);
984
985         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
986                 return EINVAL;
987
988         switch (IFM_SUBTYPE(ifm->ifm_media)) {
989         case IFM_AUTO:
990                 sc->hw.mac.autoneg = DO_AUTO_NEG;
991                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
992                 break;
993
994         case IFM_1000_LX:
995         case IFM_1000_SX:
996         case IFM_1000_T:
997                 sc->hw.mac.autoneg = DO_AUTO_NEG;
998                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
999                 break;
1000
1001         case IFM_100_TX:
1002                 sc->hw.mac.autoneg = FALSE;
1003                 sc->hw.phy.autoneg_advertised = 0;
1004                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1005                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1006                 else
1007                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1008                 break;
1009
1010         case IFM_10_T:
1011                 sc->hw.mac.autoneg = FALSE;
1012                 sc->hw.phy.autoneg_advertised = 0;
1013                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1014                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1015                 else
1016                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1017                 break;
1018
1019         default:
1020                 if_printf(ifp, "Unsupported media type\n");
1021                 break;
1022         }
1023
1024         igb_init(sc);
1025
1026         return 0;
1027 }
1028
1029 static void
1030 igb_set_promisc(struct igb_softc *sc)
1031 {
1032         struct ifnet *ifp = &sc->arpcom.ac_if;
1033         struct e1000_hw *hw = &sc->hw;
1034         uint32_t reg;
1035
1036         if (sc->vf_ifp) {
1037                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1038                 return;
1039         }
1040
1041         reg = E1000_READ_REG(hw, E1000_RCTL);
1042         if (ifp->if_flags & IFF_PROMISC) {
1043                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1044                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1045         } else if (ifp->if_flags & IFF_ALLMULTI) {
1046                 reg |= E1000_RCTL_MPE;
1047                 reg &= ~E1000_RCTL_UPE;
1048                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1049         }
1050 }
1051
1052 static void
1053 igb_disable_promisc(struct igb_softc *sc)
1054 {
1055         struct e1000_hw *hw = &sc->hw;
1056         uint32_t reg;
1057
1058         if (sc->vf_ifp) {
1059                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1060                 return;
1061         }
1062         reg = E1000_READ_REG(hw, E1000_RCTL);
1063         reg &= ~E1000_RCTL_UPE;
1064         reg &= ~E1000_RCTL_MPE;
1065         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1066 }
1067
1068 static void
1069 igb_set_multi(struct igb_softc *sc)
1070 {
1071         struct ifnet *ifp = &sc->arpcom.ac_if;
1072         struct ifmultiaddr *ifma;
1073         uint32_t reg_rctl = 0;
1074         uint8_t *mta;
1075         int mcnt = 0;
1076
1077         mta = sc->mta;
1078         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1079
1080         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1081                 if (ifma->ifma_addr->sa_family != AF_LINK)
1082                         continue;
1083
1084                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1085                         break;
1086
1087                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1088                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1089                 mcnt++;
1090         }
1091
1092         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1093                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1094                 reg_rctl |= E1000_RCTL_MPE;
1095                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1096         } else {
1097                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1098         }
1099 }
1100
1101 static void
1102 igb_timer(void *xsc)
1103 {
1104         struct igb_softc *sc = xsc;
1105
1106         lwkt_serialize_enter(&sc->main_serialize);
1107
1108         igb_update_link_status(sc);
1109         igb_update_stats_counters(sc);
1110
1111         callout_reset(&sc->timer, hz, igb_timer, sc);
1112
1113         lwkt_serialize_exit(&sc->main_serialize);
1114 }
1115
1116 static void
1117 igb_update_link_status(struct igb_softc *sc)
1118 {
1119         struct ifnet *ifp = &sc->arpcom.ac_if;
1120         struct e1000_hw *hw = &sc->hw;
1121         uint32_t link_check, thstat, ctrl;
1122
1123         link_check = thstat = ctrl = 0;
1124
1125         /* Get the cached link value or read for real */
1126         switch (hw->phy.media_type) {
1127         case e1000_media_type_copper:
1128                 if (hw->mac.get_link_status) {
1129                         /* Do the work to read phy */
1130                         e1000_check_for_link(hw);
1131                         link_check = !hw->mac.get_link_status;
1132                 } else {
1133                         link_check = TRUE;
1134                 }
1135                 break;
1136
1137         case e1000_media_type_fiber:
1138                 e1000_check_for_link(hw);
1139                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1140                 break;
1141
1142         case e1000_media_type_internal_serdes:
1143                 e1000_check_for_link(hw);
1144                 link_check = hw->mac.serdes_has_link;
1145                 break;
1146
1147         /* VF device is type_unknown */
1148         case e1000_media_type_unknown:
1149                 e1000_check_for_link(hw);
1150                 link_check = !hw->mac.get_link_status;
1151                 /* Fall thru */
1152         default:
1153                 break;
1154         }
1155
1156         /* Check for thermal downshift or shutdown */
1157         if (hw->mac.type == e1000_i350) {
1158                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1159                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1160         }
1161
1162         /* Now we check if a transition has happened */
1163         if (link_check && sc->link_active == 0) {
1164                 e1000_get_speed_and_duplex(hw, 
1165                     &sc->link_speed, &sc->link_duplex);
1166                 if (bootverbose) {
1167                         if_printf(ifp, "Link is up %d Mbps %s\n",
1168                             sc->link_speed,
1169                             sc->link_duplex == FULL_DUPLEX ?
1170                             "Full Duplex" : "Half Duplex");
1171                 }
1172                 sc->link_active = 1;
1173
1174                 ifp->if_baudrate = sc->link_speed * 1000000;
1175                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1176                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1177                         if_printf(ifp, "Link: thermal downshift\n");
1178                 /* This can sleep */
1179                 ifp->if_link_state = LINK_STATE_UP;
1180                 if_link_state_change(ifp);
1181         } else if (!link_check && sc->link_active == 1) {
1182                 ifp->if_baudrate = sc->link_speed = 0;
1183                 sc->link_duplex = 0;
1184                 if (bootverbose)
1185                         if_printf(ifp, "Link is Down\n");
1186                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1187                     (thstat & E1000_THSTAT_PWR_DOWN))
1188                         if_printf(ifp, "Link: thermal shutdown\n");
1189                 sc->link_active = 0;
1190                 /* This can sleep */
1191                 ifp->if_link_state = LINK_STATE_DOWN;
1192                 if_link_state_change(ifp);
1193         }
1194 }
1195
1196 static void
1197 igb_stop(struct igb_softc *sc)
1198 {
1199         struct ifnet *ifp = &sc->arpcom.ac_if;
1200         int i;
1201
1202         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1203
1204         igb_disable_intr(sc);
1205
1206         callout_stop(&sc->timer);
1207
1208         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1209         ifp->if_timer = 0;
1210
1211         e1000_reset_hw(&sc->hw);
1212         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1213
1214         e1000_led_off(&sc->hw);
1215         e1000_cleanup_led(&sc->hw);
1216
1217         for (i = 0; i < sc->tx_ring_cnt; ++i)
1218                 igb_free_tx_ring(&sc->tx_rings[i]);
1219         for (i = 0; i < sc->rx_ring_cnt; ++i)
1220                 igb_free_rx_ring(&sc->rx_rings[i]);
1221 }
1222
1223 static void
1224 igb_reset(struct igb_softc *sc)
1225 {
1226         struct ifnet *ifp = &sc->arpcom.ac_if;
1227         struct e1000_hw *hw = &sc->hw;
1228         struct e1000_fc_info *fc = &hw->fc;
1229         uint32_t pba = 0;
1230         uint16_t hwm;
1231
1232         /* Let the firmware know the OS is in control */
1233         igb_get_hw_control(sc);
1234
1235         /*
1236          * Packet Buffer Allocation (PBA)
1237          * Writing PBA sets the receive portion of the buffer
1238          * the remainder is used for the transmit buffer.
1239          */
1240         switch (hw->mac.type) {
1241         case e1000_82575:
1242                 pba = E1000_PBA_32K;
1243                 break;
1244
1245         case e1000_82576:
1246         case e1000_vfadapt:
1247                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1248                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1249                 break;
1250
1251         case e1000_82580:
1252         case e1000_i350:
1253         case e1000_vfadapt_i350:
1254                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1255                 pba = e1000_rxpbs_adjust_82580(pba);
1256                 break;
1257                 /* XXX pba = E1000_PBA_35K; */
1258
1259         default:
1260                 break;
1261         }
1262
1263         /* Special needs in case of Jumbo frames */
1264         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1265                 uint32_t tx_space, min_tx, min_rx;
1266
1267                 pba = E1000_READ_REG(hw, E1000_PBA);
1268                 tx_space = pba >> 16;
1269                 pba &= 0xffff;
1270
1271                 min_tx = (sc->max_frame_size +
1272                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1273                 min_tx = roundup2(min_tx, 1024);
1274                 min_tx >>= 10;
1275                 min_rx = sc->max_frame_size;
1276                 min_rx = roundup2(min_rx, 1024);
1277                 min_rx >>= 10;
1278                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1279                         pba = pba - (min_tx - tx_space);
1280                         /*
1281                          * if short on rx space, rx wins
1282                          * and must trump tx adjustment
1283                          */
1284                         if (pba < min_rx)
1285                                 pba = min_rx;
1286                 }
1287                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1288         }
1289
1290         /*
1291          * These parameters control the automatic generation (Tx) and
1292          * response (Rx) to Ethernet PAUSE frames.
1293          * - High water mark should allow for at least two frames to be
1294          *   received after sending an XOFF.
1295          * - Low water mark works best when it is very near the high water mark.
1296          *   This allows the receiver to restart by sending XON when it has
1297          *   drained a bit.
1298          */
1299         hwm = min(((pba << 10) * 9 / 10),
1300             ((pba << 10) - 2 * sc->max_frame_size));
1301
1302         if (hw->mac.type < e1000_82576) {
1303                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1304                 fc->low_water = fc->high_water - 8;
1305         } else {
1306                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1307                 fc->low_water = fc->high_water - 16;
1308         }
1309         fc->pause_time = IGB_FC_PAUSE_TIME;
1310         fc->send_xon = TRUE;
1311
1312         /* Issue a global reset */
1313         e1000_reset_hw(hw);
1314         E1000_WRITE_REG(hw, E1000_WUC, 0);
1315
1316         if (e1000_init_hw(hw) < 0)
1317                 if_printf(ifp, "Hardware Initialization Failed\n");
1318
1319         /* Setup DMA Coalescing */
1320         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1321                 uint32_t reg;
1322
1323                 hwm = (pba - 4) << 10;
1324                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1325                     & E1000_DMACR_DMACTHR_MASK;
1326
1327                 /* transition to L0x or L1 if available..*/
1328                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1329
1330                 /* timer = +-1000 usec in 32usec intervals */
1331                 reg |= (1000 >> 5);
1332                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1333
1334                 /* No lower threshold */
1335                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1336
1337                 /* set hwm to PBA -  2 * max frame size */
1338                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1339
1340                 /* Set the interval before transition */
1341                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1342                 reg |= 0x800000FF; /* 255 usec */
1343                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1344
1345                 /* free space in tx packet buffer to wake from DMA coal */
1346                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1347                     (20480 - (2 * sc->max_frame_size)) >> 6);
1348
1349                 /* make low power state decision controlled by DMA coal */
1350                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1351                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1352                     reg | E1000_PCIEMISC_LX_DECISION);
1353                 if_printf(ifp, "DMA Coalescing enabled\n");
1354         }
1355
1356         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1357         e1000_get_phy_info(hw);
1358         e1000_check_for_link(hw);
1359 }
1360
1361 static void
1362 igb_setup_ifp(struct igb_softc *sc)
1363 {
1364         struct ifnet *ifp = &sc->arpcom.ac_if;
1365
1366         if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1367         ifp->if_softc = sc;
1368         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1369         ifp->if_init =  igb_init;
1370         ifp->if_ioctl = igb_ioctl;
1371         ifp->if_start = igb_start;
1372         ifp->if_serialize = igb_serialize;
1373         ifp->if_deserialize = igb_deserialize;
1374         ifp->if_tryserialize = igb_tryserialize;
1375 #ifdef INVARIANTS
1376         ifp->if_serialize_assert = igb_serialize_assert;
1377 #endif
1378 #ifdef DEVICE_POLLING
1379         ifp->if_poll = igb_poll;
1380 #endif
1381         ifp->if_watchdog = igb_watchdog;
1382
1383         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1384         ifq_set_ready(&ifp->if_snd);
1385
1386         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1387
1388         ifp->if_capabilities =
1389             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1390         if (IGB_ENABLE_HWRSS(sc))
1391                 ifp->if_capabilities |= IFCAP_RSS;
1392         ifp->if_capenable = ifp->if_capabilities;
1393         ifp->if_hwassist = IGB_CSUM_FEATURES;
1394
1395         /*
1396          * Tell the upper layer(s) we support long frames
1397          */
1398         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1399
1400         /*
1401          * Specify the media types supported by this adapter and register
1402          * callbacks to update media and link information
1403          */
1404         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1405         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1406             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1407                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1408                     0, NULL);
1409                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1410         } else {
1411                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1412                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1413                     0, NULL);
1414                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1415                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1416                     0, NULL);
1417                 if (sc->hw.phy.type != e1000_phy_ife) {
1418                         ifmedia_add(&sc->media,
1419                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1420                         ifmedia_add(&sc->media,
1421                             IFM_ETHER | IFM_1000_T, 0, NULL);
1422                 }
1423         }
1424         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1425         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1426 }
1427
1428 static void
1429 igb_add_sysctl(struct igb_softc *sc)
1430 {
1431 #ifdef IGB_RSS_DEBUG
1432         char rx_pkt[32];
1433         int i;
1434 #endif
1435
1436         sysctl_ctx_init(&sc->sysctl_ctx);
1437         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1438             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1439             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1440         if (sc->sysctl_tree == NULL) {
1441                 device_printf(sc->dev, "can't add sysctl node\n");
1442                 return;
1443         }
1444
1445         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1446             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1447         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1448             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1449             "# of RX descs");
1450         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1451             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1452             "# of TX descs");
1453
1454         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1455             OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1456             sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1457
1458         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1459             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1460             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1461             "# of segments per TX interrupt");
1462
1463 #ifdef IGB_RSS_DEBUG
1464         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1465             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1466             "RSS debug level");
1467         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1468                 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
1469                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1470                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, rx_pkt,
1471                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1472         }
1473 #endif
1474 }
1475
1476 static int
1477 igb_alloc_rings(struct igb_softc *sc)
1478 {
1479         int error, i;
1480
1481         /*
1482          * Create top level busdma tag
1483          */
1484         error = bus_dma_tag_create(NULL, 1, 0,
1485             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1486             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1487             &sc->parent_tag);
1488         if (error) {
1489                 device_printf(sc->dev, "could not create top level DMA tag\n");
1490                 return error;
1491         }
1492
1493         /*
1494          * Allocate TX descriptor rings and buffers
1495          */
1496         sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1497             M_DEVBUF, M_WAITOK | M_ZERO);
1498         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1499                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1500
1501                 /* Set up some basics */
1502                 txr->sc = sc;
1503                 txr->me = i;
1504                 lwkt_serialize_init(&txr->tx_serialize);
1505
1506                 error = igb_create_tx_ring(txr);
1507                 if (error)
1508                         return error;
1509         }
1510
1511         /*
1512          * Allocate RX descriptor rings and buffers
1513          */ 
1514         sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1515             M_DEVBUF, M_WAITOK | M_ZERO);
1516         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1517                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1518
1519                 /* Set up some basics */
1520                 rxr->sc = sc;
1521                 rxr->me = i;
1522                 lwkt_serialize_init(&rxr->rx_serialize);
1523
1524                 error = igb_create_rx_ring(rxr);
1525                 if (error)
1526                         return error;
1527         }
1528
1529         return 0;
1530 }
1531
1532 static void
1533 igb_free_rings(struct igb_softc *sc)
1534 {
1535         int i;
1536
1537         if (sc->tx_rings != NULL) {
1538                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1539                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1540
1541                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1542                 }
1543                 kfree(sc->tx_rings, M_DEVBUF);
1544         }
1545
1546         if (sc->rx_rings != NULL) {
1547                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1548                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1549
1550                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1551                 }
1552                 kfree(sc->rx_rings, M_DEVBUF);
1553         }
1554 }
1555
1556 static int
1557 igb_create_tx_ring(struct igb_tx_ring *txr)
1558 {
1559         int tsize, error, i;
1560
1561         /*
1562          * Validate number of transmit descriptors. It must not exceed
1563          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1564          */
1565         if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1566             (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1567                 device_printf(txr->sc->dev,
1568                     "Using %d TX descriptors instead of %d!\n",
1569                     IGB_DEFAULT_TXD, igb_txd);
1570                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1571         } else {
1572                 txr->num_tx_desc = igb_txd;
1573         }
1574
1575         /*
1576          * Allocate TX descriptor ring
1577          */
1578         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1579             IGB_DBA_ALIGN);
1580         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1581             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1582             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1583         if (txr->txdma.dma_vaddr == NULL) {
1584                 device_printf(txr->sc->dev,
1585                     "Unable to allocate TX Descriptor memory\n");
1586                 return ENOMEM;
1587         }
1588         txr->tx_base = txr->txdma.dma_vaddr;
1589         bzero(txr->tx_base, tsize);
1590
1591         txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1592             M_DEVBUF, M_WAITOK | M_ZERO);
1593
1594         /*
1595          * Allocate TX head write-back buffer
1596          */
1597         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1598             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1599             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1600         if (txr->tx_hdr == NULL) {
1601                 device_printf(txr->sc->dev,
1602                     "Unable to allocate TX head write-back buffer\n");
1603                 return ENOMEM;
1604         }
1605
1606         /*
1607          * Create DMA tag for TX buffers
1608          */
1609         error = bus_dma_tag_create(txr->sc->parent_tag,
1610             1, 0,               /* alignment, bounds */
1611             BUS_SPACE_MAXADDR,  /* lowaddr */
1612             BUS_SPACE_MAXADDR,  /* highaddr */
1613             NULL, NULL,         /* filter, filterarg */
1614             IGB_TSO_SIZE,       /* maxsize */
1615             IGB_MAX_SCATTER,    /* nsegments */
1616             PAGE_SIZE,          /* maxsegsize */
1617             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1618             BUS_DMA_ONEBPAGE,   /* flags */
1619             &txr->tx_tag);
1620         if (error) {
1621                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1622                 kfree(txr->tx_buf, M_DEVBUF);
1623                 txr->tx_buf = NULL;
1624                 return error;
1625         }
1626
1627         /*
1628          * Create DMA maps for TX buffers
1629          */
1630         for (i = 0; i < txr->num_tx_desc; ++i) {
1631                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1632
1633                 error = bus_dmamap_create(txr->tx_tag,
1634                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1635                 if (error) {
1636                         device_printf(txr->sc->dev,
1637                             "Unable to create TX DMA map\n");
1638                         igb_destroy_tx_ring(txr, i);
1639                         return error;
1640                 }
1641         }
1642
1643         /*
1644          * Initialize various watermark
1645          */
1646         txr->spare_desc = IGB_TX_SPARE;
1647         txr->intr_nsegs = txr->num_tx_desc / 16;
1648         txr->oact_hi_desc = txr->num_tx_desc / 2;
1649         txr->oact_lo_desc = txr->num_tx_desc / 8;
1650         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1651                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1652         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1653                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1654
1655         return 0;
1656 }
1657
1658 static void
1659 igb_free_tx_ring(struct igb_tx_ring *txr)
1660 {
1661         int i;
1662
1663         for (i = 0; i < txr->num_tx_desc; ++i) {
1664                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1665
1666                 if (txbuf->m_head != NULL) {
1667                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1668                         m_freem(txbuf->m_head);
1669                         txbuf->m_head = NULL;
1670                 }
1671         }
1672 }
1673
1674 static void
1675 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1676 {
1677         int i;
1678
1679         if (txr->txdma.dma_vaddr != NULL) {
1680                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1681                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1682                     txr->txdma.dma_map);
1683                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1684                 txr->txdma.dma_vaddr = NULL;
1685         }
1686
1687         if (txr->tx_hdr != NULL) {
1688                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1689                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1690                     txr->tx_hdr_dmap);
1691                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1692                 txr->tx_hdr = NULL;
1693         }
1694
1695         if (txr->tx_buf == NULL)
1696                 return;
1697
1698         for (i = 0; i < ndesc; ++i) {
1699                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1700
1701                 KKASSERT(txbuf->m_head == NULL);
1702                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1703         }
1704         bus_dma_tag_destroy(txr->tx_tag);
1705
1706         kfree(txr->tx_buf, M_DEVBUF);
1707         txr->tx_buf = NULL;
1708 }
1709
1710 static void
1711 igb_init_tx_ring(struct igb_tx_ring *txr)
1712 {
1713         /* Clear the old descriptor contents */
1714         bzero(txr->tx_base,
1715             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1716
1717         /* Clear TX head write-back buffer */
1718         *(txr->tx_hdr) = 0;
1719
1720         /* Reset indices */
1721         txr->next_avail_desc = 0;
1722         txr->next_to_clean = 0;
1723         txr->tx_nsegs = 0;
1724
1725         /* Set number of descriptors available */
1726         txr->tx_avail = txr->num_tx_desc;
1727 }
1728
1729 static void
1730 igb_init_tx_unit(struct igb_softc *sc)
1731 {
1732         struct e1000_hw *hw = &sc->hw;
1733         uint32_t tctl;
1734         int i;
1735
1736         /* Setup the Tx Descriptor Rings */
1737         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1738                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1739                 uint64_t bus_addr = txr->txdma.dma_paddr;
1740                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1741                 uint32_t txdctl = 0;
1742                 uint32_t dca_txctrl;
1743
1744                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1745                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1746                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1747                     (uint32_t)(bus_addr >> 32));
1748                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1749                     (uint32_t)bus_addr);
1750
1751                 /* Setup the HW Tx Head and Tail descriptor pointers */
1752                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1753                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1754
1755                 txdctl |= IGB_TX_PTHRESH;
1756                 txdctl |= IGB_TX_HTHRESH << 8;
1757                 txdctl |= IGB_TX_WTHRESH << 16;
1758                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1759                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1760
1761                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1762                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1763                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1764
1765                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1766                     (uint32_t)(hdr_paddr >> 32));
1767                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1768                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1769         }
1770
1771         if (sc->vf_ifp)
1772                 return;
1773
1774         e1000_config_collision_dist(hw);
1775
1776         /* Program the Transmit Control Register */
1777         tctl = E1000_READ_REG(hw, E1000_TCTL);
1778         tctl &= ~E1000_TCTL_CT;
1779         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1780             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1781
1782         /* This write will effectively turn on the transmit unit. */
1783         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1784 }
1785
1786 static boolean_t
1787 igb_txctx(struct igb_tx_ring *txr, struct mbuf *mp)
1788 {
1789         struct e1000_adv_tx_context_desc *TXD;
1790         struct igb_tx_buf *txbuf;
1791         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1792         struct ether_vlan_header *eh;
1793         struct ip *ip = NULL;
1794         int ehdrlen, ctxd, ip_hlen = 0;
1795         uint16_t etype, vlantag = 0;
1796         boolean_t offload = TRUE;
1797
1798         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1799                 offload = FALSE;
1800
1801         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1802         ctxd = txr->next_avail_desc;
1803         txbuf = &txr->tx_buf[ctxd];
1804         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1805
1806         /*
1807          * In advanced descriptors the vlan tag must 
1808          * be placed into the context descriptor, thus
1809          * we need to be here just for that setup.
1810          */
1811         if (mp->m_flags & M_VLANTAG) {
1812                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1813                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1814         } else if (!offload) {
1815                 return FALSE;
1816         }
1817
1818         /*
1819          * Determine where frame payload starts.
1820          * Jump over vlan headers if already present,
1821          * helpful for QinQ too.
1822          */
1823         KASSERT(mp->m_len >= ETHER_HDR_LEN,
1824             ("igb_txctx_pullup is not called (eh)?\n"));
1825         eh = mtod(mp, struct ether_vlan_header *);
1826         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1827                 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
1828                     ("igb_txctx_pullup is not called (evh)?\n"));
1829                 etype = ntohs(eh->evl_proto);
1830                 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
1831         } else {
1832                 etype = ntohs(eh->evl_encap_proto);
1833                 ehdrlen = ETHER_HDR_LEN;
1834         }
1835
1836         /* Set the ether header length */
1837         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1838
1839         switch (etype) {
1840         case ETHERTYPE_IP:
1841                 KASSERT(mp->m_len >= ehdrlen + IGB_IPVHL_SIZE,
1842                     ("igb_txctx_pullup is not called (eh+ip_vhl)?\n"));
1843
1844                 /* NOTE: We could only safely access ip.ip_vhl part */
1845                 ip = (struct ip *)(mp->m_data + ehdrlen);
1846                 ip_hlen = ip->ip_hl << 2;
1847
1848                 if (mp->m_pkthdr.csum_flags & CSUM_IP)
1849                         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1850                 break;
1851
1852 #ifdef notyet
1853         case ETHERTYPE_IPV6:
1854                 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1855                 ip_hlen = sizeof(struct ip6_hdr);
1856                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
1857                 break;
1858 #endif
1859
1860         default:
1861                 offload = FALSE;
1862                 break;
1863         }
1864
1865         vlan_macip_lens |= ip_hlen;
1866         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1867
1868         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1869                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1870         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1871                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1872
1873         /* 82575 needs the queue index added */
1874         if (txr->sc->hw.mac.type == e1000_82575)
1875                 mss_l4len_idx = txr->me << 4;
1876
1877         /* Now copy bits into descriptor */
1878         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1879         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1880         TXD->seqnum_seed = htole32(0);
1881         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1882
1883         txbuf->m_head = NULL;
1884
1885         /* We've consumed the first desc, adjust counters */
1886         if (++ctxd == txr->num_tx_desc)
1887                 ctxd = 0;
1888         txr->next_avail_desc = ctxd;
1889         --txr->tx_avail;
1890
1891         return offload;
1892 }
1893
1894 static void
1895 igb_txeof(struct igb_tx_ring *txr)
1896 {
1897         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1898         int first, hdr, avail;
1899
1900         if (txr->tx_avail == txr->num_tx_desc)
1901                 return;
1902
1903         first = txr->next_to_clean;
1904         hdr = *(txr->tx_hdr);
1905
1906         if (first == hdr)
1907                 return;
1908
1909         avail = txr->tx_avail;
1910         while (first != hdr) {
1911                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1912
1913                 ++avail;
1914                 if (txbuf->m_head) {
1915                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1916                         m_freem(txbuf->m_head);
1917                         txbuf->m_head = NULL;
1918                         ++ifp->if_opackets;
1919                 }
1920                 if (++first == txr->num_tx_desc)
1921                         first = 0;
1922         }
1923         txr->next_to_clean = first;
1924         txr->tx_avail = avail;
1925
1926         /*
1927          * If we have a minimum free, clear IFF_OACTIVE
1928          * to tell the stack that it is OK to send packets.
1929          */
1930         if (IGB_IS_NOT_OACTIVE(txr)) {
1931                 ifp->if_flags &= ~IFF_OACTIVE;
1932
1933                 /*
1934                  * We have enough TX descriptors, turn off
1935                  * the watchdog.  We allow small amount of
1936                  * packets (roughly intr_nsegs) pending on
1937                  * the transmit ring.
1938                  */
1939                 ifp->if_timer = 0;
1940         }
1941 }
1942
1943 static int
1944 igb_create_rx_ring(struct igb_rx_ring *rxr)
1945 {
1946         int rsize, i, error;
1947
1948         /*
1949          * Validate number of receive descriptors. It must not exceed
1950          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1951          */
1952         if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1953             (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1954                 device_printf(rxr->sc->dev,
1955                     "Using %d RX descriptors instead of %d!\n",
1956                     IGB_DEFAULT_RXD, igb_rxd);
1957                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1958         } else {
1959                 rxr->num_rx_desc = igb_rxd;
1960         }
1961
1962         /*
1963          * Allocate RX descriptor ring
1964          */
1965         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1966             IGB_DBA_ALIGN);
1967         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1968             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1969             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1970             &rxr->rxdma.dma_paddr);
1971         if (rxr->rxdma.dma_vaddr == NULL) {
1972                 device_printf(rxr->sc->dev,
1973                     "Unable to allocate RxDescriptor memory\n");
1974                 return ENOMEM;
1975         }
1976         rxr->rx_base = rxr->rxdma.dma_vaddr;
1977         bzero(rxr->rx_base, rsize);
1978
1979         rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
1980             M_DEVBUF, M_WAITOK | M_ZERO);
1981
1982         /*
1983          * Create DMA tag for RX buffers
1984          */
1985         error = bus_dma_tag_create(rxr->sc->parent_tag,
1986             1, 0,               /* alignment, bounds */
1987             BUS_SPACE_MAXADDR,  /* lowaddr */
1988             BUS_SPACE_MAXADDR,  /* highaddr */
1989             NULL, NULL,         /* filter, filterarg */
1990             MCLBYTES,           /* maxsize */
1991             1,                  /* nsegments */
1992             MCLBYTES,           /* maxsegsize */
1993             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
1994             &rxr->rx_tag);
1995         if (error) {
1996                 device_printf(rxr->sc->dev,
1997                     "Unable to create RX payload DMA tag\n");
1998                 kfree(rxr->rx_buf, M_DEVBUF);
1999                 rxr->rx_buf = NULL;
2000                 return error;
2001         }
2002
2003         /*
2004          * Create spare DMA map for RX buffers
2005          */
2006         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2007             &rxr->rx_sparemap);
2008         if (error) {
2009                 device_printf(rxr->sc->dev,
2010                     "Unable to create spare RX DMA maps\n");
2011                 bus_dma_tag_destroy(rxr->rx_tag);
2012                 kfree(rxr->rx_buf, M_DEVBUF);
2013                 rxr->rx_buf = NULL;
2014                 return error;
2015         }
2016
2017         /*
2018          * Create DMA maps for RX buffers
2019          */
2020         for (i = 0; i < rxr->num_rx_desc; i++) {
2021                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2022
2023                 error = bus_dmamap_create(rxr->rx_tag,
2024                     BUS_DMA_WAITOK, &rxbuf->map);
2025                 if (error) {
2026                         device_printf(rxr->sc->dev,
2027                             "Unable to create RX DMA maps\n");
2028                         igb_destroy_rx_ring(rxr, i);
2029                         return error;
2030                 }
2031         }
2032         return 0;
2033 }
2034
2035 static void
2036 igb_free_rx_ring(struct igb_rx_ring *rxr)
2037 {
2038         int i;
2039
2040         for (i = 0; i < rxr->num_rx_desc; ++i) {
2041                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2042
2043                 if (rxbuf->m_head != NULL) {
2044                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2045                         m_freem(rxbuf->m_head);
2046                         rxbuf->m_head = NULL;
2047                 }
2048         }
2049
2050         if (rxr->fmp != NULL)
2051                 m_freem(rxr->fmp);
2052         rxr->fmp = NULL;
2053         rxr->lmp = NULL;
2054 }
2055
2056 static void
2057 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2058 {
2059         int i;
2060
2061         if (rxr->rxdma.dma_vaddr != NULL) {
2062                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2063                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2064                     rxr->rxdma.dma_map);
2065                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2066                 rxr->rxdma.dma_vaddr = NULL;
2067         }
2068
2069         if (rxr->rx_buf == NULL)
2070                 return;
2071
2072         for (i = 0; i < ndesc; ++i) {
2073                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2074
2075                 KKASSERT(rxbuf->m_head == NULL);
2076                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2077         }
2078         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2079         bus_dma_tag_destroy(rxr->rx_tag);
2080
2081         kfree(rxr->rx_buf, M_DEVBUF);
2082         rxr->rx_buf = NULL;
2083 }
2084
2085 static void
2086 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2087 {
2088         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2089         rxd->wb.upper.status_error = 0;
2090 }
2091
2092 static int
2093 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2094 {
2095         struct mbuf *m;
2096         bus_dma_segment_t seg;
2097         bus_dmamap_t map;
2098         struct igb_rx_buf *rxbuf;
2099         int error, nseg;
2100
2101         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2102         if (m == NULL) {
2103                 if (wait) {
2104                         if_printf(&rxr->sc->arpcom.ac_if,
2105                             "Unable to allocate RX mbuf\n");
2106                 }
2107                 return ENOBUFS;
2108         }
2109         m->m_len = m->m_pkthdr.len = MCLBYTES;
2110
2111         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2112                 m_adj(m, ETHER_ALIGN);
2113
2114         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2115             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2116         if (error) {
2117                 m_freem(m);
2118                 if (wait) {
2119                         if_printf(&rxr->sc->arpcom.ac_if,
2120                             "Unable to load RX mbuf\n");
2121                 }
2122                 return error;
2123         }
2124
2125         rxbuf = &rxr->rx_buf[i];
2126         if (rxbuf->m_head != NULL)
2127                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2128
2129         map = rxbuf->map;
2130         rxbuf->map = rxr->rx_sparemap;
2131         rxr->rx_sparemap = map;
2132
2133         rxbuf->m_head = m;
2134         rxbuf->paddr = seg.ds_addr;
2135
2136         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2137         return 0;
2138 }
2139
2140 static int
2141 igb_init_rx_ring(struct igb_rx_ring *rxr)
2142 {
2143         int i;
2144
2145         /* Clear the ring contents */
2146         bzero(rxr->rx_base,
2147             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2148
2149         /* Now replenish the ring mbufs */
2150         for (i = 0; i < rxr->num_rx_desc; ++i) {
2151                 int error;
2152
2153                 error = igb_newbuf(rxr, i, TRUE);
2154                 if (error)
2155                         return error;
2156         }
2157
2158         /* Setup our descriptor indices */
2159         rxr->next_to_check = 0;
2160
2161         rxr->fmp = NULL;
2162         rxr->lmp = NULL;
2163         rxr->discard = FALSE;
2164
2165         return 0;
2166 }
2167
2168 static void
2169 igb_init_rx_unit(struct igb_softc *sc)
2170 {
2171         struct ifnet *ifp = &sc->arpcom.ac_if;
2172         struct e1000_hw *hw = &sc->hw;
2173         uint32_t rctl, rxcsum, srrctl = 0;
2174         int i;
2175
2176         /*
2177          * Make sure receives are disabled while setting
2178          * up the descriptor ring
2179          */
2180         rctl = E1000_READ_REG(hw, E1000_RCTL);
2181         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2182
2183 #if 0
2184         /*
2185         ** Set up for header split
2186         */
2187         if (igb_header_split) {
2188                 /* Use a standard mbuf for the header */
2189                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2190                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2191         } else
2192 #endif
2193                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2194
2195         /*
2196         ** Set up for jumbo frames
2197         */
2198         if (ifp->if_mtu > ETHERMTU) {
2199                 rctl |= E1000_RCTL_LPE;
2200 #if 0
2201                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2202                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2203                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2204                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2205                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2206                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2207                 }
2208                 /* Set maximum packet len */
2209                 psize = adapter->max_frame_size;
2210                 /* are we on a vlan? */
2211                 if (adapter->ifp->if_vlantrunk != NULL)
2212                         psize += VLAN_TAG_SIZE;
2213                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2214 #else
2215                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2216                 rctl |= E1000_RCTL_SZ_2048;
2217 #endif
2218         } else {
2219                 rctl &= ~E1000_RCTL_LPE;
2220                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2221                 rctl |= E1000_RCTL_SZ_2048;
2222         }
2223
2224         /* Setup the Base and Length of the Rx Descriptor Rings */
2225         for (i = 0; i < sc->rx_ring_cnt; ++i) {
2226                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2227                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2228                 uint32_t rxdctl;
2229
2230                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2231                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2232                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2233                     (uint32_t)(bus_addr >> 32));
2234                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2235                     (uint32_t)bus_addr);
2236                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2237                 /* Enable this Queue */
2238                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2239                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2240                 rxdctl &= 0xFFF00000;
2241                 rxdctl |= IGB_RX_PTHRESH;
2242                 rxdctl |= IGB_RX_HTHRESH << 8;
2243                 rxdctl |= IGB_RX_WTHRESH << 16;
2244                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2245         }
2246
2247         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2248         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2249
2250         /*
2251          * Receive Checksum Offload for TCP and UDP
2252          *
2253          * Checksum offloading is also enabled if multiple receive
2254          * queue is to be supported, since we need it to figure out
2255          * fragments.
2256          */
2257         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2258                 /*
2259                  * NOTE:
2260                  * PCSD must be enabled to enable multiple
2261                  * receive queues.
2262                  */
2263                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2264                     E1000_RXCSUM_PCSD;
2265         } else {
2266                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2267                     E1000_RXCSUM_PCSD);
2268         }
2269         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2270
2271         if (IGB_ENABLE_HWRSS(sc)) {
2272                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2273                 uint32_t reta, reta_shift;
2274
2275                 /*
2276                  * NOTE:
2277                  * When we reach here, RSS has already been disabled
2278                  * in igb_stop(), so we could safely configure RSS key
2279                  * and redirect table.
2280                  */
2281
2282                 /*
2283                  * Configure RSS key
2284                  */
2285                 toeplitz_get_key(key, sizeof(key));
2286                 for (i = 0; i < IGB_NRSSRK; ++i) {
2287                         uint32_t rssrk;
2288
2289                         rssrk = IGB_RSSRK_VAL(key, i);
2290                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2291
2292                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2293                 }
2294
2295                 /*
2296                  * Configure RSS redirect table in following fashion:
2297                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2298                  */
2299                 reta_shift = IGB_RETA_SHIFT;
2300                 if (hw->mac.type == e1000_82575)
2301                         reta_shift = IGB_RETA_SHIFT_82575;
2302                 reta = 0;
2303                 for (i = 0; i < IGB_RETA_SIZE; ++i) {
2304                         uint32_t q;
2305
2306                         q = (i % sc->rx_ring_cnt) << reta_shift;
2307                         reta |= q << (8 * i);
2308                 }
2309                 IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2310
2311                 for (i = 0; i < IGB_NRETA; ++i)
2312                         E1000_WRITE_REG(hw, E1000_RETA(i), reta);
2313
2314                 /*
2315                  * Enable multiple receive queues.
2316                  * Enable IPv4 RSS standard hash functions.
2317                  * Disable RSS interrupt on 82575
2318                  */
2319                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2320                                 E1000_MRQC_ENABLE_RSS_4Q |
2321                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2322                                 E1000_MRQC_RSS_FIELD_IPV4);
2323         }
2324
2325         /* Setup the Receive Control Register */
2326         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2327         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2328             E1000_RCTL_RDMTS_HALF |
2329             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2330         /* Strip CRC bytes. */
2331         rctl |= E1000_RCTL_SECRC;
2332         /* Make sure VLAN Filters are off */
2333         rctl &= ~E1000_RCTL_VFE;
2334         /* Don't store bad packets */
2335         rctl &= ~E1000_RCTL_SBP;
2336
2337         /* Enable Receives */
2338         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2339
2340         /*
2341          * Setup the HW Rx Head and Tail Descriptor Pointers
2342          *   - needs to be after enable
2343          */
2344         for (i = 0; i < sc->rx_ring_cnt; ++i) {
2345                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2346
2347                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2348                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2349         }
2350 }
2351
2352 static void
2353 igb_rxeof(struct igb_rx_ring *rxr, int count)
2354 {
2355         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2356         union e1000_adv_rx_desc *cur;
2357         uint32_t staterr;
2358         int i;
2359
2360         i = rxr->next_to_check;
2361         cur = &rxr->rx_base[i];
2362         staterr = le32toh(cur->wb.upper.status_error);
2363
2364         if ((staterr & E1000_RXD_STAT_DD) == 0)
2365                 return;
2366
2367         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2368                 struct pktinfo *pi = NULL, pi0;
2369                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2370                 struct mbuf *m = NULL;
2371                 boolean_t eop;
2372
2373                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2374                 if (eop)
2375                         --count;
2376
2377                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2378                     !rxr->discard) {
2379                         struct mbuf *mp = rxbuf->m_head;
2380                         uint32_t hash, hashtype;
2381                         uint16_t vlan;
2382                         int len;
2383
2384                         len = le16toh(cur->wb.upper.length);
2385                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2386                             (staterr & E1000_RXDEXT_STATERR_LB))
2387                                 vlan = be16toh(cur->wb.upper.vlan);
2388                         else
2389                                 vlan = le16toh(cur->wb.upper.vlan);
2390
2391                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2392                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2393                             E1000_RXDADV_RSSTYPE_MASK;
2394
2395                         IGB_RSS_DPRINTF(rxr->sc, 10,
2396                             "ring%d, hash 0x%08x, hashtype %u\n",
2397                             rxr->me, hash, hashtype);
2398
2399                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2400                             BUS_DMASYNC_POSTREAD);
2401
2402                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2403                                 ifp->if_iqdrops++;
2404                                 goto discard;
2405                         }
2406
2407                         mp->m_len = len;
2408                         if (rxr->fmp == NULL) {
2409                                 mp->m_pkthdr.len = len;
2410                                 rxr->fmp = mp;
2411                                 rxr->lmp = mp;
2412                         } else {
2413                                 rxr->lmp->m_next = mp;
2414                                 rxr->lmp = rxr->lmp->m_next;
2415                                 rxr->fmp->m_pkthdr.len += len;
2416                         }
2417
2418                         if (eop) {
2419                                 m = rxr->fmp;
2420                                 rxr->fmp = NULL;
2421                                 rxr->lmp = NULL;
2422
2423                                 m->m_pkthdr.rcvif = ifp;
2424                                 ifp->if_ipackets++;
2425
2426                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2427                                         igb_rxcsum(staterr, m);
2428
2429                                 if (staterr & E1000_RXD_STAT_VP) {
2430                                         m->m_pkthdr.ether_vlantag = vlan;
2431                                         m->m_flags |= M_VLANTAG;
2432                                 }
2433
2434                                 if (ifp->if_capenable & IFCAP_RSS) {
2435                                         pi = igb_rssinfo(m, &pi0,
2436                                             hash, hashtype, staterr);
2437                                 }
2438 #ifdef IGB_RSS_DEBUG
2439                                 rxr->rx_packets++;
2440 #endif
2441                         }
2442                 } else {
2443                         ifp->if_ierrors++;
2444 discard:
2445                         igb_setup_rxdesc(cur, rxbuf);
2446                         if (!eop)
2447                                 rxr->discard = TRUE;
2448                         else
2449                                 rxr->discard = FALSE;
2450                         if (rxr->fmp != NULL) {
2451                                 m_freem(rxr->fmp);
2452                                 rxr->fmp = NULL;
2453                                 rxr->lmp = NULL;
2454                         }
2455                         m = NULL;
2456                 }
2457
2458                 if (m != NULL)
2459                         ether_input_pkt(ifp, m, pi);
2460
2461                 /* Advance our pointers to the next descriptor. */
2462                 if (++i == rxr->num_rx_desc)
2463                         i = 0;
2464
2465                 cur = &rxr->rx_base[i];
2466                 staterr = le32toh(cur->wb.upper.status_error);
2467         }
2468         rxr->next_to_check = i;
2469
2470         if (--i < 0)
2471                 i = rxr->num_rx_desc - 1;
2472         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2473 }
2474
2475
2476 static void
2477 igb_set_vlan(struct igb_softc *sc)
2478 {
2479         struct e1000_hw *hw = &sc->hw;
2480         uint32_t reg;
2481 #if 0
2482         struct ifnet *ifp = sc->arpcom.ac_if;
2483 #endif
2484
2485         if (sc->vf_ifp) {
2486                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2487                 return;
2488         }
2489
2490         reg = E1000_READ_REG(hw, E1000_CTRL);
2491         reg |= E1000_CTRL_VME;
2492         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2493
2494 #if 0
2495         /* Enable the Filter Table */
2496         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2497                 reg = E1000_READ_REG(hw, E1000_RCTL);
2498                 reg &= ~E1000_RCTL_CFIEN;
2499                 reg |= E1000_RCTL_VFE;
2500                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2501         }
2502 #endif
2503
2504         /* Update the frame size */
2505         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2506             sc->max_frame_size + VLAN_TAG_SIZE);
2507
2508 #if 0
2509         /* Don't bother with table if no vlans */
2510         if ((adapter->num_vlans == 0) ||
2511             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2512                 return;
2513         /*
2514         ** A soft reset zero's out the VFTA, so
2515         ** we need to repopulate it now.
2516         */
2517         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2518                 if (adapter->shadow_vfta[i] != 0) {
2519                         if (adapter->vf_ifp)
2520                                 e1000_vfta_set_vf(hw,
2521                                     adapter->shadow_vfta[i], TRUE);
2522                         else
2523                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2524                                  i, adapter->shadow_vfta[i]);
2525                 }
2526 #endif
2527 }
2528
2529 static void
2530 igb_enable_intr(struct igb_softc *sc)
2531 {
2532         lwkt_serialize_handler_enable(&sc->main_serialize);
2533
2534         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2535                 /* XXX MSI-X should use sc->intr_mask */
2536                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2537                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2538                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2539                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2540         } else {
2541                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2542         }
2543         E1000_WRITE_FLUSH(&sc->hw);
2544 }
2545
2546 static void
2547 igb_disable_intr(struct igb_softc *sc)
2548 {
2549         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2550                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2551                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2552         }
2553         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2554         E1000_WRITE_FLUSH(&sc->hw);
2555
2556         lwkt_serialize_handler_disable(&sc->main_serialize);
2557 }
2558
2559 /*
2560  * Bit of a misnomer, what this really means is
2561  * to enable OS management of the system... aka
2562  * to disable special hardware management features 
2563  */
2564 static void
2565 igb_get_mgmt(struct igb_softc *sc)
2566 {
2567         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2568                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2569                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2570
2571                 /* disable hardware interception of ARP */
2572                 manc &= ~E1000_MANC_ARP_EN;
2573
2574                 /* enable receiving management packets to the host */
2575                 manc |= E1000_MANC_EN_MNG2HOST;
2576                 manc2h |= 1 << 5; /* Mng Port 623 */
2577                 manc2h |= 1 << 6; /* Mng Port 664 */
2578                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2579                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2580         }
2581 }
2582
2583 /*
2584  * Give control back to hardware management controller
2585  * if there is one.
2586  */
2587 static void
2588 igb_rel_mgmt(struct igb_softc *sc)
2589 {
2590         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2591                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2592
2593                 /* Re-enable hardware interception of ARP */
2594                 manc |= E1000_MANC_ARP_EN;
2595                 manc &= ~E1000_MANC_EN_MNG2HOST;
2596
2597                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2598         }
2599 }
2600
2601 /*
2602  * Sets CTRL_EXT:DRV_LOAD bit.
2603  *
2604  * For ASF and Pass Through versions of f/w this means that
2605  * the driver is loaded. 
2606  */
2607 static void
2608 igb_get_hw_control(struct igb_softc *sc)
2609 {
2610         uint32_t ctrl_ext;
2611
2612         if (sc->vf_ifp)
2613                 return;
2614
2615         /* Let firmware know the driver has taken over */
2616         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2617         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2618             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2619 }
2620
2621 /*
2622  * Resets CTRL_EXT:DRV_LOAD bit.
2623  *
2624  * For ASF and Pass Through versions of f/w this means that the
2625  * driver is no longer loaded.
2626  */
2627 static void
2628 igb_rel_hw_control(struct igb_softc *sc)
2629 {
2630         uint32_t ctrl_ext;
2631
2632         if (sc->vf_ifp)
2633                 return;
2634
2635         /* Let firmware taken over control of h/w */
2636         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2637         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2638             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2639 }
2640
2641 static int
2642 igb_is_valid_ether_addr(const uint8_t *addr)
2643 {
2644         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2645
2646         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2647                 return FALSE;
2648         return TRUE;
2649 }
2650
2651 /*
2652  * Enable PCI Wake On Lan capability
2653  */
2654 static void
2655 igb_enable_wol(device_t dev)
2656 {
2657         uint16_t cap, status;
2658         uint8_t id;
2659
2660         /* First find the capabilities pointer*/
2661         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2662
2663         /* Read the PM Capabilities */
2664         id = pci_read_config(dev, cap, 1);
2665         if (id != PCIY_PMG)     /* Something wrong */
2666                 return;
2667
2668         /*
2669          * OK, we have the power capabilities,
2670          * so now get the status register
2671          */
2672         cap += PCIR_POWER_STATUS;
2673         status = pci_read_config(dev, cap, 2);
2674         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2675         pci_write_config(dev, cap, status, 2);
2676 }
2677
2678 static void
2679 igb_update_stats_counters(struct igb_softc *sc)
2680 {
2681         struct e1000_hw *hw = &sc->hw;
2682         struct e1000_hw_stats *stats;
2683         struct ifnet *ifp = &sc->arpcom.ac_if;
2684
2685         /* 
2686          * The virtual function adapter has only a
2687          * small controlled set of stats, do only 
2688          * those and return.
2689          */
2690         if (sc->vf_ifp) {
2691                 igb_update_vf_stats_counters(sc);
2692                 return;
2693         }
2694         stats = sc->stats;
2695
2696         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2697             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2698                 stats->symerrs +=
2699                     E1000_READ_REG(hw,E1000_SYMERRS);
2700                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2701         }
2702
2703         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2704         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2705         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2706         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2707
2708         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2709         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2710         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2711         stats->dc += E1000_READ_REG(hw, E1000_DC);
2712         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2713         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2714         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2715
2716         /*
2717          * For watchdog management we need to know if we have been
2718          * paused during the last interval, so capture that here.
2719          */ 
2720         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2721         stats->xoffrxc += sc->pause_frames;
2722         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2723         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2724         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2725         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2726         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2727         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2728         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2729         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2730         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2731         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2732         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2733         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2734
2735         /* For the 64-bit byte counters the low dword must be read first. */
2736         /* Both registers clear on the read of the high dword */
2737
2738         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2739             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2740         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2741             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2742
2743         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2744         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2745         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2746         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2747         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2748
2749         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2750         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2751
2752         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2753         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2754         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2755         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2756         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2757         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2758         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2759         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2760         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2761         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2762
2763         /* Interrupt Counts */
2764
2765         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2766         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2767         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2768         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2769         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2770         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2771         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2772         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2773         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2774
2775         /* Host to Card Statistics */
2776
2777         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2778         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2779         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2780         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2781         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2782         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2783         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2784         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2785             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2786         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2787             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2788         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2789         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2790         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2791
2792         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2793         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2794         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2795         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2796         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2797         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2798
2799         ifp->if_collisions = stats->colc;
2800
2801         /* Rx Errors */
2802         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2803             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2804
2805         /* Tx Errors */
2806         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2807
2808         /* Driver specific counters */
2809         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2810         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2811         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2812         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2813         sc->packet_buf_alloc_tx =
2814             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2815         sc->packet_buf_alloc_rx =
2816             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2817 }
2818
2819 static void
2820 igb_vf_init_stats(struct igb_softc *sc)
2821 {
2822         struct e1000_hw *hw = &sc->hw;
2823         struct e1000_vf_stats *stats;
2824
2825         stats = sc->stats;
2826         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2827         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2828         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2829         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2830         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2831 }
2832  
2833 static void
2834 igb_update_vf_stats_counters(struct igb_softc *sc)
2835 {
2836         struct e1000_hw *hw = &sc->hw;
2837         struct e1000_vf_stats *stats;
2838
2839         if (sc->link_speed == 0)
2840                 return;
2841
2842         stats = sc->stats;
2843         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2844         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2845         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2846         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2847         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2848 }
2849
2850 #ifdef DEVICE_POLLING
2851
2852 static void
2853 igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2854 {
2855         struct igb_softc *sc = ifp->if_softc;
2856         uint32_t reg_icr;
2857
2858         ASSERT_SERIALIZED(&sc->main_serialize);
2859
2860         switch (cmd) {
2861         case POLL_REGISTER:
2862                 igb_disable_intr(sc);
2863                 break;
2864
2865         case POLL_DEREGISTER:
2866                 igb_enable_intr(sc);
2867                 break;
2868
2869         case POLL_AND_CHECK_STATUS:
2870                 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2871                 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2872                         sc->hw.mac.get_link_status = 1;
2873                         igb_update_link_status(sc);
2874                 }
2875                 /* FALL THROUGH */
2876         case POLL_ONLY:
2877                 if (ifp->if_flags & IFF_RUNNING) {
2878                         struct igb_tx_ring *txr;
2879                         int i;
2880
2881                         for (i = 0; i < sc->rx_ring_cnt; ++i) {
2882                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2883
2884                                 lwkt_serialize_enter(&rxr->rx_serialize);
2885                                 igb_rxeof(rxr, count);
2886                                 lwkt_serialize_exit(&rxr->rx_serialize);
2887                         }
2888
2889                         txr = &sc->tx_rings[0];
2890                         lwkt_serialize_enter(&txr->tx_serialize);
2891                         igb_txeof(txr);
2892                         if (!ifq_is_empty(&ifp->if_snd))
2893                                 if_devstart(ifp);
2894                         lwkt_serialize_exit(&txr->tx_serialize);
2895                 }
2896                 break;
2897         }
2898 }
2899
2900 #endif /* DEVICE_POLLING */
2901
2902 static void
2903 igb_intr(void *xsc)
2904 {
2905         struct igb_softc *sc = xsc;
2906         struct ifnet *ifp = &sc->arpcom.ac_if;
2907         uint32_t eicr;
2908
2909         ASSERT_SERIALIZED(&sc->main_serialize);
2910
2911         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
2912
2913         if (eicr == 0)
2914                 return;
2915
2916         if (ifp->if_flags & IFF_RUNNING) {
2917                 struct igb_tx_ring *txr;
2918                 int i;
2919
2920                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2921                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
2922
2923                         if (eicr & rxr->rx_intr_mask) {
2924                                 lwkt_serialize_enter(&rxr->rx_serialize);
2925                                 igb_rxeof(rxr, -1);
2926                                 lwkt_serialize_exit(&rxr->rx_serialize);
2927                         }
2928                 }
2929
2930                 txr = &sc->tx_rings[0];
2931                 if (eicr & txr->tx_intr_mask) {
2932                         lwkt_serialize_enter(&txr->tx_serialize);
2933                         igb_txeof(txr);
2934                         if (!ifq_is_empty(&ifp->if_snd))
2935                                 if_devstart(ifp);
2936                         lwkt_serialize_exit(&txr->tx_serialize);
2937                 }
2938         }
2939
2940         if (eicr & E1000_EICR_OTHER) {
2941                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2942
2943                 /* Link status change */
2944                 if (icr & E1000_ICR_LSC) {
2945                         sc->hw.mac.get_link_status = 1;
2946                         igb_update_link_status(sc);
2947                 }
2948         }
2949
2950         /*
2951          * Reading EICR has the side effect to clear interrupt mask,
2952          * so all interrupts need to be enabled here.
2953          */
2954         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2955 }
2956
2957 static void
2958 igb_shared_intr(void *xsc)
2959 {
2960         struct igb_softc *sc = xsc;
2961         struct ifnet *ifp = &sc->arpcom.ac_if;
2962         uint32_t reg_icr;
2963
2964         ASSERT_SERIALIZED(&sc->main_serialize);
2965
2966         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2967
2968         /* Hot eject?  */
2969         if (reg_icr == 0xffffffff)
2970                 return;
2971
2972         /* Definitely not our interrupt.  */
2973         if (reg_icr == 0x0)
2974                 return;
2975
2976         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
2977                 return;
2978
2979         if (ifp->if_flags & IFF_RUNNING) {
2980                 struct igb_tx_ring *txr;
2981                 int i;
2982
2983                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2984                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
2985
2986                         lwkt_serialize_enter(&rxr->rx_serialize);
2987                         igb_rxeof(rxr, -1);
2988                         lwkt_serialize_exit(&rxr->rx_serialize);
2989                 }
2990
2991                 txr = &sc->tx_rings[0];
2992                 lwkt_serialize_enter(&txr->tx_serialize);
2993                 igb_txeof(txr);
2994                 if (!ifq_is_empty(&ifp->if_snd))
2995                         if_devstart(ifp);
2996                 lwkt_serialize_exit(&txr->tx_serialize);
2997         }
2998
2999         /* Link status change */
3000         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3001                 sc->hw.mac.get_link_status = 1;
3002                 igb_update_link_status(sc);
3003         }
3004
3005         if (reg_icr & E1000_ICR_RXO)
3006                 sc->rx_overruns++;
3007 }
3008
3009 static int
3010 igb_txctx_pullup(struct igb_tx_ring *txr, struct mbuf **m0)
3011 {
3012         struct mbuf *m = *m0;
3013         struct ether_header *eh;
3014         int len;
3015
3016         txr->ctx_try_pullup++;
3017
3018         len = ETHER_HDR_LEN + IGB_IPVHL_SIZE;
3019
3020         if (__predict_false(!M_WRITABLE(m))) {
3021                 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3022                         txr->ctx_drop1++;
3023                         m_freem(m);
3024                         *m0 = NULL;
3025                         return ENOBUFS;
3026                 }
3027                 eh = mtod(m, struct ether_header *);
3028
3029                 if (eh->ether_type == htons(ETHERTYPE_VLAN))
3030                         len += EVL_ENCAPLEN;
3031
3032                 if (m->m_len < len) {
3033                         txr->ctx_drop2++;
3034                         m_freem(m);
3035                         *m0 = NULL;
3036                         return ENOBUFS;
3037                 }
3038                 return 0;
3039         }
3040
3041         if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3042                 txr->ctx_pullup1++;
3043                 m = m_pullup(m, ETHER_HDR_LEN);
3044                 if (m == NULL) {
3045                         txr->ctx_pullup1_failed++;
3046                         *m0 = NULL;
3047                         return ENOBUFS;
3048                 }
3049                 *m0 = m;
3050         }
3051         eh = mtod(m, struct ether_header *);
3052
3053         if (eh->ether_type == htons(ETHERTYPE_VLAN))
3054                 len += EVL_ENCAPLEN;
3055
3056         if (m->m_len < len) {
3057                 txr->ctx_pullup2++;
3058                 m = m_pullup(m, len);
3059                 if (m == NULL) {
3060                         txr->ctx_pullup2_failed++;
3061                         *m0 = NULL;
3062                         return ENOBUFS;
3063                 }
3064                 *m0 = m;
3065         }
3066         return 0;
3067 }
3068
3069 static int
3070 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3071 {
3072         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3073         bus_dmamap_t map;
3074         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3075         union e1000_adv_tx_desc *txd = NULL;
3076         struct mbuf *m_head = *m_headp;
3077         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3078         int maxsegs, nsegs, i, j, error, last = 0;
3079         uint32_t hdrlen = 0;
3080
3081         if (m_head->m_len < IGB_TXCSUM_MINHL &&
3082             ((m_head->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) ||
3083              (m_head->m_flags & M_VLANTAG))) {
3084                 /*
3085                  * Make sure that ethernet header and ip.ip_hl are in
3086                  * contiguous memory, since if TXCSUM or VLANTAG is
3087                  * enabled, later TX context descriptor's setup need
3088                  * to access ip.ip_hl.
3089                  */
3090                 error = igb_txctx_pullup(txr, m_headp);
3091                 if (error) {
3092                         KKASSERT(*m_headp == NULL);
3093                         return error;
3094                 }
3095                 m_head = *m_headp;
3096         }
3097
3098         /* Set basic descriptor constants */
3099         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3100         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3101         if (m_head->m_flags & M_VLANTAG)
3102                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3103
3104         /*
3105          * Map the packet for DMA.
3106          */
3107         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3108         tx_buf_mapped = tx_buf;
3109         map = tx_buf->map;
3110
3111         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3112         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3113         if (maxsegs > IGB_MAX_SCATTER)
3114                 maxsegs = IGB_MAX_SCATTER;
3115
3116         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3117             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3118         if (error) {
3119                 if (error == ENOBUFS)
3120                         txr->sc->mbuf_defrag_failed++;
3121                 else
3122                         txr->sc->no_tx_dma_setup++;
3123
3124                 m_freem(*m_headp);
3125                 *m_headp = NULL;
3126                 return error;
3127         }
3128         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3129
3130         m_head = *m_headp;
3131
3132 #if 0
3133         /*
3134          * Set up the context descriptor:
3135          * used when any hardware offload is done.
3136          * This includes CSUM, VLAN, and TSO. It
3137          * will use the first descriptor.
3138          */
3139         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3140                 if (igb_tso_setup(txr, m_head, &hdrlen)) {
3141                         cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3142                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3143                         olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3144                 } else
3145                         return (ENXIO); 
3146         } else if (igb_tx_ctx_setup(txr, m_head))
3147                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3148 #else
3149         if (igb_txctx(txr, m_head)) {
3150                 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3151                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3152                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3153                 txr->tx_nsegs++;
3154         }
3155 #endif
3156
3157         txr->tx_nsegs += nsegs;
3158         if (txr->tx_nsegs >= txr->intr_nsegs) {
3159                 /*
3160                  * Report Status (RS) is turned on every intr_nsegs
3161                  * descriptors (roughly).
3162                  */
3163                 txr->tx_nsegs = 0;
3164                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3165         }
3166
3167         /* Calculate payload length */
3168         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3169             << E1000_ADVTXD_PAYLEN_SHIFT);
3170
3171         /* 82575 needs the queue index added */
3172         if (txr->sc->hw.mac.type == e1000_82575)
3173                 olinfo_status |= txr->me << 4;
3174
3175         /* Set up our transmit descriptors */
3176         i = txr->next_avail_desc;
3177         for (j = 0; j < nsegs; j++) {
3178                 bus_size_t seg_len;
3179                 bus_addr_t seg_addr;
3180
3181                 tx_buf = &txr->tx_buf[i];
3182                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3183                 seg_addr = segs[j].ds_addr;
3184                 seg_len = segs[j].ds_len;
3185
3186                 txd->read.buffer_addr = htole64(seg_addr);
3187                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3188                 txd->read.olinfo_status = htole32(olinfo_status);
3189                 last = i;
3190                 if (++i == txr->num_tx_desc)
3191                         i = 0;
3192                 tx_buf->m_head = NULL;
3193         }
3194
3195         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3196         txr->next_avail_desc = i;
3197         txr->tx_avail -= nsegs;
3198
3199         tx_buf->m_head = m_head;
3200         tx_buf_mapped->map = tx_buf->map;
3201         tx_buf->map = map;
3202
3203         /*
3204          * Last Descriptor of Packet needs End Of Packet (EOP)
3205          */
3206         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3207
3208         /*
3209          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3210          * that this frame is available to transmit.
3211          */
3212         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3213         ++txr->tx_packets;
3214
3215         return 0;
3216 }
3217
3218 static void
3219 igb_start(struct ifnet *ifp)
3220 {
3221         struct igb_softc *sc = ifp->if_softc;
3222         struct igb_tx_ring *txr = &sc->tx_rings[0];
3223         struct mbuf *m_head;
3224
3225         ASSERT_SERIALIZED(&txr->tx_serialize);
3226
3227         if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
3228                 return;
3229
3230         if (!sc->link_active) {
3231                 ifq_purge(&ifp->if_snd);
3232                 return;
3233         }
3234
3235         if (!IGB_IS_NOT_OACTIVE(txr))
3236                 igb_txeof(txr);
3237
3238         while (!ifq_is_empty(&ifp->if_snd)) {
3239                 if (IGB_IS_OACTIVE(txr)) {
3240                         ifp->if_flags |= IFF_OACTIVE;
3241                         /* Set watchdog on */
3242                         ifp->if_timer = 5;
3243                         break;
3244                 }
3245
3246                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3247                 if (m_head == NULL)
3248                         break;
3249
3250                 if (igb_encap(txr, &m_head)) {
3251                         ifp->if_oerrors++;
3252                         continue;
3253                 }
3254
3255                 /* Send a copy of the frame to the BPF listener */
3256                 ETHER_BPF_MTAP(ifp, m_head);
3257         }
3258 }
3259
3260 static void
3261 igb_watchdog(struct ifnet *ifp)
3262 {
3263         struct igb_softc *sc = ifp->if_softc;
3264         struct igb_tx_ring *txr = &sc->tx_rings[0];
3265
3266         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3267
3268         /* 
3269          * If flow control has paused us since last checking
3270          * it invalidates the watchdog timing, so dont run it.
3271          */
3272         if (sc->pause_frames) {
3273                 sc->pause_frames = 0;
3274                 ifp->if_timer = 5;
3275                 return;
3276         }
3277
3278         if_printf(ifp, "Watchdog timeout -- resetting\n");
3279         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3280             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3281             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3282         if_printf(ifp, "TX(%d) desc avail = %d, "
3283             "Next TX to Clean = %d\n",
3284             txr->me, txr->tx_avail, txr->next_to_clean);
3285
3286         ifp->if_oerrors++;
3287         sc->watchdog_events++;
3288
3289         igb_init(sc);
3290         if (!ifq_is_empty(&ifp->if_snd))
3291                 if_devstart(ifp);
3292 }
3293
3294 static void
3295 igb_set_eitr(struct igb_softc *sc)
3296 {
3297         uint32_t itr = 0;
3298
3299         if (sc->intr_rate > 0) {
3300                 if (sc->hw.mac.type == e1000_82575) {
3301                         itr = 1000000000 / 256 / sc->intr_rate;
3302                         /*
3303                          * NOTE:
3304                          * Document is wrong on the 2 bits left shift
3305                          */
3306                 } else {
3307                         itr = 1000000 / sc->intr_rate;
3308                         itr <<= 2;
3309                 }
3310                 itr &= 0x7FFC;
3311         }
3312         if (sc->hw.mac.type == e1000_82575)
3313                 itr |= itr << 16;
3314         else
3315                 itr |= E1000_EITR_CNT_IGNR;
3316         E1000_WRITE_REG(&sc->hw, E1000_EITR(0), itr);
3317 }
3318
3319 static int
3320 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3321 {
3322         struct igb_softc *sc = (void *)arg1;
3323         struct ifnet *ifp = &sc->arpcom.ac_if;
3324         int error, intr_rate;
3325
3326         intr_rate = sc->intr_rate;
3327         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3328         if (error || req->newptr == NULL)
3329                 return error;
3330         if (intr_rate < 0)
3331                 return EINVAL;
3332
3333         ifnet_serialize_all(ifp);
3334
3335         sc->intr_rate = intr_rate;
3336         if (ifp->if_flags & IFF_RUNNING)
3337                 igb_set_eitr(sc);
3338
3339         ifnet_deserialize_all(ifp);
3340
3341         if (bootverbose)
3342                 if_printf(ifp, "Interrupt rate set to %d/sec\n", sc->intr_rate);
3343         return 0;
3344 }
3345
3346 static int
3347 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3348 {
3349         struct igb_softc *sc = (void *)arg1;
3350         struct ifnet *ifp = &sc->arpcom.ac_if;
3351         struct igb_tx_ring *txr = &sc->tx_rings[0];
3352         int error, nsegs;
3353
3354         nsegs = txr->intr_nsegs;
3355         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3356         if (error || req->newptr == NULL)
3357                 return error;
3358         if (nsegs <= 0)
3359                 return EINVAL;
3360
3361         ifnet_serialize_all(ifp);
3362
3363         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3364             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3365                 error = EINVAL;
3366         } else {
3367                 error = 0;
3368                 txr->intr_nsegs = nsegs;
3369         }
3370
3371         ifnet_deserialize_all(ifp);
3372
3373         return error;
3374 }
3375
3376 static void
3377 igb_init_intr(struct igb_softc *sc)
3378 {
3379         if (sc->flags & IGB_FLAG_SHARED_INTR)
3380                 igb_set_eitr(sc);
3381         else
3382                 igb_init_unshared_intr(sc);
3383 }
3384
3385 static void
3386 igb_init_unshared_intr(struct igb_softc *sc)
3387 {
3388         struct e1000_hw *hw = &sc->hw;
3389         const struct igb_rx_ring *rxr;
3390         const struct igb_tx_ring *txr;
3391         uint32_t ivar, index;
3392         int i;
3393
3394         /*
3395          * Enable extended mode
3396          */
3397         if (sc->hw.mac.type != e1000_82575) {
3398                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_NSICR);
3399         } else {
3400                 uint32_t tmp;
3401
3402                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3403                 tmp |= E1000_CTRL_EXT_IRCA;
3404                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3405         }
3406
3407         /*
3408          * Map TX/RX interrupts to EICR
3409          */
3410         switch (sc->hw.mac.type) {
3411         case e1000_82580:
3412         case e1000_i350:
3413         case e1000_vfadapt:
3414         case e1000_vfadapt_i350:
3415                 /* RX entries */
3416                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3417                         rxr = &sc->rx_rings[i];
3418
3419                         index = i >> 1;
3420                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3421
3422                         if (i & 1) {
3423                                 ivar &= 0xff00ffff;
3424                                 ivar |=
3425                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3426                         } else {
3427                                 ivar &= 0xffffff00;
3428                                 ivar |=
3429                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3430                         }
3431                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3432                 }
3433                 /* TX entries */
3434                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3435                         txr = &sc->tx_rings[i];
3436
3437                         index = i >> 1;
3438                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3439
3440                         if (i & 1) {
3441                                 ivar &= 0x00ffffff;
3442                                 ivar |=
3443                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3444                         } else {
3445                                 ivar &= 0xffff00ff;
3446                                 ivar |=
3447                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3448                         }
3449                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3450                 }
3451                 /* Clear unused IVAR_MISC */
3452                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3453                 break;
3454
3455         case e1000_82576:
3456                 /* RX entries */
3457                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3458                         rxr = &sc->rx_rings[i];
3459
3460                         index = i & 0x7; /* Each IVAR has two entries */
3461                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3462
3463                         if (i < 8) {
3464                                 ivar &= 0xffffff00;
3465                                 ivar |=
3466                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3467                         } else {
3468                                 ivar &= 0xff00ffff;
3469                                 ivar |=
3470                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3471                         }
3472                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3473                 }
3474                 /* TX entries */
3475                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3476                         txr = &sc->tx_rings[i];
3477
3478                         index = i & 0x7; /* Each IVAR has two entries */
3479                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3480
3481                         if (i < 8) {
3482                                 ivar &= 0xffff00ff;
3483                                 ivar |=
3484                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3485                         } else {
3486                                 ivar &= 0x00ffffff;
3487                                 ivar |=
3488                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3489                         }
3490                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3491                 }
3492                 /* Clear unused IVAR_MISC */
3493                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3494                 break;
3495
3496         case e1000_82575:
3497                 /*
3498                  * Enable necessary interrupt bits.
3499                  *
3500                  * The name of the register is confusing; in addition to
3501                  * configuring the first vector of MSI-X, it also configures
3502                  * which bits of EICR could be set by the hardware even when
3503                  * MSI or line interrupt is used; it thus controls interrupt
3504                  * generation.  It MUST be configured explicitly; the default
3505                  * value mentioned in the datasheet is wrong: RX queue0 and
3506                  * TX queue0 are NOT enabled by default.
3507                  */
3508                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3509                 break;
3510
3511         default:
3512                 break;
3513         }
3514
3515         /*
3516          * Configure interrupt moderation
3517          */
3518         igb_set_eitr(sc);
3519 }
3520
3521 static int
3522 igb_setup_intr(struct igb_softc *sc)
3523 {
3524         struct ifnet *ifp = &sc->arpcom.ac_if;
3525         int error, i, intr_bit, intr_bitmax;
3526
3527         /*
3528          * Setup interrupt mask
3529          */
3530         switch (sc->hw.mac.type) {
3531         case e1000_82575:
3532                 intr_bitmax = IGB_MAX_TXRXINT_82575;
3533                 break;
3534         case e1000_82580:
3535                 intr_bitmax = IGB_MAX_TXRXINT_82580;
3536                 break;
3537         case e1000_i350:
3538                 intr_bitmax = IGB_MAX_TXRXINT_I350;
3539                 break;
3540         case e1000_82576:
3541                 intr_bitmax = IGB_MAX_TXRXINT_82576;
3542                 break;
3543         default:
3544                 intr_bitmax = IGB_MIN_TXRXINT;
3545                 break;
3546         }
3547         intr_bit = 0;
3548         for (i = 0; i < sc->tx_ring_cnt; ++i)
3549                 igb_setup_tx_intr(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3550         for (i = 0; i < sc->rx_ring_cnt; ++i)
3551                 igb_setup_rx_intr(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3552
3553         sc->intr_mask = E1000_EICR_OTHER;
3554         for (i = 0; i < sc->rx_ring_cnt; ++i)
3555                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3556         for (i = 0; i < sc->tx_ring_cnt; ++i)
3557                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3558
3559         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3560                 int unshared;
3561
3562                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3563                 if (!unshared) {
3564                         sc->flags |= IGB_FLAG_SHARED_INTR;
3565                         if (bootverbose)
3566                                 device_printf(sc->dev, "IRQ shared\n");
3567                 } else if (bootverbose) {
3568                         device_printf(sc->dev, "IRQ unshared\n");
3569                 }
3570         }
3571
3572         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3573             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_shared_intr : igb_intr,
3574             sc, &sc->intr_tag, &sc->main_serialize);
3575         if (error) {
3576                 device_printf(sc->dev, "Failed to register interrupt handler");
3577                 return error;
3578         }
3579
3580         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3581         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3582
3583         return 0;
3584 }
3585
3586 static void
3587 igb_setup_tx_intr(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3588 {
3589         if (txr->sc->hw.mac.type == e1000_82575) {
3590                 txr->tx_intr_bit = 0;   /* unused */
3591                 switch (txr->me) {
3592                 case 0:
3593                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3594                         break;
3595                 case 1:
3596                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3597                         break;
3598                 case 2:
3599                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3600                         break;
3601                 case 3:
3602                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3603                         break;
3604                 default:
3605                         panic("unsupported # of TX ring, %d\n", txr->me);
3606                 }
3607         } else {
3608                 int intr_bit = *intr_bit0;
3609
3610                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3611                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3612
3613                 *intr_bit0 = intr_bit + 1;
3614         }
3615 }
3616
3617 static void
3618 igb_setup_rx_intr(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3619 {
3620         if (rxr->sc->hw.mac.type == e1000_82575) {
3621                 rxr->rx_intr_bit = 0;   /* unused */
3622                 switch (rxr->me) {
3623                 case 0:
3624                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3625                         break;
3626                 case 1:
3627                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3628                         break;
3629                 case 2:
3630                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3631                         break;
3632                 case 3:
3633                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3634                         break;
3635                 default:
3636                         panic("unsupported # of RX ring, %d\n", rxr->me);
3637                 }
3638         } else {
3639                 int intr_bit = *intr_bit0;
3640
3641                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3642                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3643
3644                 *intr_bit0 = intr_bit + 1;
3645         }
3646 }
3647
3648 static void
3649 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3650 {
3651         struct igb_softc *sc = ifp->if_softc;
3652
3653         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3654             sc->tx_serialize, sc->rx_serialize, slz);
3655 }
3656
3657 static void
3658 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3659 {
3660         struct igb_softc *sc = ifp->if_softc;
3661
3662         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3663             sc->tx_serialize, sc->rx_serialize, slz);
3664 }
3665
3666 static int
3667 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3668 {
3669         struct igb_softc *sc = ifp->if_softc;
3670
3671         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3672             sc->tx_serialize, sc->rx_serialize, slz);
3673 }
3674
3675 #ifdef INVARIANTS
3676
3677 static void
3678 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3679     boolean_t serialized)
3680 {
3681         struct igb_softc *sc = ifp->if_softc;
3682
3683         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3684             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3685 }
3686
3687 #endif  /* INVARIANTS */