2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_SIZE (0x10000)
75 #define BIOS_COUNT (BIOS_SIZE/4)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
82 #define PROCENTRY_FLAG_EN 0x01
83 #define PROCENTRY_FLAG_BP 0x02
84 #define IOAPICENTRY_FLAG_EN 0x01
87 /* MP Floating Pointer Structure */
88 typedef struct MPFPS {
101 /* MP Configuration Table Header */
102 typedef struct MPCTH {
104 u_short base_table_length;
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
119 typedef struct PROCENTRY {
124 u_long cpu_signature;
125 u_long feature_flags;
130 typedef struct BUSENTRY {
136 typedef struct IOAPICENTRY {
142 } *io_apic_entry_ptr;
144 typedef struct INTENTRY {
154 /* descriptions of MP basetable entries */
155 typedef struct BASETABLE_ENTRY {
164 vm_size_t mp_cth_mapsz;
167 typedef int (*mptable_iter_func)(void *, const void *, int);
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
175 #if defined(CHECK_POINTS)
176 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
179 #define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
187 #define CHECK_PRINT(S); \
188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
197 #else /* CHECK_POINTS */
199 #define CHECK_INIT(D)
200 #define CHECK_PRINT(S)
202 #endif /* CHECK_POINTS */
205 * Values to send to the POST hardware.
207 #define MP_BOOTADDRESS_POST 0x10
208 #define MP_PROBE_POST 0x11
209 #define MPTABLE_PASS1_POST 0x12
211 #define MP_START_POST 0x13
212 #define MP_ENABLE_POST 0x14
213 #define MPTABLE_PASS2_POST 0x15
215 #define START_ALL_APS_POST 0x16
216 #define INSTALL_AP_TRAMP_POST 0x17
217 #define START_AP_POST 0x18
219 #define MP_ANNOUNCE_POST 0x19
221 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
222 int current_postcode;
224 /** XXX FIXME: what system files declare these??? */
225 extern struct region_descriptor r_gdt, r_idt;
227 int mp_naps; /* # of Applications processors */
229 static int mp_nbusses; /* # of busses */
230 int mp_napics; /* # of IO APICs */
233 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
234 u_int32_t *io_apic_versions;
238 u_int32_t cpu_apic_versions[MAXCPU];
240 extern int64_t tsc_offsets[];
242 extern u_long ebda_addr;
245 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
249 * APIC ID logical/physical mapping structures.
250 * We oversize these to simplify boot-time config.
252 int cpu_num_to_apic_id[NAPICID];
254 int io_num_to_apic_id[NAPICID];
256 int apic_id_to_logical[NAPICID];
258 /* AP uses this during bootstrap. Do not staticize. */
262 /* Hotwire a 0->4MB V==P mapping */
263 extern pt_entry_t *KPTphys;
266 * SMP page table page. Setup by locore to point to a page table
267 * page from which we allocate per-cpu privatespace areas io_apics,
271 #define IO_MAPPING_START_INDEX \
272 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
274 extern pt_entry_t *SMPpt;
275 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
277 struct pcb stoppcbs[MAXCPU];
279 static basetable_entry basetable_entry_types[] =
281 {0, 20, "Processor"},
289 * Local data and functions.
292 static u_int boot_address;
293 static u_int base_memory;
294 static int mp_finish;
296 static void mp_enable(u_int boot_addr);
298 static int mptable_iterate_entries(const mpcth_t,
299 mptable_iter_func, void *);
300 static int mptable_probe(void);
301 static int mptable_search(void);
302 static int mptable_check(vm_paddr_t);
303 static int mptable_search_sig(u_int32_t target, int count);
304 static int mptable_hyperthread_fixup(u_int, int);
305 static void mptable_pass1(struct mptable_pos *);
306 static void mptable_pass2(struct mptable_pos *);
307 static void mptable_default(int type);
308 static void mptable_fix(void);
309 static int mptable_map(struct mptable_pos *, vm_paddr_t);
310 static void mptable_unmap(struct mptable_pos *);
311 static void mptable_imcr(struct mptable_pos *);
313 static int mptable_lapic_probe(struct lapic_enumerator *);
314 static void mptable_lapic_enumerate(struct lapic_enumerator *);
315 static void mptable_lapic_default(void);
318 static void setup_apic_irq_mapping(void);
319 static int apic_int_is_bus_type(int intr, int bus_type);
321 static int start_all_aps(u_int boot_addr);
322 static void install_ap_tramp(u_int boot_addr);
323 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
325 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
326 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
327 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
330 * Calculate usable address in base memory for AP trampoline code.
333 mp_bootaddress(u_int basemem)
335 POSTCODE(MP_BOOTADDRESS_POST);
337 base_memory = basemem;
339 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
340 if ((base_memory - boot_address) < bootMP_size)
341 boot_address -= 4096; /* not enough, lower by 4k */
352 mpfps_paddr = mptable_search();
353 if (mptable_check(mpfps_paddr))
360 * Look for an Intel MP spec table (ie, SMP capable hardware).
369 * Make sure our SMPpt[] page table is big enough to hold all the
372 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
374 POSTCODE(MP_PROBE_POST);
376 /* see if EBDA exists */
377 if (ebda_addr != 0) {
378 /* search first 1K of EBDA */
379 target = (u_int32_t)ebda_addr;
380 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
383 /* last 1K of base memory, effective 'top of base' passed in */
384 target = (u_int32_t)(base_memory - 0x400);
385 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
389 /* search the BIOS */
390 target = (u_int32_t)BIOS_BASE;
391 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
398 struct mptable_check_cbarg {
404 mptable_check_callback(void *xarg, const void *pos, int type)
406 const struct PROCENTRY *ent;
407 struct mptable_check_cbarg *arg = xarg;
413 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
417 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
418 if (arg->found_bsp) {
419 kprintf("more than one BSP in base MP table\n");
428 mptable_check(vm_paddr_t mpfps_paddr)
430 struct mptable_pos mpt;
431 struct mptable_check_cbarg arg;
435 if (mpfps_paddr == 0)
438 error = mptable_map(&mpt, mpfps_paddr);
442 if (mpt.mp_fps->mpfb1 != 0)
450 if (cth->apic_address == 0)
453 bzero(&arg, sizeof(arg));
454 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
456 if (arg.cpu_count == 0) {
457 kprintf("MP table contains no processor entries\n");
459 } else if (!arg.found_bsp) {
460 kprintf("MP table does not contains BSP entry\n");
470 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
472 int count, total_size;
473 const void *position;
475 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
476 total_size = cth->base_table_length - sizeof(struct MPCTH);
477 position = (const uint8_t *)cth + sizeof(struct MPCTH);
478 count = cth->entry_count;
483 KKASSERT(total_size >= 0);
484 if (total_size == 0) {
485 kprintf("invalid base MP table, "
486 "entry count and length mismatch\n");
490 type = *(const uint8_t *)position;
492 case 0: /* processor_entry */
493 case 1: /* bus_entry */
494 case 2: /* io_apic_entry */
495 case 3: /* int_entry */
496 case 4: /* int_entry */
499 kprintf("unknown base MP table entry type %d\n", type);
503 if (total_size < basetable_entry_types[type].length) {
504 kprintf("invalid base MP table length, "
505 "does not contain all entries\n");
508 total_size -= basetable_entry_types[type].length;
510 error = func(arg, position, type);
514 position = (const uint8_t *)position +
515 basetable_entry_types[type].length;
522 * Startup the SMP processors.
527 POSTCODE(MP_START_POST);
528 mp_enable(boot_address);
533 * Print various information about the SMP system hardware and setup.
540 POSTCODE(MP_ANNOUNCE_POST);
542 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
543 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
544 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
545 for (x = 1; x <= mp_naps; ++x) {
546 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
547 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
551 for (x = 0; x < mp_napics; ++x) {
552 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
553 kprintf(", version: 0x%08x", io_apic_versions[x]);
554 kprintf(", at 0x%08x\n", io_apic_address[x]);
557 kprintf(" Warning: APIC I/O disabled\n");
562 * AP cpu's call this to sync up protected mode.
564 * WARNING! We must ensure that the cpu is sufficiently initialized to
565 * be able to use to the FP for our optimized bzero/bcopy code before
566 * we enter more mainstream C code.
568 * WARNING! %fs is not set up on entry. This routine sets up %fs.
574 int x, myid = bootAP;
576 struct mdglobaldata *md;
577 struct privatespace *ps;
579 ps = &CPU_prvspace[myid];
581 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
582 gdt_segs[GPROC0_SEL].ssd_base =
583 (int) &ps->mdglobaldata.gd_common_tss;
584 ps->mdglobaldata.mi.gd_prvspace = ps;
586 for (x = 0; x < NGDT; x++) {
587 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
590 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
591 r_gdt.rd_base = (int) &gdt[myid * NGDT];
592 lgdt(&r_gdt); /* does magic intra-segment return */
597 mdcpu->gd_currentldt = _default_ldt;
599 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
600 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
602 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
604 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
605 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
606 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
607 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
608 md->gd_common_tssd = *md->gd_tss_gdt;
612 * Set to a known state:
613 * Set by mpboot.s: CR0_PG, CR0_PE
614 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
617 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
619 pmap_set_opt(); /* PSE/4MB pages, etc */
621 /* set up CPU registers and state */
624 /* set up FPU state on the AP */
625 npxinit(__INITIAL_NPXCW__);
627 /* set up SSE registers */
631 /*******************************************************************
632 * local functions and data
636 * start the SMP system
639 mp_enable(u_int boot_addr)
645 vm_paddr_t mpfps_paddr;
646 struct mptable_pos mpt;
648 POSTCODE(MP_ENABLE_POST);
652 mpfps_paddr = mptable_probe();
654 mptable_map(&mpt, mpfps_paddr);
661 panic("no MP table, disable APIC_IO!\n");
663 mptable_map(&mpt, mpfps_paddr);
666 * Examine the MP table for needed info
673 /* Post scan cleanup */
676 setup_apic_irq_mapping();
678 /* fill the LOGICAL io_apic_versions table */
679 for (apic = 0; apic < mp_napics; ++apic) {
680 ux = io_apic_read(apic, IOAPIC_VER);
681 io_apic_versions[apic] = ux;
682 io_apic_set_id(apic, IO_TO_ID(apic));
685 /* program each IO APIC in the system */
686 for (apic = 0; apic < mp_napics; ++apic)
687 if (io_apic_setup(apic) < 0)
688 panic("IO APIC setup failure");
693 * These are required for SMP operation
696 /* install a 'Spurious INTerrupt' vector */
697 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
698 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
700 /* install an inter-CPU IPI for TLB invalidation */
701 setidt(XINVLTLB_OFFSET, Xinvltlb,
702 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
704 /* install an inter-CPU IPI for IPIQ messaging */
705 setidt(XIPIQ_OFFSET, Xipiq,
706 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
708 /* install a timer vector */
709 setidt(XTIMER_OFFSET, Xtimer,
710 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
712 /* install an inter-CPU IPI for CPU stop/restart */
713 setidt(XCPUSTOP_OFFSET, Xcpustop,
714 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
716 /* start each Application Processor */
717 start_all_aps(boot_addr);
722 * look for the MP spec signature
725 /* string defined by the Intel MP Spec as identifying the MP table */
726 #define MP_SIG 0x5f504d5f /* _MP_ */
727 #define NEXT(X) ((X) += 4)
729 mptable_search_sig(u_int32_t target, int count)
735 KKASSERT(target != 0);
737 map_size = count * sizeof(u_int32_t);
738 addr = pmap_mapdev((vm_paddr_t)target, map_size);
741 for (x = 0; x < count; NEXT(x)) {
742 if (addr[x] == MP_SIG) {
743 /* make array index a byte index */
744 ret = target + (x * sizeof(u_int32_t));
749 pmap_unmapdev((vm_offset_t)addr, map_size);
754 typedef struct BUSDATA {
756 enum busTypes bus_type;
759 typedef struct INTDATA {
769 typedef struct BUSTYPENAME {
774 static bus_type_name bus_type_table[] =
780 {UNKNOWN_BUSTYPE, "---"},
783 {UNKNOWN_BUSTYPE, "---"},
784 {UNKNOWN_BUSTYPE, "---"},
785 {UNKNOWN_BUSTYPE, "---"},
786 {UNKNOWN_BUSTYPE, "---"},
787 {UNKNOWN_BUSTYPE, "---"},
789 {UNKNOWN_BUSTYPE, "---"},
790 {UNKNOWN_BUSTYPE, "---"},
791 {UNKNOWN_BUSTYPE, "---"},
792 {UNKNOWN_BUSTYPE, "---"},
794 {UNKNOWN_BUSTYPE, "---"}
796 /* from MP spec v1.4, table 5-1 */
797 static int default_data[7][5] =
799 /* nbus, id0, type0, id1, type1 */
800 {1, 0, ISA, 255, 255},
801 {1, 0, EISA, 255, 255},
802 {1, 0, EISA, 255, 255},
803 {1, 0, MCA, 255, 255},
805 {2, 0, EISA, 1, PCI},
813 static bus_datum *bus_data;
815 /* the IO INT data, one entry per possible APIC INTerrupt */
816 static io_int *io_apic_ints;
821 static int processor_entry (const struct PROCENTRY *entry, int cpu);
823 static int bus_entry (const struct BUSENTRY *entry, int bus);
824 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
825 static int int_entry (const struct INTENTRY *entry, int intr);
827 static int lookup_bus_type (char *name);
832 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
834 const struct IOAPICENTRY *ioapic_ent;
837 case 1: /* bus_entry */
841 case 2: /* io_apic_entry */
843 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
844 io_apic_address[mp_napics++] =
845 (vm_offset_t)ioapic_ent->apic_address;
849 case 3: /* int_entry */
859 * 1st pass on motherboard's Intel MP specification table.
868 mptable_pass1(struct mptable_pos *mpt)
874 POSTCODE(MPTABLE_PASS1_POST);
877 KKASSERT(fps != NULL);
879 /* clear various tables */
880 for (x = 0; x < NAPICID; ++x)
881 io_apic_address[x] = ~0; /* IO APIC address table */
887 /* check for use of 'default' configuration */
888 if (fps->mpfb1 != 0) {
889 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
890 mp_nbusses = default_data[fps->mpfb1 - 1][0];
896 error = mptable_iterate_entries(mpt->mp_cth,
897 mptable_ioapic_pass1_callback, NULL);
899 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
906 struct mptable_ioapic2_cbarg {
913 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
915 struct mptable_ioapic2_cbarg *arg = xarg;
919 if (bus_entry(pos, arg->bus))
924 if (io_apic_entry(pos, arg->apic))
929 if (int_entry(pos, arg->intr))
939 * 2nd pass on motherboard's Intel MP specification table.
942 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
943 * IO_TO_ID(N), logical IO to APIC ID table
948 mptable_pass2(struct mptable_pos *mpt)
951 struct mptable_ioapic2_cbarg arg;
955 POSTCODE(MPTABLE_PASS2_POST);
958 KKASSERT(fps != NULL);
960 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
962 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
963 M_DEVBUF, M_WAITOK | M_ZERO);
964 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
966 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
969 for (x = 0; x < mp_napics; x++)
970 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
972 /* clear various tables */
973 for (x = 0; x < NAPICID; ++x) {
974 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
975 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
978 /* clear bus data table */
979 for (x = 0; x < mp_nbusses; ++x)
980 bus_data[x].bus_id = 0xff;
982 /* clear IO APIC INT table */
983 for (x = 0; x < (nintrs + 1); ++x) {
984 io_apic_ints[x].int_type = 0xff;
985 io_apic_ints[x].int_vector = 0xff;
988 /* check for use of 'default' configuration */
989 if (fps->mpfb1 != 0) {
990 mptable_default(fps->mpfb1);
994 bzero(&arg, sizeof(arg));
995 error = mptable_iterate_entries(mpt->mp_cth,
996 mptable_ioapic_pass2_callback, &arg);
998 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1003 * Check if we should perform a hyperthreading "fix-up" to
1004 * enumerate any logical CPU's that aren't already listed
1007 * XXX: We assume that all of the physical CPUs in the
1008 * system have the same number of logical CPUs.
1010 * XXX: We assume that APIC ID's are allocated such that
1011 * the APIC ID's for a physical processor are aligned
1012 * with the number of logical CPU's in the processor.
1015 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1017 int i, id, lcpus_max, logical_cpus;
1019 if ((cpu_feature & CPUID_HTT) == 0)
1022 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1026 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1028 * INSTRUCTION SET REFERENCE, A-M (#253666)
1029 * Page 3-181, Table 3-20
1030 * "The nearest power-of-2 integer that is not smaller
1031 * than EBX[23:16] is the number of unique initial APIC
1032 * IDs reserved for addressing different logical
1033 * processors in a physical package."
1035 for (i = 0; ; ++i) {
1036 if ((1 << i) >= lcpus_max) {
1043 KKASSERT(cpu_count != 0);
1044 if (cpu_count == lcpus_max) {
1045 /* We have nothing to fix */
1047 } else if (cpu_count == 1) {
1048 /* XXX this may be incorrect */
1049 logical_cpus = lcpus_max;
1051 int cur, prev, dist;
1054 * Calculate the distances between two nearest
1055 * APIC IDs. If all such distances are same,
1056 * then it is the number of missing cpus that
1057 * we are going to fill later.
1059 dist = cur = prev = -1;
1060 for (id = 0; id < MAXCPU; ++id) {
1061 if ((id_mask & 1 << id) == 0)
1066 int new_dist = cur - prev;
1072 * Make sure that all distances
1073 * between two nearest APIC IDs
1076 if (dist != new_dist)
1084 /* Must be power of 2 */
1085 if (dist & (dist - 1))
1088 /* Can't exceed CPU package capacity */
1089 if (dist > lcpus_max)
1090 logical_cpus = lcpus_max;
1092 logical_cpus = dist;
1096 * For each APIC ID of a CPU that is set in the mask,
1097 * scan the other candidate APIC ID's for this
1098 * physical processor. If any of those ID's are
1099 * already in the table, then kill the fixup.
1101 for (id = 0; id < MAXCPU; id++) {
1102 if ((id_mask & 1 << id) == 0)
1104 /* First, make sure we are on a logical_cpus boundary. */
1105 if (id % logical_cpus != 0)
1107 for (i = id + 1; i < id + logical_cpus; i++)
1108 if ((id_mask & 1 << i) != 0)
1111 return logical_cpus;
1115 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1119 vm_size_t cth_mapsz = 0;
1121 bzero(mpt, sizeof(*mpt));
1123 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1124 if (fps->pap != 0) {
1126 * Map configuration table header to get
1127 * the base table size
1129 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1130 cth_mapsz = cth->base_table_length;
1131 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1133 if (cth_mapsz < sizeof(*cth)) {
1134 kprintf("invalid base MP table length %d\n",
1136 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1141 * Map the base table
1143 cth = pmap_mapdev(fps->pap, cth_mapsz);
1148 mpt->mp_cth_mapsz = cth_mapsz;
1154 mptable_unmap(struct mptable_pos *mpt)
1156 if (mpt->mp_cth != NULL) {
1157 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1159 mpt->mp_cth_mapsz = 0;
1161 if (mpt->mp_fps != NULL) {
1162 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1170 assign_apic_irq(int apic, int intpin, int irq)
1174 if (int_to_apicintpin[irq].ioapic != -1)
1175 panic("assign_apic_irq: inconsistent table");
1177 int_to_apicintpin[irq].ioapic = apic;
1178 int_to_apicintpin[irq].int_pin = intpin;
1179 int_to_apicintpin[irq].apic_address = ioapic[apic];
1180 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1182 for (x = 0; x < nintrs; x++) {
1183 if ((io_apic_ints[x].int_type == 0 ||
1184 io_apic_ints[x].int_type == 3) &&
1185 io_apic_ints[x].int_vector == 0xff &&
1186 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1187 io_apic_ints[x].dst_apic_int == intpin)
1188 io_apic_ints[x].int_vector = irq;
1193 revoke_apic_irq(int irq)
1199 if (int_to_apicintpin[irq].ioapic == -1)
1200 panic("revoke_apic_irq: inconsistent table");
1202 oldapic = int_to_apicintpin[irq].ioapic;
1203 oldintpin = int_to_apicintpin[irq].int_pin;
1205 int_to_apicintpin[irq].ioapic = -1;
1206 int_to_apicintpin[irq].int_pin = 0;
1207 int_to_apicintpin[irq].apic_address = NULL;
1208 int_to_apicintpin[irq].redirindex = 0;
1210 for (x = 0; x < nintrs; x++) {
1211 if ((io_apic_ints[x].int_type == 0 ||
1212 io_apic_ints[x].int_type == 3) &&
1213 io_apic_ints[x].int_vector != 0xff &&
1214 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1215 io_apic_ints[x].dst_apic_int == oldintpin)
1216 io_apic_ints[x].int_vector = 0xff;
1224 allocate_apic_irq(int intr)
1230 if (io_apic_ints[intr].int_vector != 0xff)
1231 return; /* Interrupt handler already assigned */
1233 if (io_apic_ints[intr].int_type != 0 &&
1234 (io_apic_ints[intr].int_type != 3 ||
1235 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1236 io_apic_ints[intr].dst_apic_int == 0)))
1237 return; /* Not INT or ExtInt on != (0, 0) */
1240 while (irq < APIC_INTMAPSIZE &&
1241 int_to_apicintpin[irq].ioapic != -1)
1244 if (irq >= APIC_INTMAPSIZE)
1245 return; /* No free interrupt handlers */
1247 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1248 intpin = io_apic_ints[intr].dst_apic_int;
1250 assign_apic_irq(apic, intpin, irq);
1251 io_apic_setup_intpin(apic, intpin);
1256 swap_apic_id(int apic, int oldid, int newid)
1263 return; /* Nothing to do */
1265 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1266 apic, oldid, newid);
1268 /* Swap physical APIC IDs in interrupt entries */
1269 for (x = 0; x < nintrs; x++) {
1270 if (io_apic_ints[x].dst_apic_id == oldid)
1271 io_apic_ints[x].dst_apic_id = newid;
1272 else if (io_apic_ints[x].dst_apic_id == newid)
1273 io_apic_ints[x].dst_apic_id = oldid;
1276 /* Swap physical APIC IDs in IO_TO_ID mappings */
1277 for (oapic = 0; oapic < mp_napics; oapic++)
1278 if (IO_TO_ID(oapic) == newid)
1281 if (oapic < mp_napics) {
1282 kprintf("Changing APIC ID for IO APIC #%d from "
1283 "%d to %d in MP table\n",
1284 oapic, newid, oldid);
1285 IO_TO_ID(oapic) = oldid;
1287 IO_TO_ID(apic) = newid;
1292 fix_id_to_io_mapping(void)
1296 for (x = 0; x < NAPICID; x++)
1299 for (x = 0; x <= mp_naps; x++)
1300 if (CPU_TO_ID(x) < NAPICID)
1301 ID_TO_IO(CPU_TO_ID(x)) = x;
1303 for (x = 0; x < mp_napics; x++)
1304 if (IO_TO_ID(x) < NAPICID)
1305 ID_TO_IO(IO_TO_ID(x)) = x;
1310 first_free_apic_id(void)
1314 for (freeid = 0; freeid < NAPICID; freeid++) {
1315 for (x = 0; x <= mp_naps; x++)
1316 if (CPU_TO_ID(x) == freeid)
1320 for (x = 0; x < mp_napics; x++)
1321 if (IO_TO_ID(x) == freeid)
1332 io_apic_id_acceptable(int apic, int id)
1334 int cpu; /* Logical CPU number */
1335 int oapic; /* Logical IO APIC number for other IO APIC */
1338 return 0; /* Out of range */
1340 for (cpu = 0; cpu <= mp_naps; cpu++)
1341 if (CPU_TO_ID(cpu) == id)
1342 return 0; /* Conflict with CPU */
1344 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1345 if (IO_TO_ID(oapic) == id)
1346 return 0; /* Conflict with other APIC */
1348 return 1; /* ID is acceptable for IO APIC */
1353 io_apic_find_int_entry(int apic, int pin)
1357 /* search each of the possible INTerrupt sources */
1358 for (x = 0; x < nintrs; ++x) {
1359 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1360 (pin == io_apic_ints[x].dst_apic_int))
1361 return (&io_apic_ints[x]);
1369 * parse an Intel MP specification table
1377 int apic; /* IO APIC unit number */
1378 int freeid; /* Free physical APIC ID */
1379 int physid; /* Current physical IO APIC ID */
1381 int bus_0 = 0; /* Stop GCC warning */
1382 int bus_pci = 0; /* Stop GCC warning */
1386 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1387 * did it wrong. The MP spec says that when more than 1 PCI bus
1388 * exists the BIOS must begin with bus entries for the PCI bus and use
1389 * actual PCI bus numbering. This implies that when only 1 PCI bus
1390 * exists the BIOS can choose to ignore this ordering, and indeed many
1391 * MP motherboards do ignore it. This causes a problem when the PCI
1392 * sub-system makes requests of the MP sub-system based on PCI bus
1393 * numbers. So here we look for the situation and renumber the
1394 * busses and associated INTs in an effort to "make it right".
1397 /* find bus 0, PCI bus, count the number of PCI busses */
1398 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1399 if (bus_data[x].bus_id == 0) {
1402 if (bus_data[x].bus_type == PCI) {
1408 * bus_0 == slot of bus with ID of 0
1409 * bus_pci == slot of last PCI bus encountered
1412 /* check the 1 PCI bus case for sanity */
1413 /* if it is number 0 all is well */
1414 if (num_pci_bus == 1 &&
1415 bus_data[bus_pci].bus_id != 0) {
1417 /* mis-numbered, swap with whichever bus uses slot 0 */
1419 /* swap the bus entry types */
1420 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1421 bus_data[bus_0].bus_type = PCI;
1423 /* swap each relavant INTerrupt entry */
1424 id = bus_data[bus_pci].bus_id;
1425 for (x = 0; x < nintrs; ++x) {
1426 if (io_apic_ints[x].src_bus_id == id) {
1427 io_apic_ints[x].src_bus_id = 0;
1429 else if (io_apic_ints[x].src_bus_id == 0) {
1430 io_apic_ints[x].src_bus_id = id;
1435 /* Assign IO APIC IDs.
1437 * First try the existing ID. If a conflict is detected, try
1438 * the ID in the MP table. If a conflict is still detected, find
1441 * We cannot use the ID_TO_IO table before all conflicts has been
1442 * resolved and the table has been corrected.
1444 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1446 /* First try to use the value set by the BIOS */
1447 physid = io_apic_get_id(apic);
1448 if (io_apic_id_acceptable(apic, physid)) {
1449 if (IO_TO_ID(apic) != physid)
1450 swap_apic_id(apic, IO_TO_ID(apic), physid);
1454 /* Then check if the value in the MP table is acceptable */
1455 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1458 /* Last resort, find a free APIC ID and use it */
1459 freeid = first_free_apic_id();
1460 if (freeid >= NAPICID)
1461 panic("No free physical APIC IDs found");
1463 if (io_apic_id_acceptable(apic, freeid)) {
1464 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1467 panic("Free physical APIC ID not usable");
1469 fix_id_to_io_mapping();
1471 /* detect and fix broken Compaq MP table */
1472 if (apic_int_type(0, 0) == -1) {
1473 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1474 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1475 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1476 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1477 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1478 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1480 } else if (apic_int_type(0, 0) == 0) {
1481 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1482 for (x = 0; x < nintrs; ++x)
1483 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1484 (0 == io_apic_ints[x].dst_apic_int)) {
1485 io_apic_ints[x].int_type = 3;
1486 io_apic_ints[x].int_vector = 0xff;
1492 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1493 * controllers universally come in pairs. If IRQ 14 is specified
1494 * as an ISA interrupt, then IRQ 15 had better be too.
1496 * [ Shuttle XPC / AMD Athlon X2 ]
1497 * The MPTable is missing an entry for IRQ 15. Note that the
1498 * ACPI table has an entry for both 14 and 15.
1500 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1501 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1502 io14 = io_apic_find_int_entry(0, 14);
1503 io_apic_ints[nintrs] = *io14;
1504 io_apic_ints[nintrs].src_bus_irq = 15;
1505 io_apic_ints[nintrs].dst_apic_int = 15;
1513 /* Assign low level interrupt handlers */
1515 setup_apic_irq_mapping(void)
1521 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1522 int_to_apicintpin[x].ioapic = -1;
1523 int_to_apicintpin[x].int_pin = 0;
1524 int_to_apicintpin[x].apic_address = NULL;
1525 int_to_apicintpin[x].redirindex = 0;
1528 /* First assign ISA/EISA interrupts */
1529 for (x = 0; x < nintrs; x++) {
1530 int_vector = io_apic_ints[x].src_bus_irq;
1531 if (int_vector < APIC_INTMAPSIZE &&
1532 io_apic_ints[x].int_vector == 0xff &&
1533 int_to_apicintpin[int_vector].ioapic == -1 &&
1534 (apic_int_is_bus_type(x, ISA) ||
1535 apic_int_is_bus_type(x, EISA)) &&
1536 io_apic_ints[x].int_type == 0) {
1537 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1538 io_apic_ints[x].dst_apic_int,
1543 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1544 for (x = 0; x < nintrs; x++) {
1545 if (io_apic_ints[x].dst_apic_int == 0 &&
1546 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1547 io_apic_ints[x].int_vector == 0xff &&
1548 int_to_apicintpin[0].ioapic == -1 &&
1549 io_apic_ints[x].int_type == 3) {
1550 assign_apic_irq(0, 0, 0);
1554 /* PCI interrupt assignment is deferred */
1560 mp_set_cpuids(int cpu_id, int apic_id)
1562 CPU_TO_ID(cpu_id) = apic_id;
1563 ID_TO_CPU(apic_id) = cpu_id;
1567 processor_entry(const struct PROCENTRY *entry, int cpu)
1571 /* check for usability */
1572 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1575 /* check for BSP flag */
1576 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1577 mp_set_cpuids(0, entry->apic_id);
1578 return 0; /* its already been counted */
1581 /* add another AP to list, if less than max number of CPUs */
1582 else if (cpu < MAXCPU) {
1583 mp_set_cpuids(cpu, entry->apic_id);
1593 bus_entry(const struct BUSENTRY *entry, int bus)
1598 /* encode the name into an index */
1599 for (x = 0; x < 6; ++x) {
1600 if ((c = entry->bus_type[x]) == ' ')
1606 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1607 panic("unknown bus type: '%s'", name);
1609 bus_data[bus].bus_id = entry->bus_id;
1610 bus_data[bus].bus_type = x;
1616 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1618 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1621 IO_TO_ID(apic) = entry->apic_id;
1622 ID_TO_IO(entry->apic_id) = apic;
1630 lookup_bus_type(char *name)
1634 for (x = 0; x < MAX_BUSTYPE; ++x)
1635 if (strcmp(bus_type_table[x].name, name) == 0)
1636 return bus_type_table[x].type;
1638 return UNKNOWN_BUSTYPE;
1644 int_entry(const struct INTENTRY *entry, int intr)
1648 io_apic_ints[intr].int_type = entry->int_type;
1649 io_apic_ints[intr].int_flags = entry->int_flags;
1650 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1651 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1652 if (entry->dst_apic_id == 255) {
1653 /* This signal goes to all IO APICS. Select an IO APIC
1654 with sufficient number of interrupt pins */
1655 for (apic = 0; apic < mp_napics; apic++)
1656 if (((io_apic_read(apic, IOAPIC_VER) &
1657 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1658 entry->dst_apic_int)
1660 if (apic < mp_napics)
1661 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1663 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1665 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1666 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1672 apic_int_is_bus_type(int intr, int bus_type)
1676 for (bus = 0; bus < mp_nbusses; ++bus)
1677 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1678 && ((int) bus_data[bus].bus_type == bus_type))
1685 * Given a traditional ISA INT mask, return an APIC mask.
1688 isa_apic_mask(u_int isa_mask)
1693 #if defined(SKIP_IRQ15_REDIRECT)
1694 if (isa_mask == (1 << 15)) {
1695 kprintf("skipping ISA IRQ15 redirect\n");
1698 #endif /* SKIP_IRQ15_REDIRECT */
1700 isa_irq = ffs(isa_mask); /* find its bit position */
1701 if (isa_irq == 0) /* doesn't exist */
1703 --isa_irq; /* make it zero based */
1705 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1709 return (1 << apic_pin); /* convert pin# to a mask */
1713 * Determine which APIC pin an ISA/EISA INT is attached to.
1715 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1716 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1717 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1718 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1720 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1722 isa_apic_irq(int isa_irq)
1726 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1727 if (INTTYPE(intr) == 0) { /* standard INT */
1728 if (SRCBUSIRQ(intr) == isa_irq) {
1729 if (apic_int_is_bus_type(intr, ISA) ||
1730 apic_int_is_bus_type(intr, EISA)) {
1731 if (INTIRQ(intr) == 0xff)
1732 return -1; /* unassigned */
1733 return INTIRQ(intr); /* found */
1738 return -1; /* NOT found */
1743 * Determine which APIC pin a PCI INT is attached to.
1745 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1746 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1747 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1749 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1753 --pciInt; /* zero based */
1755 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1756 if ((INTTYPE(intr) == 0) /* standard INT */
1757 && (SRCBUSID(intr) == pciBus)
1758 && (SRCBUSDEVICE(intr) == pciDevice)
1759 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1760 if (apic_int_is_bus_type(intr, PCI)) {
1761 if (INTIRQ(intr) == 0xff)
1762 allocate_apic_irq(intr);
1763 if (INTIRQ(intr) == 0xff)
1764 return -1; /* unassigned */
1765 return INTIRQ(intr); /* exact match */
1770 return -1; /* NOT found */
1774 next_apic_irq(int irq)
1781 for (intr = 0; intr < nintrs; intr++) {
1782 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1784 bus = SRCBUSID(intr);
1785 bustype = apic_bus_type(bus);
1786 if (bustype != ISA &&
1792 if (intr >= nintrs) {
1795 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1796 if (INTTYPE(ointr) != 0)
1798 if (bus != SRCBUSID(ointr))
1800 if (bustype == PCI) {
1801 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1803 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1806 if (bustype == ISA || bustype == EISA) {
1807 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1810 if (INTPIN(intr) == INTPIN(ointr))
1814 if (ointr >= nintrs) {
1817 return INTIRQ(ointr);
1832 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1835 * Exactly what this means is unclear at this point. It is a solution
1836 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1837 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1838 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1842 undirect_isa_irq(int rirq)
1846 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1847 /** FIXME: tickle the MB redirector chip */
1851 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1858 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1861 undirect_pci_irq(int rirq)
1865 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1867 /** FIXME: tickle the MB redirector chip */
1871 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1881 * given a bus ID, return:
1882 * the bus type if found
1886 apic_bus_type(int id)
1890 for (x = 0; x < mp_nbusses; ++x)
1891 if (bus_data[x].bus_id == id)
1892 return bus_data[x].bus_type;
1898 * given a LOGICAL APIC# and pin#, return:
1899 * the associated src bus ID if found
1903 apic_src_bus_id(int apic, int pin)
1907 /* search each of the possible INTerrupt sources */
1908 for (x = 0; x < nintrs; ++x)
1909 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1910 (pin == io_apic_ints[x].dst_apic_int))
1911 return (io_apic_ints[x].src_bus_id);
1913 return -1; /* NOT found */
1917 * given a LOGICAL APIC# and pin#, return:
1918 * the associated src bus IRQ if found
1922 apic_src_bus_irq(int apic, int pin)
1926 for (x = 0; x < nintrs; x++)
1927 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1928 (pin == io_apic_ints[x].dst_apic_int))
1929 return (io_apic_ints[x].src_bus_irq);
1931 return -1; /* NOT found */
1936 * given a LOGICAL APIC# and pin#, return:
1937 * the associated INTerrupt type if found
1941 apic_int_type(int apic, int pin)
1945 /* search each of the possible INTerrupt sources */
1946 for (x = 0; x < nintrs; ++x) {
1947 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1948 (pin == io_apic_ints[x].dst_apic_int))
1949 return (io_apic_ints[x].int_type);
1951 return -1; /* NOT found */
1955 * Return the IRQ associated with an APIC pin
1958 apic_irq(int apic, int pin)
1963 for (x = 0; x < nintrs; ++x) {
1964 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1965 (pin == io_apic_ints[x].dst_apic_int)) {
1966 res = io_apic_ints[x].int_vector;
1969 if (apic != int_to_apicintpin[res].ioapic)
1970 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1971 if (pin != int_to_apicintpin[res].int_pin)
1972 panic("apic_irq inconsistent table (2)");
1981 * given a LOGICAL APIC# and pin#, return:
1982 * the associated trigger mode if found
1986 apic_trigger(int apic, int pin)
1990 /* search each of the possible INTerrupt sources */
1991 for (x = 0; x < nintrs; ++x)
1992 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1993 (pin == io_apic_ints[x].dst_apic_int))
1994 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1996 return -1; /* NOT found */
2001 * given a LOGICAL APIC# and pin#, return:
2002 * the associated 'active' level if found
2006 apic_polarity(int apic, int pin)
2010 /* search each of the possible INTerrupt sources */
2011 for (x = 0; x < nintrs; ++x)
2012 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2013 (pin == io_apic_ints[x].dst_apic_int))
2014 return (io_apic_ints[x].int_flags & 0x03);
2016 return -1; /* NOT found */
2022 * set data according to MP defaults
2023 * FIXME: probably not complete yet...
2026 mptable_default(int type)
2028 #if defined(APIC_IO)
2033 kprintf(" MP default config type: %d\n", type);
2036 kprintf(" bus: ISA, APIC: 82489DX\n");
2039 kprintf(" bus: EISA, APIC: 82489DX\n");
2042 kprintf(" bus: EISA, APIC: 82489DX\n");
2045 kprintf(" bus: MCA, APIC: 82489DX\n");
2048 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2051 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2054 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2057 kprintf(" future type\n");
2063 /* one and only IO APIC */
2064 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2067 * sanity check, refer to MP spec section 3.6.6, last paragraph
2068 * necessary as some hardware isn't properly setting up the IO APIC
2070 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2071 if (io_apic_id != 2) {
2073 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2074 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2075 io_apic_set_id(0, 2);
2078 IO_TO_ID(0) = io_apic_id;
2079 ID_TO_IO(io_apic_id) = 0;
2081 /* fill out bus entries */
2090 bus_data[0].bus_id = default_data[type - 1][1];
2091 bus_data[0].bus_type = default_data[type - 1][2];
2092 bus_data[1].bus_id = default_data[type - 1][3];
2093 bus_data[1].bus_type = default_data[type - 1][4];
2096 /* case 4: case 7: MCA NOT supported */
2097 default: /* illegal/reserved */
2098 panic("BAD default MP config: %d", type);
2102 /* general cases from MP v1.4, table 5-2 */
2103 for (pin = 0; pin < 16; ++pin) {
2104 io_apic_ints[pin].int_type = 0;
2105 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2106 io_apic_ints[pin].src_bus_id = 0;
2107 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2108 io_apic_ints[pin].dst_apic_id = io_apic_id;
2109 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2112 /* special cases from MP v1.4, table 5-2 */
2114 io_apic_ints[2].int_type = 0xff; /* N/C */
2115 io_apic_ints[13].int_type = 0xff; /* N/C */
2116 #if !defined(APIC_MIXED_MODE)
2118 panic("sorry, can't support type 2 default yet");
2119 #endif /* APIC_MIXED_MODE */
2122 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2125 io_apic_ints[0].int_type = 0xff; /* N/C */
2127 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2128 #endif /* APIC_IO */
2132 * Map a physical memory address representing I/O into KVA. The I/O
2133 * block is assumed not to cross a page boundary.
2136 permanent_io_mapping(vm_paddr_t pa)
2142 KKASSERT(pa < 0x100000000LL);
2144 pgeflag = 0; /* not used for SMP yet */
2147 * If the requested physical address has already been incidently
2148 * mapped, just use the existing mapping. Otherwise create a new
2151 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2152 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2153 ((vm_offset_t)pa & PG_FRAME)) {
2157 if (i == SMPpt_alloc_index) {
2158 if (i == NPTEPG - 2) {
2159 panic("permanent_io_mapping: We ran out of space"
2162 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2163 ((vm_offset_t)pa & PG_FRAME));
2164 ++SMPpt_alloc_index;
2166 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2167 ((vm_offset_t)pa & PAGE_MASK);
2168 return ((void *)vaddr);
2172 * start each AP in our list
2175 start_all_aps(u_int boot_addr)
2179 u_char mpbiosreason;
2180 u_long mpbioswarmvec;
2181 struct mdglobaldata *gd;
2182 struct privatespace *ps;
2186 POSTCODE(START_ALL_APS_POST);
2188 /* Initialize BSP's local APIC */
2189 apic_initialize(TRUE);
2191 /* install the AP 1st level boot code */
2192 install_ap_tramp(boot_addr);
2195 /* save the current value of the warm-start vector */
2196 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2197 outb(CMOS_REG, BIOS_RESET);
2198 mpbiosreason = inb(CMOS_DATA);
2200 /* set up temporary P==V mapping for AP boot */
2201 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2202 kptbase = (uintptr_t)(void *)KPTphys;
2203 for (x = 0; x < NKPT; x++) {
2204 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2205 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2210 for (x = 1; x <= mp_naps; ++x) {
2212 /* This is a bit verbose, it will go away soon. */
2214 /* first page of AP's private space */
2215 pg = x * i386_btop(sizeof(struct privatespace));
2217 /* allocate new private data page(s) */
2218 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2219 MDGLOBALDATA_BASEALLOC_SIZE);
2220 /* wire it into the private page table page */
2221 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2222 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2223 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2225 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2227 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2228 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2229 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2230 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2232 /* allocate and set up an idle stack data page */
2233 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2234 for (i = 0; i < UPAGES; i++) {
2235 SMPpt[pg + 4 + i] = (pt_entry_t)
2236 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2239 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2240 bzero(gd, sizeof(*gd));
2241 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2243 /* prime data page for it to use */
2244 mi_gdinit(&gd->mi, x);
2246 gd->gd_CMAP1 = &SMPpt[pg + 0];
2247 gd->gd_CMAP2 = &SMPpt[pg + 1];
2248 gd->gd_CMAP3 = &SMPpt[pg + 2];
2249 gd->gd_PMAP1 = &SMPpt[pg + 3];
2250 gd->gd_CADDR1 = ps->CPAGE1;
2251 gd->gd_CADDR2 = ps->CPAGE2;
2252 gd->gd_CADDR3 = ps->CPAGE3;
2253 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2254 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2255 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2257 /* setup a vector to our boot code */
2258 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2259 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2260 outb(CMOS_REG, BIOS_RESET);
2261 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2264 * Setup the AP boot stack
2266 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2269 /* attempt to start the Application Processor */
2270 CHECK_INIT(99); /* setup checkpoints */
2271 if (!start_ap(gd, boot_addr)) {
2272 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2273 CHECK_PRINT("trace"); /* show checkpoints */
2274 /* better panic as the AP may be running loose */
2275 kprintf("panic y/n? [y] ");
2276 if (cngetc() != 'n')
2279 CHECK_PRINT("trace"); /* show checkpoints */
2281 /* record its version info */
2282 cpu_apic_versions[x] = cpu_apic_versions[0];
2285 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2288 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2289 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2292 ncpus2_shift = shift;
2293 ncpus2 = 1 << shift;
2294 ncpus2_mask = ncpus2 - 1;
2296 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2297 if ((1 << shift) < ncpus)
2299 ncpus_fit = 1 << shift;
2300 ncpus_fit_mask = ncpus_fit - 1;
2302 /* build our map of 'other' CPUs */
2303 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2304 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2305 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2307 /* fill in our (BSP) APIC version */
2308 cpu_apic_versions[0] = lapic.version;
2310 /* restore the warmstart vector */
2311 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2312 outb(CMOS_REG, BIOS_RESET);
2313 outb(CMOS_DATA, mpbiosreason);
2316 * NOTE! The idlestack for the BSP was setup by locore. Finish
2317 * up, clean out the P==V mapping we did earlier.
2319 for (x = 0; x < NKPT; x++)
2323 /* number of APs actually started */
2329 * load the 1st level AP boot code into base memory.
2332 /* targets for relocation */
2333 extern void bigJump(void);
2334 extern void bootCodeSeg(void);
2335 extern void bootDataSeg(void);
2336 extern void MPentry(void);
2337 extern u_int MP_GDT;
2338 extern u_int mp_gdtbase;
2341 install_ap_tramp(u_int boot_addr)
2344 int size = *(int *) ((u_long) & bootMP_size);
2345 u_char *src = (u_char *) ((u_long) bootMP);
2346 u_char *dst = (u_char *) boot_addr + KERNBASE;
2347 u_int boot_base = (u_int) bootMP;
2352 POSTCODE(INSTALL_AP_TRAMP_POST);
2354 for (x = 0; x < size; ++x)
2358 * modify addresses in code we just moved to basemem. unfortunately we
2359 * need fairly detailed info about mpboot.s for this to work. changes
2360 * to mpboot.s might require changes here.
2363 /* boot code is located in KERNEL space */
2364 dst = (u_char *) boot_addr + KERNBASE;
2366 /* modify the lgdt arg */
2367 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2368 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2370 /* modify the ljmp target for MPentry() */
2371 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2372 *dst32 = ((u_int) MPentry - KERNBASE);
2374 /* modify the target for boot code segment */
2375 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2376 dst8 = (u_int8_t *) (dst16 + 1);
2377 *dst16 = (u_int) boot_addr & 0xffff;
2378 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2380 /* modify the target for boot data segment */
2381 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2382 dst8 = (u_int8_t *) (dst16 + 1);
2383 *dst16 = (u_int) boot_addr & 0xffff;
2384 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2389 * this function starts the AP (application processor) identified
2390 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2391 * to accomplish this. This is necessary because of the nuances
2392 * of the different hardware we might encounter. It ain't pretty,
2393 * but it seems to work.
2395 * NOTE: eventually an AP gets to ap_init(), which is called just
2396 * before the AP goes into the LWKT scheduler's idle loop.
2399 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2403 u_long icr_lo, icr_hi;
2405 POSTCODE(START_AP_POST);
2407 /* get the PHYSICAL APIC ID# */
2408 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2410 /* calculate the vector */
2411 vector = (boot_addr >> 12) & 0xff;
2413 /* Make sure the target cpu sees everything */
2417 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2418 * and running the target CPU. OR this INIT IPI might be latched (P5
2419 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2423 /* setup the address for the target AP */
2424 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2425 icr_hi |= (physical_cpu << 24);
2426 lapic.icr_hi = icr_hi;
2428 /* do an INIT IPI: assert RESET */
2429 icr_lo = lapic.icr_lo & 0xfff00000;
2430 lapic.icr_lo = icr_lo | 0x0000c500;
2432 /* wait for pending status end */
2433 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2436 /* do an INIT IPI: deassert RESET */
2437 lapic.icr_lo = icr_lo | 0x00008500;
2439 /* wait for pending status end */
2440 u_sleep(10000); /* wait ~10mS */
2441 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2445 * next we do a STARTUP IPI: the previous INIT IPI might still be
2446 * latched, (P5 bug) this 1st STARTUP would then terminate
2447 * immediately, and the previously started INIT IPI would continue. OR
2448 * the previous INIT IPI has already run. and this STARTUP IPI will
2449 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2453 /* do a STARTUP IPI */
2454 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2455 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2457 u_sleep(200); /* wait ~200uS */
2460 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2461 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2462 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2463 * recognized after hardware RESET or INIT IPI.
2466 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2467 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2469 u_sleep(200); /* wait ~200uS */
2471 /* wait for it to start, see ap_init() */
2472 set_apic_timer(5000000);/* == 5 seconds */
2473 while (read_apic_timer()) {
2474 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2475 return 1; /* return SUCCESS */
2477 return 0; /* return FAILURE */
2482 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2484 * If for some reason we were unable to start all cpus we cannot safely
2485 * use broadcast IPIs.
2491 if (smp_startup_mask == smp_active_mask) {
2492 all_but_self_ipi(XINVLTLB_OFFSET);
2494 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2495 APIC_DELMODE_FIXED);
2501 * When called the executing CPU will send an IPI to all other CPUs
2502 * requesting that they halt execution.
2504 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2506 * - Signals all CPUs in map to stop.
2507 * - Waits for each to stop.
2514 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2515 * from executing at same time.
2518 stop_cpus(u_int map)
2520 map &= smp_active_mask;
2522 /* send the Xcpustop IPI to all CPUs in map */
2523 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2525 while ((stopped_cpus & map) != map)
2533 * Called by a CPU to restart stopped CPUs.
2535 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2537 * - Signals all CPUs in map to restart.
2538 * - Waits for each to restart.
2546 restart_cpus(u_int map)
2548 /* signal other cpus to restart */
2549 started_cpus = map & smp_active_mask;
2551 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2558 * This is called once the mpboot code has gotten us properly relocated
2559 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2560 * and when it returns the scheduler will call the real cpu_idle() main
2561 * loop for the idlethread. Interrupts are disabled on entry and should
2562 * remain disabled at return.
2570 * Adjust smp_startup_mask to signal the BSP that we have started
2571 * up successfully. Note that we do not yet hold the BGL. The BSP
2572 * is waiting for our signal.
2574 * We can't set our bit in smp_active_mask yet because we are holding
2575 * interrupts physically disabled and remote cpus could deadlock
2576 * trying to send us an IPI.
2578 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2582 * Interlock for finalization. Wait until mp_finish is non-zero,
2583 * then get the MP lock.
2585 * Note: We are in a critical section.
2587 * Note: We have to synchronize td_mpcount to our desired MP state
2588 * before calling cpu_try_mplock().
2590 * Note: we are the idle thread, we can only spin.
2592 * Note: The load fence is memory volatile and prevents the compiler
2593 * from improperly caching mp_finish, and the cpu from improperly
2596 while (mp_finish == 0)
2598 ++curthread->td_mpcount;
2599 while (cpu_try_mplock() == 0)
2602 if (cpu_feature & CPUID_TSC) {
2604 * The BSP is constantly updating tsc0_offset, figure out the
2605 * relative difference to synchronize ktrdump.
2607 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2610 /* BSP may have changed PTD while we're waiting for the lock */
2613 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2617 /* Build our map of 'other' CPUs. */
2618 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2620 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2622 /* A quick check from sanity claus */
2623 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2624 if (mycpu->gd_cpuid != apic_id) {
2625 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2626 kprintf("SMP: apic_id = %d\n", apic_id);
2627 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2628 panic("cpuid mismatch! boom!!");
2631 /* Initialize AP's local APIC for irq's */
2632 apic_initialize(FALSE);
2634 /* Set memory range attributes for this CPU to match the BSP */
2635 mem_range_AP_init();
2638 * Once we go active we must process any IPIQ messages that may
2639 * have been queued, because no actual IPI will occur until we
2640 * set our bit in the smp_active_mask. If we don't the IPI
2641 * message interlock could be left set which would also prevent
2644 * The idle loop doesn't expect the BGL to be held and while
2645 * lwkt_switch() normally cleans things up this is a special case
2646 * because we returning almost directly into the idle loop.
2648 * The idle thread is never placed on the runq, make sure
2649 * nothing we've done put it there.
2651 KKASSERT(curthread->td_mpcount == 1);
2652 smp_active_mask |= 1 << mycpu->gd_cpuid;
2655 * Enable interrupts here. idle_restore will also do it, but
2656 * doing it here lets us clean up any strays that got posted to
2657 * the CPU during the AP boot while we are still in a critical
2660 __asm __volatile("sti; pause; pause"::);
2661 mdcpu->gd_fpending = 0;
2662 mdcpu->gd_ipending = 0;
2664 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2665 lwkt_process_ipiq();
2668 * Releasing the mp lock lets the BSP finish up the SMP init
2671 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2675 * Get SMP fully working before we start initializing devices.
2683 kprintf("Finish MP startup\n");
2684 if (cpu_feature & CPUID_TSC)
2685 tsc0_offset = rdtsc();
2688 while (smp_active_mask != smp_startup_mask) {
2690 if (cpu_feature & CPUID_TSC)
2691 tsc0_offset = rdtsc();
2693 while (try_mplock() == 0)
2696 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2699 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2702 cpu_send_ipiq(int dcpu)
2704 if ((1 << dcpu) & smp_active_mask)
2705 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2708 #if 0 /* single_apic_ipi_passive() not working yet */
2710 * Returns 0 on failure, 1 on success
2713 cpu_send_ipiq_passive(int dcpu)
2716 if ((1 << dcpu) & smp_active_mask) {
2717 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2718 APIC_DELMODE_FIXED);
2724 struct mptable_lapic_cbarg1 {
2727 u_int ht_apicid_mask;
2731 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2733 const struct PROCENTRY *ent;
2734 struct mptable_lapic_cbarg1 *arg = xarg;
2740 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2744 if (ent->apic_id < 32) {
2745 arg->ht_apicid_mask |= 1 << ent->apic_id;
2746 } else if (arg->ht_fixup) {
2747 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2753 struct mptable_lapic_cbarg2 {
2760 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2762 const struct PROCENTRY *ent;
2763 struct mptable_lapic_cbarg2 *arg = xarg;
2769 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2770 KKASSERT(!arg->found_bsp);
2774 if (processor_entry(ent, arg->cpu))
2777 if (arg->logical_cpus) {
2778 struct PROCENTRY proc;
2782 * Create fake mptable processor entries
2783 * and feed them to processor_entry() to
2784 * enumerate the logical CPUs.
2786 bzero(&proc, sizeof(proc));
2788 proc.cpu_flags = PROCENTRY_FLAG_EN;
2789 proc.apic_id = ent->apic_id;
2791 for (i = 1; i < arg->logical_cpus; i++) {
2793 processor_entry(&proc, arg->cpu);
2801 mptable_imcr(struct mptable_pos *mpt)
2803 /* record whether PIC or virtual-wire mode */
2804 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2805 mpt->mp_fps->mpfb2 & 0x80);
2808 struct mptable_lapic_enumerator {
2809 struct lapic_enumerator enumerator;
2810 vm_paddr_t mpfps_paddr;
2814 mptable_lapic_default(void)
2816 int ap_apicid, bsp_apicid;
2818 mp_naps = 1; /* exclude BSP */
2820 /* Map local apic before the id field is accessed */
2821 lapic_init(DEFAULT_APIC_BASE);
2823 bsp_apicid = APIC_ID(lapic.id);
2824 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2827 mp_set_cpuids(0, bsp_apicid);
2828 /* one and only AP */
2829 mp_set_cpuids(1, ap_apicid);
2835 * ID_TO_CPU(N), APIC ID to logical CPU table
2836 * CPU_TO_ID(N), logical CPU to APIC ID table
2839 mptable_lapic_enumerate(struct lapic_enumerator *e)
2841 struct mptable_pos mpt;
2842 struct mptable_lapic_cbarg1 arg1;
2843 struct mptable_lapic_cbarg2 arg2;
2845 int error, logical_cpus = 0;
2846 vm_offset_t lapic_addr;
2847 vm_paddr_t mpfps_paddr;
2849 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
2850 KKASSERT(mpfps_paddr != 0);
2852 error = mptable_map(&mpt, mpfps_paddr);
2854 panic("mptable_lapic_enumerate mptable_map failed\n");
2856 KKASSERT(mpt.mp_fps != NULL);
2859 * Check for use of 'default' configuration
2861 if (mpt.mp_fps->mpfb1 != 0) {
2862 mptable_lapic_default();
2863 mptable_unmap(&mpt);
2868 KKASSERT(cth != NULL);
2870 /* Save local apic address */
2871 lapic_addr = (vm_offset_t)cth->apic_address;
2872 KKASSERT(lapic_addr != 0);
2875 * Find out how many CPUs do we have
2877 bzero(&arg1, sizeof(arg1));
2878 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2880 error = mptable_iterate_entries(cth,
2881 mptable_lapic_pass1_callback, &arg1);
2883 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2884 KKASSERT(arg1.cpu_count != 0);
2886 /* See if we need to fixup HT logical CPUs. */
2887 if (arg1.ht_fixup) {
2888 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2890 if (logical_cpus != 0)
2891 arg1.cpu_count *= logical_cpus;
2893 mp_naps = arg1.cpu_count;
2895 /* Qualify the numbers again, after possible HT fixup */
2896 if (mp_naps > MAXCPU) {
2897 kprintf("Warning: only using %d of %d available CPUs!\n",
2902 --mp_naps; /* subtract the BSP */
2905 * Link logical CPU id to local apic id
2907 bzero(&arg2, sizeof(arg2));
2909 arg2.logical_cpus = logical_cpus;
2911 error = mptable_iterate_entries(cth,
2912 mptable_lapic_pass2_callback, &arg2);
2914 panic("mptable_iterate_entries(lapic_pass2) failed\n");
2915 KKASSERT(arg2.found_bsp);
2917 /* Map local apic */
2918 lapic_init(lapic_addr);
2920 mptable_unmap(&mpt);
2924 mptable_lapic_probe(struct lapic_enumerator *e)
2926 vm_paddr_t mpfps_paddr;
2928 mpfps_paddr = mptable_probe();
2929 if (mpfps_paddr == 0)
2932 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
2936 static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
2938 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
2939 .lapic_probe = mptable_lapic_probe,
2940 .lapic_enumerate = mptable_lapic_enumerate
2945 mptable_apic_register(void)
2947 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
2949 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);