bce: Rework MSI checkout for 5706 and 5708
[dragonfly.git] / sys / dev / netif / bce / if_bce.c
1 /*-
2  * Copyright (c) 2006-2007 Broadcom Corporation
3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15  *    may be used to endorse or promote products derived from this software
16  *    without specific prior written consent.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28  * THE POSSIBILITY OF SUCH DAMAGE.
29  *
30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
31  */
32
33 /*
34  * The following controllers are supported by this driver:
35  *   BCM5706C A2, A3
36  *   BCM5706S A2, A3
37  *   BCM5708C B1, B2
38  *   BCM5708S B1, B2
39  *   BCM5709C A1, C0
40  *   BCM5716  C0
41  *
42  * The following controllers are not supported by this driver:
43  *   BCM5706C A0, A1
44  *   BCM5706S A0, A1
45  *   BCM5708C A0, B0
46  *   BCM5708S A0, B0
47  *   BCM5709C A0, B0, B1
48  *   BCM5709S A0, A1, B0, B1, B2, C0
49  */
50
51 #include "opt_bce.h"
52 #include "opt_polling.h"
53
54 #include <sys/param.h>
55 #include <sys/bus.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
59 #include <sys/mbuf.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
62 #ifdef BCE_DEBUG
63 #include <sys/random.h>
64 #endif
65 #include <sys/rman.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
70
71 #include <netinet/ip.h>
72 #include <netinet/tcp.h>
73
74 #include <net/bpf.h>
75 #include <net/ethernet.h>
76 #include <net/if.h>
77 #include <net/if_arp.h>
78 #include <net/if_dl.h>
79 #include <net/if_media.h>
80 #include <net/if_types.h>
81 #include <net/ifq_var.h>
82 #include <net/vlan/if_vlan_var.h>
83 #include <net/vlan/if_vlan_ether.h>
84
85 #include <dev/netif/mii_layer/mii.h>
86 #include <dev/netif/mii_layer/miivar.h>
87 #include <dev/netif/mii_layer/brgphyreg.h>
88
89 #include <bus/pci/pcireg.h>
90 #include <bus/pci/pcivar.h>
91
92 #include "miibus_if.h"
93
94 #include <dev/netif/bce/if_bcereg.h>
95 #include <dev/netif/bce/if_bcefw.h>
96
97 #define BCE_MSI_CKINTVL         ((10 * hz) / 1000)      /* 10ms */
98
99 /****************************************************************************/
100 /* BCE Debug Options                                                        */
101 /****************************************************************************/
102 #ifdef BCE_DEBUG
103
104 static uint32_t bce_debug = BCE_WARN;
105
106 /*
107  *          0 = Never             
108  *          1 = 1 in 2,147,483,648
109  *        256 = 1 in     8,388,608
110  *       2048 = 1 in     1,048,576
111  *      65536 = 1 in        32,768
112  *    1048576 = 1 in         2,048
113  *  268435456 = 1 in             8
114  *  536870912 = 1 in             4
115  * 1073741824 = 1 in             2
116  *
117  * bce_debug_mbuf_allocation_failure:
118  *     How often to simulate an mbuf allocation failure.
119  *
120  * bce_debug_dma_map_addr_failure:
121  *     How often to simulate a DMA mapping failure.
122  *
123  * bce_debug_bootcode_running_failure:
124  *     How often to simulate a bootcode failure.
125  */
126 static int      bce_debug_mbuf_allocation_failure = 0;
127 static int      bce_debug_dma_map_addr_failure = 0;
128 static int      bce_debug_bootcode_running_failure = 0;
129
130 #endif  /* BCE_DEBUG */
131
132
133 /****************************************************************************/
134 /* PCI Device ID Table                                                      */
135 /*                                                                          */
136 /* Used by bce_probe() to identify the devices supported by this driver.    */
137 /****************************************************************************/
138 #define BCE_DEVDESC_MAX         64
139
140 static struct bce_type bce_devs[] = {
141         /* BCM5706C Controllers and OEM boards. */
142         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
143                 "HP NC370T Multifunction Gigabit Server Adapter" },
144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
145                 "HP NC370i Multifunction Gigabit Server Adapter" },
146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
147                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
149                 "HP NC371i Multifunction Gigabit Server Adapter" },
150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
151                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
152
153         /* BCM5706S controllers and OEM boards. */
154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
155                 "HP NC370F Multifunction Gigabit Server Adapter" },
156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
157                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
158
159         /* BCM5708C controllers and OEM boards. */
160         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
161                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
162         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
163                 "HP NC373i Multifunction Gigabit Server Adapter" },
164         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
165                 "HP NC374m PCIe Multifunction Adapter" },
166         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
167                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
168
169         /* BCM5708S controllers and OEM boards. */
170         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
171                 "HP NC373m Multifunction Gigabit Server Adapter" },
172         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
173                 "HP NC373i Multifunction Gigabit Server Adapter" },
174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
175                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
176         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
177                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
178
179         /* BCM5709C controllers and OEM boards. */
180         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
181                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
182         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
183                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
184         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
185                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
186
187         /* BCM5709S controllers and OEM boards. */
188         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
189                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
190         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
191                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
192         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
193                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
194
195         /* BCM5716 controllers and OEM boards. */
196         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
197                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
198
199         { 0, 0, 0, 0, NULL }
200 };
201
202
203 /****************************************************************************/
204 /* Supported Flash NVRAM device data.                                       */
205 /****************************************************************************/
206 static const struct flash_spec flash_table[] =
207 {
208 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
209 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
210
211         /* Slow EEPROM */
212         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
213          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
214          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
215          "EEPROM - slow"},
216         /* Expansion entry 0001 */
217         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
218          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
219          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
220          "Entry 0001"},
221         /* Saifun SA25F010 (non-buffered flash) */
222         /* strap, cfg1, & write1 need updates */
223         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
224          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
225          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
226          "Non-buffered flash (128kB)"},
227         /* Saifun SA25F020 (non-buffered flash) */
228         /* strap, cfg1, & write1 need updates */
229         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
230          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
231          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
232          "Non-buffered flash (256kB)"},
233         /* Expansion entry 0100 */
234         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
235          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
236          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
237          "Entry 0100"},
238         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
239         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
240          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
241          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
242          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
243         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
244         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
245          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
246          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
247          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
248         /* Saifun SA25F005 (non-buffered flash) */
249         /* strap, cfg1, & write1 need updates */
250         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
251          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
252          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
253          "Non-buffered flash (64kB)"},
254         /* Fast EEPROM */
255         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
256          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
257          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
258          "EEPROM - fast"},
259         /* Expansion entry 1001 */
260         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
261          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
262          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
263          "Entry 1001"},
264         /* Expansion entry 1010 */
265         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
266          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
267          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
268          "Entry 1010"},
269         /* ATMEL AT45DB011B (buffered flash) */
270         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
271          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
272          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
273          "Buffered flash (128kB)"},
274         /* Expansion entry 1100 */
275         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
276          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
277          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
278          "Entry 1100"},
279         /* Expansion entry 1101 */
280         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
281          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
282          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
283          "Entry 1101"},
284         /* Ateml Expansion entry 1110 */
285         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
286          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
287          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
288          "Entry 1110 (Atmel)"},
289         /* ATMEL AT45DB021B (buffered flash) */
290         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
291          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
292          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
293          "Buffered flash (256kB)"},
294 };
295
296 /*
297  * The BCM5709 controllers transparently handle the
298  * differences between Atmel 264 byte pages and all
299  * flash devices which use 256 byte pages, so no
300  * logical-to-physical mapping is required in the
301  * driver.
302  */
303 static struct flash_spec flash_5709 = {
304         .flags          = BCE_NV_BUFFERED,
305         .page_bits      = BCM5709_FLASH_PAGE_BITS,
306         .page_size      = BCM5709_FLASH_PAGE_SIZE,
307         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
308         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
309         .name           = "5709/5716 buffered flash (256kB)",
310 };
311
312
313 /****************************************************************************/
314 /* DragonFly device entry points.                                           */
315 /****************************************************************************/
316 static int      bce_probe(device_t);
317 static int      bce_attach(device_t);
318 static int      bce_detach(device_t);
319 static void     bce_shutdown(device_t);
320
321 /****************************************************************************/
322 /* BCE Debug Data Structure Dump Routines                                   */
323 /****************************************************************************/
324 #ifdef BCE_DEBUG
325 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
326 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
327 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
328 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
329 static void     bce_dump_l2fhdr(struct bce_softc *, int,
330                                 struct l2_fhdr *) __unused;
331 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
332 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
333 static void     bce_dump_status_block(struct bce_softc *);
334 static void     bce_dump_driver_state(struct bce_softc *);
335 static void     bce_dump_stats_block(struct bce_softc *) __unused;
336 static void     bce_dump_hw_state(struct bce_softc *);
337 static void     bce_dump_txp_state(struct bce_softc *);
338 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
339 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
340 static void     bce_freeze_controller(struct bce_softc *) __unused;
341 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
342 static void     bce_breakpoint(struct bce_softc *);
343 #endif  /* BCE_DEBUG */
344
345
346 /****************************************************************************/
347 /* BCE Register/Memory Access Routines                                      */
348 /****************************************************************************/
349 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
350 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
351 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
352 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
353 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
354 static int      bce_miibus_read_reg(device_t, int, int);
355 static int      bce_miibus_write_reg(device_t, int, int, int);
356 static void     bce_miibus_statchg(device_t);
357
358
359 /****************************************************************************/
360 /* BCE NVRAM Access Routines                                                */
361 /****************************************************************************/
362 static int      bce_acquire_nvram_lock(struct bce_softc *);
363 static int      bce_release_nvram_lock(struct bce_softc *);
364 static void     bce_enable_nvram_access(struct bce_softc *);
365 static void     bce_disable_nvram_access(struct bce_softc *);
366 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
367                                      uint32_t);
368 static int      bce_init_nvram(struct bce_softc *);
369 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
370 static int      bce_nvram_test(struct bce_softc *);
371
372 /****************************************************************************/
373 /* BCE DMA Allocate/Free Routines                                           */
374 /****************************************************************************/
375 static int      bce_dma_alloc(struct bce_softc *);
376 static void     bce_dma_free(struct bce_softc *);
377 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
378
379 /****************************************************************************/
380 /* BCE Firmware Synchronization and Load                                    */
381 /****************************************************************************/
382 static int      bce_fw_sync(struct bce_softc *, uint32_t);
383 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
384                                  uint32_t, uint32_t);
385 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
386                                 struct fw_info *);
387 static void     bce_start_cpu(struct bce_softc *, struct cpu_reg *);
388 static void     bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
389 static void     bce_start_rxp_cpu(struct bce_softc *);
390 static void     bce_init_rxp_cpu(struct bce_softc *);
391 static void     bce_init_txp_cpu(struct bce_softc *);
392 static void     bce_init_tpat_cpu(struct bce_softc *);
393 static void     bce_init_cp_cpu(struct bce_softc *);
394 static void     bce_init_com_cpu(struct bce_softc *);
395 static void     bce_init_cpus(struct bce_softc *);
396
397 static void     bce_stop(struct bce_softc *);
398 static int      bce_reset(struct bce_softc *, uint32_t);
399 static int      bce_chipinit(struct bce_softc *);
400 static int      bce_blockinit(struct bce_softc *);
401 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
402                                uint32_t *, int);
403 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
404 static void     bce_probe_pci_caps(struct bce_softc *);
405 static void     bce_print_adapter_info(struct bce_softc *);
406 static void     bce_get_media(struct bce_softc *);
407
408 static void     bce_init_tx_context(struct bce_softc *);
409 static int      bce_init_tx_chain(struct bce_softc *);
410 static void     bce_init_rx_context(struct bce_softc *);
411 static int      bce_init_rx_chain(struct bce_softc *);
412 static void     bce_free_rx_chain(struct bce_softc *);
413 static void     bce_free_tx_chain(struct bce_softc *);
414
415 static int      bce_encap(struct bce_softc *, struct mbuf **);
416 static int      bce_tso_setup(struct bce_softc *, struct mbuf **,
417                     uint16_t *, uint16_t *);
418 static void     bce_start(struct ifnet *);
419 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
420 static void     bce_watchdog(struct ifnet *);
421 static int      bce_ifmedia_upd(struct ifnet *);
422 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
423 static void     bce_init(void *);
424 static void     bce_mgmt_init(struct bce_softc *);
425
426 static int      bce_init_ctx(struct bce_softc *);
427 static void     bce_get_mac_addr(struct bce_softc *);
428 static void     bce_set_mac_addr(struct bce_softc *);
429 static void     bce_phy_intr(struct bce_softc *);
430 static void     bce_rx_intr(struct bce_softc *, int, uint16_t);
431 static void     bce_tx_intr(struct bce_softc *, uint16_t);
432 static void     bce_disable_intr(struct bce_softc *);
433 static void     bce_enable_intr(struct bce_softc *);
434 static void     bce_reenable_intr(struct bce_softc *);
435
436 #ifdef DEVICE_POLLING
437 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
438 #endif
439 static void     bce_intr(struct bce_softc *);
440 static void     bce_intr_legacy(void *);
441 static void     bce_intr_msi(void *);
442 static void     bce_intr_msi_oneshot(void *);
443 static void     bce_set_rx_mode(struct bce_softc *);
444 static void     bce_stats_update(struct bce_softc *);
445 static void     bce_tick(void *);
446 static void     bce_tick_serialized(struct bce_softc *);
447 static void     bce_pulse(void *);
448 static void     bce_check_msi(void *);
449 static void     bce_add_sysctls(struct bce_softc *);
450
451 static void     bce_coal_change(struct bce_softc *);
452 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
453 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
454 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
455 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
456 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
457 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
458 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
459 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
460 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
461                                        uint32_t *, uint32_t);
462
463 /*
464  * NOTE:
465  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
466  * takes 1023 as the TX ticks limit.  However, using 1023 will
467  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
468  * there is _no_ network activity on the NIC.
469  */
470 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
471 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
472 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
473 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
474 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
475 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
476 static uint32_t bce_rx_ticks_int = 150;         /* bcm: 18 */
477 static uint32_t bce_rx_ticks = 150;             /* bcm: 18 */
478
479 static int      bce_msi_enable = 1;
480
481 static int      bce_rx_pages = RX_PAGES_DEFAULT;
482 static int      bce_tx_pages = TX_PAGES_DEFAULT;
483
484 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
485 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
486 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
487 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
488 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
489 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
490 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
491 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
492 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
493 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
494 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
495
496 /****************************************************************************/
497 /* DragonFly device dispatch table.                                         */
498 /****************************************************************************/
499 static device_method_t bce_methods[] = {
500         /* Device interface */
501         DEVMETHOD(device_probe,         bce_probe),
502         DEVMETHOD(device_attach,        bce_attach),
503         DEVMETHOD(device_detach,        bce_detach),
504         DEVMETHOD(device_shutdown,      bce_shutdown),
505
506         /* bus interface */
507         DEVMETHOD(bus_print_child,      bus_generic_print_child),
508         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
509
510         /* MII interface */
511         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
512         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
513         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
514
515         { 0, 0 }
516 };
517
518 static driver_t bce_driver = {
519         "bce",
520         bce_methods,
521         sizeof(struct bce_softc)
522 };
523
524 static devclass_t bce_devclass;
525
526
527 DECLARE_DUMMY_MODULE(if_bce);
528 MODULE_DEPEND(bce, miibus, 1, 1, 1);
529 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
530 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
531
532
533 /****************************************************************************/
534 /* Device probe function.                                                   */
535 /*                                                                          */
536 /* Compares the device to the driver's list of supported devices and        */
537 /* reports back to the OS whether this is the right driver for the device.  */
538 /*                                                                          */
539 /* Returns:                                                                 */
540 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
541 /****************************************************************************/
542 static int
543 bce_probe(device_t dev)
544 {
545         struct bce_type *t;
546         uint16_t vid, did, svid, sdid;
547
548         /* Get the data for the device to be probed. */
549         vid  = pci_get_vendor(dev);
550         did  = pci_get_device(dev);
551         svid = pci_get_subvendor(dev);
552         sdid = pci_get_subdevice(dev);
553
554         /* Look through the list of known devices for a match. */
555         for (t = bce_devs; t->bce_name != NULL; ++t) {
556                 if (vid == t->bce_vid && did == t->bce_did && 
557                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
558                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
559                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
560                         char *descbuf;
561
562                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
563
564                         /* Print out the device identity. */
565                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
566                                   t->bce_name,
567                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
568
569                         device_set_desc_copy(dev, descbuf);
570                         kfree(descbuf, M_TEMP);
571                         return 0;
572                 }
573         }
574         return ENXIO;
575 }
576
577
578 /****************************************************************************/
579 /* PCI Capabilities Probe Function.                                         */
580 /*                                                                          */
581 /* Walks the PCI capabiites list for the device to find what features are   */
582 /* supported.                                                               */
583 /*                                                                          */
584 /* Returns:                                                                 */
585 /*   None.                                                                  */
586 /****************************************************************************/
587 static void
588 bce_print_adapter_info(struct bce_softc *sc)
589 {
590         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
591
592         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
593                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
594
595         /* Bus info. */
596         if (sc->bce_flags & BCE_PCIE_FLAG) {
597                 kprintf("Bus (PCIe x%d, ", sc->link_width);
598                 switch (sc->link_speed) {
599                 case 1:
600                         kprintf("2.5Gbps); ");
601                         break;
602                 case 2:
603                         kprintf("5Gbps); ");
604                         break;
605                 default:
606                         kprintf("Unknown link speed); ");
607                         break;
608                 }
609         } else {
610                 kprintf("Bus (PCI%s, %s, %dMHz); ",
611                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
612                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
613                     sc->bus_speed_mhz);
614         }
615
616         /* Firmware version and device features. */
617         kprintf("B/C (%s)", sc->bce_bc_ver);
618
619         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
620             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
621                 kprintf("; Flags(");
622                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
623                         kprintf("MFW[%s]", sc->bce_mfw_ver);
624                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
625                         kprintf(" 2.5G");
626                 kprintf(")");
627         }
628         kprintf("\n");
629 }
630
631
632 /****************************************************************************/
633 /* PCI Capabilities Probe Function.                                         */
634 /*                                                                          */
635 /* Walks the PCI capabiites list for the device to find what features are   */
636 /* supported.                                                               */
637 /*                                                                          */
638 /* Returns:                                                                 */
639 /*   None.                                                                  */
640 /****************************************************************************/
641 static void
642 bce_probe_pci_caps(struct bce_softc *sc)
643 {
644         device_t dev = sc->bce_dev;
645         uint8_t ptr;
646
647         if (pci_is_pcix(dev))
648                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
649
650         ptr = pci_get_pciecap_ptr(dev);
651         if (ptr) {
652                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
653
654                 sc->link_speed = link_status & 0xf;
655                 sc->link_width = (link_status >> 4) & 0x3f;
656                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
657                 sc->bce_flags |= BCE_PCIE_FLAG;
658         }
659 }
660
661
662 /****************************************************************************/
663 /* Device attach function.                                                  */
664 /*                                                                          */
665 /* Allocates device resources, performs secondary chip identification,      */
666 /* resets and initializes the hardware, and initializes driver instance     */
667 /* variables.                                                               */
668 /*                                                                          */
669 /* Returns:                                                                 */
670 /*   0 on success, positive value on failure.                               */
671 /****************************************************************************/
672 static int
673 bce_attach(device_t dev)
674 {
675         struct bce_softc *sc = device_get_softc(dev);
676         struct ifnet *ifp = &sc->arpcom.ac_if;
677         uint32_t val;
678         u_int irq_flags;
679         void (*irq_handle)(void *);
680         int rid, rc = 0;
681         int i, j;
682         struct mii_probe_args mii_args;
683         uintptr_t mii_priv = 0;
684
685         sc->bce_dev = dev;
686         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
687
688         pci_enable_busmaster(dev);
689
690         bce_probe_pci_caps(sc);
691
692         /* Allocate PCI memory resources. */
693         rid = PCIR_BAR(0);
694         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
695                                                  RF_ACTIVE | PCI_RF_DENSE);
696         if (sc->bce_res_mem == NULL) {
697                 device_printf(dev, "PCI memory allocation failed\n");
698                 return ENXIO;
699         }
700         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
701         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
702
703         /* Allocate PCI IRQ resources. */
704         sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
705             &sc->bce_irq_rid, &irq_flags);
706
707         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
708             &sc->bce_irq_rid, irq_flags);
709         if (sc->bce_res_irq == NULL) {
710                 device_printf(dev, "PCI map interrupt failed\n");
711                 rc = ENXIO;
712                 goto fail;
713         }
714
715         /*
716          * Configure byte swap and enable indirect register access.
717          * Rely on CPU to do target byte swapping on big endian systems.
718          * Access to registers outside of PCI configurtion space are not
719          * valid until this is done.
720          */
721         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
722                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
723                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
724
725         /* Save ASIC revsion info. */
726         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
727
728         /* Weed out any non-production controller revisions. */
729         switch (BCE_CHIP_ID(sc)) {
730         case BCE_CHIP_ID_5706_A0:
731         case BCE_CHIP_ID_5706_A1:
732         case BCE_CHIP_ID_5708_A0:
733         case BCE_CHIP_ID_5708_B0:
734         case BCE_CHIP_ID_5709_A0:
735         case BCE_CHIP_ID_5709_B0:
736         case BCE_CHIP_ID_5709_B1:
737 #ifdef foo
738         /* 5709C B2 seems to work fine */
739         case BCE_CHIP_ID_5709_B2:
740 #endif
741                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
742                               BCE_CHIP_ID(sc));
743                 rc = ENODEV;
744                 goto fail;
745         }
746
747         mii_priv |= BRGPHY_FLAG_WIRESPEED;
748         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
749                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax ||
750                     BCE_CHIP_REV(sc) == BCE_CHIP_REV_Bx)
751                         mii_priv |= BRGPHY_FLAG_NO_EARLYDAC;
752         } else {
753                 mii_priv |= BRGPHY_FLAG_BER_BUG;
754         }
755
756         if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
757                 irq_handle = bce_intr_legacy;
758         } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
759                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
760                         irq_handle = bce_intr_msi_oneshot;
761                         sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
762                 } else {
763                         irq_handle = bce_intr_msi;
764                         sc->bce_flags |= BCE_CHECK_MSI_FLAG;
765                 }
766         } else {
767                 panic("%s: unsupported intr type %d",
768                     device_get_nameunit(dev), sc->bce_irq_type);
769         }
770
771         /*
772          * Find the base address for shared memory access.
773          * Newer versions of bootcode use a signature and offset
774          * while older versions use a fixed address.
775          */
776         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
777         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
778             BCE_SHM_HDR_SIGNATURE_SIG) {
779                 /* Multi-port devices use different offsets in shared memory. */
780                 sc->bce_shmem_base = REG_RD_IND(sc,
781                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
782         } else {
783                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
784         }
785         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
786
787         /* Fetch the bootcode revision. */
788         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
789         for (i = 0, j = 0; i < 3; i++) {
790                 uint8_t num;
791                 int k, skip0;
792
793                 num = (uint8_t)(val >> (24 - (i * 8)));
794                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
795                         if (num >= k || !skip0 || k == 1) {
796                                 sc->bce_bc_ver[j++] = (num / k) + '0';
797                                 skip0 = 0;
798                         }
799                 }
800                 if (i != 2)
801                         sc->bce_bc_ver[j++] = '.';
802         }
803
804         /* Check if any management firwmare is running. */
805         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
806         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
807                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
808
809                 /* Allow time for firmware to enter the running state. */
810                 for (i = 0; i < 30; i++) {
811                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
812                         if (val & BCE_CONDITION_MFW_RUN_MASK)
813                                 break;
814                         DELAY(10000);
815                 }
816         }
817
818         /* Check the current bootcode state. */
819         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
820             BCE_CONDITION_MFW_RUN_MASK;
821         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
822             val != BCE_CONDITION_MFW_RUN_NONE) {
823                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
824
825                 for (i = 0, j = 0; j < 3; j++) {
826                         val = bce_reg_rd_ind(sc, addr + j * 4);
827                         val = bswap32(val);
828                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
829                         i += 4;
830                 }
831         }
832
833         /* Get PCI bus information (speed and type). */
834         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
835         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
836                 uint32_t clkreg;
837
838                 sc->bce_flags |= BCE_PCIX_FLAG;
839
840                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
841                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
842                 switch (clkreg) {
843                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
844                         sc->bus_speed_mhz = 133;
845                         break;
846
847                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
848                         sc->bus_speed_mhz = 100;
849                         break;
850
851                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
852                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
853                         sc->bus_speed_mhz = 66;
854                         break;
855
856                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
857                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
858                         sc->bus_speed_mhz = 50;
859                         break;
860
861                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
862                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
863                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
864                         sc->bus_speed_mhz = 33;
865                         break;
866                 }
867         } else {
868                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
869                         sc->bus_speed_mhz = 66;
870                 else
871                         sc->bus_speed_mhz = 33;
872         }
873
874         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
875                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
876
877         /* Reset the controller. */
878         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
879         if (rc != 0)
880                 goto fail;
881
882         /* Initialize the controller. */
883         rc = bce_chipinit(sc);
884         if (rc != 0) {
885                 device_printf(dev, "Controller initialization failed!\n");
886                 goto fail;
887         }
888
889         /* Perform NVRAM test. */
890         rc = bce_nvram_test(sc);
891         if (rc != 0) {
892                 device_printf(dev, "NVRAM test failed!\n");
893                 goto fail;
894         }
895
896         /* Fetch the permanent Ethernet MAC address. */
897         bce_get_mac_addr(sc);
898
899         /*
900          * Trip points control how many BDs
901          * should be ready before generating an
902          * interrupt while ticks control how long
903          * a BD can sit in the chain before
904          * generating an interrupt.  Set the default 
905          * values for the RX and TX rings.
906          */
907
908 #ifdef BCE_DRBUG
909         /* Force more frequent interrupts. */
910         sc->bce_tx_quick_cons_trip_int = 1;
911         sc->bce_tx_quick_cons_trip     = 1;
912         sc->bce_tx_ticks_int           = 0;
913         sc->bce_tx_ticks               = 0;
914
915         sc->bce_rx_quick_cons_trip_int = 1;
916         sc->bce_rx_quick_cons_trip     = 1;
917         sc->bce_rx_ticks_int           = 0;
918         sc->bce_rx_ticks               = 0;
919 #else
920         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
921         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
922         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
923         sc->bce_tx_ticks               = bce_tx_ticks;
924
925         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
926         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
927         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
928         sc->bce_rx_ticks               = bce_rx_ticks;
929 #endif
930
931         /* Update statistics once every second. */
932         sc->bce_stats_ticks = 1000000 & 0xffff00;
933
934         /* Find the media type for the adapter. */
935         bce_get_media(sc);
936
937         /* Allocate DMA memory resources. */
938         rc = bce_dma_alloc(sc);
939         if (rc != 0) {
940                 device_printf(dev, "DMA resource allocation failed!\n");
941                 goto fail;
942         }
943
944         /* Initialize the ifnet interface. */
945         ifp->if_softc = sc;
946         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
947         ifp->if_ioctl = bce_ioctl;
948         ifp->if_start = bce_start;
949         ifp->if_init = bce_init;
950         ifp->if_watchdog = bce_watchdog;
951 #ifdef DEVICE_POLLING
952         ifp->if_poll = bce_poll;
953 #endif
954         ifp->if_mtu = ETHERMTU;
955         ifp->if_hwassist = BCE_CSUM_FEATURES | CSUM_TSO;
956         ifp->if_capabilities = BCE_IF_CAPABILITIES;
957         ifp->if_capenable = ifp->if_capabilities;
958         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD(sc));
959         ifq_set_ready(&ifp->if_snd);
960
961         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
962                 ifp->if_baudrate = IF_Gbps(2.5);
963         else
964                 ifp->if_baudrate = IF_Gbps(1);
965
966         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
967         sc->mbuf_alloc_size  = MCLBYTES;
968
969         /*
970          * Look for our PHY.
971          */
972         mii_probe_args_init(&mii_args, bce_ifmedia_upd, bce_ifmedia_sts);
973         mii_args.mii_probemask = 1 << sc->bce_phy_addr;
974         mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
975         mii_args.mii_priv = mii_priv;
976
977         rc = mii_probe(dev, &sc->bce_miibus, &mii_args);
978         if (rc != 0) {
979                 device_printf(dev, "PHY probe failed!\n");
980                 goto fail;
981         }
982
983         /* Attach to the Ethernet interface list. */
984         ether_ifattach(ifp, sc->eaddr, NULL);
985
986         callout_init_mp(&sc->bce_tick_callout);
987         callout_init_mp(&sc->bce_pulse_callout);
988         callout_init_mp(&sc->bce_ckmsi_callout);
989
990         /* Hookup IRQ last. */
991         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
992                             &sc->bce_intrhand, ifp->if_serializer);
993         if (rc != 0) {
994                 device_printf(dev, "Failed to setup IRQ!\n");
995                 ether_ifdetach(ifp);
996                 goto fail;
997         }
998
999         ifp->if_cpuid = rman_get_cpuid(sc->bce_res_irq);
1000         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1001         sc->bce_intr_cpuid = ifp->if_cpuid;
1002
1003         /* Print some important debugging info. */
1004         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
1005
1006         /* Add the supported sysctls to the kernel. */
1007         bce_add_sysctls(sc);
1008
1009         /*
1010          * The chip reset earlier notified the bootcode that
1011          * a driver is present.  We now need to start our pulse
1012          * routine so that the bootcode is reminded that we're
1013          * still running.
1014          */
1015         bce_pulse(sc);
1016
1017         /* Get the firmware running so IPMI still works */
1018         bce_mgmt_init(sc);
1019
1020         if (bootverbose)
1021                 bce_print_adapter_info(sc);
1022
1023         return 0;
1024 fail:
1025         bce_detach(dev);
1026         return(rc);
1027 }
1028
1029
1030 /****************************************************************************/
1031 /* Device detach function.                                                  */
1032 /*                                                                          */
1033 /* Stops the controller, resets the controller, and releases resources.     */
1034 /*                                                                          */
1035 /* Returns:                                                                 */
1036 /*   0 on success, positive value on failure.                               */
1037 /****************************************************************************/
1038 static int
1039 bce_detach(device_t dev)
1040 {
1041         struct bce_softc *sc = device_get_softc(dev);
1042
1043         if (device_is_attached(dev)) {
1044                 struct ifnet *ifp = &sc->arpcom.ac_if;
1045                 uint32_t msg;
1046
1047                 /* Stop and reset the controller. */
1048                 lwkt_serialize_enter(ifp->if_serializer);
1049                 callout_stop(&sc->bce_pulse_callout);
1050                 bce_stop(sc);
1051                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1052                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1053                 else
1054                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1055                 bce_reset(sc, msg);
1056                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1057                 lwkt_serialize_exit(ifp->if_serializer);
1058
1059                 ether_ifdetach(ifp);
1060         }
1061
1062         /* If we have a child device on the MII bus remove it too. */
1063         if (sc->bce_miibus)
1064                 device_delete_child(dev, sc->bce_miibus);
1065         bus_generic_detach(dev);
1066
1067         if (sc->bce_res_irq != NULL) {
1068                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1069                     sc->bce_res_irq);
1070         }
1071
1072         if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1073                 pci_release_msi(dev);
1074
1075         if (sc->bce_res_mem != NULL) {
1076                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1077                                      sc->bce_res_mem);
1078         }
1079
1080         bce_dma_free(sc);
1081
1082         if (sc->bce_sysctl_tree != NULL)
1083                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1084
1085         return 0;
1086 }
1087
1088
1089 /****************************************************************************/
1090 /* Device shutdown function.                                                */
1091 /*                                                                          */
1092 /* Stops and resets the controller.                                         */
1093 /*                                                                          */
1094 /* Returns:                                                                 */
1095 /*   Nothing                                                                */
1096 /****************************************************************************/
1097 static void
1098 bce_shutdown(device_t dev)
1099 {
1100         struct bce_softc *sc = device_get_softc(dev);
1101         struct ifnet *ifp = &sc->arpcom.ac_if;
1102         uint32_t msg;
1103
1104         lwkt_serialize_enter(ifp->if_serializer);
1105         bce_stop(sc);
1106         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1107                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1108         else
1109                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1110         bce_reset(sc, msg);
1111         lwkt_serialize_exit(ifp->if_serializer);
1112 }
1113
1114
1115 /****************************************************************************/
1116 /* Indirect register read.                                                  */
1117 /*                                                                          */
1118 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1119 /* configuration space.  Using this mechanism avoids issues with posted     */
1120 /* reads but is much slower than memory-mapped I/O.                         */
1121 /*                                                                          */
1122 /* Returns:                                                                 */
1123 /*   The value of the register.                                             */
1124 /****************************************************************************/
1125 static uint32_t
1126 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1127 {
1128         device_t dev = sc->bce_dev;
1129
1130         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1131 #ifdef BCE_DEBUG
1132         {
1133                 uint32_t val;
1134                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1135                 DBPRINT(sc, BCE_EXCESSIVE,
1136                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1137                         __func__, offset, val);
1138                 return val;
1139         }
1140 #else
1141         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1142 #endif
1143 }
1144
1145
1146 /****************************************************************************/
1147 /* Indirect register write.                                                 */
1148 /*                                                                          */
1149 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1150 /* configuration space.  Using this mechanism avoids issues with posted     */
1151 /* writes but is muchh slower than memory-mapped I/O.                       */
1152 /*                                                                          */
1153 /* Returns:                                                                 */
1154 /*   Nothing.                                                               */
1155 /****************************************************************************/
1156 static void
1157 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1158 {
1159         device_t dev = sc->bce_dev;
1160
1161         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1162                 __func__, offset, val);
1163
1164         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1165         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1166 }
1167
1168
1169 /****************************************************************************/
1170 /* Shared memory write.                                                     */
1171 /*                                                                          */
1172 /* Writes NetXtreme II shared memory region.                                */
1173 /*                                                                          */
1174 /* Returns:                                                                 */
1175 /*   Nothing.                                                               */
1176 /****************************************************************************/
1177 static void
1178 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1179 {
1180         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1181 }
1182
1183
1184 /****************************************************************************/
1185 /* Shared memory read.                                                      */
1186 /*                                                                          */
1187 /* Reads NetXtreme II shared memory region.                                 */
1188 /*                                                                          */
1189 /* Returns:                                                                 */
1190 /*   The 32 bit value read.                                                 */
1191 /****************************************************************************/
1192 static u32
1193 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1194 {
1195         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1196 }
1197
1198
1199 /****************************************************************************/
1200 /* Context memory write.                                                    */
1201 /*                                                                          */
1202 /* The NetXtreme II controller uses context memory to track connection      */
1203 /* information for L2 and higher network protocols.                         */
1204 /*                                                                          */
1205 /* Returns:                                                                 */
1206 /*   Nothing.                                                               */
1207 /****************************************************************************/
1208 static void
1209 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1210     uint32_t ctx_val)
1211 {
1212         uint32_t idx, offset = ctx_offset + cid_addr;
1213         uint32_t val, retry_cnt = 5;
1214
1215         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1216             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1217                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1218                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1219
1220                 for (idx = 0; idx < retry_cnt; idx++) {
1221                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1222                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1223                                 break;
1224                         DELAY(5);
1225                 }
1226
1227                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1228                         device_printf(sc->bce_dev,
1229                             "Unable to write CTX memory: "
1230                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1231                             cid_addr, ctx_offset);
1232                 }
1233         } else {
1234                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1235                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1236         }
1237 }
1238
1239
1240 /****************************************************************************/
1241 /* PHY register read.                                                       */
1242 /*                                                                          */
1243 /* Implements register reads on the MII bus.                                */
1244 /*                                                                          */
1245 /* Returns:                                                                 */
1246 /*   The value of the register.                                             */
1247 /****************************************************************************/
1248 static int
1249 bce_miibus_read_reg(device_t dev, int phy, int reg)
1250 {
1251         struct bce_softc *sc = device_get_softc(dev);
1252         uint32_t val;
1253         int i;
1254
1255         /* Make sure we are accessing the correct PHY address. */
1256         KASSERT(phy == sc->bce_phy_addr,
1257             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1258
1259         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1260                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1261                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1262
1263                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1264                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1265
1266                 DELAY(40);
1267         }
1268
1269         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1270               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1271               BCE_EMAC_MDIO_COMM_START_BUSY;
1272         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1273
1274         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1275                 DELAY(10);
1276
1277                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1278                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1279                         DELAY(5);
1280
1281                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1282                         val &= BCE_EMAC_MDIO_COMM_DATA;
1283                         break;
1284                 }
1285         }
1286
1287         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1288                 if_printf(&sc->arpcom.ac_if,
1289                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1290                           phy, reg);
1291                 val = 0x0;
1292         } else {
1293                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1294         }
1295
1296         DBPRINT(sc, BCE_EXCESSIVE,
1297                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1298                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1299
1300         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1301                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1302                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1303
1304                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1305                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1306
1307                 DELAY(40);
1308         }
1309         return (val & 0xffff);
1310 }
1311
1312
1313 /****************************************************************************/
1314 /* PHY register write.                                                      */
1315 /*                                                                          */
1316 /* Implements register writes on the MII bus.                               */
1317 /*                                                                          */
1318 /* Returns:                                                                 */
1319 /*   The value of the register.                                             */
1320 /****************************************************************************/
1321 static int
1322 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1323 {
1324         struct bce_softc *sc = device_get_softc(dev);
1325         uint32_t val1;
1326         int i;
1327
1328         /* Make sure we are accessing the correct PHY address. */
1329         KASSERT(phy == sc->bce_phy_addr,
1330             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1331
1332         DBPRINT(sc, BCE_EXCESSIVE,
1333                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1334                 __func__, phy, (uint16_t)(reg & 0xffff),
1335                 (uint16_t)(val & 0xffff));
1336
1337         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1338                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1339                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1340
1341                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1342                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1343
1344                 DELAY(40);
1345         }
1346
1347         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1348                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1349                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1350         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1351
1352         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1353                 DELAY(10);
1354
1355                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1356                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1357                         DELAY(5);
1358                         break;
1359                 }
1360         }
1361
1362         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1363                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1364
1365         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1366                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1367                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1368
1369                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1370                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1371
1372                 DELAY(40);
1373         }
1374         return 0;
1375 }
1376
1377
1378 /****************************************************************************/
1379 /* MII bus status change.                                                   */
1380 /*                                                                          */
1381 /* Called by the MII bus driver when the PHY establishes link to set the    */
1382 /* MAC interface registers.                                                 */
1383 /*                                                                          */
1384 /* Returns:                                                                 */
1385 /*   Nothing.                                                               */
1386 /****************************************************************************/
1387 static void
1388 bce_miibus_statchg(device_t dev)
1389 {
1390         struct bce_softc *sc = device_get_softc(dev);
1391         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1392
1393         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1394                 mii->mii_media_active);
1395
1396 #ifdef BCE_DEBUG
1397         /* Decode the interface media flags. */
1398         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1399         switch(IFM_TYPE(mii->mii_media_active)) {
1400         case IFM_ETHER:
1401                 kprintf("Ethernet )");
1402                 break;
1403         default:
1404                 kprintf("Unknown )");
1405                 break;
1406         }
1407
1408         kprintf(" Media Options: ( ");
1409         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1410         case IFM_AUTO:
1411                 kprintf("Autoselect )");
1412                 break;
1413         case IFM_MANUAL:
1414                 kprintf("Manual )");
1415                 break;
1416         case IFM_NONE:
1417                 kprintf("None )");
1418                 break;
1419         case IFM_10_T:
1420                 kprintf("10Base-T )");
1421                 break;
1422         case IFM_100_TX:
1423                 kprintf("100Base-TX )");
1424                 break;
1425         case IFM_1000_SX:
1426                 kprintf("1000Base-SX )");
1427                 break;
1428         case IFM_1000_T:
1429                 kprintf("1000Base-T )");
1430                 break;
1431         default:
1432                 kprintf("Other )");
1433                 break;
1434         }
1435
1436         kprintf(" Global Options: (");
1437         if (mii->mii_media_active & IFM_FDX)
1438                 kprintf(" FullDuplex");
1439         if (mii->mii_media_active & IFM_HDX)
1440                 kprintf(" HalfDuplex");
1441         if (mii->mii_media_active & IFM_LOOP)
1442                 kprintf(" Loopback");
1443         if (mii->mii_media_active & IFM_FLAG0)
1444                 kprintf(" Flag0");
1445         if (mii->mii_media_active & IFM_FLAG1)
1446                 kprintf(" Flag1");
1447         if (mii->mii_media_active & IFM_FLAG2)
1448                 kprintf(" Flag2");
1449         kprintf(" )\n");
1450 #endif
1451
1452         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1453
1454         /*
1455          * Set MII or GMII interface based on the speed negotiated
1456          * by the PHY.
1457          */
1458         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 
1459             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1460                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1461                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1462         } else {
1463                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1464                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1465         }
1466
1467         /*
1468          * Set half or full duplex based on the duplicity negotiated
1469          * by the PHY.
1470          */
1471         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1472                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1473                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1474         } else {
1475                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1476                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1477         }
1478 }
1479
1480
1481 /****************************************************************************/
1482 /* Acquire NVRAM lock.                                                      */
1483 /*                                                                          */
1484 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1485 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1486 /* for use by the driver.                                                   */
1487 /*                                                                          */
1488 /* Returns:                                                                 */
1489 /*   0 on success, positive value on failure.                               */
1490 /****************************************************************************/
1491 static int
1492 bce_acquire_nvram_lock(struct bce_softc *sc)
1493 {
1494         uint32_t val;
1495         int j;
1496
1497         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1498
1499         /* Request access to the flash interface. */
1500         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1501         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1502                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1503                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1504                         break;
1505
1506                 DELAY(5);
1507         }
1508
1509         if (j >= NVRAM_TIMEOUT_COUNT) {
1510                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1511                 return EBUSY;
1512         }
1513         return 0;
1514 }
1515
1516
1517 /****************************************************************************/
1518 /* Release NVRAM lock.                                                      */
1519 /*                                                                          */
1520 /* When the caller is finished accessing NVRAM the lock must be released.   */
1521 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1522 /* for use by the driver.                                                   */
1523 /*                                                                          */
1524 /* Returns:                                                                 */
1525 /*   0 on success, positive value on failure.                               */
1526 /****************************************************************************/
1527 static int
1528 bce_release_nvram_lock(struct bce_softc *sc)
1529 {
1530         int j;
1531         uint32_t val;
1532
1533         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1534
1535         /*
1536          * Relinquish nvram interface.
1537          */
1538         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1539
1540         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1541                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1542                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1543                         break;
1544
1545                 DELAY(5);
1546         }
1547
1548         if (j >= NVRAM_TIMEOUT_COUNT) {
1549                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1550                 return EBUSY;
1551         }
1552         return 0;
1553 }
1554
1555
1556 /****************************************************************************/
1557 /* Enable NVRAM access.                                                     */
1558 /*                                                                          */
1559 /* Before accessing NVRAM for read or write operations the caller must      */
1560 /* enabled NVRAM access.                                                    */
1561 /*                                                                          */
1562 /* Returns:                                                                 */
1563 /*   Nothing.                                                               */
1564 /****************************************************************************/
1565 static void
1566 bce_enable_nvram_access(struct bce_softc *sc)
1567 {
1568         uint32_t val;
1569
1570         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1571
1572         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1573         /* Enable both bits, even on read. */
1574         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1575                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1576 }
1577
1578
1579 /****************************************************************************/
1580 /* Disable NVRAM access.                                                    */
1581 /*                                                                          */
1582 /* When the caller is finished accessing NVRAM access must be disabled.     */
1583 /*                                                                          */
1584 /* Returns:                                                                 */
1585 /*   Nothing.                                                               */
1586 /****************************************************************************/
1587 static void
1588 bce_disable_nvram_access(struct bce_softc *sc)
1589 {
1590         uint32_t val;
1591
1592         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1593
1594         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1595
1596         /* Disable both bits, even after read. */
1597         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1598                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1599 }
1600
1601
1602 /****************************************************************************/
1603 /* Read a dword (32 bits) from NVRAM.                                       */
1604 /*                                                                          */
1605 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1606 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1607 /*                                                                          */
1608 /* Returns:                                                                 */
1609 /*   0 on success and the 32 bit value read, positive value on failure.     */
1610 /****************************************************************************/
1611 static int
1612 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1613                      uint32_t cmd_flags)
1614 {
1615         uint32_t cmd;
1616         int i, rc = 0;
1617
1618         /* Build the command word. */
1619         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1620
1621         /* Calculate the offset for buffered flash. */
1622         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1623                 offset = ((offset / sc->bce_flash_info->page_size) <<
1624                           sc->bce_flash_info->page_bits) +
1625                          (offset % sc->bce_flash_info->page_size);
1626         }
1627
1628         /*
1629          * Clear the DONE bit separately, set the address to read,
1630          * and issue the read.
1631          */
1632         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1633         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1634         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1635
1636         /* Wait for completion. */
1637         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1638                 uint32_t val;
1639
1640                 DELAY(5);
1641
1642                 val = REG_RD(sc, BCE_NVM_COMMAND);
1643                 if (val & BCE_NVM_COMMAND_DONE) {
1644                         val = REG_RD(sc, BCE_NVM_READ);
1645
1646                         val = be32toh(val);
1647                         memcpy(ret_val, &val, 4);
1648                         break;
1649                 }
1650         }
1651
1652         /* Check for errors. */
1653         if (i >= NVRAM_TIMEOUT_COUNT) {
1654                 if_printf(&sc->arpcom.ac_if,
1655                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1656                           offset);
1657                 rc = EBUSY;
1658         }
1659         return rc;
1660 }
1661
1662
1663 /****************************************************************************/
1664 /* Initialize NVRAM access.                                                 */
1665 /*                                                                          */
1666 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1667 /* access that device.                                                      */
1668 /*                                                                          */
1669 /* Returns:                                                                 */
1670 /*   0 on success, positive value on failure.                               */
1671 /****************************************************************************/
1672 static int
1673 bce_init_nvram(struct bce_softc *sc)
1674 {
1675         uint32_t val;
1676         int j, entry_count, rc = 0;
1677         const struct flash_spec *flash;
1678
1679         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1680
1681         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1682             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1683                 sc->bce_flash_info = &flash_5709;
1684                 goto bce_init_nvram_get_flash_size;
1685         }
1686
1687         /* Determine the selected interface. */
1688         val = REG_RD(sc, BCE_NVM_CFG1);
1689
1690         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1691
1692         /*
1693          * Flash reconfiguration is required to support additional
1694          * NVRAM devices not directly supported in hardware.
1695          * Check if the flash interface was reconfigured
1696          * by the bootcode.
1697          */
1698
1699         if (val & 0x40000000) {
1700                 /* Flash interface reconfigured by bootcode. */
1701
1702                 DBPRINT(sc, BCE_INFO_LOAD, 
1703                         "%s(): Flash WAS reconfigured.\n", __func__);
1704
1705                 for (j = 0, flash = flash_table; j < entry_count;
1706                      j++, flash++) {
1707                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1708                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1709                                 sc->bce_flash_info = flash;
1710                                 break;
1711                         }
1712                 }
1713         } else {
1714                 /* Flash interface not yet reconfigured. */
1715                 uint32_t mask;
1716
1717                 DBPRINT(sc, BCE_INFO_LOAD, 
1718                         "%s(): Flash was NOT reconfigured.\n", __func__);
1719
1720                 if (val & (1 << 23))
1721                         mask = FLASH_BACKUP_STRAP_MASK;
1722                 else
1723                         mask = FLASH_STRAP_MASK;
1724
1725                 /* Look for the matching NVRAM device configuration data. */
1726                 for (j = 0, flash = flash_table; j < entry_count;
1727                      j++, flash++) {
1728                         /* Check if the device matches any of the known devices. */
1729                         if ((val & mask) == (flash->strapping & mask)) {
1730                                 /* Found a device match. */
1731                                 sc->bce_flash_info = flash;
1732
1733                                 /* Request access to the flash interface. */
1734                                 rc = bce_acquire_nvram_lock(sc);
1735                                 if (rc != 0)
1736                                         return rc;
1737
1738                                 /* Reconfigure the flash interface. */
1739                                 bce_enable_nvram_access(sc);
1740                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1741                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1742                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1743                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1744                                 bce_disable_nvram_access(sc);
1745                                 bce_release_nvram_lock(sc);
1746                                 break;
1747                         }
1748                 }
1749         }
1750
1751         /* Check if a matching device was found. */
1752         if (j == entry_count) {
1753                 sc->bce_flash_info = NULL;
1754                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1755                 return ENODEV;
1756         }
1757
1758 bce_init_nvram_get_flash_size:
1759         /* Write the flash config data to the shared memory interface. */
1760         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1761             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1762         if (val)
1763                 sc->bce_flash_size = val;
1764         else
1765                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1766
1767         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1768                 __func__, sc->bce_flash_info->total_size);
1769
1770         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1771
1772         return rc;
1773 }
1774
1775
1776 /****************************************************************************/
1777 /* Read an arbitrary range of data from NVRAM.                              */
1778 /*                                                                          */
1779 /* Prepares the NVRAM interface for access and reads the requested data     */
1780 /* into the supplied buffer.                                                */
1781 /*                                                                          */
1782 /* Returns:                                                                 */
1783 /*   0 on success and the data read, positive value on failure.             */
1784 /****************************************************************************/
1785 static int
1786 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1787                int buf_size)
1788 {
1789         uint32_t cmd_flags, offset32, len32, extra;
1790         int rc = 0;
1791
1792         if (buf_size == 0)
1793                 return 0;
1794
1795         /* Request access to the flash interface. */
1796         rc = bce_acquire_nvram_lock(sc);
1797         if (rc != 0)
1798                 return rc;
1799
1800         /* Enable access to flash interface */
1801         bce_enable_nvram_access(sc);
1802
1803         len32 = buf_size;
1804         offset32 = offset;
1805         extra = 0;
1806
1807         cmd_flags = 0;
1808
1809         /* XXX should we release nvram lock if read_dword() fails? */
1810         if (offset32 & 3) {
1811                 uint8_t buf[4];
1812                 uint32_t pre_len;
1813
1814                 offset32 &= ~3;
1815                 pre_len = 4 - (offset & 3);
1816
1817                 if (pre_len >= len32) {
1818                         pre_len = len32;
1819                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1820                 } else {
1821                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1822                 }
1823
1824                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1825                 if (rc)
1826                         return rc;
1827
1828                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1829
1830                 offset32 += 4;
1831                 ret_buf += pre_len;
1832                 len32 -= pre_len;
1833         }
1834
1835         if (len32 & 3) {
1836                 extra = 4 - (len32 & 3);
1837                 len32 = (len32 + 4) & ~3;
1838         }
1839
1840         if (len32 == 4) {
1841                 uint8_t buf[4];
1842
1843                 if (cmd_flags)
1844                         cmd_flags = BCE_NVM_COMMAND_LAST;
1845                 else
1846                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1847                                     BCE_NVM_COMMAND_LAST;
1848
1849                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1850
1851                 memcpy(ret_buf, buf, 4 - extra);
1852         } else if (len32 > 0) {
1853                 uint8_t buf[4];
1854
1855                 /* Read the first word. */
1856                 if (cmd_flags)
1857                         cmd_flags = 0;
1858                 else
1859                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1860
1861                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1862
1863                 /* Advance to the next dword. */
1864                 offset32 += 4;
1865                 ret_buf += 4;
1866                 len32 -= 4;
1867
1868                 while (len32 > 4 && rc == 0) {
1869                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1870
1871                         /* Advance to the next dword. */
1872                         offset32 += 4;
1873                         ret_buf += 4;
1874                         len32 -= 4;
1875                 }
1876
1877                 if (rc)
1878                         goto bce_nvram_read_locked_exit;
1879
1880                 cmd_flags = BCE_NVM_COMMAND_LAST;
1881                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1882
1883                 memcpy(ret_buf, buf, 4 - extra);
1884         }
1885
1886 bce_nvram_read_locked_exit:
1887         /* Disable access to flash interface and release the lock. */
1888         bce_disable_nvram_access(sc);
1889         bce_release_nvram_lock(sc);
1890
1891         return rc;
1892 }
1893
1894
1895 /****************************************************************************/
1896 /* Verifies that NVRAM is accessible and contains valid data.               */
1897 /*                                                                          */
1898 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1899 /* correct.                                                                 */
1900 /*                                                                          */
1901 /* Returns:                                                                 */
1902 /*   0 on success, positive value on failure.                               */
1903 /****************************************************************************/
1904 static int
1905 bce_nvram_test(struct bce_softc *sc)
1906 {
1907         uint32_t buf[BCE_NVRAM_SIZE / 4];
1908         uint32_t magic, csum;
1909         uint8_t *data = (uint8_t *)buf;
1910         int rc = 0;
1911
1912         /*
1913          * Check that the device NVRAM is valid by reading
1914          * the magic value at offset 0.
1915          */
1916         rc = bce_nvram_read(sc, 0, data, 4);
1917         if (rc != 0)
1918                 return rc;
1919
1920         magic = be32toh(buf[0]);
1921         if (magic != BCE_NVRAM_MAGIC) {
1922                 if_printf(&sc->arpcom.ac_if,
1923                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1924                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1925                 return ENODEV;
1926         }
1927
1928         /*
1929          * Verify that the device NVRAM includes valid
1930          * configuration data.
1931          */
1932         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1933         if (rc != 0)
1934                 return rc;
1935
1936         csum = ether_crc32_le(data, 0x100);
1937         if (csum != BCE_CRC32_RESIDUAL) {
1938                 if_printf(&sc->arpcom.ac_if,
1939                           "Invalid Manufacturing Information NVRAM CRC! "
1940                           "Expected: 0x%08X, Found: 0x%08X\n",
1941                           BCE_CRC32_RESIDUAL, csum);
1942                 return ENODEV;
1943         }
1944
1945         csum = ether_crc32_le(data + 0x100, 0x100);
1946         if (csum != BCE_CRC32_RESIDUAL) {
1947                 if_printf(&sc->arpcom.ac_if,
1948                           "Invalid Feature Configuration Information "
1949                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1950                           BCE_CRC32_RESIDUAL, csum);
1951                 rc = ENODEV;
1952         }
1953         return rc;
1954 }
1955
1956
1957 /****************************************************************************/
1958 /* Identifies the current media type of the controller and sets the PHY     */
1959 /* address.                                                                 */
1960 /*                                                                          */
1961 /* Returns:                                                                 */
1962 /*   Nothing.                                                               */
1963 /****************************************************************************/
1964 static void
1965 bce_get_media(struct bce_softc *sc)
1966 {
1967         uint32_t val;
1968
1969         sc->bce_phy_addr = 1;
1970
1971         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1972             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1973                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1974                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1975                 uint32_t strap;
1976
1977                 /*
1978                  * The BCM5709S is software configurable
1979                  * for Copper or SerDes operation.
1980                  */
1981                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1982                         return;
1983                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1984                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1985                         return;
1986                 }
1987
1988                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1989                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1990                 } else {
1991                         strap =
1992                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1993                 }
1994
1995                 if (pci_get_function(sc->bce_dev) == 0) {
1996                         switch (strap) {
1997                         case 0x4:
1998                         case 0x5:
1999                         case 0x6:
2000                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2001                                 break;
2002                         }
2003                 } else {
2004                         switch (strap) {
2005                         case 0x1:
2006                         case 0x2:
2007                         case 0x4:
2008                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2009                                 break;
2010                         }
2011                 }
2012         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
2013                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2014         }
2015
2016         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2017                 sc->bce_flags |= BCE_NO_WOL_FLAG;
2018                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2019                         sc->bce_phy_addr = 2;
2020                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2021                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2022                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2023                 }
2024         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2025             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2026                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2027         }
2028 }
2029
2030
2031 /****************************************************************************/
2032 /* Free any DMA memory owned by the driver.                                 */
2033 /*                                                                          */
2034 /* Scans through each data structre that requires DMA memory and frees      */
2035 /* the memory if allocated.                                                 */
2036 /*                                                                          */
2037 /* Returns:                                                                 */
2038 /*   Nothing.                                                               */
2039 /****************************************************************************/
2040 static void
2041 bce_dma_free(struct bce_softc *sc)
2042 {
2043         int i;
2044
2045         /* Destroy the status block. */
2046         if (sc->status_tag != NULL) {
2047                 if (sc->status_block != NULL) {
2048                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2049                         bus_dmamem_free(sc->status_tag, sc->status_block,
2050                                         sc->status_map);
2051                 }
2052                 bus_dma_tag_destroy(sc->status_tag);
2053         }
2054
2055         /* Destroy the statistics block. */
2056         if (sc->stats_tag != NULL) {
2057                 if (sc->stats_block != NULL) {
2058                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2059                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2060                                         sc->stats_map);
2061                 }
2062                 bus_dma_tag_destroy(sc->stats_tag);
2063         }
2064
2065         /* Destroy the CTX DMA stuffs. */
2066         if (sc->ctx_tag != NULL) {
2067                 for (i = 0; i < sc->ctx_pages; i++) {
2068                         if (sc->ctx_block[i] != NULL) {
2069                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2070                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2071                                                 sc->ctx_map[i]);
2072                         }
2073                 }
2074                 bus_dma_tag_destroy(sc->ctx_tag);
2075         }
2076
2077         /* Destroy the TX buffer descriptor DMA stuffs. */
2078         if (sc->tx_bd_chain_tag != NULL) {
2079                 for (i = 0; i < sc->tx_pages; i++) {
2080                         if (sc->tx_bd_chain[i] != NULL) {
2081                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2082                                                   sc->tx_bd_chain_map[i]);
2083                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2084                                                 sc->tx_bd_chain[i],
2085                                                 sc->tx_bd_chain_map[i]);
2086                         }
2087                 }
2088                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2089         }
2090
2091         /* Destroy the RX buffer descriptor DMA stuffs. */
2092         if (sc->rx_bd_chain_tag != NULL) {
2093                 for (i = 0; i < sc->rx_pages; i++) {
2094                         if (sc->rx_bd_chain[i] != NULL) {
2095                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2096                                                   sc->rx_bd_chain_map[i]);
2097                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2098                                                 sc->rx_bd_chain[i],
2099                                                 sc->rx_bd_chain_map[i]);
2100                         }
2101                 }
2102                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2103         }
2104
2105         /* Destroy the TX mbuf DMA stuffs. */
2106         if (sc->tx_mbuf_tag != NULL) {
2107                 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2108                         /* Must have been unloaded in bce_stop() */
2109                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2110                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2111                                            sc->tx_mbuf_map[i]);
2112                 }
2113                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2114         }
2115
2116         /* Destroy the RX mbuf DMA stuffs. */
2117         if (sc->rx_mbuf_tag != NULL) {
2118                 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2119                         /* Must have been unloaded in bce_stop() */
2120                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2121                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2122                                            sc->rx_mbuf_map[i]);
2123                 }
2124                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2125                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2126         }
2127
2128         /* Destroy the parent tag */
2129         if (sc->parent_tag != NULL)
2130                 bus_dma_tag_destroy(sc->parent_tag);
2131
2132         if (sc->tx_bd_chain_map != NULL)
2133                 kfree(sc->tx_bd_chain_map, M_DEVBUF);
2134         if (sc->tx_bd_chain != NULL)
2135                 kfree(sc->tx_bd_chain, M_DEVBUF);
2136         if (sc->tx_bd_chain_paddr != NULL)
2137                 kfree(sc->tx_bd_chain_paddr, M_DEVBUF);
2138
2139         if (sc->rx_bd_chain_map != NULL)
2140                 kfree(sc->rx_bd_chain_map, M_DEVBUF);
2141         if (sc->rx_bd_chain != NULL)
2142                 kfree(sc->rx_bd_chain, M_DEVBUF);
2143         if (sc->rx_bd_chain_paddr != NULL)
2144                 kfree(sc->rx_bd_chain_paddr, M_DEVBUF);
2145
2146         if (sc->tx_mbuf_map != NULL)
2147                 kfree(sc->tx_mbuf_map, M_DEVBUF);
2148         if (sc->tx_mbuf_ptr != NULL)
2149                 kfree(sc->tx_mbuf_ptr, M_DEVBUF);
2150
2151         if (sc->rx_mbuf_map != NULL)
2152                 kfree(sc->rx_mbuf_map, M_DEVBUF);
2153         if (sc->rx_mbuf_ptr != NULL)
2154                 kfree(sc->rx_mbuf_ptr, M_DEVBUF);
2155         if (sc->rx_mbuf_paddr != NULL)
2156                 kfree(sc->rx_mbuf_paddr, M_DEVBUF);
2157 }
2158
2159
2160 /****************************************************************************/
2161 /* Get DMA memory from the OS.                                              */
2162 /*                                                                          */
2163 /* Validates that the OS has provided DMA buffers in response to a          */
2164 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2165 /* When the callback is used the OS will return 0 for the mapping function  */
2166 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2167 /* failures back to the caller.                                             */
2168 /*                                                                          */
2169 /* Returns:                                                                 */
2170 /*   Nothing.                                                               */
2171 /****************************************************************************/
2172 static void
2173 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2174 {
2175         bus_addr_t *busaddr = arg;
2176
2177         /*
2178          * Simulate a mapping failure.
2179          * XXX not correct.
2180          */
2181         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2182                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2183                         __FILE__, __LINE__);
2184                 error = ENOMEM);
2185                 
2186         /* Check for an error and signal the caller that an error occurred. */
2187         if (error)
2188                 return;
2189
2190         KASSERT(nseg == 1, ("only one segment is allowed"));
2191         *busaddr = segs->ds_addr;
2192 }
2193
2194
2195 /****************************************************************************/
2196 /* Allocate any DMA memory needed by the driver.                            */
2197 /*                                                                          */
2198 /* Allocates DMA memory needed for the various global structures needed by  */
2199 /* hardware.                                                                */
2200 /*                                                                          */
2201 /* Memory alignment requirements:                                           */
2202 /* -----------------+----------+----------+----------+----------+           */
2203 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2204 /* -----------------+----------+----------+----------+----------+           */
2205 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2206 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2207 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2208 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2209 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2210 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2211 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2212 /* -----------------+----------+----------+----------+----------+           */
2213 /*                                                                          */
2214 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2215 /*                                                                          */
2216 /* Returns:                                                                 */
2217 /*   0 for success, positive value for failure.                             */
2218 /****************************************************************************/
2219 static int
2220 bce_dma_alloc(struct bce_softc *sc)
2221 {
2222         struct ifnet *ifp = &sc->arpcom.ac_if;
2223         int i, j, rc = 0, pages;
2224         bus_addr_t busaddr, max_busaddr;
2225         bus_size_t status_align, stats_align;
2226
2227         pages = device_getenv_int(sc->bce_dev, "rx_pages", bce_rx_pages);
2228         if (pages <= 0 || pages > RX_PAGES_MAX || !powerof2(pages)) {
2229                 device_printf(sc->bce_dev, "invalid # of RX pages\n");
2230                 pages = RX_PAGES_DEFAULT;
2231         }
2232         sc->rx_pages = pages;
2233
2234         pages = device_getenv_int(sc->bce_dev, "tx_pages", bce_tx_pages);
2235         if (pages <= 0 || pages > TX_PAGES_MAX || !powerof2(pages)) {
2236                 device_printf(sc->bce_dev, "invalid # of TX pages\n");
2237                 pages = TX_PAGES_DEFAULT;
2238         }
2239         sc->tx_pages = pages;
2240
2241         sc->tx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->tx_pages,
2242             M_DEVBUF, M_WAITOK | M_ZERO);
2243         sc->tx_bd_chain = kmalloc(sizeof(struct tx_bd *) * sc->tx_pages,
2244             M_DEVBUF, M_WAITOK | M_ZERO);
2245         sc->tx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->tx_pages,
2246             M_DEVBUF, M_WAITOK | M_ZERO);
2247
2248         sc->rx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->rx_pages,
2249             M_DEVBUF, M_WAITOK | M_ZERO);
2250         sc->rx_bd_chain = kmalloc(sizeof(struct rx_bd *) * sc->rx_pages,
2251             M_DEVBUF, M_WAITOK | M_ZERO);
2252         sc->rx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->rx_pages,
2253             M_DEVBUF, M_WAITOK | M_ZERO);
2254
2255         sc->tx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_TX_BD(sc),
2256             M_DEVBUF, M_WAITOK | M_ZERO);
2257         sc->tx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_TX_BD(sc),
2258             M_DEVBUF, M_WAITOK | M_ZERO);
2259
2260         sc->rx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_RX_BD(sc),
2261             M_DEVBUF, M_WAITOK | M_ZERO);
2262         sc->rx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_RX_BD(sc),
2263             M_DEVBUF, M_WAITOK | M_ZERO);
2264         sc->rx_mbuf_paddr = kmalloc(sizeof(bus_addr_t) * TOTAL_RX_BD(sc),
2265             M_DEVBUF, M_WAITOK | M_ZERO);
2266
2267         /*
2268          * The embedded PCIe to PCI-X bridge (EPB) 
2269          * in the 5708 cannot address memory above 
2270          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 
2271          */
2272         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2273                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2274         else
2275                 max_busaddr = BUS_SPACE_MAXADDR;
2276
2277         /*
2278          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2279          */
2280         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2281             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2282                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2283                 if (sc->ctx_pages == 0)
2284                         sc->ctx_pages = 1;
2285                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2286                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2287                             sc->ctx_pages);
2288                         return ENOMEM;
2289                 }
2290                 status_align = 16;
2291                 stats_align = 16;
2292         } else {
2293                 status_align = 8;
2294                 stats_align = 8;
2295         }
2296
2297         /*
2298          * Allocate the parent bus DMA tag appropriate for PCI.
2299          */
2300         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2301                                 max_busaddr, BUS_SPACE_MAXADDR,
2302                                 NULL, NULL,
2303                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2304                                 BUS_SPACE_MAXSIZE_32BIT,
2305                                 0, &sc->parent_tag);
2306         if (rc != 0) {
2307                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2308                 return rc;
2309         }
2310
2311         /*
2312          * Allocate status block.
2313          */
2314         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2315                                 status_align, BCE_STATUS_BLK_SZ,
2316                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2317                                 &sc->status_tag, &sc->status_map,
2318                                 &sc->status_block_paddr);
2319         if (sc->status_block == NULL) {
2320                 if_printf(ifp, "Could not allocate status block!\n");
2321                 return ENOMEM;
2322         }
2323
2324         /*
2325          * Allocate statistics block.
2326          */
2327         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2328                                 stats_align, BCE_STATS_BLK_SZ,
2329                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2330                                 &sc->stats_tag, &sc->stats_map,
2331                                 &sc->stats_block_paddr);
2332         if (sc->stats_block == NULL) {
2333                 if_printf(ifp, "Could not allocate statistics block!\n");
2334                 return ENOMEM;
2335         }
2336
2337         /*
2338          * Allocate context block, if needed
2339          */
2340         if (sc->ctx_pages != 0) {
2341                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2342                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2343                                         NULL, NULL,
2344                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2345                                         0, &sc->ctx_tag);
2346                 if (rc != 0) {
2347                         if_printf(ifp, "Could not allocate "
2348                                   "context block DMA tag!\n");
2349                         return rc;
2350                 }
2351
2352                 for (i = 0; i < sc->ctx_pages; i++) {
2353                         rc = bus_dmamem_alloc(sc->ctx_tag,
2354                                               (void **)&sc->ctx_block[i],
2355                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2356                                               BUS_DMA_COHERENT,
2357                                               &sc->ctx_map[i]);
2358                         if (rc != 0) {
2359                                 if_printf(ifp, "Could not allocate %dth context "
2360                                           "DMA memory!\n", i);
2361                                 return rc;
2362                         }
2363
2364                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2365                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2366                                              bce_dma_map_addr, &busaddr,
2367                                              BUS_DMA_WAITOK);
2368                         if (rc != 0) {
2369                                 if (rc == EINPROGRESS) {
2370                                         panic("%s coherent memory loading "
2371                                               "is still in progress!", ifp->if_xname);
2372                                 }
2373                                 if_printf(ifp, "Could not map %dth context "
2374                                           "DMA memory!\n", i);
2375                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2376                                                 sc->ctx_map[i]);
2377                                 sc->ctx_block[i] = NULL;
2378                                 return rc;
2379                         }
2380                         sc->ctx_paddr[i] = busaddr;
2381                 }
2382         }
2383
2384         /*
2385          * Create a DMA tag for the TX buffer descriptor chain,
2386          * allocate and clear the  memory, and fetch the
2387          * physical address of the block.
2388          */
2389         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2390                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2391                                 NULL, NULL,
2392                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2393                                 0, &sc->tx_bd_chain_tag);
2394         if (rc != 0) {
2395                 if_printf(ifp, "Could not allocate "
2396                           "TX descriptor chain DMA tag!\n");
2397                 return rc;
2398         }
2399
2400         for (i = 0; i < sc->tx_pages; i++) {
2401                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2402                                       (void **)&sc->tx_bd_chain[i],
2403                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2404                                       BUS_DMA_COHERENT,
2405                                       &sc->tx_bd_chain_map[i]);
2406                 if (rc != 0) {
2407                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2408                                   "chain DMA memory!\n", i);
2409                         return rc;
2410                 }
2411
2412                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2413                                      sc->tx_bd_chain_map[i],
2414                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2415                                      bce_dma_map_addr, &busaddr,
2416                                      BUS_DMA_WAITOK);
2417                 if (rc != 0) {
2418                         if (rc == EINPROGRESS) {
2419                                 panic("%s coherent memory loading "
2420                                       "is still in progress!", ifp->if_xname);
2421                         }
2422                         if_printf(ifp, "Could not map %dth TX descriptor "
2423                                   "chain DMA memory!\n", i);
2424                         bus_dmamem_free(sc->tx_bd_chain_tag,
2425                                         sc->tx_bd_chain[i],
2426                                         sc->tx_bd_chain_map[i]);
2427                         sc->tx_bd_chain[i] = NULL;
2428                         return rc;
2429                 }
2430
2431                 sc->tx_bd_chain_paddr[i] = busaddr;
2432                 /* DRC - Fix for 64 bit systems. */
2433                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 
2434                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2435         }
2436
2437         /* Create a DMA tag for TX mbufs. */
2438         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2439                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2440                                 NULL, NULL,
2441                                 IP_MAXPACKET + sizeof(struct ether_vlan_header),
2442                                 BCE_MAX_SEGMENTS, PAGE_SIZE,
2443                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2444                                 BUS_DMA_ONEBPAGE,
2445                                 &sc->tx_mbuf_tag);
2446         if (rc != 0) {
2447                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2448                 return rc;
2449         }
2450
2451         /* Create DMA maps for the TX mbufs clusters. */
2452         for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2453                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2454                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2455                                        &sc->tx_mbuf_map[i]);
2456                 if (rc != 0) {
2457                         for (j = 0; j < i; ++j) {
2458                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2459                                                    sc->tx_mbuf_map[i]);
2460                         }
2461                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2462                         sc->tx_mbuf_tag = NULL;
2463
2464                         if_printf(ifp, "Unable to create "
2465                                   "%dth TX mbuf DMA map!\n", i);
2466                         return rc;
2467                 }
2468         }
2469
2470         /*
2471          * Create a DMA tag for the RX buffer descriptor chain,
2472          * allocate and clear the  memory, and fetch the physical
2473          * address of the blocks.
2474          */
2475         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2476                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2477                                 NULL, NULL,
2478                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2479                                 0, &sc->rx_bd_chain_tag);
2480         if (rc != 0) {
2481                 if_printf(ifp, "Could not allocate "
2482                           "RX descriptor chain DMA tag!\n");
2483                 return rc;
2484         }
2485
2486         for (i = 0; i < sc->rx_pages; i++) {
2487                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2488                                       (void **)&sc->rx_bd_chain[i],
2489                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2490                                       BUS_DMA_COHERENT,
2491                                       &sc->rx_bd_chain_map[i]);
2492                 if (rc != 0) {
2493                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2494                                   "chain DMA memory!\n", i);
2495                         return rc;
2496                 }
2497
2498                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2499                                      sc->rx_bd_chain_map[i],
2500                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2501                                      bce_dma_map_addr, &busaddr,
2502                                      BUS_DMA_WAITOK);
2503                 if (rc != 0) {
2504                         if (rc == EINPROGRESS) {
2505                                 panic("%s coherent memory loading "
2506                                       "is still in progress!", ifp->if_xname);
2507                         }
2508                         if_printf(ifp, "Could not map %dth RX descriptor "
2509                                   "chain DMA memory!\n", i);
2510                         bus_dmamem_free(sc->rx_bd_chain_tag,
2511                                         sc->rx_bd_chain[i],
2512                                         sc->rx_bd_chain_map[i]);
2513                         sc->rx_bd_chain[i] = NULL;
2514                         return rc;
2515                 }
2516
2517                 sc->rx_bd_chain_paddr[i] = busaddr;
2518                 /* DRC - Fix for 64 bit systems. */
2519                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2520                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2521         }
2522
2523         /* Create a DMA tag for RX mbufs. */
2524         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2525                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2526                                 NULL, NULL,
2527                                 MCLBYTES, 1, MCLBYTES,
2528                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2529                                 BUS_DMA_WAITOK,
2530                                 &sc->rx_mbuf_tag);
2531         if (rc != 0) {
2532                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2533                 return rc;
2534         }
2535
2536         /* Create tmp DMA map for RX mbuf clusters. */
2537         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2538                                &sc->rx_mbuf_tmpmap);
2539         if (rc != 0) {
2540                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2541                 sc->rx_mbuf_tag = NULL;
2542
2543                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2544                 return rc;
2545         }
2546
2547         /* Create DMA maps for the RX mbuf clusters. */
2548         for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2549                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2550                                        &sc->rx_mbuf_map[i]);
2551                 if (rc != 0) {
2552                         for (j = 0; j < i; ++j) {
2553                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2554                                                    sc->rx_mbuf_map[j]);
2555                         }
2556                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2557                         sc->rx_mbuf_tag = NULL;
2558
2559                         if_printf(ifp, "Unable to create "
2560                                   "%dth RX mbuf DMA map!\n", i);
2561                         return rc;
2562                 }
2563         }
2564         return 0;
2565 }
2566
2567
2568 /****************************************************************************/
2569 /* Firmware synchronization.                                                */
2570 /*                                                                          */
2571 /* Before performing certain events such as a chip reset, synchronize with  */
2572 /* the firmware first.                                                      */
2573 /*                                                                          */
2574 /* Returns:                                                                 */
2575 /*   0 for success, positive value for failure.                             */
2576 /****************************************************************************/
2577 static int
2578 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2579 {
2580         int i, rc = 0;
2581         uint32_t val;
2582
2583         /* Don't waste any time if we've timed out before. */
2584         if (sc->bce_fw_timed_out)
2585                 return EBUSY;
2586
2587         /* Increment the message sequence number. */
2588         sc->bce_fw_wr_seq++;
2589         msg_data |= sc->bce_fw_wr_seq;
2590
2591         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2592
2593         /* Send the message to the bootcode driver mailbox. */
2594         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2595
2596         /* Wait for the bootcode to acknowledge the message. */
2597         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2598                 /* Check for a response in the bootcode firmware mailbox. */
2599                 val = bce_shmem_rd(sc, BCE_FW_MB);
2600                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2601                         break;
2602                 DELAY(1000);
2603         }
2604
2605         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2606         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2607             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2608                 if_printf(&sc->arpcom.ac_if,
2609                           "Firmware synchronization timeout! "
2610                           "msg_data = 0x%08X\n", msg_data);
2611
2612                 msg_data &= ~BCE_DRV_MSG_CODE;
2613                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2614
2615                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2616
2617                 sc->bce_fw_timed_out = 1;
2618                 rc = EBUSY;
2619         }
2620         return rc;
2621 }
2622
2623
2624 /****************************************************************************/
2625 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2626 /*                                                                          */
2627 /* Returns:                                                                 */
2628 /*   Nothing.                                                               */
2629 /****************************************************************************/
2630 static void
2631 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2632                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2633 {
2634         int i;
2635         uint32_t val;
2636
2637         for (i = 0; i < rv2p_code_len; i += 8) {
2638                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2639                 rv2p_code++;
2640                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2641                 rv2p_code++;
2642
2643                 if (rv2p_proc == RV2P_PROC1) {
2644                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2645                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2646                 } else {
2647                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2648                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2649                 }
2650         }
2651
2652         /* Reset the processor, un-stall is done later. */
2653         if (rv2p_proc == RV2P_PROC1)
2654                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2655         else
2656                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2657 }
2658
2659
2660 /****************************************************************************/
2661 /* Load RISC processor firmware.                                            */
2662 /*                                                                          */
2663 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2664 /* associated with a particular processor.                                  */
2665 /*                                                                          */
2666 /* Returns:                                                                 */
2667 /*   Nothing.                                                               */
2668 /****************************************************************************/
2669 static void
2670 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2671                 struct fw_info *fw)
2672 {
2673         uint32_t offset;
2674         int j;
2675
2676         bce_halt_cpu(sc, cpu_reg);
2677
2678         /* Load the Text area. */
2679         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2680         if (fw->text) {
2681                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2682                         REG_WR_IND(sc, offset, fw->text[j]);
2683         }
2684
2685         /* Load the Data area. */
2686         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2687         if (fw->data) {
2688                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2689                         REG_WR_IND(sc, offset, fw->data[j]);
2690         }
2691
2692         /* Load the SBSS area. */
2693         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2694         if (fw->sbss) {
2695                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2696                         REG_WR_IND(sc, offset, fw->sbss[j]);
2697         }
2698
2699         /* Load the BSS area. */
2700         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2701         if (fw->bss) {
2702                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2703                         REG_WR_IND(sc, offset, fw->bss[j]);
2704         }
2705
2706         /* Load the Read-Only area. */
2707         offset = cpu_reg->spad_base +
2708                 (fw->rodata_addr - cpu_reg->mips_view_base);
2709         if (fw->rodata) {
2710                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2711                         REG_WR_IND(sc, offset, fw->rodata[j]);
2712         }
2713
2714         /* Clear the pre-fetch instruction and set the FW start address. */
2715         REG_WR_IND(sc, cpu_reg->inst, 0);
2716         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2717 }
2718
2719
2720 /****************************************************************************/
2721 /* Starts the RISC processor.                                               */
2722 /*                                                                          */
2723 /* Assumes the CPU starting address has already been set.                   */
2724 /*                                                                          */
2725 /* Returns:                                                                 */
2726 /*   Nothing.                                                               */
2727 /****************************************************************************/
2728 static void
2729 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2730 {
2731         uint32_t val;
2732
2733         /* Start the CPU. */
2734         val = REG_RD_IND(sc, cpu_reg->mode);
2735         val &= ~cpu_reg->mode_value_halt;
2736         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2737         REG_WR_IND(sc, cpu_reg->mode, val);
2738 }
2739
2740
2741 /****************************************************************************/
2742 /* Halts the RISC processor.                                                */
2743 /*                                                                          */
2744 /* Returns:                                                                 */
2745 /*   Nothing.                                                               */
2746 /****************************************************************************/
2747 static void
2748 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2749 {
2750         uint32_t val;
2751
2752         /* Halt the CPU. */
2753         val = REG_RD_IND(sc, cpu_reg->mode);
2754         val |= cpu_reg->mode_value_halt;
2755         REG_WR_IND(sc, cpu_reg->mode, val);
2756         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2757 }
2758
2759
2760 /****************************************************************************/
2761 /* Start the RX CPU.                                                        */
2762 /*                                                                          */
2763 /* Returns:                                                                 */
2764 /*   Nothing.                                                               */
2765 /****************************************************************************/
2766 static void
2767 bce_start_rxp_cpu(struct bce_softc *sc)
2768 {
2769         struct cpu_reg cpu_reg;
2770
2771         cpu_reg.mode = BCE_RXP_CPU_MODE;
2772         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2773         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2774         cpu_reg.state = BCE_RXP_CPU_STATE;
2775         cpu_reg.state_value_clear = 0xffffff;
2776         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2777         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2778         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2779         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2780         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2781         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2782         cpu_reg.mips_view_base = 0x8000000;
2783
2784         bce_start_cpu(sc, &cpu_reg);
2785 }
2786
2787
2788 /****************************************************************************/
2789 /* Initialize the RX CPU.                                                   */
2790 /*                                                                          */
2791 /* Returns:                                                                 */
2792 /*   Nothing.                                                               */
2793 /****************************************************************************/
2794 static void
2795 bce_init_rxp_cpu(struct bce_softc *sc)
2796 {
2797         struct cpu_reg cpu_reg;
2798         struct fw_info fw;
2799
2800         cpu_reg.mode = BCE_RXP_CPU_MODE;
2801         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2802         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2803         cpu_reg.state = BCE_RXP_CPU_STATE;
2804         cpu_reg.state_value_clear = 0xffffff;
2805         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2806         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2807         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2808         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2809         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2810         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2811         cpu_reg.mips_view_base = 0x8000000;
2812
2813         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2814             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2815                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2816                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2817                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2818                 fw.start_addr = bce_RXP_b09FwStartAddr;
2819
2820                 fw.text_addr = bce_RXP_b09FwTextAddr;
2821                 fw.text_len = bce_RXP_b09FwTextLen;
2822                 fw.text_index = 0;
2823                 fw.text = bce_RXP_b09FwText;
2824
2825                 fw.data_addr = bce_RXP_b09FwDataAddr;
2826                 fw.data_len = bce_RXP_b09FwDataLen;
2827                 fw.data_index = 0;
2828                 fw.data = bce_RXP_b09FwData;
2829
2830                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2831                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2832                 fw.sbss_index = 0;
2833                 fw.sbss = bce_RXP_b09FwSbss;
2834
2835                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2836                 fw.bss_len = bce_RXP_b09FwBssLen;
2837                 fw.bss_index = 0;
2838                 fw.bss = bce_RXP_b09FwBss;
2839
2840                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2841                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2842                 fw.rodata_index = 0;
2843                 fw.rodata = bce_RXP_b09FwRodata;
2844         } else {
2845                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2846                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2847                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2848                 fw.start_addr = bce_RXP_b06FwStartAddr;
2849
2850                 fw.text_addr = bce_RXP_b06FwTextAddr;
2851                 fw.text_len = bce_RXP_b06FwTextLen;
2852                 fw.text_index = 0;
2853                 fw.text = bce_RXP_b06FwText;
2854
2855                 fw.data_addr = bce_RXP_b06FwDataAddr;
2856                 fw.data_len = bce_RXP_b06FwDataLen;
2857                 fw.data_index = 0;
2858                 fw.data = bce_RXP_b06FwData;
2859
2860                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2861                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2862                 fw.sbss_index = 0;
2863                 fw.sbss = bce_RXP_b06FwSbss;
2864
2865                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2866                 fw.bss_len = bce_RXP_b06FwBssLen;
2867                 fw.bss_index = 0;
2868                 fw.bss = bce_RXP_b06FwBss;
2869
2870                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2871                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2872                 fw.rodata_index = 0;
2873                 fw.rodata = bce_RXP_b06FwRodata;
2874         }
2875
2876         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2877         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2878         /* Delay RXP start until initialization is complete. */
2879 }
2880
2881
2882 /****************************************************************************/
2883 /* Initialize the TX CPU.                                                   */
2884 /*                                                                          */
2885 /* Returns:                                                                 */
2886 /*   Nothing.                                                               */
2887 /****************************************************************************/
2888 static void
2889 bce_init_txp_cpu(struct bce_softc *sc)
2890 {
2891         struct cpu_reg cpu_reg;
2892         struct fw_info fw;
2893
2894         cpu_reg.mode = BCE_TXP_CPU_MODE;
2895         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2896         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2897         cpu_reg.state = BCE_TXP_CPU_STATE;
2898         cpu_reg.state_value_clear = 0xffffff;
2899         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2900         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2901         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2902         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2903         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2904         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2905         cpu_reg.mips_view_base = 0x8000000;
2906
2907         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2908             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2909                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2910                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2911                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2912                 fw.start_addr = bce_TXP_b09FwStartAddr;
2913
2914                 fw.text_addr = bce_TXP_b09FwTextAddr;
2915                 fw.text_len = bce_TXP_b09FwTextLen;
2916                 fw.text_index = 0;
2917                 fw.text = bce_TXP_b09FwText;
2918
2919                 fw.data_addr = bce_TXP_b09FwDataAddr;
2920                 fw.data_len = bce_TXP_b09FwDataLen;
2921                 fw.data_index = 0;
2922                 fw.data = bce_TXP_b09FwData;
2923
2924                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2925                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2926                 fw.sbss_index = 0;
2927                 fw.sbss = bce_TXP_b09FwSbss;
2928
2929                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2930                 fw.bss_len = bce_TXP_b09FwBssLen;
2931                 fw.bss_index = 0;
2932                 fw.bss = bce_TXP_b09FwBss;
2933
2934                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2935                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2936                 fw.rodata_index = 0;
2937                 fw.rodata = bce_TXP_b09FwRodata;
2938         } else {
2939                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2940                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2941                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2942                 fw.start_addr = bce_TXP_b06FwStartAddr;
2943
2944                 fw.text_addr = bce_TXP_b06FwTextAddr;
2945                 fw.text_len = bce_TXP_b06FwTextLen;
2946                 fw.text_index = 0;
2947                 fw.text = bce_TXP_b06FwText;
2948
2949                 fw.data_addr = bce_TXP_b06FwDataAddr;
2950                 fw.data_len = bce_TXP_b06FwDataLen;
2951                 fw.data_index = 0;
2952                 fw.data = bce_TXP_b06FwData;
2953
2954                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2955                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2956                 fw.sbss_index = 0;
2957                 fw.sbss = bce_TXP_b06FwSbss;
2958
2959                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2960                 fw.bss_len = bce_TXP_b06FwBssLen;
2961                 fw.bss_index = 0;
2962                 fw.bss = bce_TXP_b06FwBss;
2963
2964                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2965                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2966                 fw.rodata_index = 0;
2967                 fw.rodata = bce_TXP_b06FwRodata;
2968         }
2969
2970         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2971         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2972         bce_start_cpu(sc, &cpu_reg);
2973 }
2974
2975
2976 /****************************************************************************/
2977 /* Initialize the TPAT CPU.                                                 */
2978 /*                                                                          */
2979 /* Returns:                                                                 */
2980 /*   Nothing.                                                               */
2981 /****************************************************************************/
2982 static void
2983 bce_init_tpat_cpu(struct bce_softc *sc)
2984 {
2985         struct cpu_reg cpu_reg;
2986         struct fw_info fw;
2987
2988         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2989         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2990         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2991         cpu_reg.state = BCE_TPAT_CPU_STATE;
2992         cpu_reg.state_value_clear = 0xffffff;
2993         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2994         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2995         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2996         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2997         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2998         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2999         cpu_reg.mips_view_base = 0x8000000;
3000
3001         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3002             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3003                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
3004                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
3005                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
3006                 fw.start_addr = bce_TPAT_b09FwStartAddr;
3007
3008                 fw.text_addr = bce_TPAT_b09FwTextAddr;
3009                 fw.text_len = bce_TPAT_b09FwTextLen;
3010                 fw.text_index = 0;
3011                 fw.text = bce_TPAT_b09FwText;
3012
3013                 fw.data_addr = bce_TPAT_b09FwDataAddr;
3014                 fw.data_len = bce_TPAT_b09FwDataLen;
3015                 fw.data_index = 0;
3016                 fw.data = bce_TPAT_b09FwData;
3017
3018                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3019                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
3020                 fw.sbss_index = 0;
3021                 fw.sbss = bce_TPAT_b09FwSbss;
3022
3023                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
3024                 fw.bss_len = bce_TPAT_b09FwBssLen;
3025                 fw.bss_index = 0;
3026                 fw.bss = bce_TPAT_b09FwBss;
3027
3028                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3029                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
3030                 fw.rodata_index = 0;
3031                 fw.rodata = bce_TPAT_b09FwRodata;
3032         } else {
3033                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3034                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3035                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3036                 fw.start_addr = bce_TPAT_b06FwStartAddr;
3037
3038                 fw.text_addr = bce_TPAT_b06FwTextAddr;
3039                 fw.text_len = bce_TPAT_b06FwTextLen;
3040                 fw.text_index = 0;
3041                 fw.text = bce_TPAT_b06FwText;
3042
3043                 fw.data_addr = bce_TPAT_b06FwDataAddr;
3044                 fw.data_len = bce_TPAT_b06FwDataLen;
3045                 fw.data_index = 0;
3046                 fw.data = bce_TPAT_b06FwData;
3047
3048                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3049                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3050                 fw.sbss_index = 0;
3051                 fw.sbss = bce_TPAT_b06FwSbss;
3052
3053                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3054                 fw.bss_len = bce_TPAT_b06FwBssLen;
3055                 fw.bss_index = 0;
3056                 fw.bss = bce_TPAT_b06FwBss;
3057
3058                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3059                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3060                 fw.rodata_index = 0;
3061                 fw.rodata = bce_TPAT_b06FwRodata;
3062         }
3063
3064         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3065         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3066         bce_start_cpu(sc, &cpu_reg);
3067 }
3068
3069
3070 /****************************************************************************/
3071 /* Initialize the CP CPU.                                                   */
3072 /*                                                                          */
3073 /* Returns:                                                                 */
3074 /*   Nothing.                                                               */
3075 /****************************************************************************/
3076 static void
3077 bce_init_cp_cpu(struct bce_softc *sc)
3078 {
3079         struct cpu_reg cpu_reg;
3080         struct fw_info fw;
3081
3082         cpu_reg.mode = BCE_CP_CPU_MODE;
3083         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3084         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3085         cpu_reg.state = BCE_CP_CPU_STATE;
3086         cpu_reg.state_value_clear = 0xffffff;
3087         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3088         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3089         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3090         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3091         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3092         cpu_reg.spad_base = BCE_CP_SCRATCH;
3093         cpu_reg.mips_view_base = 0x8000000;
3094
3095         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3096             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3097                 fw.ver_major = bce_CP_b09FwReleaseMajor;
3098                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3099                 fw.ver_fix = bce_CP_b09FwReleaseFix;
3100                 fw.start_addr = bce_CP_b09FwStartAddr;
3101
3102                 fw.text_addr = bce_CP_b09FwTextAddr;
3103                 fw.text_len = bce_CP_b09FwTextLen;
3104                 fw.text_index = 0;
3105                 fw.text = bce_CP_b09FwText;
3106
3107                 fw.data_addr = bce_CP_b09FwDataAddr;
3108                 fw.data_len = bce_CP_b09FwDataLen;
3109                 fw.data_index = 0;
3110                 fw.data = bce_CP_b09FwData;
3111
3112                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3113                 fw.sbss_len = bce_CP_b09FwSbssLen;
3114                 fw.sbss_index = 0;
3115                 fw.sbss = bce_CP_b09FwSbss;
3116
3117                 fw.bss_addr = bce_CP_b09FwBssAddr;
3118                 fw.bss_len = bce_CP_b09FwBssLen;
3119                 fw.bss_index = 0;
3120                 fw.bss = bce_CP_b09FwBss;
3121
3122                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3123                 fw.rodata_len = bce_CP_b09FwRodataLen;
3124                 fw.rodata_index = 0;
3125                 fw.rodata = bce_CP_b09FwRodata;
3126         } else {
3127                 fw.ver_major = bce_CP_b06FwReleaseMajor;
3128                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3129                 fw.ver_fix = bce_CP_b06FwReleaseFix;
3130                 fw.start_addr = bce_CP_b06FwStartAddr;
3131
3132                 fw.text_addr = bce_CP_b06FwTextAddr;
3133                 fw.text_len = bce_CP_b06FwTextLen;
3134                 fw.text_index = 0;
3135                 fw.text = bce_CP_b06FwText;
3136
3137                 fw.data_addr = bce_CP_b06FwDataAddr;
3138                 fw.data_len = bce_CP_b06FwDataLen;
3139                 fw.data_index = 0;
3140                 fw.data = bce_CP_b06FwData;
3141
3142                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3143                 fw.sbss_len = bce_CP_b06FwSbssLen;
3144                 fw.sbss_index = 0;
3145                 fw.sbss = bce_CP_b06FwSbss;
3146
3147                 fw.bss_addr = bce_CP_b06FwBssAddr;
3148                 fw.bss_len = bce_CP_b06FwBssLen;
3149                 fw.bss_index = 0;
3150                 fw.bss = bce_CP_b06FwBss;
3151
3152                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3153                 fw.rodata_len = bce_CP_b06FwRodataLen;
3154                 fw.rodata_index = 0;
3155                 fw.rodata = bce_CP_b06FwRodata;
3156         }
3157
3158         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3159         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3160         bce_start_cpu(sc, &cpu_reg);
3161 }
3162
3163
3164 /****************************************************************************/
3165 /* Initialize the COM CPU.                                                 */
3166 /*                                                                          */
3167 /* Returns:                                                                 */
3168 /*   Nothing.                                                               */
3169 /****************************************************************************/
3170 static void
3171 bce_init_com_cpu(struct bce_softc *sc)
3172 {
3173         struct cpu_reg cpu_reg;
3174         struct fw_info fw;
3175
3176         cpu_reg.mode = BCE_COM_CPU_MODE;
3177         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3178         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3179         cpu_reg.state = BCE_COM_CPU_STATE;
3180         cpu_reg.state_value_clear = 0xffffff;
3181         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3182         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3183         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3184         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3185         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3186         cpu_reg.spad_base = BCE_COM_SCRATCH;
3187         cpu_reg.mips_view_base = 0x8000000;
3188
3189         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3190             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3191                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3192                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3193                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3194                 fw.start_addr = bce_COM_b09FwStartAddr;
3195
3196                 fw.text_addr = bce_COM_b09FwTextAddr;
3197                 fw.text_len = bce_COM_b09FwTextLen;
3198                 fw.text_index = 0;
3199                 fw.text = bce_COM_b09FwText;
3200
3201                 fw.data_addr = bce_COM_b09FwDataAddr;
3202                 fw.data_len = bce_COM_b09FwDataLen;
3203                 fw.data_index = 0;
3204                 fw.data = bce_COM_b09FwData;
3205
3206                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3207                 fw.sbss_len = bce_COM_b09FwSbssLen;
3208                 fw.sbss_index = 0;
3209                 fw.sbss = bce_COM_b09FwSbss;
3210
3211                 fw.bss_addr = bce_COM_b09FwBssAddr;
3212                 fw.bss_len = bce_COM_b09FwBssLen;
3213                 fw.bss_index = 0;
3214                 fw.bss = bce_COM_b09FwBss;
3215
3216                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3217                 fw.rodata_len = bce_COM_b09FwRodataLen;
3218                 fw.rodata_index = 0;
3219                 fw.rodata = bce_COM_b09FwRodata;
3220         } else {
3221                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3222                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3223                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3224                 fw.start_addr = bce_COM_b06FwStartAddr;
3225
3226                 fw.text_addr = bce_COM_b06FwTextAddr;
3227                 fw.text_len = bce_COM_b06FwTextLen;
3228                 fw.text_index = 0;
3229                 fw.text = bce_COM_b06FwText;
3230
3231                 fw.data_addr = bce_COM_b06FwDataAddr;
3232                 fw.data_len = bce_COM_b06FwDataLen;
3233                 fw.data_index = 0;
3234                 fw.data = bce_COM_b06FwData;
3235
3236                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3237                 fw.sbss_len = bce_COM_b06FwSbssLen;
3238                 fw.sbss_index = 0;
3239                 fw.sbss = bce_COM_b06FwSbss;
3240
3241                 fw.bss_addr = bce_COM_b06FwBssAddr;
3242                 fw.bss_len = bce_COM_b06FwBssLen;
3243                 fw.bss_index = 0;
3244                 fw.bss = bce_COM_b06FwBss;
3245
3246                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3247                 fw.rodata_len = bce_COM_b06FwRodataLen;
3248                 fw.rodata_index = 0;
3249                 fw.rodata = bce_COM_b06FwRodata;
3250         }
3251
3252         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3253         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3254         bce_start_cpu(sc, &cpu_reg);
3255 }
3256
3257
3258 /****************************************************************************/
3259 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3260 /*                                                                          */
3261 /* Loads the firmware for each CPU and starts the CPU.                      */
3262 /*                                                                          */
3263 /* Returns:                                                                 */
3264 /*   Nothing.                                                               */
3265 /****************************************************************************/
3266 static void
3267 bce_init_cpus(struct bce_softc *sc)
3268 {
3269         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3270             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3271                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3272                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3273                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3274                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3275                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3276                 } else {
3277                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3278                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3279                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3280                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3281                 }
3282         } else {
3283                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3284                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3285                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3286                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3287         }
3288
3289         bce_init_rxp_cpu(sc);
3290         bce_init_txp_cpu(sc);
3291         bce_init_tpat_cpu(sc);
3292         bce_init_com_cpu(sc);
3293         bce_init_cp_cpu(sc);
3294 }
3295
3296
3297 /****************************************************************************/
3298 /* Initialize context memory.                                               */
3299 /*                                                                          */
3300 /* Clears the memory associated with each Context ID (CID).                 */
3301 /*                                                                          */
3302 /* Returns:                                                                 */
3303 /*   Nothing.                                                               */
3304 /****************************************************************************/
3305 static int
3306 bce_init_ctx(struct bce_softc *sc)
3307 {
3308         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3309             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3310                 /* DRC: Replace this constant value with a #define. */
3311                 int i, retry_cnt = 10;
3312                 uint32_t val;
3313
3314                 /*
3315                  * BCM5709 context memory may be cached
3316                  * in host memory so prepare the host memory
3317                  * for access.
3318                  */
3319                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3320                     (1 << 12);
3321                 val |= (BCM_PAGE_BITS - 8) << 16;
3322                 REG_WR(sc, BCE_CTX_COMMAND, val);
3323
3324                 /* Wait for mem init command to complete. */
3325                 for (i = 0; i < retry_cnt; i++) {
3326                         val = REG_RD(sc, BCE_CTX_COMMAND);
3327                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3328                                 break;
3329                         DELAY(2);
3330                 }
3331                 if (i == retry_cnt) {
3332                         device_printf(sc->bce_dev,
3333                             "Context memory initialization failed!\n");
3334                         return ETIMEDOUT;
3335                 }
3336
3337                 for (i = 0; i < sc->ctx_pages; i++) {
3338                         int j;
3339
3340                         /*
3341                          * Set the physical address of the context
3342                          * memory cache.
3343                          */
3344                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3345                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3346                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3347                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3348                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3349                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3350                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3351
3352                         /*
3353                          * Verify that the context memory write was successful.
3354                          */
3355                         for (j = 0; j < retry_cnt; j++) {
3356                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3357                                 if ((val &
3358                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3359                                         break;
3360                                 DELAY(5);
3361                         }
3362                         if (j == retry_cnt) {
3363                                 device_printf(sc->bce_dev,
3364                                     "Failed to initialize context page!\n");
3365                                 return ETIMEDOUT;
3366                         }
3367                 }
3368         } else {
3369                 uint32_t vcid_addr, offset;
3370
3371                 /*
3372                  * For the 5706/5708, context memory is local to
3373                  * the controller, so initialize the controller
3374                  * context memory.
3375                  */
3376
3377                 vcid_addr = GET_CID_ADDR(96);
3378                 while (vcid_addr) {
3379                         vcid_addr -= PHY_CTX_SIZE;
3380
3381                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3382                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3383
3384                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3385                                 CTX_WR(sc, 0x00, offset, 0);
3386
3387                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3388                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3389                 }
3390         }
3391         return 0;
3392 }
3393
3394
3395 /****************************************************************************/
3396 /* Fetch the permanent MAC address of the controller.                       */
3397 /*                                                                          */
3398 /* Returns:                                                                 */
3399 /*   Nothing.                                                               */
3400 /****************************************************************************/
3401 static void
3402 bce_get_mac_addr(struct bce_softc *sc)
3403 {
3404         uint32_t mac_lo = 0, mac_hi = 0;
3405
3406         /*
3407          * The NetXtreme II bootcode populates various NIC
3408          * power-on and runtime configuration items in a
3409          * shared memory area.  The factory configured MAC
3410          * address is available from both NVRAM and the
3411          * shared memory area so we'll read the value from
3412          * shared memory for speed.
3413          */
3414
3415         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3416         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3417
3418         if (mac_lo == 0 && mac_hi == 0) {
3419                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3420         } else {
3421                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3422                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3423                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3424                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3425                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3426                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3427         }
3428
3429         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3430 }
3431
3432
3433 /****************************************************************************/
3434 /* Program the MAC address.                                                 */
3435 /*                                                                          */
3436 /* Returns:                                                                 */
3437 /*   Nothing.                                                               */
3438 /****************************************************************************/
3439 static void
3440 bce_set_mac_addr(struct bce_softc *sc)
3441 {
3442         const uint8_t *mac_addr = sc->eaddr;
3443         uint32_t val;
3444
3445         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3446                 sc->eaddr, ":");
3447
3448         val = (mac_addr[0] << 8) | mac_addr[1];
3449         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3450
3451         val = (mac_addr[2] << 24) |
3452               (mac_addr[3] << 16) |
3453               (mac_addr[4] << 8) |
3454               mac_addr[5];
3455         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3456 }
3457
3458
3459 /****************************************************************************/
3460 /* Stop the controller.                                                     */
3461 /*                                                                          */
3462 /* Returns:                                                                 */
3463 /*   Nothing.                                                               */
3464 /****************************************************************************/
3465 static void
3466 bce_stop(struct bce_softc *sc)
3467 {
3468         struct ifnet *ifp = &sc->arpcom.ac_if;
3469
3470         ASSERT_SERIALIZED(ifp->if_serializer);
3471
3472         callout_stop(&sc->bce_tick_callout);
3473
3474         /* Disable the transmit/receive blocks. */
3475         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3476         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3477         DELAY(20);
3478
3479         bce_disable_intr(sc);
3480
3481         /* Free the RX lists. */
3482         bce_free_rx_chain(sc);
3483
3484         /* Free TX buffers. */
3485         bce_free_tx_chain(sc);
3486
3487         sc->bce_link = 0;
3488         sc->bce_coalchg_mask = 0;
3489
3490         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3491         ifp->if_timer = 0;
3492 }
3493
3494
3495 static int
3496 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3497 {
3498         uint32_t val;
3499         int i, rc = 0;
3500
3501         /* Wait for pending PCI transactions to complete. */
3502         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3503                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3504                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3505                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3506                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3507         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3508         DELAY(5);
3509
3510         /* Disable DMA */
3511         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3512             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3513                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3514                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3515                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3516         }
3517
3518         /* Assume bootcode is running. */
3519         sc->bce_fw_timed_out = 0;
3520         sc->bce_drv_cardiac_arrest = 0;
3521
3522         /* Give the firmware a chance to prepare for the reset. */
3523         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3524         if (rc) {
3525                 if_printf(&sc->arpcom.ac_if,
3526                           "Firmware is not ready for reset\n");
3527                 return rc;
3528         }
3529
3530         /* Set a firmware reminder that this is a soft reset. */
3531         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3532             BCE_DRV_RESET_SIGNATURE_MAGIC);
3533
3534         /* Dummy read to force the chip to complete all current transactions. */
3535         val = REG_RD(sc, BCE_MISC_ID);
3536
3537         /* Chip reset. */
3538         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3539             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3540                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3541                 REG_RD(sc, BCE_MISC_COMMAND);
3542                 DELAY(5);
3543
3544                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3545                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3546
3547                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3548         } else {
3549                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3550                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3551                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3552                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3553
3554                 /* Allow up to 30us for reset to complete. */
3555                 for (i = 0; i < 10; i++) {
3556                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3557                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3558                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3559                                 break;
3560                         DELAY(10);
3561                 }
3562
3563                 /* Check that reset completed successfully. */
3564                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3565                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3566                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3567                         return EBUSY;
3568                 }
3569         }
3570
3571         /* Make sure byte swapping is properly configured. */
3572         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3573         if (val != 0x01020304) {
3574                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3575                 return ENODEV;
3576         }
3577
3578         /* Just completed a reset, assume that firmware is running again. */
3579         sc->bce_fw_timed_out = 0;
3580         sc->bce_drv_cardiac_arrest = 0;
3581
3582         /* Wait for the firmware to finish its initialization. */
3583         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3584         if (rc) {
3585                 if_printf(&sc->arpcom.ac_if,
3586                           "Firmware did not complete initialization!\n");
3587         }
3588         return rc;
3589 }
3590
3591
3592 static int
3593 bce_chipinit(struct bce_softc *sc)
3594 {
3595         uint32_t val;
3596         int rc = 0;
3597
3598         /* Make sure the interrupt is not active. */
3599         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3600         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3601
3602         /*
3603          * Initialize DMA byte/word swapping, configure the number of DMA
3604          * channels and PCI clock compensation delay.
3605          */
3606         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3607               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3608 #if BYTE_ORDER == BIG_ENDIAN
3609               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3610 #endif
3611               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3612               DMA_READ_CHANS << 12 |
3613               DMA_WRITE_CHANS << 16;
3614
3615         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3616
3617         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3618                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3619
3620         /*
3621          * This setting resolves a problem observed on certain Intel PCI
3622          * chipsets that cannot handle multiple outstanding DMA operations.
3623          * See errata E9_5706A1_65.
3624          */
3625         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3626             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3627             !(sc->bce_flags & BCE_PCIX_FLAG))
3628                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3629
3630         REG_WR(sc, BCE_DMA_CONFIG, val);
3631
3632         /* Enable the RX_V2P and Context state machines before access. */
3633         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3634                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3635                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3636                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3637
3638         /* Initialize context mapping and zero out the quick contexts. */
3639         rc = bce_init_ctx(sc);
3640         if (rc != 0)
3641                 return rc;
3642
3643         /* Initialize the on-boards CPUs */
3644         bce_init_cpus(sc);
3645
3646         /* Enable management frames (NC-SI) to flow to the MCP. */
3647         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3648                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3649                     BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3650                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3651         }
3652
3653         /* Prepare NVRAM for access. */
3654         rc = bce_init_nvram(sc);
3655         if (rc != 0)
3656                 return rc;
3657
3658         /* Set the kernel bypass block size */
3659         val = REG_RD(sc, BCE_MQ_CONFIG);
3660         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3661         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3662
3663         /* Enable bins used on the 5709/5716. */
3664         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3665             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3666                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3667                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3668                         val |= BCE_MQ_CONFIG_HALT_DIS;
3669         }
3670
3671         REG_WR(sc, BCE_MQ_CONFIG, val);
3672
3673         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3674         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3675         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3676
3677         /* Set the page size and clear the RV2P processor stall bits. */
3678         val = (BCM_PAGE_BITS - 8) << 24;
3679         REG_WR(sc, BCE_RV2P_CONFIG, val);
3680
3681         /* Configure page size. */
3682         val = REG_RD(sc, BCE_TBDR_CONFIG);
3683         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;