2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <machine/globaldata.h>
34 #include <machine/smp.h>
35 #include <machine/cputypes.h>
36 #include <machine/md_var.h>
37 #include <machine/pmap.h>
38 #include <machine_base/apic/mpapic.h>
39 #include <machine_base/apic/ioapic_abi.h>
40 #include <machine/segments.h>
41 #include <sys/thread2.h>
43 #include <machine/intr_machdep.h>
45 #define IOAPIC_COUNT_MAX 16
46 #define IOAPIC_ID_MASK (IOAPIC_COUNT_MAX - 1)
49 extern pt_entry_t *SMPpt;
51 /* EISA Edge/Level trigger control registers */
52 #define ELCR0 0x4d0 /* eisa irq 0-7 */
53 #define ELCR1 0x4d1 /* eisa irq 8-15 */
62 TAILQ_ENTRY(ioapic_info) io_link;
64 TAILQ_HEAD(ioapic_info_list, ioapic_info);
66 struct ioapic_intsrc {
68 enum intr_trigger int_trig;
69 enum intr_polarity int_pola;
73 struct ioapic_info_list ioc_list;
74 struct ioapic_intsrc ioc_intsrc[16]; /* XXX magic number */
77 static void lapic_timer_calibrate(void);
78 static void lapic_timer_set_divisor(int);
79 static void lapic_timer_fixup_handler(void *);
80 static void lapic_timer_restart_handler(void *);
82 void lapic_timer_process(void);
83 void lapic_timer_process_frame(struct intrframe *);
85 static int lapic_timer_enable = 1;
86 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
88 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
89 static void lapic_timer_intr_enable(struct cputimer_intr *);
90 static void lapic_timer_intr_restart(struct cputimer_intr *);
91 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
93 static int lapic_unused_apic_id(int);
95 static void ioapic_setup(const struct ioapic_info *);
96 static int ioapic_alloc_apic_id(int);
97 static void ioapic_set_apic_id(const struct ioapic_info *);
98 static void ioapic_gsi_setup(int);
99 static const struct ioapic_info *
100 ioapic_gsi_search(int);
101 static void ioapic_pin_prog(void *, int, int,
102 enum intr_trigger, enum intr_polarity, uint32_t);
104 static struct cputimer_intr lapic_cputimer_intr = {
106 .reload = lapic_timer_intr_reload,
107 .enable = lapic_timer_intr_enable,
108 .config = cputimer_intr_default_config,
109 .restart = lapic_timer_intr_restart,
110 .pmfixup = lapic_timer_intr_pmfixup,
111 .initclock = cputimer_intr_default_initclock,
112 .next = SLIST_ENTRY_INITIALIZER,
114 .type = CPUTIMER_INTR_LAPIC,
115 .prio = CPUTIMER_INTR_PRIO_LAPIC,
116 .caps = CPUTIMER_INTR_CAP_NONE
120 * pointers to pmapped apic hardware.
123 volatile ioapic_t **ioapic;
125 static int lapic_timer_divisor_idx = -1;
126 static const uint32_t lapic_timer_divisors[] = {
127 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
128 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
130 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
134 static struct ioapic_conf ioapic_conf;
137 * Enable LAPIC, configure interrupts.
140 lapic_init(boolean_t bsp)
148 * Since IDT is shared between BSP and APs, these vectors
149 * only need to be installed once; we do it on BSP.
152 /* Install a 'Spurious INTerrupt' vector */
153 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
154 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
156 /* Install an inter-CPU IPI for TLB invalidation */
157 setidt(XINVLTLB_OFFSET, Xinvltlb,
158 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
160 /* Install an inter-CPU IPI for IPIQ messaging */
161 setidt(XIPIQ_OFFSET, Xipiq,
162 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
164 /* Install a timer vector */
165 setidt(XTIMER_OFFSET, Xtimer,
166 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
168 /* Install an inter-CPU IPI for CPU stop/restart */
169 setidt(XCPUSTOP_OFFSET, Xcpustop,
170 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
174 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
175 * aggregate interrupt input from the 8259. The INTA cycle
176 * will be routed to the external controller (the 8259) which
177 * is expected to supply the vector.
179 * Must be setup edge triggered, active high.
181 * Disable LINT0 on BSP, if I/O APIC is enabled.
183 * Disable LINT0 on the APs. It doesn't matter what delivery
184 * mode we use because we leave it masked.
186 temp = lapic.lvt_lint0;
187 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
188 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
190 temp |= APIC_LVT_DM_EXTINT;
192 temp |= APIC_LVT_MASKED;
194 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
196 lapic.lvt_lint0 = temp;
199 * Setup LINT1 as NMI.
201 * Must be setup edge trigger, active high.
203 * Enable LINT1 on BSP, if I/O APIC is enabled.
205 * Disable LINT1 on the APs.
207 temp = lapic.lvt_lint1;
208 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
209 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
210 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
211 if (bsp && apic_io_enable)
212 temp &= ~APIC_LVT_MASKED;
213 lapic.lvt_lint1 = temp;
216 * Mask the LAPIC error interrupt, LAPIC performance counter
219 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
220 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
223 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
225 timer = lapic.lvt_timer;
226 timer &= ~APIC_LVTT_VECTOR;
227 timer |= XTIMER_OFFSET;
228 timer |= APIC_LVTT_MASKED;
229 lapic.lvt_timer = timer;
232 * Set the Task Priority Register as needed. At the moment allow
233 * interrupts on all cpus (the APs will remain CLId until they are
234 * ready to deal). We could disable all but IPIs by setting
235 * temp |= TPR_IPI for cpu != 0.
238 temp &= ~APIC_TPR_PRIO; /* clear priority field */
239 #ifdef SMP /* APIC-IO */
240 if (!apic_io_enable) {
243 * If we are NOT running the IO APICs, the LAPIC will only be used
244 * for IPIs. Set the TPR to prevent any unintentional interrupts.
247 #ifdef SMP /* APIC-IO */
257 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
258 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
261 * Set the spurious interrupt vector. The low 4 bits of the vector
264 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
265 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
266 temp &= ~APIC_SVR_VECTOR;
267 temp |= XSPURIOUSINT_OFFSET;
272 * Pump out a few EOIs to clean out interrupts that got through
273 * before we were able to set the TPR.
280 lapic_timer_calibrate();
281 if (lapic_timer_enable) {
282 cputimer_intr_register(&lapic_cputimer_intr);
283 cputimer_intr_select(&lapic_cputimer_intr, 0);
286 lapic_timer_set_divisor(lapic_timer_divisor_idx);
290 apic_dump("apic_initialize()");
294 lapic_timer_set_divisor(int divisor_idx)
296 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
297 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
301 lapic_timer_oneshot(u_int count)
305 value = lapic.lvt_timer;
306 value &= ~APIC_LVTT_PERIODIC;
307 lapic.lvt_timer = value;
308 lapic.icr_timer = count;
312 lapic_timer_oneshot_quick(u_int count)
314 lapic.icr_timer = count;
318 lapic_timer_calibrate(void)
322 /* Try to calibrate the local APIC timer. */
323 for (lapic_timer_divisor_idx = 0;
324 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
325 lapic_timer_divisor_idx++) {
326 lapic_timer_set_divisor(lapic_timer_divisor_idx);
327 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
329 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
330 if (value != APIC_TIMER_MAX_COUNT)
333 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
334 panic("lapic: no proper timer divisor?!\n");
335 lapic_cputimer_intr.freq = value / 2;
337 kprintf("lapic: divisor index %d, frequency %u Hz\n",
338 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
342 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
346 gd->gd_timer_running = 0;
348 count = sys_cputimer->count();
349 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
350 systimer_intr(&count, 0, frame);
354 lapic_timer_process(void)
356 lapic_timer_process_oncpu(mycpu, NULL);
360 lapic_timer_process_frame(struct intrframe *frame)
362 lapic_timer_process_oncpu(mycpu, frame);
366 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
368 struct globaldata *gd = mycpu;
370 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
374 if (gd->gd_timer_running) {
375 if (reload < lapic.ccr_timer)
376 lapic_timer_oneshot_quick(reload);
378 gd->gd_timer_running = 1;
379 lapic_timer_oneshot_quick(reload);
384 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
388 timer = lapic.lvt_timer;
389 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
390 lapic.lvt_timer = timer;
392 lapic_timer_fixup_handler(NULL);
396 lapic_timer_fixup_handler(void *arg)
403 if (cpu_vendor_id == CPU_VENDOR_AMD) {
405 * Detect the presence of C1E capability mostly on latest
406 * dual-cores (or future) k8 family. This feature renders
407 * the local APIC timer dead, so we disable it by reading
408 * the Interrupt Pending Message register and clearing both
409 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
412 * "BIOS and Kernel Developer's Guide for AMD NPT
413 * Family 0Fh Processors"
414 * #32559 revision 3.00
416 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
417 (cpu_id & 0x0fff0000) >= 0x00040000) {
420 msr = rdmsr(0xc0010055);
421 if (msr & 0x18000000) {
422 struct globaldata *gd = mycpu;
424 kprintf("cpu%d: AMD C1E detected\n",
426 wrmsr(0xc0010055, msr & ~0x18000000ULL);
429 * We are kinda stalled;
432 gd->gd_timer_running = 1;
433 lapic_timer_oneshot_quick(2);
443 lapic_timer_restart_handler(void *dummy __unused)
447 lapic_timer_fixup_handler(&started);
449 struct globaldata *gd = mycpu;
451 gd->gd_timer_running = 1;
452 lapic_timer_oneshot_quick(2);
457 * This function is called only by ACPI-CA code currently:
458 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
459 * module controls PM. So once ACPI-CA is attached, we try
460 * to apply the fixup to prevent LAPIC timer from hanging.
463 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
465 lwkt_send_ipiq_mask(smp_active_mask,
466 lapic_timer_fixup_handler, NULL);
470 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
472 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
477 * dump contents of local APIC registers
482 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
483 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
484 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
488 #ifdef SMP /* APIC-IO */
494 #define IOAPIC_ISA_INTS 16
495 #define REDIRCNT_IOAPIC(A) \
496 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
498 static int trigger (int apic, int pin, u_int32_t * flags);
499 static void polarity (int apic, int pin, u_int32_t * flags, int level);
501 #define DEFAULT_FLAGS \
507 #define DEFAULT_ISA_FLAGS \
516 io_apic_set_id(int apic, int id)
520 ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* get current contents */
521 if (((ux & APIC_ID_MASK) >> 24) != id) {
522 kprintf("Changing APIC ID for IO APIC #%d"
523 " from %d to %d on chip\n",
524 apic, ((ux & APIC_ID_MASK) >> 24), id);
525 ux &= ~APIC_ID_MASK; /* clear the ID field */
527 ioapic_write(ioapic[apic], IOAPIC_ID, ux); /* write new value */
528 ux = ioapic_read(ioapic[apic], IOAPIC_ID); /* re-read && test */
529 if (((ux & APIC_ID_MASK) >> 24) != id)
530 panic("can't control IO APIC #%d ID, reg: 0x%08x",
537 io_apic_get_id(int apic)
539 return (ioapic_read(ioapic[apic], IOAPIC_ID) & APIC_ID_MASK) >> 24;
548 io_apic_setup_intpin(int apic, int pin)
550 int bus, bustype, irq;
551 u_char select; /* the select register is 8 bits */
552 u_int32_t flags; /* the window register is 32 bits */
553 u_int32_t target; /* the window register is 32 bits */
554 u_int32_t vector; /* the window register is 32 bits */
559 select = pin * 2 + IOAPIC_REDTBL0; /* register */
562 * Always clear an IO APIC pin before [re]programming it. This is
563 * particularly important if the pin is set up for a level interrupt
564 * as the IOART_REM_IRR bit might be set. When we reprogram the
565 * vector any EOI from pending ints on this pin could be lost and
566 * IRR might never get reset.
568 * To fix this problem, clear the vector and make sure it is
569 * programmed as an edge interrupt. This should theoretically
570 * clear IRR so we can later, safely program it as a level
575 flags = ioapic_read(ioapic[apic], select) & IOART_RESV;
576 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
577 flags |= IOART_DESTPHY | IOART_DELFIXED;
579 target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
580 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
584 ioapic_write(ioapic[apic], select, flags | vector);
585 ioapic_write(ioapic[apic], select + 1, target);
590 * We only deal with vectored interrupts here. ? documentation is
591 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
594 * This test also catches unconfigured pins.
596 if (apic_int_type(apic, pin) != 0)
600 * Leave the pin unprogrammed if it does not correspond to
603 irq = apic_irq(apic, pin);
607 /* determine the bus type for this pin */
608 bus = apic_src_bus_id(apic, pin);
611 bustype = apic_bus_type(bus);
613 if ((bustype == ISA) &&
614 (pin < IOAPIC_ISA_INTS) &&
616 (apic_polarity(apic, pin) == 0x1) &&
617 (apic_trigger(apic, pin) == 0x3)) {
619 * A broken BIOS might describe some ISA
620 * interrupts as active-high level-triggered.
621 * Use default ISA flags for those interrupts.
623 flags = DEFAULT_ISA_FLAGS;
626 * Program polarity and trigger mode according to
629 flags = DEFAULT_FLAGS;
630 level = trigger(apic, pin, &flags);
632 int_to_apicintpin[irq].flags |= IOAPIC_IM_FLAG_LEVEL;
633 polarity(apic, pin, &flags, level);
637 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
638 kgetenv_int(envpath, &cpuid);
640 /* ncpus may not be available yet */
645 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
646 apic, pin, irq, cpuid);
650 * Program the appropriate registers. This routing may be
651 * overridden when an interrupt handler for a device is
652 * actually added (see register_int(), which calls through
653 * the MACHINTR ABI to set up an interrupt handler/vector).
655 * The order in which we must program the two registers for
656 * safety is unclear! XXX
660 vector = IDT_OFFSET + irq; /* IDT vec */
661 target = ioapic_read(ioapic[apic], select + 1) & IOART_HI_DEST_RESV;
662 /* Deliver all interrupts to CPU0 (BSP) */
663 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
665 flags |= ioapic_read(ioapic[apic], select) & IOART_RESV;
666 ioapic_write(ioapic[apic], select, flags | vector);
667 ioapic_write(ioapic[apic], select + 1, target);
673 io_apic_setup(int apic)
678 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
679 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
681 for (pin = 0; pin < maxpin; ++pin) {
682 io_apic_setup_intpin(apic, pin);
685 if (apic_int_type(apic, pin) >= 0) {
686 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
687 " cannot program!\n", apic, pin);
692 /* return GOOD status */
695 #undef DEFAULT_ISA_FLAGS
699 #define DEFAULT_EXTINT_FLAGS \
708 * XXX this function is only used by 8254 setup
709 * Setup the source of External INTerrupts.
712 ext_int_setup(int apic, int intr)
714 u_char select; /* the select register is 8 bits */
715 u_int32_t flags; /* the window register is 32 bits */
716 u_int32_t target; /* the window register is 32 bits */
717 u_int32_t vector; /* the window register is 32 bits */
721 if (apic_int_type(apic, intr) != 3)
725 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
726 kgetenv_int(envpath, &cpuid);
728 /* ncpus may not be available yet */
732 /* Deliver interrupts to CPU0 (BSP) */
733 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
735 select = IOAPIC_REDTBL0 + (2 * intr);
736 vector = IDT_OFFSET + intr;
737 flags = DEFAULT_EXTINT_FLAGS;
739 ioapic_write(ioapic[apic], select, flags | vector);
740 ioapic_write(ioapic[apic], select + 1, target);
744 #undef DEFAULT_EXTINT_FLAGS
748 * Set the trigger level for an IO APIC pin.
751 trigger(int apic, int pin, u_int32_t * flags)
756 static int intcontrol = -1;
758 switch (apic_trigger(apic, pin)) {
764 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
768 *flags |= IOART_TRGRLVL;
776 if ((id = apic_src_bus_id(apic, pin)) == -1)
779 switch (apic_bus_type(id)) {
781 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
785 eirq = apic_src_bus_irq(apic, pin);
787 if (eirq < 0 || eirq > 15) {
788 kprintf("EISA IRQ %d?!?!\n", eirq);
792 if (intcontrol == -1) {
793 intcontrol = inb(ELCR1) << 8;
794 intcontrol |= inb(ELCR0);
795 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
798 /* Use ELCR settings to determine level or edge mode */
799 level = (intcontrol >> eirq) & 1;
802 * Note that on older Neptune chipset based systems, any
803 * pci interrupts often show up here and in the ELCR as well
804 * as level sensitive interrupts attributed to the EISA bus.
808 *flags |= IOART_TRGRLVL;
810 *flags &= ~IOART_TRGRLVL;
815 *flags |= IOART_TRGRLVL;
824 panic("bad APIC IO INT flags");
829 * Set the polarity value for an IO APIC pin.
832 polarity(int apic, int pin, u_int32_t * flags, int level)
836 switch (apic_polarity(apic, pin)) {
842 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
846 *flags |= IOART_INTALO;
854 if ((id = apic_src_bus_id(apic, pin)) == -1)
857 switch (apic_bus_type(id)) {
859 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
863 /* polarity converter always gives active high */
864 *flags &= ~IOART_INTALO;
868 *flags |= IOART_INTALO;
877 panic("bad APIC IO INT flags");
882 * Print contents of unmasked IRQs.
889 kprintf("SMP: enabled INTs: ");
890 for (x = 0; x < APIC_INTMAPSIZE; ++x) {
891 if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0)
899 * Inter Processor Interrupt functions.
902 #endif /* SMP APIC-IO */
905 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
907 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
908 * vector is any valid SYSTEM INT vector
909 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
911 * A backlog of requests can create a deadlock between cpus. To avoid this
912 * we have to be able to accept IPIs at the same time we are trying to send
913 * them. The critical section prevents us from attempting to send additional
914 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
915 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
916 * to occur but fortunately it does not happen too often.
919 apic_ipi(int dest_type, int vector, int delivery_mode)
924 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
925 unsigned int eflags = read_eflags();
927 DEBUG_PUSH_INFO("apic_ipi");
928 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
932 write_eflags(eflags);
935 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
936 delivery_mode | vector;
937 lapic.icr_lo = icr_lo;
943 single_apic_ipi(int cpu, int vector, int delivery_mode)
949 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
950 unsigned int eflags = read_eflags();
952 DEBUG_PUSH_INFO("single_apic_ipi");
953 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
957 write_eflags(eflags);
959 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
960 icr_hi |= (CPU_TO_ID(cpu) << 24);
961 lapic.icr_hi = icr_hi;
964 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
965 | APIC_DEST_DESTFLD | delivery_mode | vector;
968 lapic.icr_lo = icr_lo;
975 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
977 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
978 * to the target, and the scheduler does not 'poll' for IPI messages.
981 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
987 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
991 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
992 icr_hi |= (CPU_TO_ID(cpu) << 24);
993 lapic.icr_hi = icr_hi;
996 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
997 | APIC_DEST_DESTFLD | delivery_mode | vector;
1000 lapic.icr_lo = icr_lo;
1008 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
1010 * target is a bitmask of destination cpus. Vector is any
1011 * valid system INT vector. Delivery mode may be either
1012 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
1015 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
1019 int n = BSFCPUMASK(target);
1020 target &= ~CPUMASK(n);
1021 single_apic_ipi(n, vector, delivery_mode);
1027 * Timer code, in development...
1028 * - suggested by rgrimes@gndrsh.aac.dev.com
1031 get_apic_timer_frequency(void)
1033 return(lapic_cputimer_intr.freq);
1037 * Load a 'downcount time' in uSeconds.
1040 set_apic_timer(int us)
1045 * When we reach here, lapic timer's frequency
1046 * must have been calculated as well as the
1047 * divisor (lapic.dcr_timer is setup during the
1048 * divisor calculation).
1050 KKASSERT(lapic_cputimer_intr.freq != 0 &&
1051 lapic_timer_divisor_idx >= 0);
1053 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
1054 lapic_timer_oneshot(count);
1059 * Read remaining time in timer.
1062 read_apic_timer(void)
1065 /** XXX FIXME: we need to return the actual remaining time,
1066 * for now we just return the remaining count.
1069 return lapic.ccr_timer;
1075 * Spin-style delay, set delay time in uS, spin till it drains.
1080 set_apic_timer(count);
1081 while (read_apic_timer())
1086 lapic_unused_apic_id(int start)
1090 for (i = start; i < NAPICID; ++i) {
1091 if (ID_TO_CPU(i) == -1)
1098 lapic_map(vm_offset_t lapic_addr)
1100 /* Local apic is mapped on last page */
1101 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
1102 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
1104 kprintf("lapic: at %p\n", (void *)lapic_addr);
1107 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
1108 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
1113 struct lapic_enumerator *e;
1116 for (i = 0; i < NAPICID; ++i)
1119 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1120 error = e->lapic_probe(e);
1125 panic("can't config lapic\n");
1127 e->lapic_enumerate(e);
1131 lapic_enumerator_register(struct lapic_enumerator *ne)
1133 struct lapic_enumerator *e;
1135 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1136 if (e->lapic_prio < ne->lapic_prio) {
1137 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
1141 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
1144 static TAILQ_HEAD(, ioapic_enumerator) ioapic_enumerators =
1145 TAILQ_HEAD_INITIALIZER(ioapic_enumerators);
1150 struct ioapic_enumerator *e;
1154 TAILQ_INIT(&ioapic_conf.ioc_list);
1155 /* XXX magic number */
1156 for (i = 0; i < 16; ++i)
1157 ioapic_conf.ioc_intsrc[i].int_gsi = -1;
1159 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
1160 error = e->ioapic_probe(e);
1166 panic("can't config I/O APIC\n");
1168 kprintf("no I/O APIC\n");
1173 if (!ioapic_use_old) {
1180 * Switch to I/O APIC MachIntrABI and reconfigure
1181 * the default IDT entries.
1183 MachIntrABI = MachIntrABI_IOAPIC;
1184 MachIntrABI.setdefault();
1187 e->ioapic_enumerate(e);
1189 if (!ioapic_use_old) {
1190 struct ioapic_info *info;
1191 int start_apic_id = 0;
1197 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
1200 if (i > IOAPIC_COUNT_MAX) /* XXX magic number */
1201 panic("ioapic_config: more than 16 I/O APIC\n");
1206 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1209 apic_id = ioapic_alloc_apic_id(start_apic_id);
1210 if (apic_id == NAPICID) {
1211 kprintf("IOAPIC: can't alloc APIC ID for "
1212 "%dth I/O APIC\n", info->io_idx);
1215 info->io_apic_id = apic_id;
1217 start_apic_id = apic_id + 1;
1221 * xAPIC allows I/O APIC's APIC ID to be same
1222 * as the LAPIC's APIC ID
1224 kprintf("IOAPIC: use xAPIC model to alloc APIC ID "
1227 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
1228 info->io_apic_id = info->io_idx;
1232 * Warning about any GSI holes
1234 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1235 const struct ioapic_info *prev_info;
1237 prev_info = TAILQ_PREV(info, ioapic_info_list, io_link);
1238 if (prev_info != NULL) {
1239 if (info->io_gsi_base !=
1240 prev_info->io_gsi_base + prev_info->io_npin) {
1241 kprintf("IOAPIC: warning gsi hole "
1243 prev_info->io_gsi_base +
1245 info->io_gsi_base - 1);
1251 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1252 kprintf("IOAPIC: idx %d, apic id %d, "
1253 "gsi base %d, npin %d\n",
1262 * Setup all I/O APIC
1264 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
1266 ioapic_abi_fixup_irqmap();
1270 MachIntrABI.cleanup();
1277 ioapic_enumerator_register(struct ioapic_enumerator *ne)
1279 struct ioapic_enumerator *e;
1281 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
1282 if (e->ioapic_prio < ne->ioapic_prio) {
1283 TAILQ_INSERT_BEFORE(e, ne, ioapic_link);
1287 TAILQ_INSERT_TAIL(&ioapic_enumerators, ne, ioapic_link);
1291 ioapic_add(void *addr, int gsi_base, int npin)
1293 struct ioapic_info *info, *ninfo;
1296 gsi_end = gsi_base + npin - 1;
1297 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1298 if ((gsi_base >= info->io_gsi_base &&
1299 gsi_base < info->io_gsi_base + info->io_npin) ||
1300 (gsi_end >= info->io_gsi_base &&
1301 gsi_end < info->io_gsi_base + info->io_npin)) {
1302 panic("ioapic_add: overlapped gsi, base %d npin %d, "
1303 "hit base %d, npin %d\n", gsi_base, npin,
1304 info->io_gsi_base, info->io_npin);
1306 if (info->io_addr == addr)
1307 panic("ioapic_add: duplicated addr %p\n", addr);
1310 ninfo = kmalloc(sizeof(*ninfo), M_DEVBUF, M_WAITOK | M_ZERO);
1311 ninfo->io_addr = addr;
1312 ninfo->io_npin = npin;
1313 ninfo->io_gsi_base = gsi_base;
1314 ninfo->io_apic_id = -1;
1317 * Create IOAPIC list in ascending order of GSI base
1319 TAILQ_FOREACH_REVERSE(info, &ioapic_conf.ioc_list,
1320 ioapic_info_list, io_link) {
1321 if (ninfo->io_gsi_base > info->io_gsi_base) {
1322 TAILQ_INSERT_AFTER(&ioapic_conf.ioc_list,
1323 info, ninfo, io_link);
1328 TAILQ_INSERT_HEAD(&ioapic_conf.ioc_list, ninfo, io_link);
1332 ioapic_intsrc(int irq, int gsi, enum intr_trigger trig, enum intr_polarity pola)
1334 struct ioapic_intsrc *int_src;
1337 int_src = &ioapic_conf.ioc_intsrc[irq];
1340 /* Don't allow mixed mode */
1341 kprintf("IOAPIC: warning intsrc irq %d -> gsi 0\n", irq);
1345 if (int_src->int_gsi != -1) {
1346 if (int_src->int_gsi != gsi) {
1347 kprintf("IOAPIC: warning intsrc irq %d, gsi "
1348 "%d -> %d\n", irq, int_src->int_gsi, gsi);
1350 if (int_src->int_trig != trig) {
1351 kprintf("IOAPIC: warning intsrc irq %d, trig "
1353 intr_str_trigger(int_src->int_trig),
1354 intr_str_trigger(trig));
1356 if (int_src->int_pola != pola) {
1357 kprintf("IOAPIC: warning intsrc irq %d, pola "
1359 intr_str_polarity(int_src->int_pola),
1360 intr_str_polarity(pola));
1363 int_src->int_gsi = gsi;
1364 int_src->int_trig = trig;
1365 int_src->int_pola = pola;
1369 ioapic_set_apic_id(const struct ioapic_info *info)
1374 id = ioapic_read(info->io_addr, IOAPIC_ID);
1376 id &= ~APIC_ID_MASK;
1377 id |= (info->io_apic_id << 24);
1379 ioapic_write(info->io_addr, IOAPIC_ID, id);
1384 id = ioapic_read(info->io_addr, IOAPIC_ID);
1385 apic_id = (id & APIC_ID_MASK) >> 24;
1388 * I/O APIC ID is a 4bits field
1390 if ((apic_id & IOAPIC_ID_MASK) !=
1391 (info->io_apic_id & IOAPIC_ID_MASK)) {
1392 panic("ioapic_set_apic_id: can't set apic id to %d, "
1393 "currently set to %d\n", info->io_apic_id, apic_id);
1398 ioapic_gsi_setup(int gsi)
1400 enum intr_trigger trig;
1401 enum intr_polarity pola;
1407 ioapic_extpin_setup(ioapic_gsi_ioaddr(gsi),
1408 ioapic_gsi_pin(gsi), 0);
1413 trig = 0; /* silence older gcc's */
1414 pola = 0; /* silence older gcc's */
1416 for (irq = 0; irq < 16; ++irq) {
1417 const struct ioapic_intsrc *int_src =
1418 &ioapic_conf.ioc_intsrc[irq];
1420 if (gsi == int_src->int_gsi) {
1421 trig = int_src->int_trig;
1422 pola = int_src->int_pola;
1429 trig = INTR_TRIGGER_EDGE;
1430 pola = INTR_POLARITY_HIGH;
1432 trig = INTR_TRIGGER_LEVEL;
1433 pola = INTR_POLARITY_LOW;
1438 ioapic_abi_set_irqmap(irq, gsi, trig, pola);
1442 ioapic_gsi_ioaddr(int gsi)
1444 const struct ioapic_info *info;
1446 info = ioapic_gsi_search(gsi);
1447 return info->io_addr;
1451 ioapic_gsi_pin(int gsi)
1453 const struct ioapic_info *info;
1455 info = ioapic_gsi_search(gsi);
1456 return gsi - info->io_gsi_base;
1459 static const struct ioapic_info *
1460 ioapic_gsi_search(int gsi)
1462 const struct ioapic_info *info;
1464 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1465 if (gsi >= info->io_gsi_base &&
1466 gsi < info->io_gsi_base + info->io_npin)
1469 panic("ioapic_gsi_search: no I/O APIC\n");
1473 ioapic_gsi(int idx, int pin)
1475 const struct ioapic_info *info;
1477 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1478 if (info->io_idx == idx)
1483 if (pin >= info->io_npin)
1485 return info->io_gsi_base + pin;
1489 ioapic_extpin_setup(void *addr, int pin, int vec)
1491 ioapic_pin_prog(addr, pin, vec,
1492 INTR_TRIGGER_CONFORM, INTR_POLARITY_CONFORM, IOART_DELEXINT);
1496 ioapic_extpin_gsi(void)
1502 ioapic_pin_setup(void *addr, int pin, int vec,
1503 enum intr_trigger trig, enum intr_polarity pola)
1506 * Always clear an I/O APIC pin before [re]programming it. This is
1507 * particularly important if the pin is set up for a level interrupt
1508 * as the IOART_REM_IRR bit might be set. When we reprogram the
1509 * vector any EOI from pending ints on this pin could be lost and
1510 * IRR might never get reset.
1512 * To fix this problem, clear the vector and make sure it is
1513 * programmed as an edge interrupt. This should theoretically
1514 * clear IRR so we can later, safely program it as a level
1517 ioapic_pin_prog(addr, pin, vec, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH,
1519 ioapic_pin_prog(addr, pin, vec, trig, pola, IOART_DELFIXED);
1523 ioapic_pin_prog(void *addr, int pin, int vec,
1524 enum intr_trigger trig, enum intr_polarity pola, uint32_t del_mode)
1526 uint32_t flags, target;
1529 KKASSERT(del_mode == IOART_DELEXINT || del_mode == IOART_DELFIXED);
1531 select = IOAPIC_REDTBL0 + (2 * pin);
1533 flags = ioapic_read(addr, select) & IOART_RESV;
1534 flags |= IOART_INTMSET | IOART_DESTPHY;
1539 * We only support limited I/O APIC mixed mode,
1540 * so even for ExtINT, we still use "fixed"
1543 flags |= IOART_DELFIXED;
1546 if (del_mode == IOART_DELEXINT) {
1547 KKASSERT(trig == INTR_TRIGGER_CONFORM &&
1548 pola == INTR_POLARITY_CONFORM);
1549 flags |= IOART_TRGREDG | IOART_INTAHI;
1552 case INTR_TRIGGER_EDGE:
1553 flags |= IOART_TRGREDG;
1556 case INTR_TRIGGER_LEVEL:
1557 flags |= IOART_TRGRLVL;
1560 case INTR_TRIGGER_CONFORM:
1561 panic("ioapic_pin_prog: trig conform is not "
1565 case INTR_POLARITY_HIGH:
1566 flags |= IOART_INTAHI;
1569 case INTR_POLARITY_LOW:
1570 flags |= IOART_INTALO;
1573 case INTR_POLARITY_CONFORM:
1574 panic("ioapic_pin_prog: pola conform is not "
1579 target = ioapic_read(addr, select + 1) & IOART_HI_DEST_RESV;
1580 target |= (CPU_TO_ID(0) << IOART_HI_DEST_SHIFT) &
1583 ioapic_write(addr, select, flags | vec);
1584 ioapic_write(addr, select + 1, target);
1588 ioapic_setup(const struct ioapic_info *info)
1592 ioapic_set_apic_id(info);
1594 for (i = 0; i < info->io_npin; ++i)
1595 ioapic_gsi_setup(info->io_gsi_base + i);
1599 ioapic_alloc_apic_id(int start)
1602 const struct ioapic_info *info;
1603 int apic_id, apic_id16;
1605 apic_id = lapic_unused_apic_id(start);
1606 if (apic_id == NAPICID) {
1607 kprintf("IOAPIC: can't find unused APIC ID\n");
1610 apic_id16 = apic_id & IOAPIC_ID_MASK;
1613 * Check against other I/O APIC's APIC ID's lower 4bits.
1615 * The new APIC ID will have to be different from others
1616 * in the lower 4bits, no matter whether xAPIC is used
1619 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
1620 if (info->io_apic_id == -1) {
1624 if ((info->io_apic_id & IOAPIC_ID_MASK) == apic_id16)
1630 kprintf("IOAPIC: APIC ID %d has same lower 4bits as "
1631 "%dth I/O APIC, keep searching...\n",
1632 apic_id, info->io_idx);
1634 start = apic_id + 1;
1636 panic("ioapic_unused_apic_id: never reached\n");