2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
37 #include "opt_ifpoll.h"
39 #include <sys/param.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/interrupt.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
48 #include <sys/serialize.h>
49 #include <sys/socket.h>
50 #include <sys/sockio.h>
51 #include <sys/sysctl.h>
53 #include <netinet/ip.h>
54 #include <netinet/tcp.h>
57 #include <net/ethernet.h>
59 #include <net/if_arp.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_poll.h>
63 #include <net/if_types.h>
64 #include <net/ifq_var.h>
65 #include <net/toeplitz.h>
66 #include <net/toeplitz2.h>
67 #include <net/vlan/if_vlan_var.h>
68 #include <net/vlan/if_vlan_ether.h>
70 #include <dev/netif/mii_layer/mii.h>
71 #include <dev/netif/mii_layer/miivar.h>
72 #include <dev/netif/mii_layer/brgphyreg.h>
74 #include <bus/pci/pcidevs.h>
75 #include <bus/pci/pcireg.h>
76 #include <bus/pci/pcivar.h>
78 #include <dev/netif/bge/if_bgereg.h>
79 #include <dev/netif/bnx/if_bnxvar.h>
81 /* "device miibus" required. See GENERIC if you get errors here. */
82 #include "miibus_if.h"
84 #define BNX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
86 #define BNX_INTR_CKINTVL ((10 * hz) / 1000) /* 10ms */
89 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...) \
91 if (sc->bnx_rss_debug >= lvl) \
92 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
94 #else /* !BNX_RSS_DEBUG */
95 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
96 #endif /* BNX_RSS_DEBUG */
98 static const struct bnx_type {
103 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
104 "Broadcom BCM5717 Gigabit Ethernet" },
105 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
106 "Broadcom BCM5717C Gigabit Ethernet" },
107 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
108 "Broadcom BCM5718 Gigabit Ethernet" },
109 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
110 "Broadcom BCM5719 Gigabit Ethernet" },
111 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
112 "Broadcom BCM5720 Gigabit Ethernet" },
114 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
115 "Broadcom BCM5725 Gigabit Ethernet" },
116 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
117 "Broadcom BCM5727 Gigabit Ethernet" },
118 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
119 "Broadcom BCM5762 Gigabit Ethernet" },
121 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
122 "Broadcom BCM57761 Gigabit Ethernet" },
123 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
124 "Broadcom BCM57762 Gigabit Ethernet" },
125 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
126 "Broadcom BCM57765 Gigabit Ethernet" },
127 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
128 "Broadcom BCM57766 Gigabit Ethernet" },
129 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
130 "Broadcom BCM57781 Gigabit Ethernet" },
131 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
132 "Broadcom BCM57782 Gigabit Ethernet" },
133 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
134 "Broadcom BCM57785 Gigabit Ethernet" },
135 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
136 "Broadcom BCM57786 Gigabit Ethernet" },
137 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
138 "Broadcom BCM57791 Fast Ethernet" },
139 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
140 "Broadcom BCM57795 Fast Ethernet" },
145 static const int bnx_tx_mailbox[BNX_TX_RING_MAX] = {
146 BGE_MBX_TX_HOST_PROD0_LO,
147 BGE_MBX_TX_HOST_PROD0_HI,
148 BGE_MBX_TX_HOST_PROD1_LO,
149 BGE_MBX_TX_HOST_PROD1_HI
152 #define BNX_IS_JUMBO_CAPABLE(sc) ((sc)->bnx_flags & BNX_FLAG_JUMBO)
153 #define BNX_IS_5717_PLUS(sc) ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
154 #define BNX_IS_57765_PLUS(sc) ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
155 #define BNX_IS_57765_FAMILY(sc) \
156 ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
158 typedef int (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
160 static int bnx_probe(device_t);
161 static int bnx_attach(device_t);
162 static int bnx_detach(device_t);
163 static void bnx_shutdown(device_t);
164 static int bnx_suspend(device_t);
165 static int bnx_resume(device_t);
166 static int bnx_miibus_readreg(device_t, int, int);
167 static int bnx_miibus_writereg(device_t, int, int, int);
168 static void bnx_miibus_statchg(device_t);
170 static void bnx_handle_status(struct bnx_softc *);
172 static void bnx_npoll(struct ifnet *, struct ifpoll_info *);
173 static void bnx_npoll_rx(struct ifnet *, void *, int);
174 static void bnx_npoll_tx(struct ifnet *, void *, int);
175 static void bnx_npoll_tx_notag(struct ifnet *, void *, int);
176 static void bnx_npoll_status(struct ifnet *);
177 static void bnx_npoll_status_notag(struct ifnet *);
179 static void bnx_intr_legacy(void *);
180 static void bnx_msi(void *);
181 static void bnx_intr(struct bnx_softc *);
182 static void bnx_msix_status(void *);
183 static void bnx_msix_tx_status(void *);
184 static void bnx_msix_rx(void *);
185 static void bnx_msix_rxtx(void *);
186 static void bnx_enable_intr(struct bnx_softc *);
187 static void bnx_disable_intr(struct bnx_softc *);
188 static void bnx_txeof(struct bnx_tx_ring *, uint16_t);
189 static void bnx_rxeof(struct bnx_rx_ret_ring *, uint16_t, int);
190 static int bnx_alloc_intr(struct bnx_softc *);
191 static int bnx_setup_intr(struct bnx_softc *);
192 static void bnx_free_intr(struct bnx_softc *);
193 static void bnx_teardown_intr(struct bnx_softc *, int);
194 static int bnx_alloc_msix(struct bnx_softc *);
195 static void bnx_free_msix(struct bnx_softc *, boolean_t);
196 static void bnx_check_intr_rxtx(void *);
197 static void bnx_check_intr_rx(void *);
198 static void bnx_check_intr_tx(void *);
199 static void bnx_rx_std_refill_ithread(void *);
200 static void bnx_rx_std_refill(void *, void *);
201 static void bnx_rx_std_refill_sched_ipi(void *);
202 static void bnx_rx_std_refill_stop(void *);
203 static void bnx_rx_std_refill_sched(struct bnx_rx_ret_ring *,
204 struct bnx_rx_std_ring *);
206 static void bnx_start(struct ifnet *, struct ifaltq_subque *);
207 static int bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
208 static void bnx_init(void *);
209 static void bnx_stop(struct bnx_softc *);
210 static void bnx_watchdog(struct ifaltq_subque *);
211 static int bnx_ifmedia_upd(struct ifnet *);
212 static void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
213 static void bnx_tick(void *);
214 static void bnx_serialize(struct ifnet *, enum ifnet_serialize);
215 static void bnx_deserialize(struct ifnet *, enum ifnet_serialize);
216 static int bnx_tryserialize(struct ifnet *, enum ifnet_serialize);
218 static void bnx_serialize_assert(struct ifnet *, enum ifnet_serialize,
221 static void bnx_serialize_skipmain(struct bnx_softc *);
222 static void bnx_deserialize_skipmain(struct bnx_softc *sc);
224 static int bnx_alloc_jumbo_mem(struct bnx_softc *);
225 static void bnx_free_jumbo_mem(struct bnx_softc *);
226 static struct bnx_jslot
227 *bnx_jalloc(struct bnx_softc *);
228 static void bnx_jfree(void *);
229 static void bnx_jref(void *);
230 static int bnx_newbuf_std(struct bnx_rx_ret_ring *, int, int);
231 static int bnx_newbuf_jumbo(struct bnx_softc *, int, int);
232 static void bnx_setup_rxdesc_std(struct bnx_rx_std_ring *, int);
233 static void bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
234 static int bnx_init_rx_ring_std(struct bnx_rx_std_ring *);
235 static void bnx_free_rx_ring_std(struct bnx_rx_std_ring *);
236 static int bnx_init_rx_ring_jumbo(struct bnx_softc *);
237 static void bnx_free_rx_ring_jumbo(struct bnx_softc *);
238 static void bnx_free_tx_ring(struct bnx_tx_ring *);
239 static int bnx_init_tx_ring(struct bnx_tx_ring *);
240 static int bnx_create_tx_ring(struct bnx_tx_ring *);
241 static void bnx_destroy_tx_ring(struct bnx_tx_ring *);
242 static int bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *);
243 static void bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *);
244 static int bnx_dma_alloc(device_t);
245 static void bnx_dma_free(struct bnx_softc *);
246 static int bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
247 bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
248 static void bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
250 bnx_defrag_shortdma(struct mbuf *);
251 static int bnx_encap(struct bnx_tx_ring *, struct mbuf **,
253 static int bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **,
254 uint16_t *, uint16_t *);
255 static void bnx_setup_serialize(struct bnx_softc *);
256 static void bnx_set_tick_cpuid(struct bnx_softc *, boolean_t);
257 static void bnx_setup_ring_cnt(struct bnx_softc *);
259 static void bnx_init_rss(struct bnx_softc *);
260 static void bnx_reset(struct bnx_softc *);
261 static int bnx_chipinit(struct bnx_softc *);
262 static int bnx_blockinit(struct bnx_softc *);
263 static void bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
264 static void bnx_enable_msi(struct bnx_softc *, boolean_t);
265 static void bnx_setmulti(struct bnx_softc *);
266 static void bnx_setpromisc(struct bnx_softc *);
267 static void bnx_stats_update_regs(struct bnx_softc *);
268 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
270 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
271 static void bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
273 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
275 static void bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
276 static void bnx_writembx(struct bnx_softc *, int, int);
277 static int bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
278 static uint8_t bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
279 static int bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
281 static void bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
282 static void bnx_copper_link_upd(struct bnx_softc *, uint32_t);
283 static void bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
284 static void bnx_link_poll(struct bnx_softc *);
286 static int bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
287 static int bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
288 static int bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
289 static int bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
291 static void bnx_coal_change(struct bnx_softc *);
292 static int bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS);
293 static int bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS);
294 static int bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
295 static int bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
296 static int bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
297 static int bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
298 static int bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
299 static int bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
300 static int bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
303 static int bnx_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS);
304 static int bnx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
305 static int bnx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
307 static int bnx_sysctl_std_refill(SYSCTL_HANDLER_ARGS);
309 static int bnx_msi_enable = 1;
310 static int bnx_msix_enable = 1;
312 static int bnx_rx_rings = 0; /* auto */
313 static int bnx_tx_rings = 0; /* auto */
315 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
316 TUNABLE_INT("hw.bnx.msix.enable", &bnx_msix_enable);
317 TUNABLE_INT("hw.bnx.rx_rings", &bnx_rx_rings);
318 TUNABLE_INT("hw.bnx.tx_rings", &bnx_tx_rings);
320 static device_method_t bnx_methods[] = {
321 /* Device interface */
322 DEVMETHOD(device_probe, bnx_probe),
323 DEVMETHOD(device_attach, bnx_attach),
324 DEVMETHOD(device_detach, bnx_detach),
325 DEVMETHOD(device_shutdown, bnx_shutdown),
326 DEVMETHOD(device_suspend, bnx_suspend),
327 DEVMETHOD(device_resume, bnx_resume),
330 DEVMETHOD(bus_print_child, bus_generic_print_child),
331 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
334 DEVMETHOD(miibus_readreg, bnx_miibus_readreg),
335 DEVMETHOD(miibus_writereg, bnx_miibus_writereg),
336 DEVMETHOD(miibus_statchg, bnx_miibus_statchg),
341 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
342 static devclass_t bnx_devclass;
344 DECLARE_DUMMY_MODULE(if_bnx);
345 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
346 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
349 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
351 device_t dev = sc->bnx_dev;
354 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
355 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
356 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
361 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
363 device_t dev = sc->bnx_dev;
365 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
366 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
367 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
371 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
373 CSR_WRITE_4(sc, off, val);
377 bnx_writembx(struct bnx_softc *sc, int off, int val)
379 CSR_WRITE_4(sc, off, val);
383 * Read a sequence of bytes from NVRAM.
386 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
392 * Read a byte of data stored in the EEPROM at address 'addr.' The
393 * BCM570x supports both the traditional bitbang interface and an
394 * auto access interface for reading the EEPROM. We use the auto
398 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
404 * Enable use of auto EEPROM access so we can avoid
405 * having to use the bitbang method.
407 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
409 /* Reset the EEPROM, load the clock period. */
410 CSR_WRITE_4(sc, BGE_EE_ADDR,
411 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
414 /* Issue the read EEPROM command. */
415 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
417 /* Wait for completion */
418 for(i = 0; i < BNX_TIMEOUT * 10; i++) {
420 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
424 if (i == BNX_TIMEOUT) {
425 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
430 byte = CSR_READ_4(sc, BGE_EE_DATA);
432 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
438 * Read a sequence of bytes from the EEPROM.
441 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
447 for (byte = 0, err = 0, i = 0; i < len; i++) {
448 err = bnx_eeprom_getbyte(sc, off + i, &byte);
458 bnx_miibus_readreg(device_t dev, int phy, int reg)
460 struct bnx_softc *sc = device_get_softc(dev);
464 KASSERT(phy == sc->bnx_phyno,
465 ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
467 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
468 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
469 CSR_WRITE_4(sc, BGE_MI_MODE,
470 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
474 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
475 BGE_MIPHY(phy) | BGE_MIREG(reg));
477 /* Poll for the PHY register access to complete. */
478 for (i = 0; i < BNX_TIMEOUT; i++) {
480 val = CSR_READ_4(sc, BGE_MI_COMM);
481 if ((val & BGE_MICOMM_BUSY) == 0) {
483 val = CSR_READ_4(sc, BGE_MI_COMM);
487 if (i == BNX_TIMEOUT) {
488 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
489 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
493 /* Restore the autopoll bit if necessary. */
494 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
495 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
499 if (val & BGE_MICOMM_READFAIL)
502 return (val & 0xFFFF);
506 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
508 struct bnx_softc *sc = device_get_softc(dev);
511 KASSERT(phy == sc->bnx_phyno,
512 ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
514 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
515 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
516 CSR_WRITE_4(sc, BGE_MI_MODE,
517 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
521 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
522 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
524 for (i = 0; i < BNX_TIMEOUT; i++) {
526 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
528 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
532 if (i == BNX_TIMEOUT) {
533 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
534 "(phy %d, reg %d, val %d)\n", phy, reg, val);
537 /* Restore the autopoll bit if necessary. */
538 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
539 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
547 bnx_miibus_statchg(device_t dev)
549 struct bnx_softc *sc;
550 struct mii_data *mii;
552 sc = device_get_softc(dev);
553 mii = device_get_softc(sc->bnx_miibus);
555 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
556 (IFM_ACTIVE | IFM_AVALID)) {
557 switch (IFM_SUBTYPE(mii->mii_media_active)) {
574 if (sc->bnx_link == 0)
577 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
578 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
579 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
580 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
582 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
585 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
586 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
588 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
593 * Memory management for jumbo frames.
596 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
598 struct ifnet *ifp = &sc->arpcom.ac_if;
599 struct bnx_jslot *entry;
605 * Create tag for jumbo mbufs.
606 * This is really a bit of a kludge. We allocate a special
607 * jumbo buffer pool which (thanks to the way our DMA
608 * memory allocation works) will consist of contiguous
609 * pages. This means that even though a jumbo buffer might
610 * be larger than a page size, we don't really need to
611 * map it into more than one DMA segment. However, the
612 * default mbuf tag will result in multi-segment mappings,
613 * so we have to create a special jumbo mbuf tag that
614 * lets us get away with mapping the jumbo buffers as
615 * a single segment. I think eventually the driver should
616 * be changed so that it uses ordinary mbufs and cluster
617 * buffers, i.e. jumbo frames can span multiple DMA
618 * descriptors. But that's a project for another day.
622 * Create DMA stuffs for jumbo RX ring.
624 error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
625 &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
626 &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
627 (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
628 &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
630 if_printf(ifp, "could not create jumbo RX ring\n");
635 * Create DMA stuffs for jumbo buffer block.
637 error = bnx_dma_block_alloc(sc, BNX_JMEM,
638 &sc->bnx_cdata.bnx_jumbo_tag,
639 &sc->bnx_cdata.bnx_jumbo_map,
640 (void **)&sc->bnx_ldata.bnx_jumbo_buf,
643 if_printf(ifp, "could not create jumbo buffer\n");
647 SLIST_INIT(&sc->bnx_jfree_listhead);
650 * Now divide it up into 9K pieces and save the addresses
651 * in an array. Note that we play an evil trick here by using
652 * the first few bytes in the buffer to hold the the address
653 * of the softc structure for this interface. This is because
654 * bnx_jfree() needs it, but it is called by the mbuf management
655 * code which will not pass it to us explicitly.
657 for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
658 entry = &sc->bnx_cdata.bnx_jslots[i];
660 entry->bnx_buf = ptr;
661 entry->bnx_paddr = paddr;
662 entry->bnx_inuse = 0;
664 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
673 bnx_free_jumbo_mem(struct bnx_softc *sc)
675 /* Destroy jumbo RX ring. */
676 bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
677 sc->bnx_cdata.bnx_rx_jumbo_ring_map,
678 sc->bnx_ldata.bnx_rx_jumbo_ring);
680 /* Destroy jumbo buffer block. */
681 bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
682 sc->bnx_cdata.bnx_jumbo_map,
683 sc->bnx_ldata.bnx_jumbo_buf);
687 * Allocate a jumbo buffer.
689 static struct bnx_jslot *
690 bnx_jalloc(struct bnx_softc *sc)
692 struct bnx_jslot *entry;
694 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
695 entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
697 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
698 entry->bnx_inuse = 1;
700 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
702 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
707 * Adjust usage count on a jumbo buffer.
712 struct bnx_jslot *entry = (struct bnx_jslot *)arg;
713 struct bnx_softc *sc = entry->bnx_sc;
716 panic("bnx_jref: can't find softc pointer!");
718 if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
719 panic("bnx_jref: asked to reference buffer "
720 "that we don't manage!");
721 } else if (entry->bnx_inuse == 0) {
722 panic("bnx_jref: buffer already free!");
724 atomic_add_int(&entry->bnx_inuse, 1);
729 * Release a jumbo buffer.
734 struct bnx_jslot *entry = (struct bnx_jslot *)arg;
735 struct bnx_softc *sc = entry->bnx_sc;
738 panic("bnx_jfree: can't find softc pointer!");
740 if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
741 panic("bnx_jfree: asked to free buffer that we don't manage!");
742 } else if (entry->bnx_inuse == 0) {
743 panic("bnx_jfree: buffer already free!");
746 * Possible MP race to 0, use the serializer. The atomic insn
747 * is still needed for races against bnx_jref().
749 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
750 atomic_subtract_int(&entry->bnx_inuse, 1);
751 if (entry->bnx_inuse == 0) {
752 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
755 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
761 * Intialize a standard receive ring descriptor.
764 bnx_newbuf_std(struct bnx_rx_ret_ring *ret, int i, int init)
766 struct mbuf *m_new = NULL;
767 bus_dma_segment_t seg;
770 struct bnx_rx_buf *rb;
772 rb = &ret->bnx_std->bnx_rx_std_buf[i];
773 KASSERT(!rb->bnx_rx_refilled, ("RX buf %dth has been refilled", i));
775 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
780 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
781 m_adj(m_new, ETHER_ALIGN);
783 error = bus_dmamap_load_mbuf_segment(ret->bnx_rx_mtag,
784 ret->bnx_rx_tmpmap, m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT);
791 bus_dmamap_sync(ret->bnx_rx_mtag, rb->bnx_rx_dmamap,
792 BUS_DMASYNC_POSTREAD);
793 bus_dmamap_unload(ret->bnx_rx_mtag, rb->bnx_rx_dmamap);
796 map = ret->bnx_rx_tmpmap;
797 ret->bnx_rx_tmpmap = rb->bnx_rx_dmamap;
799 rb->bnx_rx_dmamap = map;
800 rb->bnx_rx_mbuf = m_new;
801 rb->bnx_rx_paddr = seg.ds_addr;
802 rb->bnx_rx_len = m_new->m_len;
805 rb->bnx_rx_refilled = 1;
810 bnx_setup_rxdesc_std(struct bnx_rx_std_ring *std, int i)
812 struct bnx_rx_buf *rb;
817 rb = &std->bnx_rx_std_buf[i];
818 KASSERT(rb->bnx_rx_refilled, ("RX buf %dth is not refilled", i));
820 paddr = rb->bnx_rx_paddr;
821 len = rb->bnx_rx_len;
825 rb->bnx_rx_refilled = 0;
827 r = &std->bnx_rx_std_ring[i];
828 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
829 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
832 r->bge_flags = BGE_RXBDFLAG_END;
836 * Initialize a jumbo receive ring descriptor. This allocates
837 * a jumbo buffer from the pool managed internally by the driver.
840 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
842 struct mbuf *m_new = NULL;
843 struct bnx_jslot *buf;
846 /* Allocate the mbuf. */
847 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
851 /* Allocate the jumbo buffer */
852 buf = bnx_jalloc(sc);
858 /* Attach the buffer to the mbuf. */
859 m_new->m_ext.ext_arg = buf;
860 m_new->m_ext.ext_buf = buf->bnx_buf;
861 m_new->m_ext.ext_free = bnx_jfree;
862 m_new->m_ext.ext_ref = bnx_jref;
863 m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
865 m_new->m_flags |= M_EXT;
867 m_new->m_data = m_new->m_ext.ext_buf;
868 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
870 paddr = buf->bnx_paddr;
871 m_adj(m_new, ETHER_ALIGN);
872 paddr += ETHER_ALIGN;
874 /* Save necessary information */
875 sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_mbuf = m_new;
876 sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_paddr = paddr;
878 /* Set up the descriptor. */
879 bnx_setup_rxdesc_jumbo(sc, i);
884 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
887 struct bnx_rx_buf *rc;
889 r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
890 rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
892 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_rx_paddr);
893 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_rx_paddr);
894 r->bge_len = rc->bnx_rx_mbuf->m_len;
896 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
900 bnx_init_rx_ring_std(struct bnx_rx_std_ring *std)
904 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
905 /* Use the first RX return ring's tmp RX mbuf DMA map */
906 error = bnx_newbuf_std(&std->bnx_sc->bnx_rx_ret_ring[0], i, 1);
909 bnx_setup_rxdesc_std(std, i);
912 std->bnx_rx_std_refill = 0;
913 std->bnx_rx_std_running = 0;
915 lwkt_serialize_handler_enable(&std->bnx_rx_std_serialize);
917 std->bnx_rx_std = BGE_STD_RX_RING_CNT - 1;
918 bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO, std->bnx_rx_std);
924 bnx_free_rx_ring_std(struct bnx_rx_std_ring *std)
928 lwkt_serialize_handler_disable(&std->bnx_rx_std_serialize);
930 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
931 struct bnx_rx_buf *rb = &std->bnx_rx_std_buf[i];
933 rb->bnx_rx_refilled = 0;
934 if (rb->bnx_rx_mbuf != NULL) {
935 bus_dmamap_unload(std->bnx_rx_mtag, rb->bnx_rx_dmamap);
936 m_freem(rb->bnx_rx_mbuf);
937 rb->bnx_rx_mbuf = NULL;
939 bzero(&std->bnx_rx_std_ring[i], sizeof(struct bge_rx_bd));
944 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
949 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
950 error = bnx_newbuf_jumbo(sc, i, 1);
955 sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
957 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
958 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
959 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
961 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
967 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
971 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
972 struct bnx_rx_buf *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
974 if (rc->bnx_rx_mbuf != NULL) {
975 m_freem(rc->bnx_rx_mbuf);
976 rc->bnx_rx_mbuf = NULL;
978 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
979 sizeof(struct bge_rx_bd));
984 bnx_free_tx_ring(struct bnx_tx_ring *txr)
988 for (i = 0; i < BGE_TX_RING_CNT; i++) {
989 struct bnx_tx_buf *buf = &txr->bnx_tx_buf[i];
991 if (buf->bnx_tx_mbuf != NULL) {
992 bus_dmamap_unload(txr->bnx_tx_mtag,
994 m_freem(buf->bnx_tx_mbuf);
995 buf->bnx_tx_mbuf = NULL;
997 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd));
999 txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
1003 bnx_init_tx_ring(struct bnx_tx_ring *txr)
1005 txr->bnx_tx_cnt = 0;
1006 txr->bnx_tx_saved_considx = 0;
1007 txr->bnx_tx_prodidx = 0;
1009 /* Initialize transmit producer index for host-memory send ring. */
1010 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, txr->bnx_tx_prodidx);
1016 bnx_setmulti(struct bnx_softc *sc)
1019 struct ifmultiaddr *ifma;
1020 uint32_t hashes[4] = { 0, 0, 0, 0 };
1023 ifp = &sc->arpcom.ac_if;
1025 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1026 for (i = 0; i < 4; i++)
1027 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1031 /* First, zot all the existing filters. */
1032 for (i = 0; i < 4; i++)
1033 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1035 /* Now program new ones. */
1036 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1037 if (ifma->ifma_addr->sa_family != AF_LINK)
1040 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1041 ETHER_ADDR_LEN) & 0x7f;
1042 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1045 for (i = 0; i < 4; i++)
1046 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1050 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1051 * self-test results.
1054 bnx_chipinit(struct bnx_softc *sc)
1056 uint32_t dma_rw_ctl, mode_ctl;
1059 /* Set endian type before we access any non-PCI registers. */
1060 pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
1061 BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
1063 /* Clear the MAC control register */
1064 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1067 * Clear the MAC statistics block in the NIC's
1070 for (i = BGE_STATS_BLOCK;
1071 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1072 BNX_MEMWIN_WRITE(sc, i, 0);
1074 for (i = BGE_STATUS_BLOCK;
1075 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1076 BNX_MEMWIN_WRITE(sc, i, 0);
1078 if (BNX_IS_57765_FAMILY(sc)) {
1081 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
1082 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1083 val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1085 /* Access the lower 1K of PL PCI-E block registers. */
1086 CSR_WRITE_4(sc, BGE_MODE_CTL,
1087 val | BGE_MODECTL_PCIE_PL_SEL);
1089 val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
1090 val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
1091 CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
1093 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1095 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1096 /* Fix transmit hangs */
1097 val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
1098 val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1099 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1101 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1102 val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1104 /* Access the lower 1K of DL PCI-E block registers. */
1105 CSR_WRITE_4(sc, BGE_MODE_CTL,
1106 val | BGE_MODECTL_PCIE_DL_SEL);
1108 val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1109 val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1110 val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1111 CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1113 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1116 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1117 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1118 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1119 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1123 * Set up the PCI DMA control register.
1125 dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1127 * Disable 32bytes cache alignment for DMA write to host memory
1130 * 64bytes cache alignment for DMA write to host memory is still
1133 dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1134 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1135 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1137 * Enable HW workaround for controllers that misinterpret
1138 * a status tag update and leave interrupts permanently
1141 if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1142 sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1143 !BNX_IS_57765_FAMILY(sc))
1144 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1146 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1149 pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1152 * Set up general mode register.
1154 mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1155 BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1156 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1159 * Disable memory write invalidate. Apparently it is not supported
1160 * properly by these devices. Also ensure that INTx isn't disabled,
1161 * as these chips need it even when using MSI.
1163 PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1164 (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1166 /* Set the timer prescaler (always 66Mhz) */
1167 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1173 bnx_blockinit(struct bnx_softc *sc)
1175 struct bnx_intr_data *intr;
1176 struct bge_rcb *rcb;
1183 * Initialize the memory window pointer register so that
1184 * we can access the first 32K of internal NIC RAM. This will
1185 * allow us to set up the TX send ring RCBs and the RX return
1186 * ring RCBs, plus other things which live in NIC memory.
1188 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1190 /* Configure mbuf pool watermarks */
1191 if (BNX_IS_57765_PLUS(sc)) {
1192 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1193 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1194 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1195 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1197 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1198 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1201 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1202 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1203 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1206 /* Configure DMA resource watermarks */
1207 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1208 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1210 /* Enable buffer manager */
1211 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1213 * Change the arbitration algorithm of TXMBUF read request to
1214 * round-robin instead of priority based for BCM5719. When
1215 * TXFIFO is almost empty, RDMA will hold its request until
1216 * TXFIFO is not almost empty.
1218 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1219 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1220 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1221 sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1222 sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1223 val |= BGE_BMANMODE_LOMBUF_ATTN;
1224 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1226 /* Poll for buffer manager start indication */
1227 for (i = 0; i < BNX_TIMEOUT; i++) {
1228 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1233 if (i == BNX_TIMEOUT) {
1234 if_printf(&sc->arpcom.ac_if,
1235 "buffer manager failed to start\n");
1239 /* Enable flow-through queues */
1240 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1241 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1243 /* Wait until queue initialization is complete */
1244 for (i = 0; i < BNX_TIMEOUT; i++) {
1245 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1250 if (i == BNX_TIMEOUT) {
1251 if_printf(&sc->arpcom.ac_if,
1252 "flow-through queue init failed\n");
1257 * Summary of rings supported by the controller:
1259 * Standard Receive Producer Ring
1260 * - This ring is used to feed receive buffers for "standard"
1261 * sized frames (typically 1536 bytes) to the controller.
1263 * Jumbo Receive Producer Ring
1264 * - This ring is used to feed receive buffers for jumbo sized
1265 * frames (i.e. anything bigger than the "standard" frames)
1266 * to the controller.
1268 * Mini Receive Producer Ring
1269 * - This ring is used to feed receive buffers for "mini"
1270 * sized frames to the controller.
1271 * - This feature required external memory for the controller
1272 * but was never used in a production system. Should always
1275 * Receive Return Ring
1276 * - After the controller has placed an incoming frame into a
1277 * receive buffer that buffer is moved into a receive return
1278 * ring. The driver is then responsible to passing the
1279 * buffer up to the stack. BCM5718/BCM57785 families support
1280 * multiple receive return rings.
1283 * - This ring is used for outgoing frames. BCM5719/BCM5720
1284 * support multiple send rings.
1287 /* Initialize the standard receive producer ring control block. */
1288 rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1289 rcb->bge_hostaddr.bge_addr_lo =
1290 BGE_ADDR_LO(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1291 rcb->bge_hostaddr.bge_addr_hi =
1292 BGE_ADDR_HI(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1293 if (BNX_IS_57765_PLUS(sc)) {
1295 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1296 * Bits 15-2 : Maximum RX frame size
1297 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
1300 rcb->bge_maxlen_flags =
1301 BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1304 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1305 * Bits 15-2 : Reserved (should be 0)
1306 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1309 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1311 if (BNX_IS_5717_PLUS(sc))
1312 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1314 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1315 /* Write the standard receive producer ring control block. */
1316 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1317 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1318 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1319 if (!BNX_IS_5717_PLUS(sc))
1320 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1321 /* Reset the standard receive producer ring producer index. */
1322 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1325 * Initialize the jumbo RX producer ring control
1326 * block. We set the 'ring disabled' bit in the
1327 * flags field until we're actually ready to start
1328 * using this ring (i.e. once we set the MTU
1329 * high enough to require it).
1331 if (BNX_IS_JUMBO_CAPABLE(sc)) {
1332 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1333 /* Get the jumbo receive producer ring RCB parameters. */
1334 rcb->bge_hostaddr.bge_addr_lo =
1335 BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1336 rcb->bge_hostaddr.bge_addr_hi =
1337 BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1338 rcb->bge_maxlen_flags =
1339 BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1340 BGE_RCB_FLAG_RING_DISABLED);
1341 if (BNX_IS_5717_PLUS(sc))
1342 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1344 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1345 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1346 rcb->bge_hostaddr.bge_addr_hi);
1347 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1348 rcb->bge_hostaddr.bge_addr_lo);
1349 /* Program the jumbo receive producer ring RCB parameters. */
1350 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1351 rcb->bge_maxlen_flags);
1352 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1353 /* Reset the jumbo receive producer ring producer index. */
1354 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1358 * The BD ring replenish thresholds control how often the
1359 * hardware fetches new BD's from the producer rings in host
1360 * memory. Setting the value too low on a busy system can
1361 * starve the hardware and recue the throughpout.
1363 * Set the BD ring replentish thresholds. The recommended
1364 * values are 1/8th the number of descriptors allocated to
1368 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1369 if (BNX_IS_JUMBO_CAPABLE(sc)) {
1370 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1371 BGE_JUMBO_RX_RING_CNT/8);
1373 if (BNX_IS_57765_PLUS(sc)) {
1374 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1375 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1379 * Disable all send rings by setting the 'ring disabled' bit
1380 * in the flags field of all the TX send ring control blocks,
1381 * located in NIC memory.
1383 if (BNX_IS_5717_PLUS(sc))
1385 else if (BNX_IS_57765_FAMILY(sc) ||
1386 sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1390 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1391 for (i = 0; i < limit; i++) {
1392 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1393 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1394 vrcb += sizeof(struct bge_rcb);
1398 * Configure send ring RCBs
1400 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1401 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
1402 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
1404 BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr);
1405 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi,
1407 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo,
1409 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1410 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1411 vrcb += sizeof(struct bge_rcb);
1415 * Disable all receive return rings by setting the
1416 * 'ring disabled' bit in the flags field of all the receive
1417 * return ring control blocks, located in NIC memory.
1419 if (BNX_IS_5717_PLUS(sc)) {
1420 /* Should be 17, use 16 until we get an SRAM map. */
1422 } else if (BNX_IS_57765_FAMILY(sc) ||
1423 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1428 /* Disable all receive return rings. */
1429 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1430 for (i = 0; i < limit; i++) {
1431 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1432 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1433 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1434 BGE_RCB_FLAG_RING_DISABLED);
1435 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1436 (i * (sizeof(uint64_t))), 0);
1437 vrcb += sizeof(struct bge_rcb);
1441 * Set up receive return rings.
1443 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1444 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
1445 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
1447 BGE_HOSTADDR(taddr, ret->bnx_rx_ret_ring_paddr);
1448 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi,
1450 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo,
1452 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1453 BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0));
1454 vrcb += sizeof(struct bge_rcb);
1457 /* Set random backoff seed for TX */
1458 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1459 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1460 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1461 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1462 BGE_TX_BACKOFF_SEED_MASK);
1464 /* Set inter-packet gap */
1466 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1467 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1468 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1469 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1471 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1474 * Specify which ring to use for packets that don't match
1477 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1480 * Configure number of RX lists. One interrupt distribution
1481 * list, sixteen active lists, one bad frames class.
1483 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1485 /* Inialize RX list placement stats mask. */
1486 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1487 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1489 /* Disable host coalescing until we get it set up */
1490 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1492 /* Poll to make sure it's shut down. */
1493 for (i = 0; i < BNX_TIMEOUT; i++) {
1494 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1499 if (i == BNX_TIMEOUT) {
1500 if_printf(&sc->arpcom.ac_if,
1501 "host coalescing engine failed to idle\n");
1505 /* Set up host coalescing defaults */
1506 sc->bnx_coal_chg = BNX_RX_COAL_TICKS_CHG |
1507 BNX_TX_COAL_TICKS_CHG |
1508 BNX_RX_COAL_BDS_CHG |
1509 BNX_TX_COAL_BDS_CHG |
1510 BNX_RX_COAL_BDS_INT_CHG |
1511 BNX_TX_COAL_BDS_INT_CHG;
1512 bnx_coal_change(sc);
1515 * Set up addresses of status blocks
1517 intr = &sc->bnx_intr_data[0];
1518 bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ);
1519 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1520 BGE_ADDR_HI(intr->bnx_status_block_paddr));
1521 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1522 BGE_ADDR_LO(intr->bnx_status_block_paddr));
1523 for (i = 1; i < sc->bnx_intr_cnt; ++i) {
1524 intr = &sc->bnx_intr_data[i];
1525 bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ);
1526 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_HI + ((i - 1) * 8),
1527 BGE_ADDR_HI(intr->bnx_status_block_paddr));
1528 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_LO + ((i - 1) * 8),
1529 BGE_ADDR_LO(intr->bnx_status_block_paddr));
1532 /* Set up status block partail update size. */
1533 val = BGE_STATBLKSZ_32BYTE;
1536 * Does not seem to have visible effect in both
1537 * bulk data (1472B UDP datagram) and tiny data
1538 * (18B UDP datagram) TX tests.
1540 val |= BGE_HCCMODE_CLRTICK_TX;
1542 /* Turn on host coalescing state machine */
1543 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1545 /* Turn on RX BD completion state machine and enable attentions */
1546 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1547 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1549 /* Turn on RX list placement state machine */
1550 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1552 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1553 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1554 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1555 BGE_MACMODE_FRMHDR_DMA_ENB;
1557 if (sc->bnx_flags & BNX_FLAG_TBI)
1558 val |= BGE_PORTMODE_TBI;
1559 else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1560 val |= BGE_PORTMODE_GMII;
1562 val |= BGE_PORTMODE_MII;
1564 /* Turn on DMA, clear stats */
1565 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1567 /* Set misc. local control, enable interrupts on attentions */
1568 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1571 /* Assert GPIO pins for PHY reset */
1572 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1573 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1574 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1575 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1578 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSIX)
1579 bnx_enable_msi(sc, TRUE);
1581 /* Turn on write DMA state machine */
1582 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1583 /* Enable host coalescing bug fix. */
1584 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1585 if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1586 /* Request larger DMA burst size to get better performance. */
1587 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1589 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1592 if (BNX_IS_57765_PLUS(sc)) {
1593 uint32_t dmactl, dmactl_reg;
1595 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1596 dmactl_reg = BGE_RDMA_RSRVCTRL2;
1598 dmactl_reg = BGE_RDMA_RSRVCTRL;
1600 dmactl = CSR_READ_4(sc, dmactl_reg);
1602 * Adjust tx margin to prevent TX data corruption and
1603 * fix internal FIFO overflow.
1605 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1606 sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1607 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1608 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1609 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1610 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1611 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1612 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1613 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1616 * Enable fix for read DMA FIFO overruns.
1617 * The fix is to limit the number of RX BDs
1618 * the hardware would fetch at a fime.
1620 CSR_WRITE_4(sc, dmactl_reg,
1621 dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1624 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1625 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1626 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1627 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1628 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1629 } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1630 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1633 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1634 ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1636 ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1639 * Allow 4KB burst length reads for non-LSO frames.
1640 * Enable 512B burst length reads for buffer descriptors.
1642 CSR_WRITE_4(sc, ctrl_reg,
1643 CSR_READ_4(sc, ctrl_reg) |
1644 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1645 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1648 /* Turn on read DMA state machine */
1649 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1650 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1651 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1652 if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1653 sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1654 sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1655 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1656 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1657 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1659 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1660 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1661 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1662 BGE_RDMAMODE_H2BNC_VLAN_DET;
1664 * Allow multiple outstanding read requests from
1665 * non-LSO read DMA engine.
1667 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1669 if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
1670 val |= BGE_RDMAMODE_JMB_2K_MMRR;
1671 if (sc->bnx_flags & BNX_FLAG_TSO)
1672 val |= BGE_RDMAMODE_TSO4_ENABLE;
1673 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1674 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1677 /* Turn on RX data completion state machine */
1678 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1680 /* Turn on RX BD initiator state machine */
1681 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1683 /* Turn on RX data and RX BD initiator state machine */
1684 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1686 /* Turn on send BD completion state machine */
1687 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1689 /* Turn on send data completion state machine */
1690 val = BGE_SDCMODE_ENABLE;
1691 if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1692 val |= BGE_SDCMODE_CDELAY;
1693 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1695 /* Turn on send data initiator state machine */
1696 if (sc->bnx_flags & BNX_FLAG_TSO) {
1697 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1698 BGE_SDIMODE_HW_LSO_PRE_DMA);
1700 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1703 /* Turn on send BD initiator state machine */
1704 val = BGE_SBDIMODE_ENABLE;
1705 if (sc->bnx_tx_ringcnt > 1)
1706 val |= BGE_SBDIMODE_MULTI_TXR;
1707 CSR_WRITE_4(sc, BGE_SBDI_MODE, val);
1709 /* Turn on send BD selector state machine */
1710 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1712 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1713 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1714 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1716 /* ack/clear link change events */
1717 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1718 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1719 BGE_MACSTAT_LINK_CHANGED);
1720 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1723 * Enable attention when the link has changed state for
1724 * devices that use auto polling.
1726 if (sc->bnx_flags & BNX_FLAG_TBI) {
1727 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1729 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1730 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1736 * Clear any pending link state attention.
1737 * Otherwise some link state change events may be lost until attention
1738 * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1739 * It's not necessary on newer BCM chips - perhaps enabling link
1740 * state change attentions implies clearing pending attention.
1742 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1743 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1744 BGE_MACSTAT_LINK_CHANGED);
1746 /* Enable link state change attentions. */
1747 BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1753 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1754 * against our list and return its name if we find a match. Note
1755 * that since the Broadcom controller contains VPD support, we
1756 * can get the device name string from the controller itself instead
1757 * of the compiled-in string. This is a little slow, but it guarantees
1758 * we'll always announce the right product name.
1761 bnx_probe(device_t dev)
1763 const struct bnx_type *t;
1764 uint16_t product, vendor;
1766 if (!pci_is_pcie(dev))
1769 product = pci_get_device(dev);
1770 vendor = pci_get_vendor(dev);
1772 for (t = bnx_devs; t->bnx_name != NULL; t++) {
1773 if (vendor == t->bnx_vid && product == t->bnx_did)
1776 if (t->bnx_name == NULL)
1779 device_set_desc(dev, t->bnx_name);
1784 bnx_attach(device_t dev)
1787 struct bnx_softc *sc;
1788 struct bnx_rx_std_ring *std;
1790 int error = 0, rid, capmask, i, std_cpuid, std_cpuid_def;
1791 uint8_t ether_addr[ETHER_ADDR_LEN];
1793 uintptr_t mii_priv = 0;
1794 #if defined(BNX_TSO_DEBUG) || defined(BNX_RSS_DEBUG) || defined(BNX_TSS_DEBUG)
1797 #ifdef IFPOLL_ENABLE
1798 int offset, offset_def;
1801 sc = device_get_softc(dev);
1803 callout_init_mp(&sc->bnx_tick_timer);
1804 lwkt_serialize_init(&sc->bnx_jslot_serializer);
1805 lwkt_serialize_init(&sc->bnx_main_serialize);
1807 /* Always setup interrupt mailboxes */
1808 for (i = 0; i < BNX_INTR_MAX; ++i) {
1809 callout_init_mp(&sc->bnx_intr_data[i].bnx_intr_timer);
1810 sc->bnx_intr_data[i].bnx_sc = sc;
1811 sc->bnx_intr_data[i].bnx_intr_mbx = BGE_MBX_IRQ0_LO + (i * 8);
1812 sc->bnx_intr_data[i].bnx_intr_rid = -1;
1813 sc->bnx_intr_data[i].bnx_intr_cpuid = -1;
1816 product = pci_get_device(dev);
1818 #ifndef BURN_BRIDGES
1819 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1822 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1823 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1825 device_printf(dev, "chip is in D%d power mode "
1826 "-- setting to D0\n", pci_get_powerstate(dev));
1828 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1830 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1831 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1833 #endif /* !BURN_BRIDGE */
1836 * Map control/status registers.
1838 pci_enable_busmaster(dev);
1841 sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1844 if (sc->bnx_res == NULL) {
1845 device_printf(dev, "couldn't map memory\n");
1849 sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1850 sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1852 /* Save various chip information */
1854 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1855 BGE_PCIMISCCTL_ASICREV_SHIFT;
1856 if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1857 /* All chips having dedicated ASICREV register have CPMU */
1858 sc->bnx_flags |= BNX_FLAG_CPMU;
1861 case PCI_PRODUCT_BROADCOM_BCM5717:
1862 case PCI_PRODUCT_BROADCOM_BCM5717C:
1863 case PCI_PRODUCT_BROADCOM_BCM5718:
1864 case PCI_PRODUCT_BROADCOM_BCM5719:
1865 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1866 case PCI_PRODUCT_BROADCOM_BCM5725:
1867 case PCI_PRODUCT_BROADCOM_BCM5727:
1868 case PCI_PRODUCT_BROADCOM_BCM5762:
1869 sc->bnx_chipid = pci_read_config(dev,
1870 BGE_PCI_GEN2_PRODID_ASICREV, 4);
1873 case PCI_PRODUCT_BROADCOM_BCM57761:
1874 case PCI_PRODUCT_BROADCOM_BCM57762:
1875 case PCI_PRODUCT_BROADCOM_BCM57765:
1876 case PCI_PRODUCT_BROADCOM_BCM57766:
1877 case PCI_PRODUCT_BROADCOM_BCM57781:
1878 case PCI_PRODUCT_BROADCOM_BCM57782:
1879 case PCI_PRODUCT_BROADCOM_BCM57785:
1880 case PCI_PRODUCT_BROADCOM_BCM57786:
1881 case PCI_PRODUCT_BROADCOM_BCM57791:
1882 case PCI_PRODUCT_BROADCOM_BCM57795:
1883 sc->bnx_chipid = pci_read_config(dev,
1884 BGE_PCI_GEN15_PRODID_ASICREV, 4);
1888 sc->bnx_chipid = pci_read_config(dev,
1889 BGE_PCI_PRODID_ASICREV, 4);
1893 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1894 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1896 sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1897 sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1899 switch (sc->bnx_asicrev) {
1900 case BGE_ASICREV_BCM5717:
1901 case BGE_ASICREV_BCM5719:
1902 case BGE_ASICREV_BCM5720:
1903 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1906 case BGE_ASICREV_BCM5762:
1907 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1910 case BGE_ASICREV_BCM57765:
1911 case BGE_ASICREV_BCM57766:
1912 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1916 sc->bnx_flags |= BNX_FLAG_TSO;
1917 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1918 sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1919 sc->bnx_flags &= ~BNX_FLAG_TSO;
1921 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1922 BNX_IS_57765_FAMILY(sc)) {
1924 * All BCM57785 and BCM5718 families chips have a bug that
1925 * under certain situation interrupt will not be enabled
1926 * even if status tag is written to interrupt mailbox.
1928 * While BCM5719 and BCM5720 have a hardware workaround
1929 * which could fix the above bug.
1930 * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1933 * For the rest of the chips in these two families, we will
1934 * have to poll the status block at high rate (10ms currently)
1935 * to check whether the interrupt is hosed or not.
1936 * See bnx_check_intr_*() for details.
1938 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1941 sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1942 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1943 sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1944 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1946 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1947 device_printf(dev, "CHIP ID 0x%08x; "
1948 "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1949 sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1952 * Set various PHY quirk flags.
1955 capmask = MII_CAPMASK_DEFAULT;
1956 if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1957 product == PCI_PRODUCT_BROADCOM_BCM57795) {
1959 capmask &= ~BMSR_EXTSTAT;
1962 mii_priv |= BRGPHY_FLAG_WIRESPEED;
1963 if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1964 mii_priv |= BRGPHY_FLAG_5762_A0;
1966 /* Initialize if_name earlier, so if_printf could be used */
1967 ifp = &sc->arpcom.ac_if;
1968 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1970 /* Try to reset the chip. */
1973 if (bnx_chipinit(sc)) {
1974 device_printf(dev, "chip initialization failed\n");
1980 * Get station address
1982 error = bnx_get_eaddr(sc, ether_addr);
1984 device_printf(dev, "failed to read station address\n");
1988 /* Setup RX/TX and interrupt count */
1989 bnx_setup_ring_cnt(sc);
1991 if ((sc->bnx_rx_retcnt == 1 && sc->bnx_tx_ringcnt == 1) ||
1992 (sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt > 1)) {
1994 * The RX ring and the corresponding TX ring processing
1995 * should be on the same CPU, since they share the same
1998 sc->bnx_flags |= BNX_FLAG_RXTX_BUNDLE;
2000 device_printf(dev, "RX/TX bundle\n");
2001 if (sc->bnx_tx_ringcnt > 1) {
2003 * Multiple TX rings do not share status block
2004 * with link status, so link status will have
2005 * to save its own status_tag.
2007 sc->bnx_flags |= BNX_FLAG_STATUS_HASTAG;
2009 device_printf(dev, "status needs tag\n");
2012 KKASSERT(sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt == 1);
2014 device_printf(dev, "RX/TX not bundled\n");
2017 error = bnx_dma_alloc(dev);
2021 #ifdef IFPOLL_ENABLE
2022 if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2024 * NPOLLING RX/TX CPU offset
2026 if (sc->bnx_rx_retcnt == ncpus2) {
2030 (sc->bnx_rx_retcnt * device_get_unit(dev)) % ncpus2;
2031 offset = device_getenv_int(dev, "npoll.offset",
2033 if (offset >= ncpus2 ||
2034 offset % sc->bnx_rx_retcnt != 0) {
2035 device_printf(dev, "invalid npoll.offset %d, "
2036 "use %d\n", offset, offset_def);
2037 offset = offset_def;
2040 sc->bnx_npoll_rxoff = offset;
2041 sc->bnx_npoll_txoff = offset;
2044 * NPOLLING RX CPU offset
2046 if (sc->bnx_rx_retcnt == ncpus2) {
2050 (sc->bnx_rx_retcnt * device_get_unit(dev)) % ncpus2;
2051 offset = device_getenv_int(dev, "npoll.rxoff",
2053 if (offset >= ncpus2 ||
2054 offset % sc->bnx_rx_retcnt != 0) {
2055 device_printf(dev, "invalid npoll.rxoff %d, "
2056 "use %d\n", offset, offset_def);
2057 offset = offset_def;
2060 sc->bnx_npoll_rxoff = offset;
2063 * NPOLLING TX CPU offset
2065 offset_def = device_get_unit(dev) % ncpus2;
2066 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
2067 if (offset >= ncpus2) {
2068 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
2069 offset, offset_def);
2070 offset = offset_def;
2072 sc->bnx_npoll_txoff = offset;
2074 #endif /* IFPOLL_ENABLE */
2077 * Allocate interrupt
2079 error = bnx_alloc_intr(sc);
2083 /* Setup serializers */
2084 bnx_setup_serialize(sc);
2086 /* Set default tuneable values. */
2087 sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
2088 sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
2089 sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
2090 sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
2091 sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
2092 sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
2094 /* Set up ifnet structure */
2096 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2097 ifp->if_ioctl = bnx_ioctl;
2098 ifp->if_start = bnx_start;
2099 #ifdef IFPOLL_ENABLE
2100 ifp->if_npoll = bnx_npoll;
2102 ifp->if_init = bnx_init;
2103 ifp->if_serialize = bnx_serialize;
2104 ifp->if_deserialize = bnx_deserialize;
2105 ifp->if_tryserialize = bnx_tryserialize;
2107 ifp->if_serialize_assert = bnx_serialize_assert;
2109 ifp->if_mtu = ETHERMTU;
2110 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2112 ifp->if_capabilities |= IFCAP_HWCSUM;
2113 ifp->if_hwassist = BNX_CSUM_FEATURES;
2114 if (sc->bnx_flags & BNX_FLAG_TSO) {
2115 ifp->if_capabilities |= IFCAP_TSO;
2116 ifp->if_hwassist |= CSUM_TSO;
2118 ifp->if_capenable = ifp->if_capabilities;
2120 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2121 ifq_set_ready(&ifp->if_snd);
2122 ifq_set_subq_cnt(&ifp->if_snd, sc->bnx_tx_ringcnt);
2124 if (sc->bnx_tx_ringcnt > 1) {
2125 ifp->if_mapsubq = ifq_mapsubq_mask;
2126 ifq_set_subq_mask(&ifp->if_snd, sc->bnx_tx_ringcnt - 1);
2130 * Figure out what sort of media we have by checking the
2131 * hardware config word in the first 32k of NIC internal memory,
2132 * or fall back to examining the EEPROM if necessary.
2133 * Note: on some BCM5700 cards, this value appears to be unset.
2134 * If that's the case, we have to rely on identifying the NIC
2135 * by its PCI subsystem ID, as we do below for the SysKonnect
2138 if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2139 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2141 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2143 device_printf(dev, "failed to read EEPROM\n");
2147 hwcfg = ntohl(hwcfg);
2150 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2151 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2152 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2153 sc->bnx_flags |= BNX_FLAG_TBI;
2156 if (sc->bnx_flags & BNX_FLAG_CPMU)
2157 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
2159 sc->bnx_mi_mode = BGE_MIMODE_BASE;
2161 /* Setup link status update stuffs */
2162 if (sc->bnx_flags & BNX_FLAG_TBI) {
2163 sc->bnx_link_upd = bnx_tbi_link_upd;
2164 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2165 } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
2166 sc->bnx_link_upd = bnx_autopoll_link_upd;
2167 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2169 sc->bnx_link_upd = bnx_copper_link_upd;
2170 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2173 /* Set default PHY address */
2177 * PHY address mapping for various devices.
2179 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2180 * ---------+-------+-------+-------+-------+
2181 * BCM57XX | 1 | X | X | X |
2182 * BCM5704 | 1 | X | 1 | X |
2183 * BCM5717 | 1 | 8 | 2 | 9 |
2184 * BCM5719 | 1 | 8 | 2 | 9 |
2185 * BCM5720 | 1 | 8 | 2 | 9 |
2187 * Other addresses may respond but they are not
2188 * IEEE compliant PHYs and should be ignored.
2190 if (BNX_IS_5717_PLUS(sc)) {
2193 f = pci_get_function(dev);
2194 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
2195 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2196 BGE_SGDIGSTS_IS_SERDES)
2197 sc->bnx_phyno = f + 8;
2199 sc->bnx_phyno = f + 1;
2201 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2202 BGE_CPMU_PHY_STRAP_IS_SERDES)
2203 sc->bnx_phyno = f + 8;
2205 sc->bnx_phyno = f + 1;
2209 if (sc->bnx_flags & BNX_FLAG_TBI) {
2210 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
2211 bnx_ifmedia_upd, bnx_ifmedia_sts);
2212 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2213 ifmedia_add(&sc->bnx_ifmedia,
2214 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2215 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2216 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2217 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2219 struct mii_probe_args mii_args;
2221 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2222 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2223 mii_args.mii_capmask = capmask;
2224 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2225 mii_args.mii_priv = mii_priv;
2227 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2229 device_printf(dev, "MII without any PHY!\n");
2235 * Create sysctl nodes.
2237 sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2238 sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2239 SYSCTL_STATIC_CHILDREN(_hw),
2241 device_get_nameunit(dev),
2243 if (sc->bnx_sysctl_tree == NULL) {
2244 device_printf(dev, "can't add sysctl node\n");
2249 SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2250 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2251 "rx_rings", CTLFLAG_RD, &sc->bnx_rx_retcnt, 0, "# of RX rings");
2252 SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2253 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2254 "tx_rings", CTLFLAG_RD, &sc->bnx_tx_ringcnt, 0, "# of TX rings");
2256 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2257 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2258 OID_AUTO, "rx_coal_ticks",
2259 CTLTYPE_INT | CTLFLAG_RW,
2260 sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2261 "Receive coalescing ticks (usec).");
2262 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2263 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2264 OID_AUTO, "tx_coal_ticks",
2265 CTLTYPE_INT | CTLFLAG_RW,
2266 sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2267 "Transmit coalescing ticks (usec).");
2268 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2269 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2270 OID_AUTO, "rx_coal_bds",
2271 CTLTYPE_INT | CTLFLAG_RW,
2272 sc, 0, bnx_sysctl_rx_coal_bds, "I",
2273 "Receive max coalesced BD count.");
2274 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2275 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2276 OID_AUTO, "tx_coal_bds",
2277 CTLTYPE_INT | CTLFLAG_RW,
2278 sc, 0, bnx_sysctl_tx_coal_bds, "I",
2279 "Transmit max coalesced BD count.");
2281 * A common design characteristic for many Broadcom
2282 * client controllers is that they only support a
2283 * single outstanding DMA read operation on the PCIe
2284 * bus. This means that it will take twice as long to
2285 * fetch a TX frame that is split into header and
2286 * payload buffers as it does to fetch a single,
2287 * contiguous TX frame (2 reads vs. 1 read). For these
2288 * controllers, coalescing buffers to reduce the number
2289 * of memory reads is effective way to get maximum
2290 * performance(about 940Mbps). Without collapsing TX
2291 * buffers the maximum TCP bulk transfer performance
2292 * is about 850Mbps. However forcing coalescing mbufs
2293 * consumes a lot of CPU cycles, so leave it off by
2296 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2297 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2298 "force_defrag", CTLTYPE_INT | CTLFLAG_RW,
2299 sc, 0, bnx_sysctl_force_defrag, "I",
2300 "Force defragment on TX path");
2302 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2303 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2304 "tx_wreg", CTLTYPE_INT | CTLFLAG_RW,
2305 sc, 0, bnx_sysctl_tx_wreg, "I",
2306 "# of segments before writing to hardware register");
2308 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2309 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2310 "std_refill", CTLTYPE_INT | CTLFLAG_RW,
2311 sc, 0, bnx_sysctl_std_refill, "I",
2312 "# of packets received before scheduling standard refilling");
2314 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2315 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2316 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2317 sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2318 "Receive max coalesced BD count during interrupt.");
2319 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2320 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2321 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2322 sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2323 "Transmit max coalesced BD count during interrupt.");
2325 #ifdef IFPOLL_ENABLE
2326 if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2327 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2328 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2329 "npoll_offset", CTLTYPE_INT | CTLFLAG_RW,
2330 sc, 0, bnx_sysctl_npoll_offset, "I",
2331 "NPOLLING cpu offset");
2333 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2334 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2335 "npoll_rxoff", CTLTYPE_INT | CTLFLAG_RW,
2336 sc, 0, bnx_sysctl_npoll_rxoff, "I",
2337 "NPOLLING RX cpu offset");
2338 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2339 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2340 "npoll_txoff", CTLTYPE_INT | CTLFLAG_RW,
2341 sc, 0, bnx_sysctl_npoll_txoff, "I",
2342 "NPOLLING TX cpu offset");
2346 #ifdef BNX_RSS_DEBUG
2347 SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2348 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2349 "std_refill_mask", CTLFLAG_RD,
2350 &sc->bnx_rx_std_ring.bnx_rx_std_refill, 0, "");
2351 SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2352 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2353 "rss_debug", CTLFLAG_RW, &sc->bnx_rss_debug, 0, "");
2354 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
2355 ksnprintf(desc, sizeof(desc), "rx_pkt%d", i);
2356 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2357 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2358 desc, CTLFLAG_RW, &sc->bnx_rx_ret_ring[i].bnx_rx_pkt, "");
2361 #ifdef BNX_TSS_DEBUG
2362 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2363 ksnprintf(desc, sizeof(desc), "tx_pkt%d", i);
2364 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2365 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2366 desc, CTLFLAG_RW, &sc->bnx_tx_ring[i].bnx_tx_pkt, "");
2370 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2371 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2372 "norxbds", CTLFLAG_RW, &sc->bnx_norxbds, "");
2374 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2375 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2376 "errors", CTLFLAG_RW, &sc->bnx_errors, "");
2378 #ifdef BNX_TSO_DEBUG
2379 for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2380 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2381 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2382 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2383 desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2388 * Call MI attach routine.
2390 ether_ifattach(ifp, ether_addr, NULL);
2392 /* Setup TX rings and subqueues */
2393 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2394 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2395 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
2397 ifsq_set_cpuid(ifsq, txr->bnx_tx_cpuid);
2398 ifsq_set_hw_serialize(ifsq, &txr->bnx_tx_serialize);
2399 ifsq_set_priv(ifsq, txr);
2400 txr->bnx_ifsq = ifsq;
2402 ifsq_watchdog_init(&txr->bnx_tx_watchdog, ifsq, bnx_watchdog);
2405 device_printf(dev, "txr %d -> cpu%d\n", i,
2410 error = bnx_setup_intr(sc);
2412 ether_ifdetach(ifp);
2415 bnx_set_tick_cpuid(sc, FALSE);
2418 * Create RX standard ring refilling thread
2420 std_cpuid_def = device_get_unit(dev) % ncpus;
2421 std_cpuid = device_getenv_int(dev, "std.cpuid", std_cpuid_def);
2422 if (std_cpuid < 0 || std_cpuid >= ncpus) {
2423 device_printf(dev, "invalid std.cpuid %d, use %d\n",
2424 std_cpuid, std_cpuid_def);
2425 std_cpuid = std_cpuid_def;
2428 std = &sc->bnx_rx_std_ring;
2429 lwkt_create(bnx_rx_std_refill_ithread, std, NULL,
2430 &std->bnx_rx_std_ithread, TDF_NOSTART | TDF_INTTHREAD, std_cpuid,
2431 "%s std", device_get_nameunit(dev));
2432 lwkt_setpri(&std->bnx_rx_std_ithread, TDPRI_INT_MED);
2433 std->bnx_rx_std_ithread.td_preemptable = lwkt_preempt;
2434 sc->bnx_flags |= BNX_FLAG_STD_THREAD;
2443 bnx_detach(device_t dev)
2445 struct bnx_softc *sc = device_get_softc(dev);
2447 if (device_is_attached(dev)) {
2448 struct ifnet *ifp = &sc->arpcom.ac_if;
2450 ifnet_serialize_all(ifp);
2453 bnx_teardown_intr(sc, sc->bnx_intr_cnt);
2454 ifnet_deserialize_all(ifp);
2456 ether_ifdetach(ifp);
2459 if (sc->bnx_flags & BNX_FLAG_STD_THREAD) {
2460 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
2462 tsleep_interlock(std, 0);
2464 if (std->bnx_rx_std_ithread.td_gd == mycpu) {
2465 bnx_rx_std_refill_stop(std);
2467 lwkt_send_ipiq(std->bnx_rx_std_ithread.td_gd,
2468 bnx_rx_std_refill_stop, std);
2471 tsleep(std, PINTERLOCKED, "bnx_detach", 0);
2473 device_printf(dev, "RX std ithread exited\n");
2475 lwkt_synchronize_ipiqs("bnx_detach_ipiq");
2478 if (sc->bnx_flags & BNX_FLAG_TBI)
2479 ifmedia_removeall(&sc->bnx_ifmedia);
2481 device_delete_child(dev, sc->bnx_miibus);
2482 bus_generic_detach(dev);
2486 if (sc->bnx_msix_mem_res != NULL) {
2487 bus_release_resource(dev, SYS_RES_MEMORY, sc->bnx_msix_mem_rid,
2488 sc->bnx_msix_mem_res);
2490 if (sc->bnx_res != NULL) {
2491 bus_release_resource(dev, SYS_RES_MEMORY,
2492 BGE_PCI_BAR0, sc->bnx_res);
2495 if (sc->bnx_sysctl_tree != NULL)
2496 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2500 if (sc->bnx_serialize != NULL)
2501 kfree(sc->bnx_serialize, M_DEVBUF);
2507 bnx_reset(struct bnx_softc *sc)
2510 uint32_t cachesize, command, pcistate, reset;
2511 void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2517 write_op = bnx_writemem_direct;
2519 /* Save some important PCI state. */
2520 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2521 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2522 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2524 pci_write_config(dev, BGE_PCI_MISC_CTL,
2525 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2526 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2527 BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2529 /* Disable fastboot on controllers that support it. */
2531 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2532 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2535 * Write the magic number to SRAM at offset 0xB50.
2536 * When firmware finishes its initialization it will
2537 * write ~BGE_MAGIC_NUMBER to the same location.
2539 bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2541 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2543 /* XXX: Broadcom Linux driver. */
2544 /* Force PCI-E 1.0a mode */
2545 if (!BNX_IS_57765_PLUS(sc) &&
2546 CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2547 (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2548 BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2549 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2550 BGE_PCIE_PHY_TSTCTL_PSCRAM);
2552 if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2553 /* Prevent PCIE link training during global reset */
2554 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2559 * Set GPHY Power Down Override to leave GPHY
2560 * powered up in D0 uninitialized.
2562 if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2563 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2565 /* Issue global reset */
2566 write_op(sc, BGE_MISC_CFG, reset);
2570 /* XXX: Broadcom Linux driver. */
2571 if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2574 DELAY(500000); /* wait for link training to complete */
2575 v = pci_read_config(dev, 0xc4, 4);
2576 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2579 devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2581 /* Disable no snoop and disable relaxed ordering. */
2582 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2584 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2585 if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2586 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2587 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2590 pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2593 /* Clear error status. */
2594 pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2595 PCIEM_DEVSTS_CORR_ERR |
2596 PCIEM_DEVSTS_NFATAL_ERR |
2597 PCIEM_DEVSTS_FATAL_ERR |
2598 PCIEM_DEVSTS_UNSUPP_REQ, 2);
2600 /* Reset some of the PCI state that got zapped by reset */
2601 pci_write_config(dev, BGE_PCI_MISC_CTL,
2602 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2603 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2604 BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2605 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2606 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2607 write_op(sc, BGE_MISC_CFG, (65 << 1));
2609 /* Enable memory arbiter */
2610 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2613 * Poll until we see the 1's complement of the magic number.
2614 * This indicates that the firmware initialization is complete.
2616 for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2617 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2618 if (val == ~BGE_MAGIC_NUMBER)
2622 if (i == BNX_FIRMWARE_TIMEOUT) {
2623 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2624 "timed out, found 0x%08x\n", val);
2627 /* BCM57765 A0 needs additional time before accessing. */
2628 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2632 * XXX Wait for the value of the PCISTATE register to
2633 * return to its original pre-reset state. This is a
2634 * fairly good indicator of reset completion. If we don't
2635 * wait for the reset to fully complete, trying to read
2636 * from the device's non-PCI registers may yield garbage
2639 for (i = 0; i < BNX_TIMEOUT; i++) {
2640 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2645 /* Fix up byte swapping */
2646 CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2648 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2651 * The 5704 in TBI mode apparently needs some special
2652 * adjustment to insure the SERDES drive level is set
2655 if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2656 (sc->bnx_flags & BNX_FLAG_TBI)) {
2659 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2660 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2661 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2664 CSR_WRITE_4(sc, BGE_MI_MODE,
2665 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2668 /* XXX: Broadcom Linux driver. */
2669 if (!BNX_IS_57765_PLUS(sc)) {
2672 /* Enable Data FIFO protection. */
2673 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2674 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2679 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2680 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2681 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2686 * Frame reception handling. This is called if there's a frame
2687 * on the receive return list.
2689 * Note: we have to be able to handle two possibilities here:
2690 * 1) the frame is from the jumbo recieve ring
2691 * 2) the frame is from the standard receive ring
2695 bnx_rxeof(struct bnx_rx_ret_ring *ret, uint16_t rx_prod, int count)
2697 struct bnx_softc *sc = ret->bnx_sc;
2698 struct bnx_rx_std_ring *std = ret->bnx_std;
2699 struct ifnet *ifp = &sc->arpcom.ac_if;
2701 while (ret->bnx_rx_saved_considx != rx_prod && count != 0) {
2702 struct bge_rx_bd *cur_rx;
2703 struct bnx_rx_buf *rb;
2705 struct mbuf *m = NULL;
2706 uint16_t vlan_tag = 0;
2711 cur_rx = &ret->bnx_rx_ret_ring[ret->bnx_rx_saved_considx];
2713 rxidx = cur_rx->bge_idx;
2714 KKASSERT(rxidx < BGE_STD_RX_RING_CNT);
2716 BNX_INC(ret->bnx_rx_saved_considx, BNX_RETURN_RING_CNT);
2717 #ifdef BNX_RSS_DEBUG
2721 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2723 vlan_tag = cur_rx->bge_vlan_tag;
2726 if (ret->bnx_rx_cnt >= ret->bnx_rx_cntmax)
2727 bnx_rx_std_refill_sched(ret, std);
2730 rb = &std->bnx_rx_std_buf[rxidx];
2731 m = rb->bnx_rx_mbuf;
2732 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2733 IFNET_STAT_INC(ifp, ierrors, 1);
2735 rb->bnx_rx_refilled = 1;
2738 if (bnx_newbuf_std(ret, rxidx, 0)) {
2739 IFNET_STAT_INC(ifp, ierrors, 1);
2743 IFNET_STAT_INC(ifp, ipackets, 1);
2744 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2745 m->m_pkthdr.rcvif = ifp;
2747 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2748 (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2749 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2750 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2751 if ((cur_rx->bge_error_flag &
2752 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2753 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2755 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2756 m->m_pkthdr.csum_data =
2757 cur_rx->bge_tcp_udp_csum;
2758 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2764 * If we received a packet with a vlan tag, pass it
2765 * to vlan_input() instead of ether_input().
2768 m->m_flags |= M_VLANTAG;
2769 m->m_pkthdr.ether_vlantag = vlan_tag;
2771 ifp->if_input(ifp, m);
2773 bnx_writembx(sc, ret->bnx_rx_mbx, ret->bnx_rx_saved_considx);
2775 if (ret->bnx_rx_cnt > 0)
2776 bnx_rx_std_refill_sched(ret, std);
2780 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons)
2782 struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if;
2785 * Go through our tx ring and free mbufs for those
2786 * frames that have been sent.
2788 while (txr->bnx_tx_saved_considx != tx_cons) {
2789 struct bnx_tx_buf *buf;
2792 idx = txr->bnx_tx_saved_considx;
2793 buf = &txr->bnx_tx_buf[idx];
2794 if (buf->bnx_tx_mbuf != NULL) {
2795 IFNET_STAT_INC(ifp, opackets, 1);
2796 #ifdef BNX_TSS_DEBUG
2799 bus_dmamap_unload(txr->bnx_tx_mtag,
2800 buf->bnx_tx_dmamap);
2801 m_freem(buf->bnx_tx_mbuf);
2802 buf->bnx_tx_mbuf = NULL;
2805 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2808 if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) >=
2809 (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2810 ifsq_clr_oactive(txr->bnx_ifsq);
2812 if (txr->bnx_tx_cnt == 0)
2813 txr->bnx_tx_watchdog.wd_timer = 0;
2815 if (!ifsq_is_empty(txr->bnx_ifsq))
2816 ifsq_devstart(txr->bnx_ifsq);
2820 bnx_handle_status(struct bnx_softc *sc)
2824 status = *sc->bnx_hw_status;
2826 if (status & BGE_STATFLAG_ERROR) {
2832 val = CSR_READ_4(sc, BGE_FLOW_ATTN);
2833 if (val & ~BGE_FLOWATTN_MB_LOWAT) {
2834 if_printf(&sc->arpcom.ac_if,
2835 "flow attn 0x%08x\n", val);
2839 val = CSR_READ_4(sc, BGE_MSI_STATUS);
2840 if (val & ~BGE_MSISTAT_MSI_PCI_REQ) {
2841 if_printf(&sc->arpcom.ac_if,
2842 "msi status 0x%08x\n", val);
2846 val = CSR_READ_4(sc, BGE_RDMA_STATUS);
2848 if_printf(&sc->arpcom.ac_if,
2849 "rmda status 0x%08x\n", val);
2853 val = CSR_READ_4(sc, BGE_WDMA_STATUS);
2855 if_printf(&sc->arpcom.ac_if,
2856 "wdma status 0x%08x\n", val);
2861 bnx_serialize_skipmain(sc);
2863 bnx_deserialize_skipmain(sc);
2867 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2871 #ifdef IFPOLL_ENABLE
2874 bnx_npoll_rx(struct ifnet *ifp __unused, void *xret, int cycle)
2876 struct bnx_rx_ret_ring *ret = xret;
2879 ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
2881 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
2884 rx_prod = *ret->bnx_rx_considx;
2885 if (ret->bnx_rx_saved_considx != rx_prod)
2886 bnx_rxeof(ret, rx_prod, cycle);
2890 bnx_npoll_tx_notag(struct ifnet *ifp __unused, void *xtxr, int cycle __unused)
2892 struct bnx_tx_ring *txr = xtxr;
2895 ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
2897 tx_cons = *txr->bnx_tx_considx;
2898 if (txr->bnx_tx_saved_considx != tx_cons)
2899 bnx_txeof(txr, tx_cons);
2903 bnx_npoll_tx(struct ifnet *ifp, void *xtxr, int cycle)
2905 struct bnx_tx_ring *txr = xtxr;
2907 ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
2909 txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag;
2911 bnx_npoll_tx_notag(ifp, txr, cycle);
2915 bnx_npoll_status_notag(struct ifnet *ifp)
2917 struct bnx_softc *sc = ifp->if_softc;
2919 ASSERT_SERIALIZED(&sc->bnx_main_serialize);
2921 bnx_handle_status(sc);
2925 bnx_npoll_status(struct ifnet *ifp)
2927 struct bnx_softc *sc = ifp->if_softc;
2929 ASSERT_SERIALIZED(&sc->bnx_main_serialize);
2931 sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag;
2933 bnx_npoll_status_notag(ifp);
2937 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2939 struct bnx_softc *sc = ifp->if_softc;
2942 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2945 if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG)
2946 info->ifpi_status.status_func = bnx_npoll_status;
2948 info->ifpi_status.status_func = bnx_npoll_status_notag;
2949 info->ifpi_status.serializer = &sc->bnx_main_serialize;
2951 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2952 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
2953 int idx = i + sc->bnx_npoll_txoff;
2955 KKASSERT(idx < ncpus2);
2956 if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2957 info->ifpi_tx[idx].poll_func =
2960 info->ifpi_tx[idx].poll_func = bnx_npoll_tx;
2962 info->ifpi_tx[idx].arg = txr;
2963 info->ifpi_tx[idx].serializer = &txr->bnx_tx_serialize;
2964 ifsq_set_cpuid(txr->bnx_ifsq, idx);
2967 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
2968 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
2969 int idx = i + sc->bnx_npoll_rxoff;
2971 KKASSERT(idx < ncpus2);
2972 info->ifpi_rx[idx].poll_func = bnx_npoll_rx;
2973 info->ifpi_rx[idx].arg = ret;
2974 info->ifpi_rx[idx].serializer =
2975 &ret->bnx_rx_ret_serialize;
2978 if (ifp->if_flags & IFF_RUNNING) {
2979 bnx_disable_intr(sc);
2980 bnx_set_tick_cpuid(sc, TRUE);
2983 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2984 ifsq_set_cpuid(sc->bnx_tx_ring[i].bnx_ifsq,
2985 sc->bnx_tx_ring[i].bnx_tx_cpuid);
2987 if (ifp->if_flags & IFF_RUNNING) {
2988 bnx_enable_intr(sc);
2989 bnx_set_tick_cpuid(sc, FALSE);
2994 #endif /* IFPOLL_ENABLE */
2997 bnx_intr_legacy(void *xsc)
2999 struct bnx_softc *sc = xsc;
3000 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
3002 if (ret->bnx_saved_status_tag == *ret->bnx_hw_status_tag) {
3005 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
3006 if (val & BGE_PCISTAT_INTR_NOTACT)
3012 * Interrupt will have to be disabled if tagged status
3013 * is used, else interrupt will always be asserted on
3014 * certain chips (at least on BCM5750 AX/BX).
3016 bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3028 bnx_intr(struct bnx_softc *sc)
3030 struct ifnet *ifp = &sc->arpcom.ac_if;
3031 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
3033 ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3035 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3037 * Use a load fence to ensure that status_tag is saved
3038 * before rx_prod, tx_cons and status.
3042 bnx_handle_status(sc);
3044 if (ifp->if_flags & IFF_RUNNING) {
3045 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
3046 uint16_t rx_prod, tx_cons;
3048 lwkt_serialize_enter(&ret->bnx_rx_ret_serialize);
3049 rx_prod = *ret->bnx_rx_considx;
3050 if (ret->bnx_rx_saved_considx != rx_prod)
3051 bnx_rxeof(ret, rx_prod, -1);
3052 lwkt_serialize_exit(&ret->bnx_rx_ret_serialize);
3054 lwkt_serialize_enter(&txr->bnx_tx_serialize);
3055 tx_cons = *txr->bnx_tx_considx;
3056 if (txr->bnx_tx_saved_considx != tx_cons)
3057 bnx_txeof(txr, tx_cons);
3058 lwkt_serialize_exit(&txr->bnx_tx_serialize);
3061 bnx_writembx(sc, BGE_MBX_IRQ0_LO, ret->bnx_saved_status_tag << 24);
3065 bnx_msix_tx_status(void *xtxr)
3067 struct bnx_tx_ring *txr = xtxr;
3068 struct bnx_softc *sc = txr->bnx_sc;
3069 struct ifnet *ifp = &sc->arpcom.ac_if;
3071 ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3073 txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag;
3075 * Use a load fence to ensure that status_tag is saved
3076 * before tx_cons and status.
3080 bnx_handle_status(sc);
3082 if (ifp->if_flags & IFF_RUNNING) {
3085 lwkt_serialize_enter(&txr->bnx_tx_serialize);
3086 tx_cons = *txr->bnx_tx_considx;
3087 if (txr->bnx_tx_saved_considx != tx_cons)
3088 bnx_txeof(txr, tx_cons);
3089 lwkt_serialize_exit(&txr->bnx_tx_serialize);
3092 bnx_writembx(sc, BGE_MBX_IRQ0_LO, txr->bnx_saved_status_tag << 24);
3096 bnx_msix_rx(void *xret)
3098 struct bnx_rx_ret_ring *ret = xret;
3101 ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
3103 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3105 * Use a load fence to ensure that status_tag is saved
3110 rx_prod = *ret->bnx_rx_considx;
3111 if (ret->bnx_rx_saved_considx != rx_prod)
3112 bnx_rxeof(ret, rx_prod, -1);
3114 bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx,
3115 ret->bnx_saved_status_tag << 24);
3119 bnx_msix_rxtx(void *xret)
3121 struct bnx_rx_ret_ring *ret = xret;
3122 struct bnx_tx_ring *txr = ret->bnx_txr;
3123 uint16_t rx_prod, tx_cons;
3125 ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
3127 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3129 * Use a load fence to ensure that status_tag is saved
3130 * before rx_prod and tx_cons.
3134 rx_prod = *ret->bnx_rx_considx;
3135 if (ret->bnx_rx_saved_considx != rx_prod)
3136 bnx_rxeof(ret, rx_prod, -1);
3138 lwkt_serialize_enter(&txr->bnx_tx_serialize);
3139 tx_cons = *txr->bnx_tx_considx;
3140 if (txr->bnx_tx_saved_considx != tx_cons)
3141 bnx_txeof(txr, tx_cons);
3142 lwkt_serialize_exit(&txr->bnx_tx_serialize);
3144 bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx,
3145 ret->bnx_saved_status_tag << 24);
3149 bnx_msix_status(void *xsc)
3151 struct bnx_softc *sc = xsc;
3153 ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3155 sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag;
3157 * Use a load fence to ensure that status_tag is saved
3162 bnx_handle_status(sc);
3164 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_saved_status_tag << 24);
3170 struct bnx_softc *sc = xsc;
3172 lwkt_serialize_enter(&sc->bnx_main_serialize);
3174 bnx_stats_update_regs(sc);
3176 if (sc->bnx_flags & BNX_FLAG_TBI) {
3178 * Since in TBI mode auto-polling can't be used we should poll
3179 * link status manually. Here we register pending link event
3180 * and trigger interrupt.
3183 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3184 } else if (!sc->bnx_link) {
3185 mii_tick(device_get_softc(sc->bnx_miibus));
3188 callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc,
3189 sc->bnx_tick_cpuid);
3191 lwkt_serialize_exit(&sc->bnx_main_serialize);
3195 bnx_stats_update_regs(struct bnx_softc *sc)
3197 struct ifnet *ifp = &sc->arpcom.ac_if;
3198 struct bge_mac_stats_regs stats;
3202 s = (uint32_t *)&stats;
3203 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3204 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3208 IFNET_STAT_SET(ifp, collisions,
3209 (stats.dot3StatsSingleCollisionFrames +
3210 stats.dot3StatsMultipleCollisionFrames +
3211 stats.dot3StatsExcessiveCollisions +
3212 stats.dot3StatsLateCollisions));
3214 val = CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3215 sc->bnx_norxbds += val;
3219 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3220 * pointers to descriptors.
3223 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx,
3226 struct bge_tx_bd *d = NULL;
3227 uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
3228 bus_dma_segment_t segs[BNX_NSEG_NEW];
3230 int error, maxsegs, nsegs, idx, i;
3231 struct mbuf *m_head = *m_head0, *m_new;
3233 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3234 #ifdef BNX_TSO_DEBUG
3238 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags);
3243 #ifdef BNX_TSO_DEBUG
3244 tso_nsegs = (m_head->m_pkthdr.len /
3245 m_head->m_pkthdr.tso_segsz) - 1;
3246 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
3247 tso_nsegs = BNX_TSO_NSTATS - 1;
3248 else if (tso_nsegs < 0)
3250 txr->bnx_sc->bnx_tsosegs[tso_nsegs]++;
3252 } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
3253 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3254 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3255 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3256 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3257 if (m_head->m_flags & M_LASTFRAG)
3258 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3259 else if (m_head->m_flags & M_FRAG)
3260 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3262 if (m_head->m_flags & M_VLANTAG) {
3263 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3264 vlan_tag = m_head->m_pkthdr.ether_vlantag;
3268 map = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
3270 maxsegs = (BGE_TX_RING_CNT - txr->bnx_tx_cnt) - BNX_NSEG_RSVD;
3271 KASSERT(maxsegs >= BNX_NSEG_SPARE,
3272 ("not enough segments %d", maxsegs));
3274 if (maxsegs > BNX_NSEG_NEW)
3275 maxsegs = BNX_NSEG_NEW;
3278 * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
3279 * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
3280 * but when such padded frames employ the bge IP/TCP checksum
3281 * offload, the hardware checksum assist gives incorrect results
3282 * (possibly from incorporating its own padding into the UDP/TCP
3283 * checksum; who knows). If we pad such runts with zeros, the
3284 * onboard checksum comes out correct.
3286 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3287 m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
3288 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
3293 if ((txr->bnx_tx_flags & BNX_TX_FLAG_SHORTDMA) &&
3294 m_head->m_next != NULL) {
3295 m_new = bnx_defrag_shortdma(m_head);
3296 if (m_new == NULL) {
3300 *m_head0 = m_head = m_new;
3302 if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3303 (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) &&
3304 m_head->m_next != NULL) {
3306 * Forcefully defragment mbuf chain to overcome hardware
3307 * limitation which only support a single outstanding
3308 * DMA read operation. If it fails, keep moving on using
3309 * the original mbuf chain.
3311 m_new = m_defrag(m_head, MB_DONTWAIT);
3313 *m_head0 = m_head = m_new;
3316 error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map,
3317 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3320 *segs_used += nsegs;
3323 bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3325 for (i = 0; ; i++) {
3326 d = &txr->bnx_tx_ring[idx];
3328 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3329 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3330 d->bge_len = segs[i].ds_len;
3331 d->bge_flags = csum_flags;
3332 d->bge_vlan_tag = vlan_tag;
3337 BNX_INC(idx, BGE_TX_RING_CNT);
3339 /* Mark the last segment as end of packet... */
3340 d->bge_flags |= BGE_TXBDFLAG_END;
3343 * Insure that the map for this transmission is placed at
3344 * the array index of the last descriptor in this chain.
3346 txr->bnx_tx_buf[*txidx].bnx_tx_dmamap = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
3347 txr->bnx_tx_buf[idx].bnx_tx_dmamap = map;
3348 txr->bnx_tx_buf[idx].bnx_tx_mbuf = m_head;
3349 txr->bnx_tx_cnt += nsegs;
3351 BNX_INC(idx, BGE_TX_RING_CNT);
3362 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3363 * to the mbuf data regions directly in the transmit descriptors.
3366 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3368 struct bnx_tx_ring *txr = ifsq_get_priv(ifsq);
3369 struct mbuf *m_head = NULL;
3373 KKASSERT(txr->bnx_ifsq == ifsq);
3374 ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
3376 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3379 prodidx = txr->bnx_tx_prodidx;
3381 while (txr->bnx_tx_buf[prodidx].bnx_tx_mbuf == NULL) {
3383 * Sanity check: avoid coming within BGE_NSEG_RSVD
3384 * descriptors of the end of the ring. Also make
3385 * sure there are BGE_NSEG_SPARE descriptors for
3386 * jumbo buffers' or TSO segments' defragmentation.
3388 if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) <
3389 (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
3390 ifsq_set_oactive(ifsq);
3394 m_head = ifsq_dequeue(ifsq, NULL);
3399 * Pack the data into the transmit ring. If we
3400 * don't have room, set the OACTIVE flag and wait
3401 * for the NIC to drain the ring.
3403 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) {
3404 ifsq_set_oactive(ifsq);
3405 IFNET_STAT_INC(ifp, oerrors, 1);
3409 if (nsegs >= txr->bnx_tx_wreg) {
3411 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
3415 ETHER_BPF_MTAP(ifp, m_head);
3418 * Set a timeout in case the chip goes out to lunch.
3420 txr->bnx_tx_watchdog.wd_timer = 5;
3425 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
3427 txr->bnx_tx_prodidx = prodidx;
3433 struct bnx_softc *sc = xsc;
3434 struct ifnet *ifp = &sc->arpcom.ac_if;
3440 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3442 /* Cancel pending I/O and flush buffers. */
3448 * Init the various state machines, ring
3449 * control blocks and firmware.
3451 if (bnx_blockinit(sc)) {
3452 if_printf(ifp, "initialization failure\n");
3458 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3459 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3461 /* Load our MAC address. */
3462 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3463 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3464 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3466 /* Enable or disable promiscuous mode as needed. */
3469 /* Program multicast filter. */
3473 if (bnx_init_rx_ring_std(&sc->bnx_rx_std_ring)) {
3474 if_printf(ifp, "RX ring initialization failed\n");
3479 /* Init jumbo RX ring. */
3480 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3481 if (bnx_init_rx_ring_jumbo(sc)) {
3482 if_printf(ifp, "Jumbo RX ring initialization failed\n");
3488 /* Init our RX return ring index */
3489 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
3490 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
3492 ret->bnx_rx_saved_considx = 0;
3493 ret->bnx_rx_cnt = 0;
3497 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3498 bnx_init_tx_ring(&sc->bnx_tx_ring[i]);
3500 /* Enable TX MAC state machine lockup fix. */
3501 mode = CSR_READ_4(sc, BGE_TX_MODE);
3502 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3503 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
3504 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
3505 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3506 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3507 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3509 /* Turn on transmitter */
3510 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3512 /* Initialize RSS */
3513 mode = BGE_RXMODE_ENABLE;
3514 if (BNX_RSS_ENABLED(sc)) {
3516 mode |= BGE_RXMODE_RSS_ENABLE |
3517 BGE_RXMODE_RSS_HASH_MASK_BITS |
3518 BGE_RXMODE_RSS_IPV4_HASH |
3519 BGE_RXMODE_RSS_TCP_IPV4_HASH;
3521 /* Turn on receiver */
3522 BNX_SETBIT(sc, BGE_RX_MODE, mode);
3525 * Set the number of good frames to receive after RX MBUF
3526 * Low Watermark has been reached. After the RX MAC receives
3527 * this number of frames, it will drop subsequent incoming
3528 * frames until the MBUF High Watermark is reached.
3530 if (BNX_IS_57765_FAMILY(sc))
3531 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3533 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3535 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI ||
3536 sc->bnx_intr_type == PCI_INTR_TYPE_MSIX) {
3538 if_printf(ifp, "MSI_MODE: %#x\n",
3539 CSR_READ_4(sc, BGE_MSI_MODE));
3543 /* Tell firmware we're alive. */
3544 BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3546 /* Enable host interrupts if polling(4) is not enabled. */
3547 PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3550 #ifdef IFPOLL_ENABLE
3551 if (ifp->if_flags & IFF_NPOLLING)
3555 bnx_disable_intr(sc);
3557 bnx_enable_intr(sc);
3558 bnx_set_tick_cpuid(sc, polling);
3560 bnx_ifmedia_upd(ifp);
3562 ifp->if_flags |= IFF_RUNNING;
3563 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3564 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3566 ifsq_clr_oactive(txr->bnx_ifsq);
3567 ifsq_watchdog_start(&txr->bnx_tx_watchdog);
3570 callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc,
3571 sc->bnx_tick_cpuid);
3575 * Set media options.
3578 bnx_ifmedia_upd(struct ifnet *ifp)
3580 struct bnx_softc *sc = ifp->if_softc;
3582 /* If this is a 1000baseX NIC, enable the TBI port. */
3583 if (sc->bnx_flags & BNX_FLAG_TBI) {
3584 struct ifmedia *ifm = &sc->bnx_ifmedia;
3586 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3589 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3594 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3595 BNX_CLRBIT(sc, BGE_MAC_MODE,
3596 BGE_MACMODE_HALF_DUPLEX);
3598 BNX_SETBIT(sc, BGE_MAC_MODE,
3599 BGE_MACMODE_HALF_DUPLEX);
3606 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3610 if (mii->mii_instance) {
3611 struct mii_softc *miisc;
3613 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3614 mii_phy_reset(miisc);
3619 * Force an interrupt so that we will call bnx_link_upd
3620 * if needed and clear any pending link state attention.
3621 * Without this we are not getting any further interrupts
3622 * for link state changes and thus will not UP the link and
3623 * not be able to send in bnx_start. The only way to get
3624 * things working was to receive a packet and get an RX
3627 * bnx_tick should help for fiber cards and we might not
3628 * need to do this here if BNX_FLAG_TBI is set but as
3629 * we poll for fiber anyway it should not harm.
3631 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3637 * Report current media status.
3640 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3642 struct bnx_softc *sc = ifp->if_softc;
3644 if (sc->bnx_flags & BNX_FLAG_TBI) {
3645 ifmr->ifm_status = IFM_AVALID;
3646 ifmr->ifm_active = IFM_ETHER;
3647 if (CSR_READ_4(sc, BGE_MAC_STS) &
3648 BGE_MACSTAT_TBI_PCS_SYNCHED) {
3649 ifmr->ifm_status |= IFM_ACTIVE;
3651 ifmr->ifm_active |= IFM_NONE;
3655 ifmr->ifm_active |= IFM_1000_SX;
3656 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3657 ifmr->ifm_active |= IFM_HDX;
3659 ifmr->ifm_active |= IFM_FDX;
3661 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3664 ifmr->ifm_active = mii->mii_media_active;
3665 ifmr->ifm_status = mii->mii_media_status;
3670 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3672 struct bnx_softc *sc = ifp->if_softc;
3673 struct ifreq *ifr = (struct ifreq *)data;
3674 int mask, error = 0;
3676 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3680 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3681 (BNX_IS_JUMBO_CAPABLE(sc) &&
3682 ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3684 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3685 ifp->if_mtu = ifr->ifr_mtu;
3686 if (ifp->if_flags & IFF_RUNNING)
3691 if (ifp->if_flags & IFF_UP) {
3692 if (ifp->if_flags & IFF_RUNNING) {
3693 mask = ifp->if_flags ^ sc->bnx_if_flags;
3696 * If only the state of the PROMISC flag
3697 * changed, then just use the 'set promisc
3698 * mode' command instead of reinitializing
3699 * the entire NIC. Doing a full re-init
3700 * means reloading the firmware and waiting
3701 * for it to start up, which may take a
3702 * second or two. Similarly for ALLMULTI.
3704 if (mask & IFF_PROMISC)
3706 if (mask & IFF_ALLMULTI)
3711 } else if (ifp->if_flags & IFF_RUNNING) {
3714 sc->bnx_if_flags = ifp->if_flags;
3718 if (ifp->if_flags & IFF_RUNNING)
3723 if (sc->bnx_flags & BNX_FLAG_TBI) {
3724 error = ifmedia_ioctl(ifp, ifr,
3725 &sc->bnx_ifmedia, command);
3727 struct mii_data *mii;
3729 mii = device_get_softc(sc->bnx_miibus);
3730 error = ifmedia_ioctl(ifp, ifr,
3731 &mii->mii_media, command);
3735 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3736 if (mask & IFCAP_HWCSUM) {
3737 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3738 if (ifp->if_capenable & IFCAP_TXCSUM)
3739 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3741 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3743 if (mask & IFCAP_TSO) {
3744 ifp->if_capenable ^= (mask & IFCAP_TSO);
3745 if (ifp->if_capenable & IFCAP_TSO)
3746 ifp->if_hwassist |= CSUM_TSO;
3748 ifp->if_hwassist &= ~CSUM_TSO;
3752 error = ether_ioctl(ifp, command, data);
3759 bnx_watchdog(struct ifaltq_subque *ifsq)
3761 struct ifnet *ifp = ifsq_get_ifp(ifsq);
3762 struct bnx_softc *sc = ifp->if_softc;
3765 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3767 if_printf(ifp, "watchdog timeout -- resetting\n");
3771 IFNET_STAT_INC(ifp, oerrors, 1);
3773 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3774 ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq);
3778 * Stop the adapter and free any mbufs allocated to the
3782 bnx_stop(struct bnx_softc *sc)
3784 struct ifnet *ifp = &sc->arpcom.ac_if;
3787 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3789 callout_stop(&sc->bnx_tick_timer);
3792 * Disable all of the receiver blocks
3794 bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3795 bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3796 bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3797 bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3798 bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3799 bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3802 * Disable all of the transmit blocks
3804 bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3805 bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3806 bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3807 bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3808 bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3809 bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3812 * Shut down all of the memory managers and related
3815 bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3816 bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3817 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3818 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3820 /* Disable host interrupts. */
3821 bnx_disable_intr(sc);
3824 * Tell firmware we're shutting down.
3826 BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3828 /* Free the RX lists. */
3829 bnx_free_rx_ring_std(&sc->bnx_rx_std_ring);
3831 /* Free jumbo RX list. */
3832 if (BNX_IS_JUMBO_CAPABLE(sc))
3833 bnx_free_rx_ring_jumbo(sc);
3835 /* Free TX buffers. */
3836 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3837 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3839 txr->bnx_saved_status_tag = 0;
3840 bnx_free_tx_ring(txr);
3843 /* Clear saved status tag */
3844 for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3845 sc->bnx_rx_ret_ring[i].bnx_saved_status_tag = 0;
3848 sc->bnx_coal_chg = 0;
3850 ifp->if_flags &= ~IFF_RUNNING;
3851 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3852 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3854 ifsq_clr_oactive(txr->bnx_ifsq);
3855 ifsq_watchdog_stop(&txr->bnx_tx_watchdog);
3860 * Stop all chip I/O so that the kernel's probe routines don't
3861 * get confused by errant DMAs when rebooting.
3864 bnx_shutdown(device_t dev)
3866 struct bnx_softc *sc = device_get_softc(dev);
3867 struct ifnet *ifp = &sc->arpcom.ac_if;
3869 ifnet_serialize_all(ifp);
3872 ifnet_deserialize_all(ifp);
3876 bnx_suspend(device_t dev)
3878 struct bnx_softc *sc = device_get_softc(dev);
3879 struct ifnet *ifp = &sc->arpcom.ac_if;
3881 ifnet_serialize_all(ifp);
3883 ifnet_deserialize_all(ifp);
3889 bnx_resume(device_t dev)
3891 struct bnx_softc *sc = device_get_softc(dev);
3892 struct ifnet *ifp = &sc->arpcom.ac_if;
3894 ifnet_serialize_all(ifp);
3896 if (ifp->if_flags & IFF_UP) {
3900 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3901 ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq);
3904 ifnet_deserialize_all(ifp);
3910 bnx_setpromisc(struct bnx_softc *sc)
3912 struct ifnet *ifp = &sc->arpcom.ac_if;
3914 if (ifp->if_flags & IFF_PROMISC)
3915 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3917 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3921 bnx_dma_free(struct bnx_softc *sc)
3923 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3926 /* Destroy RX return rings */
3927 if (sc->bnx_rx_ret_ring != NULL) {
3928 for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3929 bnx_destroy_rx_ret_ring(&sc->bnx_rx_ret_ring[i]);
3930 kfree(sc->bnx_rx_ret_ring, M_DEVBUF);
3933 /* Destroy RX mbuf DMA stuffs. */
3934 if (std->bnx_rx_mtag != NULL) {
3935 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3936 KKASSERT(std->bnx_rx_std_buf[i].bnx_rx_mbuf == NULL);
3937 bus_dmamap_destroy(std->bnx_rx_mtag,
3938 std->bnx_rx_std_buf[i].bnx_rx_dmamap);
3940 bus_dma_tag_destroy(std->bnx_rx_mtag);
3943 /* Destroy standard RX ring */
3944 bnx_dma_block_free(std->bnx_rx_std_ring_tag,
3945 std->bnx_rx_std_ring_map, std->bnx_rx_std_ring);
3947 /* Destroy TX rings */
3948 if (sc->bnx_tx_ring != NULL) {
3949 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3950 bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]);
3951 kfree(sc->bnx_tx_ring, M_DEVBUF);
3954 if (BNX_IS_JUMBO_CAPABLE(sc))
3955 bnx_free_jumbo_mem(sc);
3957 /* Destroy status blocks */
3958 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
3959 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
3961 bnx_dma_block_free(intr->bnx_status_tag,
3962 intr->bnx_status_map, intr->bnx_status_block);
3965 /* Destroy the parent tag */
3966 if (sc->bnx_cdata.bnx_parent_tag != NULL)
3967 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3971 bnx_dma_alloc(device_t dev)
3973 struct bnx_softc *sc = device_get_softc(dev);
3974 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3978 * Allocate the parent bus DMA tag appropriate for PCI.
3980 * All of the NetExtreme/NetLink controllers have 4GB boundary
3982 * Whenever an address crosses a multiple of the 4GB boundary
3983 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3984 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3985 * state machine will lockup and cause the device to hang.
3987 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3988 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3989 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3990 0, &sc->bnx_cdata.bnx_parent_tag);
3992 device_printf(dev, "could not create parent DMA tag\n");
3997 * Create DMA stuffs for status blocks.
3999 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4000 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4002 error = bnx_dma_block_alloc(sc,
4003 __VM_CACHELINE_ALIGN(BGE_STATUS_BLK_SZ),
4004 &intr->bnx_status_tag, &intr->bnx_status_map,
4005 (void *)&intr->bnx_status_block,
4006 &intr->bnx_status_block_paddr);
4009 "could not create %dth status block\n", i);
4013 sc->bnx_hw_status = &sc->bnx_intr_data[0].bnx_status_block->bge_status;
4014 if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG) {
4015 sc->bnx_hw_status_tag =
4016 &sc->bnx_intr_data[0].bnx_status_block->bge_status_tag;
4020 * Create DMA tag and maps for RX mbufs.
4023 lwkt_serialize_init(&std->bnx_rx_std_serialize);
4024 error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
4025 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4026 NULL, NULL, MCLBYTES, 1, MCLBYTES,
4027 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, &std->bnx_rx_mtag);
4029 device_printf(dev, "could not create RX mbuf DMA tag\n");
4033 for (i = 0; i < BGE_STD_RX_RING_CNT; ++i) {
4034 error = bus_dmamap_create(std->bnx_rx_mtag, BUS_DMA_WAITOK,
4035 &std->bnx_rx_std_buf[i].bnx_rx_dmamap);
4039 for (j = 0; j < i; ++j) {
4040 bus_dmamap_destroy(std->bnx_rx_mtag,
4041 std->bnx_rx_std_buf[j].bnx_rx_dmamap);
4043 bus_dma_tag_destroy(std->bnx_rx_mtag);
4044 std->bnx_rx_mtag = NULL;
4047 "could not create %dth RX mbuf DMA map\n", i);
4053 * Create DMA stuffs for standard RX ring.
4055 error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
4056 &std->bnx_rx_std_ring_tag,
4057 &std->bnx_rx_std_ring_map,
4058 (void *)&std->bnx_rx_std_ring,
4059 &std->bnx_rx_std_ring_paddr);
4061 device_printf(dev, "could not create std RX ring\n");
4066 * Create RX return rings
4068 mbx = BGE_MBX_RX_CONS0_LO;
4069 sc->bnx_rx_ret_ring = kmalloc_cachealign(
4070 sizeof(struct bnx_rx_ret_ring) * sc->bnx_rx_retcnt, M_DEVBUF,
4072 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4073 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
4074 struct bnx_intr_data *intr;
4078 ret->bnx_rx_mbx = mbx;
4079 ret->bnx_rx_cntmax = (BGE_STD_RX_RING_CNT / 4) /
4081 ret->bnx_rx_mask = 1 << i;
4083 if (!BNX_RSS_ENABLED(sc)) {
4084 intr = &sc->bnx_intr_data[0];
4086 KKASSERT(i + 1 < sc->bnx_intr_cnt);
4087 intr = &sc->bnx_intr_data[i + 1];
4091 ret->bnx_rx_considx =
4092 &intr->bnx_status_block->bge_idx[0].bge_rx_prod_idx;
4093 } else if (i == 1) {
4094 ret->bnx_rx_considx =
4095 &intr->bnx_status_block->bge_rx_jumbo_cons_idx;
4096 } else if (i == 2) {
4097 ret->bnx_rx_considx =
4098 &intr->bnx_status_block->bge_rsvd1;
4099 } else if (i == 3) {
4100 ret->bnx_rx_considx =
4101 &intr->bnx_status_block->bge_rx_mini_cons_idx;
4103 panic("unknown RX return ring %d\n", i);
4105 ret->bnx_hw_status_tag =
4106 &intr->bnx_status_block->bge_status_tag;
4108 error = bnx_create_rx_ret_ring(ret);
4111 "could not create %dth RX ret ring\n", i);
4120 sc->bnx_tx_ring = kmalloc_cachealign(
4121 sizeof(struct bnx_tx_ring) * sc->bnx_tx_ringcnt, M_DEVBUF,
4123 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4124 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
4125 struct bnx_intr_data *intr;
4128 txr->bnx_tx_mbx = bnx_tx_mailbox[i];
4130 if (sc->bnx_tx_ringcnt == 1) {
4131 intr = &sc->bnx_intr_data[0];
4133 KKASSERT(i + 1 < sc->bnx_intr_cnt);
4134 intr = &sc->bnx_intr_data[i + 1];
4137 if ((sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) == 0) {
4138 txr->bnx_hw_status_tag =
4139 &intr->bnx_status_block->bge_status_tag;
4141 txr->bnx_tx_considx =
4142 &intr->bnx_status_block->bge_idx[0].bge_tx_cons_idx;
4144 error = bnx_create_tx_ring(txr);
4147 "could not create %dth TX ring\n", i);
4153 * Create jumbo buffer pool.
4155 if (BNX_IS_JUMBO_CAPABLE(sc)) {
4156 error = bnx_alloc_jumbo_mem(sc);
4159 "could not create jumbo buffer pool\n");
4168 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
4169 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
4174 error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
4175 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4176 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4180 *tag = dmem.dmem_tag;
4181 *map = dmem.dmem_map;
4182 *addr = dmem.dmem_addr;
4183 *paddr = dmem.dmem_busaddr;
4189 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
4192 bus_dmamap_unload(tag, map);
4193 bus_dmamem_free(tag, addr, map);
4194 bus_dma_tag_destroy(tag);
4199 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
4201 struct ifnet *ifp = &sc->arpcom.ac_if;
4203 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
4206 * Sometimes PCS encoding errors are detected in
4207 * TBI mode (on fiber NICs), and for some reason
4208 * the chip will signal them as link changes.
4209 * If we get a link change event, but the 'PCS
4210 * encoding error' bit in the MAC status register
4211 * is set, don't bother doing a link check.
4212 * This avoids spurious "gigabit link up" messages
4213 * that sometimes appear on fiber NICs during
4214 * periods of heavy traffic.
4216 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4217 if (!sc->bnx_link) {
4219 if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
4220 BNX_CLRBIT(sc, BGE_MAC_MODE,
4221 BGE_MACMODE_TBI_SEND_CFGS);
4223 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4226 if_printf(ifp, "link UP\n");
4228 ifp->if_link_state = LINK_STATE_UP;
4229 if_link_state_change(ifp);
4231 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
4236 if_printf(ifp, "link DOWN\n");
4238 ifp->if_link_state = LINK_STATE_DOWN;
4239 if_link_state_change(ifp);
4243 #undef PCS_ENCODE_ERR
4245 /* Clear the attention. */
4246 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4247 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4248 BGE_MACSTAT_LINK_CHANGED);
4252 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
4254 struct ifnet *ifp = &sc->arpcom.ac_if;
4255 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
4258 bnx_miibus_statchg(sc->bnx_dev);
4262 if_printf(ifp, "link UP\n");
4264 if_printf(ifp, "link DOWN\n");
4267 /* Clear the attention. */
4268 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4269 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4270 BGE_MACSTAT_LINK_CHANGED);
4274 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
4276 struct ifnet *ifp = &sc->arpcom.ac_if;
4277 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
4281 if (!sc->bnx_link &&
4282 (mii->mii_media_status & IFM_ACTIVE) &&
4283 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4286 if_printf(ifp, "link UP\n");
4287 } else if (sc->bnx_link &&
4288 (!(mii->mii_media_status & IFM_ACTIVE) ||
4289 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4292 if_printf(ifp, "link DOWN\n");
4295 /* Clear the attention. */
4296 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4297 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4298 BGE_MACSTAT_LINK_CHANGED);
4302 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
4304 struct bnx_softc *sc = arg1;
4306 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4307 &sc->bnx_rx_coal_ticks,
4308 BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
4309 BNX_RX_COAL_TICKS_CHG);
4313 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
4315 struct bnx_softc *sc = arg1;
4317 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4318 &sc->bnx_tx_coal_ticks,
4319 BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
4320 BNX_TX_COAL_TICKS_CHG);
4324 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
4326 struct bnx_softc *sc = arg1;
4328 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4329 &sc->bnx_rx_coal_bds,
4330 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
4331 BNX_RX_COAL_BDS_CHG);
4335 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
4337 struct bnx_softc *sc = arg1;
4339 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4340 &sc->bnx_tx_coal_bds,
4341 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
4342 BNX_TX_COAL_BDS_CHG);
4346 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4348 struct bnx_softc *sc = arg1;
4350 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4351 &sc->bnx_rx_coal_bds_int,
4352 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
4353 BNX_RX_COAL_BDS_INT_CHG);
4357 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4359 struct bnx_softc *sc = arg1;
4361 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4362 &sc->bnx_tx_coal_bds_int,
4363 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
4364 BNX_TX_COAL_BDS_INT_CHG);
4368 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
4369 int coal_min, int coal_max, uint32_t coal_chg_mask)
4371 struct bnx_softc *sc = arg1;
4372 struct ifnet *ifp = &sc->arpcom.ac_if;
4375 ifnet_serialize_all(ifp);
4378 error = sysctl_handle_int(oidp, &v, 0, req);
4379 if (!error && req->newptr != NULL) {
4380 if (v < coal_min || v > coal_max) {
4384 sc->bnx_coal_chg |= coal_chg_mask;
4386 /* Commit changes */
4387 bnx_coal_change(sc);
4391 ifnet_deserialize_all(ifp);
4396 bnx_coal_change(struct bnx_softc *sc)
4398 struct ifnet *ifp = &sc->arpcom.ac_if;
4401 ASSERT_IFNET_SERIALIZED_ALL(ifp);
4403 if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
4404 if (sc->bnx_rx_retcnt == 1) {
4405 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
4406 sc->bnx_rx_coal_ticks);
4409 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, 0);
4410 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4411 CSR_WRITE_4(sc, BGE_VEC1_RX_COAL_TICKS +
4412 (i * BGE_VEC_COALSET_SIZE),
4413 sc->bnx_rx_coal_ticks);
4416 for (; i < BNX_INTR_MAX - 1; ++i) {
4417 CSR_WRITE_4(sc, BGE_VEC1_RX_COAL_TICKS +
4418 (i * BGE_VEC_COALSET_SIZE), 0);
4421 if_printf(ifp, "rx_coal_ticks -> %u\n",
4422 sc->bnx_rx_coal_ticks);
4426 if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
4427 if (sc->bnx_tx_ringcnt == 1) {
4428 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4429 sc->bnx_tx_coal_ticks);
4432 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, 0);
4433 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4434 CSR_WRITE_4(sc, BGE_VEC1_TX_COAL_TICKS +
4435 (i * BGE_VEC_COALSET_SIZE),
4436 sc->bnx_tx_coal_ticks);
4439 for (; i < BNX_INTR_MAX - 1; ++i) {
4440 CSR_WRITE_4(sc, BGE_VEC1_TX_COAL_TICKS +
4441 (i * BGE_VEC_COALSET_SIZE), 0);
4444 if_printf(ifp, "tx_coal_ticks -> %u\n",
4445 sc->bnx_tx_coal_ticks);
4449 if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
4450 if (sc->bnx_rx_retcnt == 1) {
4451 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4452 sc->bnx_rx_coal_bds);
4455 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, 0);
4456 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4457 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS +
4458 (i * BGE_VEC_COALSET_SIZE),
4459 sc->bnx_rx_coal_bds);
4462 for (; i < BNX_INTR_MAX - 1; ++i) {
4463 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS +
4464 (i * BGE_VEC_COALSET_SIZE), 0);
4467 if_printf(ifp, "rx_coal_bds -> %u\n",
4468 sc->bnx_rx_coal_bds);
4472 if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
4473 if (sc->bnx_tx_ringcnt == 1) {
4474 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4475 sc->bnx_tx_coal_bds);
4478 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, 0);
4479 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4480 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS +
4481 (i * BGE_VEC_COALSET_SIZE),
4482 sc->bnx_tx_coal_bds);
4485 for (; i < BNX_INTR_MAX - 1; ++i) {
4486 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS +
4487 (i * BGE_VEC_COALSET_SIZE), 0);
4490 if_printf(ifp, "tx_coal_bds -> %u\n",
4491 sc->bnx_tx_coal_bds);
4495 if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
4496 if (sc->bnx_rx_retcnt == 1) {
4497 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
4498 sc->bnx_rx_coal_bds_int);
4501 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
4502 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4503 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS_INT +
4504 (i * BGE_VEC_COALSET_SIZE),
4505 sc->bnx_rx_coal_bds_int);
4508 for (; i < BNX_INTR_MAX - 1; ++i) {
4509 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS_INT +
4510 (i * BGE_VEC_COALSET_SIZE), 0);
4513 if_printf(ifp, "rx_coal_bds_int -> %u\n",
4514 sc->bnx_rx_coal_bds_int);
4518 if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
4519 if (sc->bnx_tx_ringcnt == 1) {
4520 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
4521 sc->bnx_tx_coal_bds_int);
4524 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
4525 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4526 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS_INT +
4527 (i * BGE_VEC_COALSET_SIZE),
4528 sc->bnx_tx_coal_bds_int);
4531 for (; i < BNX_INTR_MAX - 1; ++i) {
4532 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS_INT +
4533 (i * BGE_VEC_COALSET_SIZE), 0);
4536 if_printf(ifp, "tx_coal_bds_int -> %u\n",
4537 sc->bnx_tx_coal_bds_int);
4541 sc->bnx_coal_chg = 0;
4545 bnx_check_intr_rxtx(void *xintr)
4547 struct bnx_intr_data *intr = xintr;
4548 struct bnx_rx_ret_ring *ret;
4549 struct bnx_tx_ring *txr;
4552 lwkt_serialize_enter(intr->bnx_intr_serialize);
4554 KKASSERT(mycpuid == intr->bnx_intr_cpuid);
4556 ifp = &intr->bnx_sc->arpcom.ac_if;
4557 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4558 lwkt_serialize_exit(intr->bnx_intr_serialize);
4562 txr = intr->bnx_txr;
4563 ret = intr->bnx_ret;
4565 if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx ||
4566 *txr->bnx_tx_considx != txr->bnx_tx_saved_considx) {
4567 if (intr->bnx_rx_check_considx == ret->bnx_rx_saved_considx &&
4568 intr->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
4569 if (!intr->bnx_intr_maylose) {
4570 intr->bnx_intr_maylose = TRUE;
4574 if_printf(ifp, "lost interrupt\n");
4575 intr->bnx_intr_func(intr->bnx_intr_arg);
4578 intr->bnx_intr_maylose = FALSE;
4579 intr->bnx_rx_check_considx = ret->bnx_rx_saved_considx;
4580 intr->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
4583 callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL,
4584 intr->bnx_intr_check, intr);
4585 lwkt_serialize_exit(intr->bnx_intr_serialize);
4589 bnx_check_intr_tx(void *xintr)
4591 struct bnx_intr_data *intr = xintr;
4592 struct bnx_tx_ring *txr;
4595 lwkt_serialize_enter(intr->bnx_intr_serialize);
4597 KKASSERT(mycpuid == intr->bnx_intr_cpuid);
4599 ifp = &intr->bnx_sc->arpcom.ac_if;
4600 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4601 lwkt_serialize_exit(intr->bnx_intr_serialize);
4605 txr = intr->bnx_txr;
4607 if (*txr->bnx_tx_considx != txr->bnx_tx_saved_considx) {
4608 if (intr->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
4609 if (!intr->bnx_intr_maylose) {
4610 intr->bnx_intr_maylose = TRUE;
4614 if_printf(ifp, "lost interrupt\n");
4615 intr->bnx_intr_func(intr->bnx_intr_arg);
4618 intr->bnx_intr_maylose = FALSE;
4619 intr->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
4622 callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL,
4623 intr->bnx_intr_check, intr);
4624 lwkt_serialize_exit(intr->bnx_intr_serialize);
4628 bnx_check_intr_rx(void *xintr)
4630 struct bnx_intr_data *intr = xintr;
4631 struct bnx_rx_ret_ring *ret;
4634 lwkt_serialize_enter(intr->bnx_intr_serialize);
4636 KKASSERT(mycpuid == intr->bnx_intr_cpuid);
4638 ifp = &intr->bnx_sc->arpcom.ac_if;
4639 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4640 lwkt_serialize_exit(intr->bnx_intr_serialize);
4644 ret = intr->bnx_ret;
4646 if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx) {
4647 if (intr->bnx_rx_check_considx == ret->bnx_rx_saved_considx) {
4648 if (!intr->bnx_intr_maylose) {
4649 intr->bnx_intr_maylose = TRUE;
4653 if_printf(ifp, "lost interrupt\n");
4654 intr->bnx_intr_func(intr->bnx_intr_arg);
4657 intr->bnx_intr_maylose = FALSE;
4658 intr->bnx_rx_check_considx = ret->bnx_rx_saved_considx;
4661 callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL,
4662 intr->bnx_intr_check, intr);
4663 lwkt_serialize_exit(intr->bnx_intr_serialize);
4667 bnx_enable_intr(struct bnx_softc *sc)
4669 struct ifnet *ifp = &sc->arpcom.ac_if;
4672 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4673 lwkt_serialize_handler_enable(
4674 sc->bnx_intr_data[i].bnx_intr_serialize);
4680 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4681 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4683 bnx_writembx(sc, intr->bnx_intr_mbx,
4684 (*intr->bnx_saved_status_tag) << 24);
4685 /* XXX Linux driver */
4686 bnx_writembx(sc, intr->bnx_intr_mbx,
4687 (*intr->bnx_saved_status_tag) << 24);
4691 * Unmask the interrupt when we stop polling.
4693 PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4694 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4697 * Trigger another interrupt, since above writing
4698 * to interrupt mailbox0 may acknowledge pending
4701 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4703 if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
4705 if_printf(ifp, "status tag bug workaround\n");
4707 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4708 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4710 if (intr->bnx_intr_check == NULL)
4712 intr->bnx_intr_maylose = FALSE;
4713 intr->bnx_rx_check_considx = 0;
4714 intr->bnx_tx_check_considx = 0;
4715 callout_reset_bycpu(&intr->bnx_intr_timer,
4716 BNX_INTR_CKINTVL, intr->bnx_intr_check, intr,
4717 intr->bnx_intr_cpuid);
4723 bnx_disable_intr(struct bnx_softc *sc)
4727 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4728 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4730 callout_stop(&intr->bnx_intr_timer);
4731 intr->bnx_intr_maylose = FALSE;
4732 intr->bnx_rx_check_considx = 0;
4733 intr->bnx_tx_check_considx = 0;
4737 * Mask the interrupt when we start polling.
4739 PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4740 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4743 * Acknowledge possible asserted interrupt.
4745 for (i = 0; i < BNX_INTR_MAX; ++i)
4746 bnx_writembx(sc, sc->bnx_intr_data[i].bnx_intr_mbx, 1);
4748 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4749 lwkt_serialize_handler_disable(
4750 sc->bnx_intr_data[i].bnx_intr_serialize);
4755 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
4760 mac_addr = bnx_readmem_ind(sc, 0x0c14);
4761 if ((mac_addr >> 16) == 0x484b) {
4762 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4763 ether_addr[1] = (uint8_t)mac_addr;
4764 mac_addr = bnx_readmem_ind(sc, 0x0c18);
4765 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4766 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4767 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4768 ether_addr[5] = (uint8_t)mac_addr;
4775 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4777 int mac_offset = BGE_EE_MAC_OFFSET;
4779 if (BNX_IS_5717_PLUS(sc)) {
4782 f = pci_get_function(sc->bnx_dev);
4784 mac_offset = BGE_EE_MAC_OFFSET_5717;
4786 mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
4789 return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4793 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4795 if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4798 return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4803 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4805 static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4806 /* NOTE: Order is critical */
4808 bnx_get_eaddr_nvram,
4809 bnx_get_eaddr_eeprom,
4812 const bnx_eaddr_fcn_t *func;
4814 for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4815 if ((*func)(sc, eaddr) == 0)
4818 return (*func == NULL ? ENXIO : 0);
4822 * NOTE: 'm' is not freed upon failure
4825 bnx_defrag_shortdma(struct mbuf *m)
4831 * If device receive two back-to-back send BDs with less than
4832 * or equal to 8 total bytes then the device may hang. The two
4833 * back-to-back send BDs must in the same frame for this failure
4834 * to occur. Scan mbuf chains and see whether two back-to-back
4835 * send BDs are there. If this is the case, allocate new mbuf
4836 * and copy the frame to workaround the silicon bug.
4838 for (n = m, found = 0; n != NULL; n = n->m_next) {
4849 n = m_defrag(m, MB_DONTWAIT);
4856 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4860 BNX_CLRBIT(sc, reg, bit);
4861 for (i = 0; i < BNX_TIMEOUT; i++) {
4862 if ((CSR_READ_4(sc, reg) & bit) == 0)
4869 bnx_link_poll(struct bnx_softc *sc)
4873 status = CSR_READ_4(sc, BGE_MAC_STS);
4874 if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4875 sc->bnx_link_evt = 0;
4876 sc->bnx_link_upd(sc, status);
4881 bnx_enable_msi(struct bnx_softc *sc, boolean_t is_msix)
4885 msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4886 msi_mode |= BGE_MSIMODE_ENABLE;
4889 * 5718-PG105-R says that "one shot" mode does not work
4890 * if MSI is used, however, it obviously works.
4892 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4894 msi_mode |= BGE_MSIMODE_MSIX_MULTIMODE;
4896 msi_mode &= ~BGE_MSIMODE_MSIX_MULTIMODE;
4897 CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4901 bnx_dma_swap_options(struct bnx_softc *sc)
4903 uint32_t dma_options;
4905 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4906 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4907 #if BYTE_ORDER == BIG_ENDIAN
4908 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4910 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
4911 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
4912 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4913 BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4914 BGE_MODECTL_HTX2B_ENABLE;
4920 bnx_setup_tso(struct bnx_tx_ring *txr, struct mbuf **mp,
4921 uint16_t *mss0, uint16_t *flags0)
4926 int thoff, iphlen, hoff, hlen;
4927 uint16_t flags, mss;
4930 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4932 hoff = m->m_pkthdr.csum_lhlen;
4933 iphlen = m->m_pkthdr.csum_iphlen;
4934 thoff = m->m_pkthdr.csum_thlen;
4936 KASSERT(hoff > 0, ("invalid ether header len"));
4937 KASSERT(iphlen > 0, ("invalid ip header len"));
4938 KASSERT(thoff > 0, ("invalid tcp header len"));
4940 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4941 m = m_pullup(m, hoff + iphlen + thoff);
4948 ip = mtodoff(m, struct ip *, hoff);
4949 th = mtodoff(m, struct tcphdr *, hoff + iphlen);
4951 mss = m->m_pkthdr.tso_segsz;
4952 flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
4954 ip->ip_len = htons(mss + iphlen + thoff);
4957 hlen = (iphlen + thoff) >> 2;
4958 mss |= ((hlen & 0x3) << 14);
4959 flags |= ((hlen & 0xf8) << 7) | ((hlen & 0x4) << 2);
4968 bnx_create_tx_ring(struct bnx_tx_ring *txr)
4970 bus_size_t txmaxsz, txmaxsegsz;
4973 lwkt_serialize_init(&txr->bnx_tx_serialize);
4976 * Create DMA tag and maps for TX mbufs.
4978 if (txr->bnx_sc->bnx_flags & BNX_FLAG_TSO)
4979 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
4981 txmaxsz = BNX_JUMBO_FRAMELEN;
4982 if (txr->bnx_sc->bnx_asicrev == BGE_ASICREV_BCM57766)
4983 txmaxsegsz = MCLBYTES;
4985 txmaxsegsz = PAGE_SIZE;
4986 error = bus_dma_tag_create(txr->bnx_sc->bnx_cdata.bnx_parent_tag,
4987 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
4988 txmaxsz, BNX_NSEG_NEW, txmaxsegsz,
4989 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
4992 device_printf(txr->bnx_sc->bnx_dev,
4993 "could not create TX mbuf DMA tag\n");
4997 for (i = 0; i < BGE_TX_RING_CNT; i++) {
4998 error = bus_dmamap_create(txr->bnx_tx_mtag,
4999 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
5000 &txr->bnx_tx_buf[i].bnx_tx_dmamap);
5004 for (j = 0; j < i; ++j) {
5005 bus_dmamap_destroy(txr->bnx_tx_mtag,
5006 txr->bnx_tx_buf[j].bnx_tx_dmamap);
5008 bus_dma_tag_destroy(txr->bnx_tx_mtag);
5009 txr->bnx_tx_mtag = NULL;
5011 device_printf(txr->bnx_sc->bnx_dev,
5012 "could not create TX mbuf DMA map\n");
5018 * Create DMA stuffs for TX ring.
5020 error = bnx_dma_block_alloc(txr->bnx_sc, BGE_TX_RING_SZ,
5021 &txr->bnx_tx_ring_tag,
5022 &txr->bnx_tx_ring_map,
5023 (void *)&txr->bnx_tx_ring,
5024 &txr->bnx_tx_ring_paddr);
5026 device_printf(txr->bnx_sc->bnx_dev,
5027 "could not create TX ring\n");
5031 txr->bnx_tx_flags |= BNX_TX_FLAG_SHORTDMA;
5032 txr->bnx_tx_wreg = BNX_TX_WREG_NSEGS;
5038 bnx_destroy_tx_ring(struct bnx_tx_ring *txr)
5040 /* Destroy TX mbuf DMA stuffs. */
5041 if (txr->bnx_tx_mtag != NULL) {
5044 for (i = 0; i < BGE_TX_RING_CNT; i++) {
5045 KKASSERT(txr->bnx_tx_buf[i].bnx_tx_mbuf == NULL);
5046 bus_dmamap_destroy(txr->bnx_tx_mtag,
5047 txr->bnx_tx_buf[i].bnx_tx_dmamap);
5049 bus_dma_tag_destroy(txr->bnx_tx_mtag);
5052 /* Destroy TX ring */
5053 bnx_dma_block_free(txr->bnx_tx_ring_tag,
5054 txr->bnx_tx_ring_map, txr->bnx_tx_ring);
5058 bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS)
5060 struct bnx_softc *sc = (void *)arg1;
5061 struct ifnet *ifp = &sc->arpcom.ac_if;
5062 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
5063 int error, defrag, i;
5065 if (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG)
5070 error = sysctl_handle_int(oidp, &defrag, 0, req);
5071 if (error || req->newptr == NULL)
5074 ifnet_serialize_all(ifp);
5075 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
5076 txr = &sc->bnx_tx_ring[i];
5078 txr->bnx_tx_flags |= BNX_TX_FLAG_FORCE_DEFRAG;
5080 txr->bnx_tx_flags &= ~BNX_TX_FLAG_FORCE_DEFRAG;
5082 ifnet_deserialize_all(ifp);
5088 bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS)
5090 struct bnx_softc *sc = (void *)arg1;
5091 struct ifnet *ifp = &sc->arpcom.ac_if;
5092 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
5093 int error, tx_wreg, i;
5095 tx_wreg = txr->bnx_tx_wreg;
5096 error = sysctl_handle_int(oidp, &tx_wreg, 0, req);
5097 if (error || req->newptr == NULL)
5100 ifnet_serialize_all(ifp);
5101 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
5102 sc->bnx_tx_ring[i].bnx_tx_wreg = tx_wreg;
5103 ifnet_deserialize_all(ifp);
5109 bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *ret)
5113 lwkt_serialize_init(&ret->bnx_rx_ret_serialize);
5116 * Create DMA stuffs for RX return ring.
5118 error = bnx_dma_block_alloc(ret->bnx_sc,
5119 BGE_RX_RTN_RING_SZ(BNX_RETURN_RING_CNT),
5120 &ret->bnx_rx_ret_ring_tag,
5121 &ret->bnx_rx_ret_ring_map,
5122 (void *)&ret->bnx_rx_ret_ring,
5123 &ret->bnx_rx_ret_ring_paddr);
5125 device_printf(ret->bnx_sc->bnx_dev,
5126 "could not create RX ret ring\n");
5130 /* Shadow standard ring's RX mbuf DMA tag */
5131 ret->bnx_rx_mtag = ret->bnx_std->bnx_rx_mtag;
5134 * Create tmp DMA map for RX mbufs.
5136 error = bus_dmamap_create(ret->bnx_rx_mtag, BUS_DMA_WAITOK,
5137 &ret->bnx_rx_tmpmap);
5139 device_printf(ret->bnx_sc->bnx_dev,
5140 "could not create tmp RX mbuf DMA map\n");
5141 ret->bnx_rx_mtag = NULL;
5148 bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *ret)
5150 /* Destroy tmp RX mbuf DMA map */
5151 if (ret->bnx_rx_mtag != NULL)
5152 bus_dmamap_destroy(ret->bnx_rx_mtag, ret->bnx_rx_tmpmap);
5154 /* Destroy RX return ring */
5155 bnx_dma_block_free(ret->bnx_rx_ret_ring_tag,
5156 ret->bnx_rx_ret_ring_map, ret->bnx_rx_ret_ring);
5160 bnx_alloc_intr(struct bnx_softc *sc)
5162 struct bnx_intr_data *intr;
5166 if (sc->bnx_intr_cnt > 1) {
5167 error = bnx_alloc_msix(sc);
5170 KKASSERT(sc->bnx_intr_type == PCI_INTR_TYPE_MSIX);
5174 KKASSERT(sc->bnx_intr_cnt == 1);
5176 intr = &sc->bnx_intr_data[0];
5177 intr->bnx_ret = &sc->bnx_rx_ret_ring[0];
5178 intr->bnx_txr = &sc->bnx_tx_ring[0];
5179 intr->bnx_intr_serialize = &sc->bnx_main_serialize;
5180 intr->bnx_intr_check = bnx_check_intr_rxtx;
5181 intr->bnx_saved_status_tag = &intr->bnx_ret->bnx_saved_status_tag;
5183 sc->bnx_intr_type = pci_alloc_1intr(sc->bnx_dev, bnx_msi_enable,
5184 &intr->bnx_intr_rid, &intr_flags);
5186 intr->bnx_intr_res = bus_alloc_resource_any(sc->bnx_dev, SYS_RES_IRQ,
5187 &intr->bnx_intr_rid, intr_flags);
5188 if (intr->bnx_intr_res == NULL) {
5189 device_printf(sc->bnx_dev, "could not alloc interrupt\n");
5193 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI) {
5194 bnx_enable_msi(sc, FALSE);
5195 intr->bnx_intr_func = bnx_msi;
5197 device_printf(sc->bnx_dev, "oneshot MSI\n");
5199 intr->bnx_intr_func = bnx_intr_legacy;
5201 intr->bnx_intr_arg = sc;
5202 intr->bnx_intr_cpuid = rman_get_cpuid(intr->bnx_intr_res);
5204 intr->bnx_txr->bnx_tx_cpuid = intr->bnx_intr_cpuid;
5210 bnx_setup_intr(struct bnx_softc *sc)
5214 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
5215 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
5217 error = bus_setup_intr_descr(sc->bnx_dev, intr->bnx_intr_res,
5218 INTR_MPSAFE, intr->bnx_intr_func, intr->bnx_intr_arg,
5219 &intr->bnx_intr_hand, intr->bnx_intr_serialize,
5220 intr->bnx_intr_desc);
5222 device_printf(sc->bnx_dev,
5223 "could not set up %dth intr\n", i);
5224 bnx_teardown_intr(sc, i);
5232 bnx_teardown_intr(struct bnx_softc *sc, int cnt)
5236 for (i = 0; i < cnt; ++i) {
5237 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
5239 bus_teardown_intr(sc->bnx_dev, intr->bnx_intr_res,
5240 intr->bnx_intr_hand);
5245 bnx_free_intr(struct bnx_softc *sc)
5247 if (sc->bnx_intr_type != PCI_INTR_TYPE_MSIX) {
5248 struct bnx_intr_data *intr;
5250 KKASSERT(sc->bnx_intr_cnt <= 1);
5251 intr = &sc->bnx_intr_data[0];
5253 if (intr->bnx_intr_res != NULL) {
5254 bus_release_resource(sc->bnx_dev, SYS_RES_IRQ,
5255 intr->bnx_intr_rid, intr->bnx_intr_res);
5257 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI)
5258 pci_release_msi(sc->bnx_dev);
5260 bnx_free_msix(sc, TRUE);
5265 bnx_setup_serialize(struct bnx_softc *sc)
5270 * Allocate serializer array
5273 /* Main + RX STD + TX + RX RET */
5274 sc->bnx_serialize_cnt = 1 + 1 + sc->bnx_tx_ringcnt + sc->bnx_rx_retcnt;
5277 kmalloc(sc->bnx_serialize_cnt * sizeof(struct lwkt_serialize *),
5278 M_DEVBUF, M_WAITOK | M_ZERO);
5283 * NOTE: Order is critical
5288 KKASSERT(i < sc->bnx_serialize_cnt);
5289 sc->bnx_serialize[i++] = &sc->bnx_main_serialize;
5291 KKASSERT(i < sc->bnx_serialize_cnt);
5292 sc->bnx_serialize[i++] = &sc->bnx_rx_std_ring.bnx_rx_std_serialize;
5294 for (j = 0; j < sc->bnx_rx_retcnt; ++j) {
5295 KKASSERT(i < sc->bnx_serialize_cnt);
5296 sc->bnx_serialize[i++] =
5297 &sc->bnx_rx_ret_ring[j].bnx_rx_ret_serialize;
5300 for (j = 0; j < sc->bnx_tx_ringcnt; ++j) {
5301 KKASSERT(i < sc->bnx_serialize_cnt);
5302 sc->bnx_serialize[i++] =
5303 &sc->bnx_tx_ring[j].bnx_tx_serialize;
5306 KKASSERT(i == sc->bnx_serialize_cnt);
5310 bnx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
5312 struct bnx_softc *sc = ifp->if_softc;
5314 ifnet_serialize_array_enter(sc->bnx_serialize,
5315 sc->bnx_serialize_cnt, slz);
5319 bnx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
5321 struct bnx_softc *sc = ifp->if_softc;
5323 ifnet_serialize_array_exit(sc->bnx_serialize,
5324 sc->bnx_serialize_cnt, slz);
5328 bnx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
5330 struct bnx_softc *sc = ifp->if_softc;
5332 return ifnet_serialize_array_try(sc->bnx_serialize,
5333 sc->bnx_serialize_cnt, slz);
5339 bnx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
5340 boolean_t serialized)
5342 struct bnx_softc *sc = ifp->if_softc;
5344 ifnet_serialize_array_assert(sc->bnx_serialize, sc->bnx_serialize_cnt,
5348 #endif /* INVARIANTS */
5350 #ifdef IFPOLL_ENABLE
5353 bnx_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS)
5355 struct bnx_softc *sc = (void *)arg1;
5356 struct ifnet *ifp = &sc->arpcom.ac_if;
5359 off = sc->bnx_npoll_rxoff;
5360 error = sysctl_handle_int(oidp, &off, 0, req);
5361 if (error || req->newptr == NULL)
5366 ifnet_serialize_all(ifp);
5367 if (off >= ncpus2 || off % sc->bnx_rx_retcnt != 0) {
5371 sc->bnx_npoll_txoff = off;
5372 sc->bnx_npoll_rxoff = off;
5374 ifnet_deserialize_all(ifp);
5380 bnx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
5382 struct bnx_softc *sc = (void *)arg1;
5383 struct ifnet *ifp = &sc->arpcom.ac_if;
5386 off = sc->bnx_npoll_rxoff;
5387 error = sysctl_handle_int(oidp, &off, 0, req);
5388 if (error || req->newptr == NULL)
5393 ifnet_serialize_all(ifp);
5394 if (off >= ncpus2 || off % sc->bnx_rx_retcnt != 0) {
5398 sc->bnx_npoll_rxoff = off;
5400 ifnet_deserialize_all(ifp);
5406 bnx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
5408 struct bnx_softc *sc = (void *)arg1;
5409 struct ifnet *ifp = &sc->arpcom.ac_if;
5412 off = sc->bnx_npoll_txoff;
5413 error = sysctl_handle_int(oidp, &off, 0, req);
5414 if (error || req->newptr == NULL)
5419 ifnet_serialize_all(ifp);
5420 if (off >= ncpus2) {
5424 sc->bnx_npoll_txoff = off;
5426 ifnet_deserialize_all(ifp);
5431 #endif /* IFPOLL_ENABLE */
5434 bnx_set_tick_cpuid(struct bnx_softc *sc, boolean_t polling)
5437 sc->bnx_tick_cpuid = 0; /* XXX */
5439 sc->bnx_tick_cpuid = sc->bnx_intr_data[0].bnx_intr_cpuid;
5443 bnx_rx_std_refill_ithread(void *xstd)
5445 struct bnx_rx_std_ring *std = xstd;
5446 struct globaldata *gd = mycpu;
5450 while (!std->bnx_rx_std_stop) {
5451 if (std->bnx_rx_std_refill) {
5452 lwkt_serialize_handler_call(
5453 &std->bnx_rx_std_serialize,
5454 bnx_rx_std_refill, std, NULL);
5460 atomic_poll_release_int(&std->bnx_rx_std_running);
5463 if (!std->bnx_rx_std_refill && !std->bnx_rx_std_stop) {
5464 lwkt_deschedule_self(gd->gd_curthread);
5477 bnx_rx_std_refill(void *xstd, void *frame __unused)
5479 struct bnx_rx_std_ring *std = xstd;
5480 int cnt, refill_mask;
5486 refill_mask = std->bnx_rx_std_refill;
5487 atomic_clear_int(&std->bnx_rx_std_refill, refill_mask);
5489 while (refill_mask) {
5490 uint16_t check_idx = std->bnx_rx_std;
5493 ret_idx = bsfl(refill_mask);
5495 struct bnx_rx_buf *rb;
5498 BNX_INC(check_idx, BGE_STD_RX_RING_CNT);
5499 rb = &std->bnx_rx_std_buf[check_idx];
5500 refilled = rb->bnx_rx_refilled;
5503 bnx_setup_rxdesc_std(std, check_idx);
5504 std->bnx_rx_std = check_idx;
5507 bnx_writembx(std->bnx_sc,
5508 BGE_MBX_RX_STD_PROD_LO,
5516 refill_mask &= ~(1 << ret_idx);
5520 bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO,
5524 if (std->bnx_rx_std_refill)
5527 atomic_poll_release_int(&std->bnx_rx_std_running);
5530 if (std->bnx_rx_std_refill)
5535 bnx_sysctl_std_refill(SYSCTL_HANDLER_ARGS)
5537 struct bnx_softc *sc = (void *)arg1;
5538 struct ifnet *ifp = &sc->arpcom.ac_if;
5539 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
5540 int error, cntmax, i;
5542 cntmax = ret->bnx_rx_cntmax;
5543 error = sysctl_handle_int(oidp, &cntmax, 0, req);
5544 if (error || req->newptr == NULL)
5547 ifnet_serialize_all(ifp);
5549 if ((cntmax * sc->bnx_rx_retcnt) > BGE_STD_RX_RING_CNT / 2) {
5554 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
5555 sc->bnx_rx_ret_ring[i].bnx_rx_cntmax = cntmax;
5559 ifnet_deserialize_all(ifp);
5565 bnx_init_rss(struct bnx_softc *sc)
5567 uint8_t key[BGE_RSS_KEYREG_CNT * BGE_RSS_KEYREG_SIZE];
5570 KKASSERT(BNX_RSS_ENABLED(sc));
5573 for (j = 0; j < BGE_RSS_INDIR_TBL_CNT; ++j) {
5576 for (i = 0; i < BGE_RSS_INDIR_TBLENT_CNT; ++i) {
5579 q = r % sc->bnx_rx_retcnt;
5580 tbl |= q << (BGE_RSS_INDIR_TBLENT_SHIFT *
5581 (BGE_RSS_INDIR_TBLENT_CNT - i - 1));
5585 BNX_RSS_DPRINTF(sc, 1, "tbl%d %08x\n", j, tbl);
5586 CSR_WRITE_4(sc, BGE_RSS_INDIR_TBL(j), tbl);
5589 toeplitz_get_key(key, sizeof(key));
5590 for (i = 0; i < BGE_RSS_KEYREG_CNT; ++i) {
5593 keyreg = BGE_RSS_KEYREG_VAL(key, i);
5595 BNX_RSS_DPRINTF(sc, 1, "key%d %08x\n", i, keyreg);
5596 CSR_WRITE_4(sc, BGE_RSS_KEYREG(i), keyreg);
5601 bnx_setup_ring_cnt(struct bnx_softc *sc)
5603 int msix_enable, i, msix_cnt, msix_cnt2, ring_max;
5605 sc->bnx_tx_ringcnt = 1;
5606 sc->bnx_rx_retcnt = 1;
5607 sc->bnx_intr_cnt = 1;
5609 msix_enable = device_getenv_int(sc->bnx_dev, "msix.enable",
5617 msix_cnt = pci_msix_count(sc->bnx_dev);
5622 while ((1 << (i + 1)) <= msix_cnt)
5627 * One MSI-X vector is dedicated to status or single TX queue,
5628 * so make sure that there are enough MSI-X vectors.
5630 if (msix_cnt == msix_cnt2) {
5633 * This probably will not happen; 57785/5718 families
5634 * come with at least 5 MSI-X vectors.
5637 if (msix_cnt2 <= 1) {
5638 device_printf(sc->bnx_dev,
5639 "MSI-X count %d could not be used\n", msix_cnt);
5642 device_printf(sc->bnx_dev, "MSI-X count %d is power of 2\n",
5647 * Setup RX ring count
5649 ring_max = BNX_RX_RING_MAX;
5650 if (ring_max > msix_cnt2)
5651 ring_max = msix_cnt2;
5652 sc->bnx_rx_retcnt = device_getenv_int(sc->bnx_dev, "rx_rings",
5654 sc->bnx_rx_retcnt = if_ring_count2(sc->bnx_rx_retcnt, ring_max);
5656 if (sc->bnx_rx_retcnt == 1)
5660 * We need one extra MSI-X vector for link status or
5661 * TX ring (if only one TX ring is enabled).
5663 sc->bnx_intr_cnt = sc->bnx_rx_retcnt + 1;
5666 * Setup TX ring count
5668 * Currently only BCM5719 and BCM5720 support multiple TX rings
5669 * and the TX ring count must be less than the RX ring count.
5671 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
5672 sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
5673 ring_max = BNX_TX_RING_MAX;
5674 if (ring_max > msix_cnt2)
5675 ring_max = msix_cnt2;
5676 if (ring_max > sc->bnx_rx_retcnt)
5677 ring_max = sc->bnx_rx_retcnt;
5678 sc->bnx_tx_ringcnt = device_getenv_int(sc->bnx_dev, "tx_rings",
5680 sc->bnx_tx_ringcnt = if_ring_count2(sc->bnx_tx_ringcnt,
5686 bnx_alloc_msix(struct bnx_softc *sc)
5688 struct bnx_intr_data *intr;
5689 boolean_t setup = FALSE;
5690 int error, i, offset, offset_def;
5692 KKASSERT(sc->bnx_intr_cnt > 1);
5693 KKASSERT(sc->bnx_intr_cnt == sc->bnx_rx_retcnt + 1);
5695 if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
5699 intr = &sc->bnx_intr_data[0];
5701 intr->bnx_intr_serialize = &sc->bnx_main_serialize;
5702 intr->bnx_saved_status_tag = &sc->bnx_saved_status_tag;
5704 intr->bnx_intr_func = bnx_msix_status;
5705 intr->bnx_intr_arg = sc;
5706 intr->bnx_intr_cpuid = 0; /* XXX */
5708 ksnprintf(intr->bnx_intr_desc0, sizeof(intr->bnx_intr_desc0),
5709 "%s sts", device_get_nameunit(sc->bnx_dev));
5710 intr->bnx_intr_desc = intr->bnx_intr_desc0;
5715 if (sc->bnx_rx_retcnt == ncpus2) {
5718 offset_def = (sc->bnx_rx_retcnt *
5719 device_get_unit(sc->bnx_dev)) % ncpus2;
5721 offset = device_getenv_int(sc->bnx_dev,
5722 "msix.offset", offset_def);
5723 if (offset >= ncpus2 ||
5724 offset % sc->bnx_rx_retcnt != 0) {
5725 device_printf(sc->bnx_dev,
5726 "invalid msix.offset %d, use %d\n",
5727 offset, offset_def);
5728 offset = offset_def;
5732 for (i = 1; i < sc->bnx_intr_cnt; ++i) {
5735 intr = &sc->bnx_intr_data[i];
5737 KKASSERT(idx < sc->bnx_rx_retcnt);
5738 intr->bnx_ret = &sc->bnx_rx_ret_ring[idx];
5739 if (idx < sc->bnx_tx_ringcnt) {
5740 intr->bnx_txr = &sc->bnx_tx_ring[idx];
5741 intr->bnx_ret->bnx_txr = intr->bnx_txr;
5744 intr->bnx_intr_serialize =
5745 &intr->bnx_ret->bnx_rx_ret_serialize;
5746 intr->bnx_saved_status_tag =
5747 &intr->bnx_ret->bnx_saved_status_tag;
5749 intr->bnx_intr_arg = intr->bnx_ret;
5750 KKASSERT(idx + offset < ncpus2);
5751 intr->bnx_intr_cpuid = idx + offset;
5753 if (intr->bnx_txr == NULL) {
5754 intr->bnx_intr_check = bnx_check_intr_rx;
5755 intr->bnx_intr_func = bnx_msix_rx;
5756 ksnprintf(intr->bnx_intr_desc0,
5757 sizeof(intr->bnx_intr_desc0), "%s rx%d",
5758 device_get_nameunit(sc->bnx_dev), idx);
5760 intr->bnx_intr_check = bnx_check_intr_rxtx;
5761 intr->bnx_intr_func = bnx_msix_rxtx;
5762 ksnprintf(intr->bnx_intr_desc0,
5763 sizeof(intr->bnx_intr_desc0), "%s rxtx%d",
5764 device_get_nameunit(sc->bnx_dev), idx);
5766 intr->bnx_txr->bnx_tx_cpuid =
5767 intr->bnx_intr_cpuid;
5769 intr->bnx_intr_desc = intr->bnx_intr_desc0;
5771 intr->bnx_ret->bnx_msix_mbx = intr->bnx_intr_mbx;
5775 * TX ring and link status
5777 offset_def = device_get_unit(sc->bnx_dev) % ncpus2;
5778 offset = device_getenv_int(sc->bnx_dev, "msix.txoff",
5780 if (offset >= ncpus2) {
5781 device_printf(sc->bnx_dev,
5782 "invalid msix.txoff %d, use %d\n",
5783 offset, offset_def);
5784 offset = offset_def;
5787 intr = &sc->bnx_intr_data[0];
5789 intr->bnx_txr = &sc->bnx_tx_ring[0];
5790 intr->bnx_intr_serialize = &sc->bnx_main_serialize;
5791 intr->bnx_intr_check = bnx_check_intr_tx;
5792 intr->bnx_saved_status_tag =
5793 &intr->bnx_txr->bnx_saved_status_tag;
5795 intr->bnx_intr_func = bnx_msix_tx_status;
5796 intr->bnx_intr_arg = intr->bnx_txr;
5797 intr->bnx_intr_cpuid = offset;
5799 ksnprintf(intr->bnx_intr_desc0, sizeof(intr->bnx_intr_desc0),
5800 "%s ststx", device_get_nameunit(sc->bnx_dev));
5801 intr->bnx_intr_desc = intr->bnx_intr_desc0;
5803 intr->bnx_txr->bnx_tx_cpuid = intr->bnx_intr_cpuid;
5808 if (sc->bnx_rx_retcnt == ncpus2) {
5811 offset_def = (sc->bnx_rx_retcnt *
5812 device_get_unit(sc->bnx_dev)) % ncpus2;
5814 offset = device_getenv_int(sc->bnx_dev,
5815 "msix.rxoff", offset_def);
5816 if (offset >= ncpus2 ||
5817 offset % sc->bnx_rx_retcnt != 0) {
5818 device_printf(sc->bnx_dev,
5819 "invalid msix.rxoff %d, use %d\n",
5820 offset, offset_def);
5821 offset = offset_def;
5825 for (i = 1; i < sc->bnx_intr_cnt; ++i) {
5828 intr = &sc->bnx_intr_data[i];
5830 KKASSERT(idx < sc->bnx_rx_retcnt);
5831 intr->bnx_ret = &sc->bnx_rx_ret_ring[idx];
5832 intr->bnx_intr_serialize =
5833 &intr->bnx_ret->bnx_rx_ret_serialize;
5834 intr->bnx_intr_check = bnx_check_intr_rx;
5835 intr->bnx_saved_status_tag =
5836 &intr->bnx_ret->bnx_saved_status_tag;
5838 intr->bnx_intr_func = bnx_msix_rx;
5839 intr->bnx_intr_arg = intr->bnx_ret;
5840 KKASSERT(idx + offset < ncpus2);
5841 intr->bnx_intr_cpuid = idx + offset;
5843 ksnprintf(intr->bnx_intr_desc0,
5844 sizeof(intr->bnx_intr_desc0), "%s rx%d",
5845 device_get_nameunit(sc->bnx_dev), idx);
5846 intr->bnx_intr_desc = intr->bnx_intr_desc0;
5848 intr->bnx_ret->bnx_msix_mbx = intr->bnx_intr_mbx;
5852 sc->bnx_msix_mem_rid = PCIR_BAR(4);
5853 sc->bnx_msix_mem_res = bus_alloc_resource_any(sc->bnx_dev,
5854 SYS_RES_MEMORY, &sc->bnx_msix_mem_rid, RF_ACTIVE);
5855 if (sc->bnx_msix_mem_res == NULL) {
5856 device_printf(sc->bnx_dev, "could not alloc MSI-X table\n");
5860 bnx_enable_msi(sc, TRUE);
5862 error = pci_setup_msix(sc->bnx_dev);
5864 device_printf(sc->bnx_dev, "could not setup MSI-X\n");
5869 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
5870 intr = &sc->bnx_intr_data[i];
5872 error = pci_alloc_msix_vector(sc->bnx_dev, i,
5873 &intr->bnx_intr_rid, intr->bnx_intr_cpuid);
5875 device_printf(sc->bnx_dev,
5876 "could not alloc MSI-X %d on cpu%d\n",
5877 i, intr->bnx_intr_cpuid);
5881 intr->bnx_intr_res = bus_alloc_resource_any(sc->bnx_dev,
5882 SYS_RES_IRQ, &intr->bnx_intr_rid, RF_ACTIVE);
5883 if (intr->bnx_intr_res == NULL) {
5884 device_printf(sc->bnx_dev,
5885 "could not alloc MSI-X %d resource\n", i);
5891 pci_enable_msix(sc->bnx_dev);
5892 sc->bnx_intr_type = PCI_INTR_TYPE_MSIX;
5895 bnx_free_msix(sc, setup);
5900 bnx_free_msix(struct bnx_softc *sc, boolean_t setup)
5904 KKASSERT(sc->bnx_intr_cnt > 1);
5906 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
5907 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
5909 if (intr->bnx_intr_res != NULL) {
5910 bus_release_resource(sc->bnx_dev, SYS_RES_IRQ,
5911 intr->bnx_intr_rid, intr->bnx_intr_res);
5913 if (intr->bnx_intr_rid >= 0) {
5914 pci_release_msix_vector(sc->bnx_dev,
5915 intr->bnx_intr_rid);
5919 pci_teardown_msix(sc->bnx_dev);
5923 bnx_rx_std_refill_sched_ipi(void *xret)
5925 struct bnx_rx_ret_ring *ret = xret;
5926 struct bnx_rx_std_ring *std = ret->bnx_std;
5927 struct globaldata *gd = mycpu;
5931 atomic_set_int(&std->bnx_rx_std_refill, ret->bnx_rx_mask);
5934 KKASSERT(std->bnx_rx_std_ithread.td_gd == gd);
5935 lwkt_schedule(&std->bnx_rx_std_ithread);
5941 bnx_rx_std_refill_stop(void *xstd)
5943 struct bnx_rx_std_ring *std = xstd;
5944 struct globaldata *gd = mycpu;
5948 std->bnx_rx_std_stop = 1;
5951 KKASSERT(std->bnx_rx_std_ithread.td_gd == gd);
5952 lwkt_schedule(&std->bnx_rx_std_ithread);
5958 bnx_serialize_skipmain(struct bnx_softc *sc)
5960 lwkt_serialize_array_enter(sc->bnx_serialize,
5961 sc->bnx_serialize_cnt, 1);
5965 bnx_deserialize_skipmain(struct bnx_softc *sc)
5967 lwkt_serialize_array_exit(sc->bnx_serialize,
5968 sc->bnx_serialize_cnt, 1);
5972 bnx_rx_std_refill_sched(struct bnx_rx_ret_ring *ret,
5973 struct bnx_rx_std_ring *std)
5975 struct globaldata *gd = mycpu;
5977 ret->bnx_rx_cnt = 0;
5982 atomic_set_int(&std->bnx_rx_std_refill, ret->bnx_rx_mask);
5984 if (atomic_poll_acquire_int(&std->bnx_rx_std_running)) {
5985 if (std->bnx_rx_std_ithread.td_gd == gd) {
5986 lwkt_schedule(&std->bnx_rx_std_ithread);
5989 std->bnx_rx_std_ithread.td_gd,
5990 bnx_rx_std_refill_sched_ipi, ret);