sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  */
  32
  33 /*
  34  * The following controllers are supported by this driver:
  35  *   BCM5706C A2, A3
  36  *   BCM5706S A2, A3
  37  *   BCM5708C B1, B2
  38  *   BCM5708S B1, B2
  39  *   BCM5709C A1, C0
  40  *   BCM5716  C0
  41  *
  42  * The following controllers are not supported by this driver:
  43  *   BCM5706C A0, A1
  44  *   BCM5706S A0, A1
  45  *   BCM5708C A0, B0
  46  *   BCM5708S A0, B0
  47  *   BCM5709C A0, B0, B1
  48  *   BCM5709S A0, A1, B0, B1, B2, C0
  49  */
  50
  51 #include "opt_bce.h"
  52 #include "opt_ifpoll.h"
  53
  54 #include <sys/param.h>
  55 #include <sys/bus.h>
  56 #include <sys/endian.h>
  57 #include <sys/kernel.h>
  58 #include <sys/interrupt.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/malloc.h>
  61 #include <sys/queue.h>
  62 #ifdef BCE_DEBUG
  63 #include <sys/random.h>
  64 #endif
  65 #include <sys/rman.h>
  66 #include <sys/serialize.h>
  67 #include <sys/socket.h>
  68 #include <sys/sockio.h>
  69 #include <sys/sysctl.h>
  70
  71 #include <netinet/ip.h>
  72 #include <netinet/tcp.h>
  73
  74 #include <net/bpf.h>
  75 #include <net/ethernet.h>
  76 #include <net/if.h>
  77 #include <net/if_arp.h>
  78 #include <net/if_dl.h>
  79 #include <net/if_media.h>
  80 #include <net/if_poll.h>
  81 #include <net/if_types.h>
  82 #include <net/ifq_var.h>
  83 #include <net/vlan/if_vlan_var.h>
  84 #include <net/vlan/if_vlan_ether.h>
  85
  86 #include <dev/netif/mii_layer/mii.h>
  87 #include <dev/netif/mii_layer/miivar.h>
  88 #include <dev/netif/mii_layer/brgphyreg.h>
  89
  90 #include <bus/pci/pcireg.h>
  91 #include <bus/pci/pcivar.h>
  92
  93 #include "miibus_if.h"
  94
  95 #include <dev/netif/bce/if_bcereg.h>
  96 #include <dev/netif/bce/if_bcefw.h>
  97
  98 #define BCE_MSI_CKINTVL         ((10 * hz) / 1000)      /* 10ms */
  99
 100 /****************************************************************************/
 101 /* BCE Debug Options                                                        */
 102 /****************************************************************************/
 103 #ifdef BCE_DEBUG
 104
 105 static uint32_t bce_debug = BCE_WARN;
 106
 107 /*
 108  *          0 = Never
 109  *          1 = 1 in 2,147,483,648
 110  *        256 = 1 in     8,388,608
 111  *       2048 = 1 in     1,048,576
 112  *      65536 = 1 in        32,768
 113  *    1048576 = 1 in         2,048
 114  *  268435456 = 1 in             8
 115  *  536870912 = 1 in             4
 116  * 1073741824 = 1 in             2
 117  *
 118  * bce_debug_mbuf_allocation_failure:
 119  *     How often to simulate an mbuf allocation failure.
 120  *
 121  * bce_debug_dma_map_addr_failure:
 122  *     How often to simulate a DMA mapping failure.
 123  *
 124  * bce_debug_bootcode_running_failure:
 125  *     How often to simulate a bootcode failure.
 126  */
 127 static int      bce_debug_mbuf_allocation_failure = 0;
 128 static int      bce_debug_dma_map_addr_failure = 0;
 129 static int      bce_debug_bootcode_running_failure = 0;
 130
 131 #endif  /* BCE_DEBUG */
 132
 133
 134 /****************************************************************************/
 135 /* PCI Device ID Table                                                      */
 136 /*                                                                          */
 137 /* Used by bce_probe() to identify the devices supported by this driver.    */
 138 /****************************************************************************/
 139 #define BCE_DEVDESC_MAX         64
 140
 141 static struct bce_type bce_devs[] = {
 142         /* BCM5706C Controllers and OEM boards. */
 143         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 144                 "HP NC370T Multifunction Gigabit Server Adapter" },
 145         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 146                 "HP NC370i Multifunction Gigabit Server Adapter" },
 147         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 148                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 149         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 150                 "HP NC371i Multifunction Gigabit Server Adapter" },
 151         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 152                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 153
 154         /* BCM5706S controllers and OEM boards. */
 155         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 156                 "HP NC370F Multifunction Gigabit Server Adapter" },
 157         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 158                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 159
 160         /* BCM5708C controllers and OEM boards. */
 161         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 162                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 163         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 164                 "HP NC373i Multifunction Gigabit Server Adapter" },
 165         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 166                 "HP NC374m PCIe Multifunction Adapter" },
 167         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 168                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 169
 170         /* BCM5708S controllers and OEM boards. */
 171         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 172                 "HP NC373m Multifunction Gigabit Server Adapter" },
 173         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 174                 "HP NC373i Multifunction Gigabit Server Adapter" },
 175         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 176                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 177         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 178                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 179
 180         /* BCM5709C controllers and OEM boards. */
 181         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 182                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 183         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 184                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 185         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 186                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 187
 188         /* BCM5709S controllers and OEM boards. */
 189         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 190                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 191         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 192                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 193         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 194                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 195
 196         /* BCM5716 controllers and OEM boards. */
 197         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
 198                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 199
 200         { 0, 0, 0, 0, NULL }
 201 };
 202
 203
 204 /****************************************************************************/
 205 /* Supported Flash NVRAM device data.                                       */
 206 /****************************************************************************/
 207 static const struct flash_spec flash_table[] =
 208 {
 209 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 210 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 211
 212         /* Slow EEPROM */
 213         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 214          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 215          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 216          "EEPROM - slow"},
 217         /* Expansion entry 0001 */
 218         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 219          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 220          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 221          "Entry 0001"},
 222         /* Saifun SA25F010 (non-buffered flash) */
 223         /* strap, cfg1, & write1 need updates */
 224         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 225          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 226          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 227          "Non-buffered flash (128kB)"},
 228         /* Saifun SA25F020 (non-buffered flash) */
 229         /* strap, cfg1, & write1 need updates */
 230         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 231          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 232          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 233          "Non-buffered flash (256kB)"},
 234         /* Expansion entry 0100 */
 235         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 236          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 237          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 238          "Entry 0100"},
 239         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 240         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 241          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 242          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 243          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 244         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 245         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 246          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 247          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 248          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 249         /* Saifun SA25F005 (non-buffered flash) */
 250         /* strap, cfg1, & write1 need updates */
 251         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 252          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 253          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 254          "Non-buffered flash (64kB)"},
 255         /* Fast EEPROM */
 256         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 257          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 258          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 259          "EEPROM - fast"},
 260         /* Expansion entry 1001 */
 261         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 262          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 263          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 264          "Entry 1001"},
 265         /* Expansion entry 1010 */
 266         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 267          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 268          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 269          "Entry 1010"},
 270         /* ATMEL AT45DB011B (buffered flash) */
 271         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 272          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 273          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 274          "Buffered flash (128kB)"},
 275         /* Expansion entry 1100 */
 276         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 277          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 278          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 279          "Entry 1100"},
 280         /* Expansion entry 1101 */
 281         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 282          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 283          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 284          "Entry 1101"},
 285         /* Ateml Expansion entry 1110 */
 286         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 287          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 288          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 289          "Entry 1110 (Atmel)"},
 290         /* ATMEL AT45DB021B (buffered flash) */
 291         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 292          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 293          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 294          "Buffered flash (256kB)"},
 295 };
 296
 297 /*
 298  * The BCM5709 controllers transparently handle the
 299  * differences between Atmel 264 byte pages and all
 300  * flash devices which use 256 byte pages, so no
 301  * logical-to-physical mapping is required in the
 302  * driver.
 303  */
 304 static struct flash_spec flash_5709 = {
 305         .flags          = BCE_NV_BUFFERED,
 306         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 307         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 308         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 309         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 310         .name           = "5709/5716 buffered flash (256kB)",
 311 };
 312
 313
 314 /****************************************************************************/
 315 /* DragonFly device entry points.                                           */
 316 /****************************************************************************/
 317 static int      bce_probe(device_t);
 318 static int      bce_attach(device_t);
 319 static int      bce_detach(device_t);
 320 static void     bce_shutdown(device_t);
 321
 322 /****************************************************************************/
 323 /* BCE Debug Data Structure Dump Routines                                   */
 324 /****************************************************************************/
 325 #ifdef BCE_DEBUG
 326 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
 327 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
 328 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
 329 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
 330 static void     bce_dump_l2fhdr(struct bce_softc *, int,
 331                                 struct l2_fhdr *) __unused;
 332 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
 333 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
 334 static void     bce_dump_status_block(struct bce_softc *);
 335 static void     bce_dump_driver_state(struct bce_softc *);
 336 static void     bce_dump_stats_block(struct bce_softc *) __unused;
 337 static void     bce_dump_hw_state(struct bce_softc *);
 338 static void     bce_dump_txp_state(struct bce_softc *);
 339 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
 340 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
 341 static void     bce_freeze_controller(struct bce_softc *) __unused;
 342 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
 343 static void     bce_breakpoint(struct bce_softc *);
 344 #endif  /* BCE_DEBUG */
 345
 346
 347 /****************************************************************************/
 348 /* BCE Register/Memory Access Routines                                      */
 349 /****************************************************************************/
 350 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 351 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 352 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
 353 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
 354 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 355 static int      bce_miibus_read_reg(device_t, int, int);
 356 static int      bce_miibus_write_reg(device_t, int, int, int);
 357 static void     bce_miibus_statchg(device_t);
 358
 359
 360 /****************************************************************************/
 361 /* BCE NVRAM Access Routines                                                */
 362 /****************************************************************************/
 363 static int      bce_acquire_nvram_lock(struct bce_softc *);
 364 static int      bce_release_nvram_lock(struct bce_softc *);
 365 static void     bce_enable_nvram_access(struct bce_softc *);
 366 static void     bce_disable_nvram_access(struct bce_softc *);
 367 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 368                                      uint32_t);
 369 static int      bce_init_nvram(struct bce_softc *);
 370 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 371 static int      bce_nvram_test(struct bce_softc *);
 372
 373 /****************************************************************************/
 374 /* BCE DMA Allocate/Free Routines                                           */
 375 /****************************************************************************/
 376 static int      bce_dma_alloc(struct bce_softc *);
 377 static void     bce_dma_free(struct bce_softc *);
 378 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 379
 380 /****************************************************************************/
 381 /* BCE Firmware Synchronization and Load                                    */
 382 /****************************************************************************/
 383 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 384 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 385                                  uint32_t, uint32_t);
 386 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 387                                 struct fw_info *);
 388 static void     bce_start_cpu(struct bce_softc *, struct cpu_reg *);
 389 static void     bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
 390 static void     bce_start_rxp_cpu(struct bce_softc *);
 391 static void     bce_init_rxp_cpu(struct bce_softc *);
 392 static void     bce_init_txp_cpu(struct bce_softc *);
 393 static void     bce_init_tpat_cpu(struct bce_softc *);
 394 static void     bce_init_cp_cpu(struct bce_softc *);
 395 static void     bce_init_com_cpu(struct bce_softc *);
 396 static void     bce_init_cpus(struct bce_softc *);
 397
 398 static void     bce_stop(struct bce_softc *);
 399 static int      bce_reset(struct bce_softc *, uint32_t);
 400 static int      bce_chipinit(struct bce_softc *);
 401 static int      bce_blockinit(struct bce_softc *);
 402 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
 403                                uint32_t *, int);
 404 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
 405 static void     bce_probe_pci_caps(struct bce_softc *);
 406 static void     bce_print_adapter_info(struct bce_softc *);
 407 static void     bce_get_media(struct bce_softc *);
 408
 409 static void     bce_init_tx_context(struct bce_softc *);
 410 static int      bce_init_tx_chain(struct bce_softc *);
 411 static void     bce_init_rx_context(struct bce_softc *);
 412 static int      bce_init_rx_chain(struct bce_softc *);
 413 static void     bce_free_rx_chain(struct bce_softc *);
 414 static void     bce_free_tx_chain(struct bce_softc *);
 415
 416 static int      bce_encap(struct bce_softc *, struct mbuf **, int *);
 417 static int      bce_tso_setup(struct bce_softc *, struct mbuf **,
 418                     uint16_t *, uint16_t *);
 419 static void     bce_start(struct ifnet *, struct ifaltq_subque *);
 420 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 421 static void     bce_watchdog(struct ifnet *);
 422 static int      bce_ifmedia_upd(struct ifnet *);
 423 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 424 static void     bce_init(void *);
 425 static void     bce_mgmt_init(struct bce_softc *);
 426
 427 static int      bce_init_ctx(struct bce_softc *);
 428 static void     bce_get_mac_addr(struct bce_softc *);
 429 static void     bce_set_mac_addr(struct bce_softc *);
 430 static void     bce_phy_intr(struct bce_softc *);
 431 static void     bce_rx_intr(struct bce_softc *, int, uint16_t);
 432 static void     bce_tx_intr(struct bce_softc *, uint16_t);
 433 static void     bce_disable_intr(struct bce_softc *);
 434 static void     bce_enable_intr(struct bce_softc *);
 435 static void     bce_reenable_intr(struct bce_softc *);
 436
 437 #ifdef IFPOLL_ENABLE
 438 static void     bce_npoll(struct ifnet *, struct ifpoll_info *);
 439 static void     bce_npoll_compat(struct ifnet *, void *, int);
 440 #endif
 441 static void     bce_intr(struct bce_softc *);
 442 static void     bce_intr_legacy(void *);
 443 static void     bce_intr_msi(void *);
 444 static void     bce_intr_msi_oneshot(void *);
 445 static void     bce_set_rx_mode(struct bce_softc *);
 446 static void     bce_stats_update(struct bce_softc *);
 447 static void     bce_tick(void *);
 448 static void     bce_tick_serialized(struct bce_softc *);
 449 static void     bce_pulse(void *);
 450 static void     bce_check_msi(void *);
 451 static void     bce_add_sysctls(struct bce_softc *);
 452
 453 static void     bce_coal_change(struct bce_softc *);
 454 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
 455 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
 456 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
 457 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
 458 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
 459 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
 460 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
 461 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
 462 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
 463                                        uint32_t *, uint32_t);
 464
 465 /*
 466  * NOTE:
 467  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
 468  * takes 1023 as the TX ticks limit.  However, using 1023 will
 469  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
 470  * there is _no_ network activity on the NIC.
 471  */
 472 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
 473 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
 474 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
 475 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
 476 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
 477 static uint32_t bce_rx_bds = 0;                 /* bcm: 6 */
 478 static uint32_t bce_rx_ticks_int = 150;         /* bcm: 18 */
 479 static uint32_t bce_rx_ticks = 150;             /* bcm: 18 */
 480
 481 static int      bce_msi_enable = 1;
 482
 483 static int      bce_rx_pages = RX_PAGES_DEFAULT;
 484 static int      bce_tx_pages = TX_PAGES_DEFAULT;
 485
 486 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
 487 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
 488 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 489 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 490 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
 491 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
 492 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 493 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 494 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
 495 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
 496 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
 497
 498 /****************************************************************************/
 499 /* DragonFly device dispatch table.                                         */
 500 /****************************************************************************/
 501 static device_method_t bce_methods[] = {
 502         /* Device interface */
 503         DEVMETHOD(device_probe,         bce_probe),
 504         DEVMETHOD(device_attach,        bce_attach),
 505         DEVMETHOD(device_detach,        bce_detach),
 506         DEVMETHOD(device_shutdown,      bce_shutdown),
 507
 508         /* bus interface */
 509         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 510         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 511
 512         /* MII interface */
 513         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 514         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 515         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 516
 517         { 0, 0 }
 518 };
 519
 520 static driver_t bce_driver = {
 521         "bce",
 522         bce_methods,
 523         sizeof(struct bce_softc)
 524 };
 525
 526 static devclass_t bce_devclass;
 527
 528
 529 DECLARE_DUMMY_MODULE(if_bce);
 530 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 531 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
 532 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 533
 534
 535 /****************************************************************************/
 536 /* Device probe function.                                                   */
 537 /*                                                                          */
 538 /* Compares the device to the driver's list of supported devices and        */
 539 /* reports back to the OS whether this is the right driver for the device.  */
 540 /*                                                                          */
 541 /* Returns:                                                                 */
 542 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 543 /****************************************************************************/
 544 static int
 545 bce_probe(device_t dev)
 546 {
 547         struct bce_type *t;
 548         uint16_t vid, did, svid, sdid;
 549
 550         /* Get the data for the device to be probed. */
 551         vid  = pci_get_vendor(dev);
 552         did  = pci_get_device(dev);
 553         svid = pci_get_subvendor(dev);
 554         sdid = pci_get_subdevice(dev);
 555
 556         /* Look through the list of known devices for a match. */
 557         for (t = bce_devs; t->bce_name != NULL; ++t) {
 558                 if (vid == t->bce_vid && did == t->bce_did &&
 559                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 560                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 561                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 562                         char *descbuf;
 563
 564                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 565
 566                         /* Print out the device identity. */
 567                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 568                                   t->bce_name,
 569                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 570
 571                         device_set_desc_copy(dev, descbuf);
 572                         kfree(descbuf, M_TEMP);
 573                         return 0;
 574                 }
 575         }
 576         return ENXIO;
 577 }
 578
 579
 580 /****************************************************************************/
 581 /* PCI Capabilities Probe Function.                                         */
 582 /*                                                                          */
 583 /* Walks the PCI capabiites list for the device to find what features are   */
 584 /* supported.                                                               */
 585 /*                                                                          */
 586 /* Returns:                                                                 */
 587 /*   None.                                                                  */
 588 /****************************************************************************/
 589 static void
 590 bce_print_adapter_info(struct bce_softc *sc)
 591 {
 592         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
 593
 594         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 595                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 596
 597         /* Bus info. */
 598         if (sc->bce_flags & BCE_PCIE_FLAG) {
 599                 kprintf("Bus (PCIe x%d, ", sc->link_width);
 600                 switch (sc->link_speed) {
 601                 case 1:
 602                         kprintf("2.5Gbps); ");
 603                         break;
 604                 case 2:
 605                         kprintf("5Gbps); ");
 606                         break;
 607                 default:
 608                         kprintf("Unknown link speed); ");
 609                         break;
 610                 }
 611         } else {
 612                 kprintf("Bus (PCI%s, %s, %dMHz); ",
 613                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 614                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
 615                     sc->bus_speed_mhz);
 616         }
 617
 618         /* Firmware version and device features. */
 619         kprintf("B/C (%s)", sc->bce_bc_ver);
 620
 621         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
 622             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 623                 kprintf("; Flags(");
 624                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
 625                         kprintf("MFW[%s]", sc->bce_mfw_ver);
 626                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 627                         kprintf(" 2.5G");
 628                 kprintf(")");
 629         }
 630         kprintf("\n");
 631 }
 632
 633
 634 /****************************************************************************/
 635 /* PCI Capabilities Probe Function.                                         */
 636 /*                                                                          */
 637 /* Walks the PCI capabiites list for the device to find what features are   */
 638 /* supported.                                                               */
 639 /*                                                                          */
 640 /* Returns:                                                                 */
 641 /*   None.                                                                  */
 642 /****************************************************************************/
 643 static void
 644 bce_probe_pci_caps(struct bce_softc *sc)
 645 {
 646         device_t dev = sc->bce_dev;
 647         uint8_t ptr;
 648
 649         if (pci_is_pcix(dev))
 650                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 651
 652         ptr = pci_get_pciecap_ptr(dev);
 653         if (ptr) {
 654                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
 655
 656                 sc->link_speed = link_status & 0xf;
 657                 sc->link_width = (link_status >> 4) & 0x3f;
 658                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 659                 sc->bce_flags |= BCE_PCIE_FLAG;
 660         }
 661 }
 662
 663
 664 /****************************************************************************/
 665 /* Device attach function.                                                  */
 666 /*                                                                          */
 667 /* Allocates device resources, performs secondary chip identification,      */
 668 /* resets and initializes the hardware, and initializes driver instance     */
 669 /* variables.                                                               */
 670 /*                                                                          */
 671 /* Returns:                                                                 */
 672 /*   0 on success, positive value on failure.                               */
 673 /****************************************************************************/
 674 static int
 675 bce_attach(device_t dev)
 676 {
 677         struct bce_softc *sc = device_get_softc(dev);
 678         struct ifnet *ifp = &sc->arpcom.ac_if;
 679         uint32_t val;
 680         u_int irq_flags;
 681         void (*irq_handle)(void *);
 682         int rid, rc = 0;
 683         int i, j;
 684         struct mii_probe_args mii_args;
 685         uintptr_t mii_priv = 0;
 686
 687         sc->bce_dev = dev;
 688         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 689
 690         pci_enable_busmaster(dev);
 691
 692         bce_probe_pci_caps(sc);
 693
 694         /* Allocate PCI memory resources. */
 695         rid = PCIR_BAR(0);
 696         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 697                                                  RF_ACTIVE | PCI_RF_DENSE);
 698         if (sc->bce_res_mem == NULL) {
 699                 device_printf(dev, "PCI memory allocation failed\n");
 700                 return ENXIO;
 701         }
 702         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 703         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 704
 705         /* Allocate PCI IRQ resources. */
 706         sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
 707             &sc->bce_irq_rid, &irq_flags);
 708
 709         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 710             &sc->bce_irq_rid, irq_flags);
 711         if (sc->bce_res_irq == NULL) {
 712                 device_printf(dev, "PCI map interrupt failed\n");
 713                 rc = ENXIO;
 714                 goto fail;
 715         }
 716
 717         /*
 718          * Configure byte swap and enable indirect register access.
 719          * Rely on CPU to do target byte swapping on big endian systems.
 720          * Access to registers outside of PCI configurtion space are not
 721          * valid until this is done.
 722          */
 723         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 724                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 725                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 726
 727         /* Save ASIC revsion info. */
 728         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 729
 730         /* Weed out any non-production controller revisions. */
 731         switch (BCE_CHIP_ID(sc)) {
 732         case BCE_CHIP_ID_5706_A0:
 733         case BCE_CHIP_ID_5706_A1:
 734         case BCE_CHIP_ID_5708_A0:
 735         case BCE_CHIP_ID_5708_B0:
 736         case BCE_CHIP_ID_5709_A0:
 737         case BCE_CHIP_ID_5709_B0:
 738         case BCE_CHIP_ID_5709_B1:
 739 #ifdef foo
 740         /* 5709C B2 seems to work fine */
 741         case BCE_CHIP_ID_5709_B2:
 742 #endif
 743                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 744                               BCE_CHIP_ID(sc));
 745                 rc = ENODEV;
 746                 goto fail;
 747         }
 748
 749         mii_priv |= BRGPHY_FLAG_WIRESPEED;
 750         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
 751                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax ||
 752                     BCE_CHIP_REV(sc) == BCE_CHIP_REV_Bx)
 753                         mii_priv |= BRGPHY_FLAG_NO_EARLYDAC;
 754         } else {
 755                 mii_priv |= BRGPHY_FLAG_BER_BUG;
 756         }
 757
 758         if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
 759                 irq_handle = bce_intr_legacy;
 760         } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
 761                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
 762                         irq_handle = bce_intr_msi_oneshot;
 763                         sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
 764                 } else {
 765                         irq_handle = bce_intr_msi;
 766                         sc->bce_flags |= BCE_CHECK_MSI_FLAG;
 767                 }
 768         } else {
 769                 panic("%s: unsupported intr type %d",
 770                     device_get_nameunit(dev), sc->bce_irq_type);
 771         }
 772
 773         /*
 774          * Find the base address for shared memory access.
 775          * Newer versions of bootcode use a signature and offset
 776          * while older versions use a fixed address.
 777          */
 778         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 779         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
 780             BCE_SHM_HDR_SIGNATURE_SIG) {
 781                 /* Multi-port devices use different offsets in shared memory. */
 782                 sc->bce_shmem_base = REG_RD_IND(sc,
 783                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
 784         } else {
 785                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 786         }
 787         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
 788
 789         /* Fetch the bootcode revision. */
 790         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
 791         for (i = 0, j = 0; i < 3; i++) {
 792                 uint8_t num;
 793                 int k, skip0;
 794
 795                 num = (uint8_t)(val >> (24 - (i * 8)));
 796                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
 797                         if (num >= k || !skip0 || k == 1) {
 798                                 sc->bce_bc_ver[j++] = (num / k) + '0';
 799                                 skip0 = 0;
 800                         }
 801                 }
 802                 if (i != 2)
 803                         sc->bce_bc_ver[j++] = '.';
 804         }
 805
 806         /* Check if any management firwmare is running. */
 807         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
 808         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
 809                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
 810
 811                 /* Allow time for firmware to enter the running state. */
 812                 for (i = 0; i < 30; i++) {
 813                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
 814                         if (val & BCE_CONDITION_MFW_RUN_MASK)
 815                                 break;
 816                         DELAY(10000);
 817                 }
 818         }
 819
 820         /* Check the current bootcode state. */
 821         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
 822             BCE_CONDITION_MFW_RUN_MASK;
 823         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
 824             val != BCE_CONDITION_MFW_RUN_NONE) {
 825                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
 826
 827                 for (i = 0, j = 0; j < 3; j++) {
 828                         val = bce_reg_rd_ind(sc, addr + j * 4);
 829                         val = bswap32(val);
 830                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
 831                         i += 4;
 832                 }
 833         }
 834
 835         /* Get PCI bus information (speed and type). */
 836         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 837         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 838                 uint32_t clkreg;
 839
 840                 sc->bce_flags |= BCE_PCIX_FLAG;
 841
 842                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 843                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 844                 switch (clkreg) {
 845                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 846                         sc->bus_speed_mhz = 133;
 847                         break;
 848
 849                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 850                         sc->bus_speed_mhz = 100;
 851                         break;
 852
 853                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 854                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 855                         sc->bus_speed_mhz = 66;
 856                         break;
 857
 858                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 859                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 860                         sc->bus_speed_mhz = 50;
 861                         break;
 862
 863                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 864                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 865                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 866                         sc->bus_speed_mhz = 33;
 867                         break;
 868                 }
 869         } else {
 870                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 871                         sc->bus_speed_mhz = 66;
 872                 else
 873                         sc->bus_speed_mhz = 33;
 874         }
 875
 876         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 877                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 878
 879         /* Reset the controller. */
 880         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 881         if (rc != 0)
 882                 goto fail;
 883
 884         /* Initialize the controller. */
 885         rc = bce_chipinit(sc);
 886         if (rc != 0) {
 887                 device_printf(dev, "Controller initialization failed!\n");
 888                 goto fail;
 889         }
 890
 891         /* Perform NVRAM test. */
 892         rc = bce_nvram_test(sc);
 893         if (rc != 0) {
 894                 device_printf(dev, "NVRAM test failed!\n");
 895                 goto fail;
 896         }
 897
 898         /* Fetch the permanent Ethernet MAC address. */
 899         bce_get_mac_addr(sc);
 900
 901         /*
 902          * Trip points control how many BDs
 903          * should be ready before generating an
 904          * interrupt while ticks control how long
 905          * a BD can sit in the chain before
 906          * generating an interrupt.  Set the default
 907          * values for the RX and TX rings.
 908          */
 909
 910 #ifdef BCE_DRBUG
 911         /* Force more frequent interrupts. */
 912         sc->bce_tx_quick_cons_trip_int = 1;
 913         sc->bce_tx_quick_cons_trip     = 1;
 914         sc->bce_tx_ticks_int           = 0;
 915         sc->bce_tx_ticks               = 0;
 916
 917         sc->bce_rx_quick_cons_trip_int = 1;
 918         sc->bce_rx_quick_cons_trip     = 1;
 919         sc->bce_rx_ticks_int           = 0;
 920         sc->bce_rx_ticks               = 0;
 921 #else
 922         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
 923         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
 924         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
 925         sc->bce_tx_ticks               = bce_tx_ticks;
 926
 927         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
 928         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
 929         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
 930         sc->bce_rx_ticks               = bce_rx_ticks;
 931 #endif
 932         sc->tx_wreg = 8;
 933
 934         /* Update statistics once every second. */
 935         sc->bce_stats_ticks = 1000000 & 0xffff00;
 936
 937         /* Find the media type for the adapter. */
 938         bce_get_media(sc);
 939
 940         /* Allocate DMA memory resources. */
 941         rc = bce_dma_alloc(sc);
 942         if (rc != 0) {
 943                 device_printf(dev, "DMA resource allocation failed!\n");
 944                 goto fail;
 945         }
 946
 947         /* Initialize the ifnet interface. */
 948         ifp->if_softc = sc;
 949         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 950         ifp->if_ioctl = bce_ioctl;
 951         ifp->if_start = bce_start;
 952         ifp->if_init = bce_init;
 953         ifp->if_watchdog = bce_watchdog;
 954 #ifdef IFPOLL_ENABLE
 955         ifp->if_npoll = bce_npoll;
 956 #endif
 957         ifp->if_mtu = ETHERMTU;
 958         ifp->if_hwassist = BCE_CSUM_FEATURES | CSUM_TSO;
 959         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 960         ifp->if_capenable = ifp->if_capabilities;
 961         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD(sc));
 962         ifq_set_ready(&ifp->if_snd);
 963
 964         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 965                 ifp->if_baudrate = IF_Gbps(2.5);
 966         else
 967                 ifp->if_baudrate = IF_Gbps(1);
 968
 969         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
 970         sc->mbuf_alloc_size  = MCLBYTES;
 971
 972         /*
 973          * Look for our PHY.
 974          */
 975         mii_probe_args_init(&mii_args, bce_ifmedia_upd, bce_ifmedia_sts);
 976         mii_args.mii_probemask = 1 << sc->bce_phy_addr;
 977         mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
 978         mii_args.mii_priv = mii_priv;
 979
 980         rc = mii_probe(dev, &sc->bce_miibus, &mii_args);
 981         if (rc != 0) {
 982                 device_printf(dev, "PHY probe failed!\n");
 983                 goto fail;
 984         }
 985
 986         /* Attach to the Ethernet interface list. */
 987         ether_ifattach(ifp, sc->eaddr, NULL);
 988
 989         callout_init_mp(&sc->bce_tick_callout);
 990         callout_init_mp(&sc->bce_pulse_callout);
 991         callout_init_mp(&sc->bce_ckmsi_callout);
 992
 993         /* Hookup IRQ last. */
 994         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
 995                             &sc->bce_intrhand, ifp->if_serializer);
 996         if (rc != 0) {
 997                 device_printf(dev, "Failed to setup IRQ!\n");
 998                 ether_ifdetach(ifp);
 999                 goto fail;
1000         }
1001
1002         sc->bce_intr_cpuid = rman_get_cpuid(sc->bce_res_irq);
1003         ifq_set_cpuid(&ifp->if_snd, sc->bce_intr_cpuid);
1004
1005         /* Print some important debugging info. */
1006         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
1007
1008         /* Add the supported sysctls to the kernel. */
1009         bce_add_sysctls(sc);
1010
1011 #ifdef IFPOLL_ENABLE
1012         ifpoll_compat_setup(&sc->bce_npoll,
1013             &sc->bce_sysctl_ctx, sc->bce_sysctl_tree, device_get_unit(dev),
1014             ifp->if_serializer);
1015 #endif
1016
1017         /*
1018          * The chip reset earlier notified the bootcode that
1019          * a driver is present.  We now need to start our pulse
1020          * routine so that the bootcode is reminded that we're
1021          * still running.
1022          */
1023         bce_pulse(sc);
1024
1025         /* Get the firmware running so IPMI still works */
1026         bce_mgmt_init(sc);
1027
1028         if (bootverbose)
1029                 bce_print_adapter_info(sc);
1030
1031         return 0;
1032 fail:
1033         bce_detach(dev);
1034         return(rc);
1035 }
1036
1037
1038 /****************************************************************************/
1039 /* Device detach function.                                                  */
1040 /*                                                                          */
1041 /* Stops the controller, resets the controller, and releases resources.     */
1042 /*                                                                          */
1043 /* Returns:                                                                 */
1044 /*   0 on success, positive value on failure.                               */
1045 /****************************************************************************/
1046 static int
1047 bce_detach(device_t dev)
1048 {
1049         struct bce_softc *sc = device_get_softc(dev);
1050
1051         if (device_is_attached(dev)) {
1052                 struct ifnet *ifp = &sc->arpcom.ac_if;
1053                 uint32_t msg;
1054
1055                 /* Stop and reset the controller. */
1056                 lwkt_serialize_enter(ifp->if_serializer);
1057                 callout_stop(&sc->bce_pulse_callout);
1058                 bce_stop(sc);
1059                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1060                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1061                 else
1062                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1063                 bce_reset(sc, msg);
1064                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1065                 lwkt_serialize_exit(ifp->if_serializer);
1066
1067                 ether_ifdetach(ifp);
1068         }
1069
1070         /* If we have a child device on the MII bus remove it too. */
1071         if (sc->bce_miibus)
1072                 device_delete_child(dev, sc->bce_miibus);
1073         bus_generic_detach(dev);
1074
1075         if (sc->bce_res_irq != NULL) {
1076                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1077                     sc->bce_res_irq);
1078         }
1079
1080         if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1081                 pci_release_msi(dev);
1082
1083         if (sc->bce_res_mem != NULL) {
1084                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1085                                      sc->bce_res_mem);
1086         }
1087
1088         bce_dma_free(sc);
1089
1090         if (sc->bce_sysctl_tree != NULL)
1091                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1092
1093         return 0;
1094 }
1095
1096
1097 /****************************************************************************/
1098 /* Device shutdown function.                                                */
1099 /*                                                                          */
1100 /* Stops and resets the controller.                                         */
1101 /*                                                                          */
1102 /* Returns:                                                                 */
1103 /*   Nothing                                                                */
1104 /****************************************************************************/
1105 static void
1106 bce_shutdown(device_t dev)
1107 {
1108         struct bce_softc *sc = device_get_softc(dev);
1109         struct ifnet *ifp = &sc->arpcom.ac_if;
1110         uint32_t msg;
1111
1112         lwkt_serialize_enter(ifp->if_serializer);
1113         bce_stop(sc);
1114         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1115                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1116         else
1117                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1118         bce_reset(sc, msg);
1119         lwkt_serialize_exit(ifp->if_serializer);
1120 }
1121
1122
1123 /****************************************************************************/
1124 /* Indirect register read.                                                  */
1125 /*                                                                          */
1126 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1127 /* configuration space.  Using this mechanism avoids issues with posted     */
1128 /* reads but is much slower than memory-mapped I/O.                         */
1129 /*                                                                          */
1130 /* Returns:                                                                 */
1131 /*   The value of the register.                                             */
1132 /****************************************************************************/
1133 static uint32_t
1134 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1135 {
1136         device_t dev = sc->bce_dev;
1137
1138         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1139 #ifdef BCE_DEBUG
1140         {
1141                 uint32_t val;
1142                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1143                 DBPRINT(sc, BCE_EXCESSIVE,
1144                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1145                         __func__, offset, val);
1146                 return val;
1147         }
1148 #else
1149         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1150 #endif
1151 }
1152
1153
1154 /****************************************************************************/
1155 /* Indirect register write.                                                 */
1156 /*                                                                          */
1157 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1158 /* configuration space.  Using this mechanism avoids issues with posted     */
1159 /* writes but is muchh slower than memory-mapped I/O.                       */
1160 /*                                                                          */
1161 /* Returns:                                                                 */
1162 /*   Nothing.                                                               */
1163 /****************************************************************************/
1164 static void
1165 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1166 {
1167         device_t dev = sc->bce_dev;
1168
1169         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1170                 __func__, offset, val);
1171
1172         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1173         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1174 }
1175
1176
1177 /****************************************************************************/
1178 /* Shared memory write.                                                     */
1179 /*                                                                          */
1180 /* Writes NetXtreme II shared memory region.                                */
1181 /*                                                                          */
1182 /* Returns:                                                                 */
1183 /*   Nothing.                                                               */
1184 /****************************************************************************/
1185 static void
1186 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1187 {
1188         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1189 }
1190
1191
1192 /****************************************************************************/
1193 /* Shared memory read.                                                      */
1194 /*                                                                          */
1195 /* Reads NetXtreme II shared memory region.                                 */
1196 /*                                                                          */
1197 /* Returns:                                                                 */
1198 /*   The 32 bit value read.                                                 */
1199 /****************************************************************************/
1200 static u32
1201 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1202 {
1203         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1204 }
1205
1206
1207 /****************************************************************************/
1208 /* Context memory write.                                                    */
1209 /*                                                                          */
1210 /* The NetXtreme II controller uses context memory to track connection      */
1211 /* information for L2 and higher network protocols.                         */
1212 /*                                                                          */
1213 /* Returns:                                                                 */
1214 /*   Nothing.                                                               */
1215 /****************************************************************************/
1216 static void
1217 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1218     uint32_t ctx_val)
1219 {
1220         uint32_t idx, offset = ctx_offset + cid_addr;
1221         uint32_t val, retry_cnt = 5;
1222
1223         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1224             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1225                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1226                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1227
1228                 for (idx = 0; idx < retry_cnt; idx++) {
1229                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1230                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1231                                 break;
1232                         DELAY(5);
1233                 }
1234
1235                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1236                         device_printf(sc->bce_dev,
1237                             "Unable to write CTX memory: "
1238                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1239                             cid_addr, ctx_offset);
1240                 }
1241         } else {
1242                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1243                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1244         }
1245 }
1246
1247
1248 /****************************************************************************/
1249 /* PHY register read.                                                       */
1250 /*                                                                          */
1251 /* Implements register reads on the MII bus.                                */
1252 /*                                                                          */
1253 /* Returns:                                                                 */
1254 /*   The value of the register.                                             */
1255 /****************************************************************************/
1256 static int
1257 bce_miibus_read_reg(device_t dev, int phy, int reg)
1258 {
1259         struct bce_softc *sc = device_get_softc(dev);
1260         uint32_t val;
1261         int i;
1262
1263         /* Make sure we are accessing the correct PHY address. */
1264         KASSERT(phy == sc->bce_phy_addr,
1265             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1266
1267         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1268                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1269                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1270
1271                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1272                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1273
1274                 DELAY(40);
1275         }
1276
1277         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1278               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1279               BCE_EMAC_MDIO_COMM_START_BUSY;
1280         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1281
1282         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1283                 DELAY(10);
1284
1285                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1286                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1287                         DELAY(5);
1288
1289                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1290                         val &= BCE_EMAC_MDIO_COMM_DATA;
1291                         break;
1292                 }
1293         }
1294
1295         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1296                 if_printf(&sc->arpcom.ac_if,
1297                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1298                           phy, reg);
1299                 val = 0x0;
1300         } else {
1301                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1302         }
1303
1304         DBPRINT(sc, BCE_EXCESSIVE,
1305                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1306                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1307
1308         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1309                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1310                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1311
1312                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1313                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1314
1315                 DELAY(40);
1316         }
1317         return (val & 0xffff);
1318 }
1319
1320
1321 /****************************************************************************/
1322 /* PHY register write.                                                      */
1323 /*                                                                          */
1324 /* Implements register writes on the MII bus.                               */
1325 /*                                                                          */
1326 /* Returns:                                                                 */
1327 /*   The value of the register.                                             */
1328 /****************************************************************************/
1329 static int
1330 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1331 {
1332         struct bce_softc *sc = device_get_softc(dev);
1333         uint32_t val1;
1334         int i;
1335
1336         /* Make sure we are accessing the correct PHY address. */
1337         KASSERT(phy == sc->bce_phy_addr,
1338             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1339
1340         DBPRINT(sc, BCE_EXCESSIVE,
1341                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1342                 __func__, phy, (uint16_t)(reg & 0xffff),
1343                 (uint16_t)(val & 0xffff));
1344
1345         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1346                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1347                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1348
1349                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1350                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1351
1352                 DELAY(40);
1353         }
1354
1355         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1356                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1357                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1358         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1359
1360         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1361                 DELAY(10);
1362
1363                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1364                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1365                         DELAY(5);
1366                         break;
1367                 }
1368         }
1369
1370         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1371                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1372
1373         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1374                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1375                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1376
1377                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1378                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1379
1380                 DELAY(40);
1381         }
1382         return 0;
1383 }
1384
1385
1386 /****************************************************************************/
1387 /* MII bus status change.                                                   */
1388 /*                                                                          */
1389 /* Called by the MII bus driver when the PHY establishes link to set the    */
1390 /* MAC interface registers.                                                 */
1391 /*                                                                          */
1392 /* Returns:                                                                 */
1393 /*   Nothing.                                                               */
1394 /****************************************************************************/
1395 static void
1396 bce_miibus_statchg(device_t dev)
1397 {
1398         struct bce_softc *sc = device_get_softc(dev);
1399         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1400
1401         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1402                 mii->mii_media_active);
1403
1404 #ifdef BCE_DEBUG
1405         /* Decode the interface media flags. */
1406         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1407         switch(IFM_TYPE(mii->mii_media_active)) {
1408         case IFM_ETHER:
1409                 kprintf("Ethernet )");
1410                 break;
1411         default:
1412                 kprintf("Unknown )");
1413                 break;
1414         }
1415
1416         kprintf(" Media Options: ( ");
1417         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1418         case IFM_AUTO:
1419                 kprintf("Autoselect )");
1420                 break;
1421         case IFM_MANUAL:
1422                 kprintf("Manual )");
1423                 break;
1424         case IFM_NONE:
1425                 kprintf("None )");
1426                 break;
1427         case IFM_10_T:
1428                 kprintf("10Base-T )");
1429                 break;
1430         case IFM_100_TX:
1431                 kprintf("100Base-TX )");
1432                 break;
1433         case IFM_1000_SX:
1434                 kprintf("1000Base-SX )");
1435                 break;
1436         case IFM_1000_T:
1437                 kprintf("1000Base-T )");
1438                 break;
1439         default:
1440                 kprintf("Other )");
1441                 break;
1442         }
1443
1444         kprintf(" Global Options: (");
1445         if (mii->mii_media_active & IFM_FDX)
1446                 kprintf(" FullDuplex");
1447         if (mii->mii_media_active & IFM_HDX)
1448                 kprintf(" HalfDuplex");
1449         if (mii->mii_media_active & IFM_LOOP)
1450                 kprintf(" Loopback");
1451         if (mii->mii_media_active & IFM_FLAG0)
1452                 kprintf(" Flag0");
1453         if (mii->mii_media_active & IFM_FLAG1)
1454                 kprintf(" Flag1");
1455         if (mii->mii_media_active & IFM_FLAG2)
1456                 kprintf(" Flag2");
1457         kprintf(" )\n");
1458 #endif
1459
1460         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1461
1462         /*
1463          * Set MII or GMII interface based on the speed negotiated
1464          * by the PHY.
1465          */
1466         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1467             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1468                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1469                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1470         } else {
1471                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1472                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1473         }
1474
1475         /*
1476          * Set half or full duplex based on the duplicity negotiated
1477          * by the PHY.
1478          */
1479         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1480                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1481                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1482         } else {
1483                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1484                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1485         }
1486 }
1487
1488
1489 /****************************************************************************/
1490 /* Acquire NVRAM lock.                                                      */
1491 /*                                                                          */
1492 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1493 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1494 /* for use by the driver.                                                   */
1495 /*                                                                          */
1496 /* Returns:                                                                 */
1497 /*   0 on success, positive value on failure.                               */
1498 /****************************************************************************/
1499 static int
1500 bce_acquire_nvram_lock(struct bce_softc *sc)
1501 {
1502         uint32_t val;
1503         int j;
1504
1505         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1506
1507         /* Request access to the flash interface. */
1508         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1509         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1510                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1511                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1512                         break;
1513
1514                 DELAY(5);
1515         }
1516
1517         if (j >= NVRAM_TIMEOUT_COUNT) {
1518                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1519                 return EBUSY;
1520         }
1521         return 0;
1522 }
1523
1524
1525 /****************************************************************************/
1526 /* Release NVRAM lock.                                                      */
1527 /*                                                                          */
1528 /* When the caller is finished accessing NVRAM the lock must be released.   */
1529 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1530 /* for use by the driver.                                                   */
1531 /*                                                                          */
1532 /* Returns:                                                                 */
1533 /*   0 on success, positive value on failure.                               */
1534 /****************************************************************************/
1535 static int
1536 bce_release_nvram_lock(struct bce_softc *sc)
1537 {
1538         int j;
1539         uint32_t val;
1540
1541         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1542
1543         /*
1544          * Relinquish nvram interface.
1545          */
1546         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1547
1548         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1549                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1550                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1551                         break;
1552
1553                 DELAY(5);
1554         }
1555
1556         if (j >= NVRAM_TIMEOUT_COUNT) {
1557                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1558                 return EBUSY;
1559         }
1560         return 0;
1561 }
1562
1563
1564 /****************************************************************************/
1565 /* Enable NVRAM access.                                                     */
1566 /*                                                                          */
1567 /* Before accessing NVRAM for read or write operations the caller must      */
1568 /* enabled NVRAM access.                                                    */
1569 /*                                                                          */
1570 /* Returns:                                                                 */
1571 /*   Nothing.                                                               */
1572 /****************************************************************************/
1573 static void
1574 bce_enable_nvram_access(struct bce_softc *sc)
1575 {
1576         uint32_t val;
1577
1578         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1579
1580         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1581         /* Enable both bits, even on read. */
1582         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1583                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1584 }
1585
1586
1587 /****************************************************************************/
1588 /* Disable NVRAM access.                                                    */
1589 /*                                                                          */
1590 /* When the caller is finished accessing NVRAM access must be disabled.     */
1591 /*                                                                          */
1592 /* Returns:                                                                 */
1593 /*   Nothing.                                                               */
1594 /****************************************************************************/
1595 static void
1596 bce_disable_nvram_access(struct bce_softc *sc)
1597 {
1598         uint32_t val;
1599
1600         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1601
1602         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1603
1604         /* Disable both bits, even after read. */
1605         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1606                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1607 }
1608
1609
1610 /****************************************************************************/
1611 /* Read a dword (32 bits) from NVRAM.                                       */
1612 /*                                                                          */
1613 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1614 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1615 /*                                                                          */
1616 /* Returns:                                                                 */
1617 /*   0 on success and the 32 bit value read, positive value on failure.     */
1618 /****************************************************************************/
1619 static int
1620 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1621                      uint32_t cmd_flags)
1622 {
1623         uint32_t cmd;
1624         int i, rc = 0;
1625
1626         /* Build the command word. */
1627         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1628
1629         /* Calculate the offset for buffered flash. */
1630         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1631                 offset = ((offset / sc->bce_flash_info->page_size) <<
1632                           sc->bce_flash_info->page_bits) +
1633                          (offset % sc->bce_flash_info->page_size);
1634         }
1635
1636         /*
1637          * Clear the DONE bit separately, set the address to read,
1638          * and issue the read.
1639          */
1640         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1641         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1642         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1643
1644         /* Wait for completion. */
1645         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1646                 uint32_t val;
1647
1648                 DELAY(5);
1649
1650                 val = REG_RD(sc, BCE_NVM_COMMAND);
1651                 if (val & BCE_NVM_COMMAND_DONE) {
1652                         val = REG_RD(sc, BCE_NVM_READ);
1653
1654                         val = be32toh(val);
1655                         memcpy(ret_val, &val, 4);
1656                         break;
1657                 }
1658         }
1659
1660         /* Check for errors. */
1661         if (i >= NVRAM_TIMEOUT_COUNT) {
1662                 if_printf(&sc->arpcom.ac_if,
1663                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1664                           offset);
1665                 rc = EBUSY;
1666         }
1667         return rc;
1668 }
1669
1670
1671 /****************************************************************************/
1672 /* Initialize NVRAM access.                                                 */
1673 /*                                                                          */
1674 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1675 /* access that device.                                                      */
1676 /*                                                                          */
1677 /* Returns:                                                                 */
1678 /*   0 on success, positive value on failure.                               */
1679 /****************************************************************************/
1680 static int
1681 bce_init_nvram(struct bce_softc *sc)
1682 {
1683         uint32_t val;
1684         int j, entry_count, rc = 0;
1685         const struct flash_spec *flash;
1686
1687         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1688
1689         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1690             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1691                 sc->bce_flash_info = &flash_5709;
1692                 goto bce_init_nvram_get_flash_size;
1693         }
1694
1695         /* Determine the selected interface. */
1696         val = REG_RD(sc, BCE_NVM_CFG1);
1697
1698         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1699
1700         /*
1701          * Flash reconfiguration is required to support additional
1702          * NVRAM devices not directly supported in hardware.
1703          * Check if the flash interface was reconfigured
1704          * by the bootcode.
1705          */
1706
1707         if (val & 0x40000000) {
1708                 /* Flash interface reconfigured by bootcode. */
1709
1710                 DBPRINT(sc, BCE_INFO_LOAD,
1711                         "%s(): Flash WAS reconfigured.\n", __func__);
1712
1713                 for (j = 0, flash = flash_table; j < entry_count;
1714                      j++, flash++) {
1715                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1716                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1717                                 sc->bce_flash_info = flash;
1718                                 break;
1719                         }
1720                 }
1721         } else {
1722                 /* Flash interface not yet reconfigured. */
1723                 uint32_t mask;
1724
1725                 DBPRINT(sc, BCE_INFO_LOAD,
1726                         "%s(): Flash was NOT reconfigured.\n", __func__);
1727
1728                 if (val & (1 << 23))
1729                         mask = FLASH_BACKUP_STRAP_MASK;
1730                 else
1731                         mask = FLASH_STRAP_MASK;
1732
1733                 /* Look for the matching NVRAM device configuration data. */
1734                 for (j = 0, flash = flash_table; j < entry_count;
1735                      j++, flash++) {
1736                         /* Check if the device matches any of the known devices. */
1737                         if ((val & mask) == (flash->strapping & mask)) {
1738                                 /* Found a device match. */
1739                                 sc->bce_flash_info = flash;
1740
1741                                 /* Request access to the flash interface. */
1742                                 rc = bce_acquire_nvram_lock(sc);
1743                                 if (rc != 0)
1744                                         return rc;
1745
1746                                 /* Reconfigure the flash interface. */
1747                                 bce_enable_nvram_access(sc);
1748                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1749                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1750                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1751                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1752                                 bce_disable_nvram_access(sc);
1753                                 bce_release_nvram_lock(sc);
1754                                 break;
1755                         }
1756                 }
1757         }
1758
1759         /* Check if a matching device was found. */
1760         if (j == entry_count) {
1761                 sc->bce_flash_info = NULL;
1762                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1763                 return ENODEV;
1764         }
1765
1766 bce_init_nvram_get_flash_size:
1767         /* Write the flash config data to the shared memory interface. */
1768         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1769             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1770         if (val)
1771                 sc->bce_flash_size = val;
1772         else
1773                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1774
1775         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1776                 __func__, sc->bce_flash_info->total_size);
1777
1778         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1779
1780         return rc;
1781 }
1782
1783
1784 /****************************************************************************/
1785 /* Read an arbitrary range of data from NVRAM.                              */
1786 /*                                                                          */
1787 /* Prepares the NVRAM interface for access and reads the requested data     */
1788 /* into the supplied buffer.                                                */
1789 /*                                                                          */
1790 /* Returns:                                                                 */
1791 /*   0 on success and the data read, positive value on failure.             */
1792 /****************************************************************************/
1793 static int
1794 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1795                int buf_size)
1796 {
1797         uint32_t cmd_flags, offset32, len32, extra;
1798         int rc = 0;
1799
1800         if (buf_size == 0)
1801                 return 0;
1802
1803         /* Request access to the flash interface. */
1804         rc = bce_acquire_nvram_lock(sc);
1805         if (rc != 0)
1806                 return rc;
1807
1808         /* Enable access to flash interface */
1809         bce_enable_nvram_access(sc);
1810
1811         len32 = buf_size;
1812         offset32 = offset;
1813         extra = 0;
1814
1815         cmd_flags = 0;
1816
1817         /* XXX should we release nvram lock if read_dword() fails? */
1818         if (offset32 & 3) {
1819                 uint8_t buf[4];
1820                 uint32_t pre_len;
1821
1822                 offset32 &= ~3;
1823                 pre_len = 4 - (offset & 3);
1824
1825                 if (pre_len >= len32) {
1826                         pre_len = len32;
1827                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1828                 } else {
1829                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1830                 }
1831
1832                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1833                 if (rc)
1834                         return rc;
1835
1836                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1837
1838                 offset32 += 4;
1839                 ret_buf += pre_len;
1840                 len32 -= pre_len;
1841         }
1842
1843         if (len32 & 3) {
1844                 extra = 4 - (len32 & 3);
1845                 len32 = (len32 + 4) & ~3;
1846         }
1847
1848         if (len32 == 4) {
1849                 uint8_t buf[4];
1850
1851                 if (cmd_flags)
1852                         cmd_flags = BCE_NVM_COMMAND_LAST;
1853                 else
1854                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1855                                     BCE_NVM_COMMAND_LAST;
1856
1857                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1858
1859                 memcpy(ret_buf, buf, 4 - extra);
1860         } else if (len32 > 0) {
1861                 uint8_t buf[4];
1862
1863                 /* Read the first word. */
1864                 if (cmd_flags)
1865                         cmd_flags = 0;
1866                 else
1867                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1868
1869                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1870
1871                 /* Advance to the next dword. */
1872                 offset32 += 4;
1873                 ret_buf += 4;
1874                 len32 -= 4;
1875
1876                 while (len32 > 4 && rc == 0) {
1877                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1878
1879                         /* Advance to the next dword. */
1880                         offset32 += 4;
1881                         ret_buf += 4;
1882                         len32 -= 4;
1883                 }
1884
1885                 if (rc)
1886                         goto bce_nvram_read_locked_exit;
1887
1888                 cmd_flags = BCE_NVM_COMMAND_LAST;
1889                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1890
1891                 memcpy(ret_buf, buf, 4 - extra);
1892         }
1893
1894 bce_nvram_read_locked_exit:
1895         /* Disable access to flash interface and release the lock. */
1896         bce_disable_nvram_access(sc);
1897         bce_release_nvram_lock(sc);
1898
1899         return rc;
1900 }
1901
1902
1903 /****************************************************************************/
1904 /* Verifies that NVRAM is accessible and contains valid data.               */
1905 /*                                                                          */
1906 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1907 /* correct.                                                                 */
1908 /*                                                                          */
1909 /* Returns:                                                                 */
1910 /*   0 on success, positive value on failure.                               */
1911 /****************************************************************************/
1912 static int
1913 bce_nvram_test(struct bce_softc *sc)
1914 {
1915         uint32_t buf[BCE_NVRAM_SIZE / 4];
1916         uint32_t magic, csum;
1917         uint8_t *data = (uint8_t *)buf;
1918         int rc = 0;
1919
1920         /*
1921          * Check that the device NVRAM is valid by reading
1922          * the magic value at offset 0.
1923          */
1924         rc = bce_nvram_read(sc, 0, data, 4);
1925         if (rc != 0)
1926                 return rc;
1927
1928         magic = be32toh(buf[0]);
1929         if (magic != BCE_NVRAM_MAGIC) {
1930                 if_printf(&sc->arpcom.ac_if,
1931                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1932                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1933                 return ENODEV;
1934         }
1935
1936         /*
1937          * Verify that the device NVRAM includes valid
1938          * configuration data.
1939          */
1940         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1941         if (rc != 0)
1942                 return rc;
1943
1944         csum = ether_crc32_le(data, 0x100);
1945         if (csum != BCE_CRC32_RESIDUAL) {
1946                 if_printf(&sc->arpcom.ac_if,
1947                           "Invalid Manufacturing Information NVRAM CRC! "
1948                           "Expected: 0x%08X, Found: 0x%08X\n",
1949                           BCE_CRC32_RESIDUAL, csum);
1950                 return ENODEV;
1951         }
1952
1953         csum = ether_crc32_le(data + 0x100, 0x100);
1954         if (csum != BCE_CRC32_RESIDUAL) {
1955                 if_printf(&sc->arpcom.ac_if,
1956                           "Invalid Feature Configuration Information "
1957                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1958                           BCE_CRC32_RESIDUAL, csum);
1959                 rc = ENODEV;
1960         }
1961         return rc;
1962 }
1963
1964
1965 /****************************************************************************/
1966 /* Identifies the current media type of the controller and sets the PHY     */
1967 /* address.                                                                 */
1968 /*                                                                          */
1969 /* Returns:                                                                 */
1970 /*   Nothing.                                                               */
1971 /****************************************************************************/
1972 static void
1973 bce_get_media(struct bce_softc *sc)
1974 {
1975         uint32_t val;
1976
1977         sc->bce_phy_addr = 1;
1978
1979         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1980             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1981                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1982                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1983                 uint32_t strap;
1984
1985                 /*
1986                  * The BCM5709S is software configurable
1987                  * for Copper or SerDes operation.
1988                  */
1989                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1990                         return;
1991                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1992                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1993                         return;
1994                 }
1995
1996                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1997                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1998                 } else {
1999                         strap =
2000                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
2001                 }
2002
2003                 if (pci_get_function(sc->bce_dev) == 0) {
2004                         switch (strap) {
2005                         case 0x4:
2006                         case 0x5:
2007                         case 0x6:
2008                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2009                                 break;
2010                         }
2011                 } else {
2012                         switch (strap) {
2013                         case 0x1:
2014                         case 0x2:
2015                         case 0x4:
2016                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2017                                 break;
2018                         }
2019                 }
2020         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
2021                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2022         }
2023
2024         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2025                 sc->bce_flags |= BCE_NO_WOL_FLAG;
2026                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2027                         sc->bce_phy_addr = 2;
2028                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2029                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2030                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2031                 }
2032         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2033             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2034                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2035         }
2036 }
2037
2038
2039 /****************************************************************************/
2040 /* Free any DMA memory owned by the driver.                                 */
2041 /*                                                                          */
2042 /* Scans through each data structre that requires DMA memory and frees      */
2043 /* the memory if allocated.                                                 */
2044 /*                                                                          */
2045 /* Returns:                                                                 */
2046 /*   Nothing.                                                               */
2047 /****************************************************************************/
2048 static void
2049 bce_dma_free(struct bce_softc *sc)
2050 {
2051         int i;
2052
2053         /* Destroy the status block. */
2054         if (sc->status_tag != NULL) {
2055                 if (sc->status_block != NULL) {
2056                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2057                         bus_dmamem_free(sc->status_tag, sc->status_block,
2058                                         sc->status_map);
2059                 }
2060                 bus_dma_tag_destroy(sc->status_tag);
2061         }
2062
2063         /* Destroy the statistics block. */
2064         if (sc->stats_tag != NULL) {
2065                 if (sc->stats_block != NULL) {
2066                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2067                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2068                                         sc->stats_map);
2069                 }
2070                 bus_dma_tag_destroy(sc->stats_tag);
2071         }
2072
2073         /* Destroy the CTX DMA stuffs. */
2074         if (sc->ctx_tag != NULL) {
2075                 for (i = 0; i < sc->ctx_pages; i++) {
2076                         if (sc->ctx_block[i] != NULL) {
2077                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2078                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2079                                                 sc->ctx_map[i]);
2080                         }
2081                 }
2082                 bus_dma_tag_destroy(sc->ctx_tag);
2083         }
2084
2085         /* Destroy the TX buffer descriptor DMA stuffs. */
2086         if (sc->tx_bd_chain_tag != NULL) {
2087                 for (i = 0; i < sc->tx_pages; i++) {
2088                         if (sc->tx_bd_chain[i] != NULL) {
2089                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2090                                                   sc->tx_bd_chain_map[i]);
2091                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2092                                                 sc->tx_bd_chain[i],
2093                                                 sc->tx_bd_chain_map[i]);
2094                         }
2095                 }
2096                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2097         }
2098
2099         /* Destroy the RX buffer descriptor DMA stuffs. */
2100         if (sc->rx_bd_chain_tag != NULL) {
2101                 for (i = 0; i < sc->rx_pages; i++) {
2102                         if (sc->rx_bd_chain[i] != NULL) {
2103                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2104                                                   sc->rx_bd_chain_map[i]);
2105                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2106                                                 sc->rx_bd_chain[i],
2107                                                 sc->rx_bd_chain_map[i]);
2108                         }
2109                 }
2110                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2111         }
2112
2113         /* Destroy the TX mbuf DMA stuffs. */
2114         if (sc->tx_mbuf_tag != NULL) {
2115                 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2116                         /* Must have been unloaded in bce_stop() */
2117                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2118                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2119                                            sc->tx_mbuf_map[i]);
2120                 }
2121                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2122         }
2123
2124         /* Destroy the RX mbuf DMA stuffs. */
2125         if (sc->rx_mbuf_tag != NULL) {
2126                 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2127                         /* Must have been unloaded in bce_stop() */
2128                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2129                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2130                                            sc->rx_mbuf_map[i]);
2131                 }
2132                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2133                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2134         }
2135
2136         /* Destroy the parent tag */
2137         if (sc->parent_tag != NULL)
2138                 bus_dma_tag_destroy(sc->parent_tag);
2139
2140         if (sc->tx_bd_chain_map != NULL)
2141                 kfree(sc->tx_bd_chain_map, M_DEVBUF);
2142         if (sc->tx_bd_chain != NULL)
2143                 kfree(sc->tx_bd_chain, M_DEVBUF);
2144         if (sc->tx_bd_chain_paddr != NULL)
2145                 kfree(sc->tx_bd_chain_paddr, M_DEVBUF);
2146
2147         if (sc->rx_bd_chain_map != NULL)
2148                 kfree(sc->rx_bd_chain_map, M_DEVBUF);
2149         if (sc->rx_bd_chain != NULL)
2150                 kfree(sc->rx_bd_chain, M_DEVBUF);
2151         if (sc->rx_bd_chain_paddr != NULL)
2152                 kfree(sc->rx_bd_chain_paddr, M_DEVBUF);
2153
2154         if (sc->tx_mbuf_map != NULL)
2155                 kfree(sc->tx_mbuf_map, M_DEVBUF);
2156         if (sc->tx_mbuf_ptr != NULL)
2157                 kfree(sc->tx_mbuf_ptr, M_DEVBUF);
2158
2159         if (sc->rx_mbuf_map != NULL)
2160                 kfree(sc->rx_mbuf_map, M_DEVBUF);
2161         if (sc->rx_mbuf_ptr != NULL)
2162                 kfree(sc->rx_mbuf_ptr, M_DEVBUF);
2163         if (sc->rx_mbuf_paddr != NULL)
2164                 kfree(sc->rx_mbuf_paddr, M_DEVBUF);
2165 }
2166
2167
2168 /****************************************************************************/
2169 /* Get DMA memory from the OS.                                              */
2170 /*                                                                          */
2171 /* Validates that the OS has provided DMA buffers in response to a          */
2172 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2173 /* When the callback is used the OS will return 0 for the mapping function  */
2174 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2175 /* failures back to the caller.                                             */
2176 /*                                                                          */
2177 /* Returns:                                                                 */
2178 /*   Nothing.                                                               */
2179 /****************************************************************************/
2180 static void
2181 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2182 {
2183         bus_addr_t *busaddr = arg;
2184
2185         /*
2186          * Simulate a mapping failure.
2187          * XXX not correct.
2188          */
2189         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2190                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2191                         __FILE__, __LINE__);
2192                 error = ENOMEM);
2193
2194         /* Check for an error and signal the caller that an error occurred. */
2195         if (error)
2196                 return;
2197
2198         KASSERT(nseg == 1, ("only one segment is allowed"));
2199         *busaddr = segs->ds_addr;
2200 }
2201
2202
2203 /****************************************************************************/
2204 /* Allocate any DMA memory needed by the driver.                            */
2205 /*                                                                          */
2206 /* Allocates DMA memory needed for the various global structures needed by  */
2207 /* hardware.                                                                */
2208 /*                                                                          */
2209 /* Memory alignment requirements:                                           */
2210 /* -----------------+----------+----------+----------+----------+           */
2211 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2212 /* -----------------+----------+----------+----------+----------+           */
2213 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2214 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2215 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2216 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2217 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2218 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2219 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2220 /* -----------------+----------+----------+----------+----------+           */
2221 /*                                                                          */
2222 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2223 /*                                                                          */
2224 /* Returns:                                                                 */
2225 /*   0 for success, positive value for failure.                             */
2226 /****************************************************************************/
2227 static int
2228 bce_dma_alloc(struct bce_softc *sc)
2229 {
2230         struct ifnet *ifp = &sc->arpcom.ac_if;
2231         int i, j, rc = 0, pages;
2232         bus_addr_t busaddr, max_busaddr;
2233         bus_size_t status_align, stats_align;
2234
2235         pages = device_getenv_int(sc->bce_dev, "rx_pages", bce_rx_pages);
2236         if (pages <= 0 || pages > RX_PAGES_MAX || !powerof2(pages)) {
2237                 device_printf(sc->bce_dev, "invalid # of RX pages\n");
2238                 pages = RX_PAGES_DEFAULT;
2239         }
2240         sc->rx_pages = pages;
2241
2242         pages = device_getenv_int(sc->bce_dev, "tx_pages", bce_tx_pages);
2243         if (pages <= 0 || pages > TX_PAGES_MAX || !powerof2(pages)) {
2244                 device_printf(sc->bce_dev, "invalid # of TX pages\n");
2245                 pages = TX_PAGES_DEFAULT;
2246         }
2247         sc->tx_pages = pages;
2248
2249         sc->tx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->tx_pages,
2250             M_DEVBUF, M_WAITOK | M_ZERO);
2251         sc->tx_bd_chain = kmalloc(sizeof(struct tx_bd *) * sc->tx_pages,
2252             M_DEVBUF, M_WAITOK | M_ZERO);
2253         sc->tx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->tx_pages,
2254             M_DEVBUF, M_WAITOK | M_ZERO);
2255
2256         sc->rx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->rx_pages,
2257             M_DEVBUF, M_WAITOK | M_ZERO);
2258         sc->rx_bd_chain = kmalloc(sizeof(struct rx_bd *) * sc->rx_pages,
2259             M_DEVBUF, M_WAITOK | M_ZERO);
2260         sc->rx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->rx_pages,
2261             M_DEVBUF, M_WAITOK | M_ZERO);
2262
2263         sc->tx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_TX_BD(sc),
2264             M_DEVBUF, M_WAITOK | M_ZERO);
2265         sc->tx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_TX_BD(sc),
2266             M_DEVBUF, M_WAITOK | M_ZERO);
2267
2268         sc->rx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_RX_BD(sc),
2269             M_DEVBUF, M_WAITOK | M_ZERO);
2270         sc->rx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_RX_BD(sc),
2271             M_DEVBUF, M_WAITOK | M_ZERO);
2272         sc->rx_mbuf_paddr = kmalloc(sizeof(bus_addr_t) * TOTAL_RX_BD(sc),
2273             M_DEVBUF, M_WAITOK | M_ZERO);
2274
2275         /*
2276          * The embedded PCIe to PCI-X bridge (EPB)
2277          * in the 5708 cannot address memory above
2278          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2279          */
2280         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2281                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2282         else
2283                 max_busaddr = BUS_SPACE_MAXADDR;
2284
2285         /*
2286          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2287          */
2288         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2289             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2290                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2291                 if (sc->ctx_pages == 0)
2292                         sc->ctx_pages = 1;
2293                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2294                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2295                             sc->ctx_pages);
2296                         return ENOMEM;
2297                 }
2298                 status_align = 16;
2299                 stats_align = 16;
2300         } else {
2301                 status_align = 8;
2302                 stats_align = 8;
2303         }
2304
2305         /*
2306          * Allocate the parent bus DMA tag appropriate for PCI.
2307          */
2308         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2309                                 max_busaddr, BUS_SPACE_MAXADDR,
2310                                 NULL, NULL,
2311                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2312                                 BUS_SPACE_MAXSIZE_32BIT,
2313                                 0, &sc->parent_tag);
2314         if (rc != 0) {
2315                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2316                 return rc;
2317         }
2318
2319         /*
2320          * Allocate status block.
2321          */
2322         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2323                                 status_align, BCE_STATUS_BLK_SZ,
2324                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2325                                 &sc->status_tag, &sc->status_map,
2326                                 &sc->status_block_paddr);
2327         if (sc->status_block == NULL) {
2328                 if_printf(ifp, "Could not allocate status block!\n");
2329                 return ENOMEM;
2330         }
2331
2332         /*
2333          * Allocate statistics block.
2334          */
2335         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2336                                 stats_align, BCE_STATS_BLK_SZ,
2337                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2338                                 &sc->stats_tag, &sc->stats_map,
2339                                 &sc->stats_block_paddr);
2340         if (sc->stats_block == NULL) {
2341                 if_printf(ifp, "Could not allocate statistics block!\n");
2342                 return ENOMEM;
2343         }
2344
2345         /*
2346          * Allocate context block, if needed
2347          */
2348         if (sc->ctx_pages != 0) {
2349                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2350                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2351                                         NULL, NULL,
2352                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2353                                         0, &sc->ctx_tag);
2354                 if (rc != 0) {
2355                         if_printf(ifp, "Could not allocate "
2356                                   "context block DMA tag!\n");
2357                         return rc;
2358                 }
2359
2360                 for (i = 0; i < sc->ctx_pages; i++) {
2361                         rc = bus_dmamem_alloc(sc->ctx_tag,
2362                                               (void **)&sc->ctx_block[i],
2363                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2364                                               BUS_DMA_COHERENT,
2365                                               &sc->ctx_map[i]);
2366                         if (rc != 0) {
2367                                 if_printf(ifp, "Could not allocate %dth context "
2368                                           "DMA memory!\n", i);
2369                                 return rc;
2370                         }
2371
2372                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2373                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2374                                              bce_dma_map_addr, &busaddr,
2375                                              BUS_DMA_WAITOK);
2376                         if (rc != 0) {
2377                                 if (rc == EINPROGRESS) {
2378                                         panic("%s coherent memory loading "
2379                                               "is still in progress!", ifp->if_xname);
2380                                 }
2381                                 if_printf(ifp, "Could not map %dth context "
2382                                           "DMA memory!\n", i);
2383                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2384                                                 sc->ctx_map[i]);
2385                                 sc->ctx_block[i] = NULL;
2386                                 return rc;
2387                         }
2388                         sc->ctx_paddr[i] = busaddr;
2389                 }
2390         }
2391
2392         /*
2393          * Create a DMA tag for the TX buffer descriptor chain,
2394          * allocate and clear the  memory, and fetch the
2395          * physical address of the block.
2396          */
2397         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2398                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2399                                 NULL, NULL,
2400                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2401                                 0, &sc->tx_bd_chain_tag);
2402         if (rc != 0) {
2403                 if_printf(ifp, "Could not allocate "
2404                           "TX descriptor chain DMA tag!\n");
2405                 return rc;
2406         }
2407
2408         for (i = 0; i < sc->tx_pages; i++) {
2409                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2410                                       (void **)&sc->tx_bd_chain[i],
2411                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2412                                       BUS_DMA_COHERENT,
2413                                       &sc->tx_bd_chain_map[i]);
2414                 if (rc != 0) {
2415                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2416                                   "chain DMA memory!\n", i);
2417                         return rc;
2418                 }
2419
2420                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2421                                      sc->tx_bd_chain_map[i],
2422                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2423                                      bce_dma_map_addr, &busaddr,
2424                                      BUS_DMA_WAITOK);
2425                 if (rc != 0) {
2426                         if (rc == EINPROGRESS) {
2427                                 panic("%s coherent memory loading "
2428                                       "is still in progress!", ifp->if_xname);
2429                         }
2430                         if_printf(ifp, "Could not map %dth TX descriptor "
2431                                   "chain DMA memory!\n", i);
2432                         bus_dmamem_free(sc->tx_bd_chain_tag,
2433                                         sc->tx_bd_chain[i],
2434                                         sc->tx_bd_chain_map[i]);
2435                         sc->tx_bd_chain[i] = NULL;
2436                         return rc;
2437                 }
2438
2439                 sc->tx_bd_chain_paddr[i] = busaddr;
2440                 /* DRC - Fix for 64 bit systems. */
2441                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2442                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2443         }
2444
2445         /* Create a DMA tag for TX mbufs. */
2446         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2447                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2448                                 NULL, NULL,
2449                                 IP_MAXPACKET + sizeof(struct ether_vlan_header),
2450                                 BCE_MAX_SEGMENTS, PAGE_SIZE,
2451                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2452                                 BUS_DMA_ONEBPAGE,
2453                                 &sc->tx_mbuf_tag);
2454         if (rc != 0) {
2455                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2456                 return rc;
2457         }
2458
2459         /* Create DMA maps for the TX mbufs clusters. */
2460         for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2461                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2462                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2463                                        &sc->tx_mbuf_map[i]);
2464                 if (rc != 0) {
2465                         for (j = 0; j < i; ++j) {
2466                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2467                                                    sc->tx_mbuf_map[i]);
2468                         }
2469                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2470                         sc->tx_mbuf_tag = NULL;
2471
2472                         if_printf(ifp, "Unable to create "
2473                                   "%dth TX mbuf DMA map!\n", i);
2474                         return rc;
2475                 }
2476         }
2477
2478         /*
2479          * Create a DMA tag for the RX buffer descriptor chain,
2480          * allocate and clear the  memory, and fetch the physical
2481          * address of the blocks.
2482          */
2483         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2484                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2485                                 NULL, NULL,
2486                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2487                                 0, &sc->rx_bd_chain_tag);
2488         if (rc != 0) {
2489                 if_printf(ifp, "Could not allocate "
2490                           "RX descriptor chain DMA tag!\n");
2491                 return rc;
2492         }
2493
2494         for (i = 0; i < sc->rx_pages; i++) {
2495                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2496                                       (void **)&sc->rx_bd_chain[i],
2497                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2498                                       BUS_DMA_COHERENT,
2499                                       &sc->rx_bd_chain_map[i]);
2500                 if (rc != 0) {
2501                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2502                                   "chain DMA memory!\n", i);
2503                         return rc;
2504                 }
2505
2506                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2507                                      sc->rx_bd_chain_map[i],
2508                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2509                                      bce_dma_map_addr, &busaddr,
2510                                      BUS_DMA_WAITOK);
2511                 if (rc != 0) {
2512                         if (rc == EINPROGRESS) {
2513                                 panic("%s coherent memory loading "
2514                                       "is still in progress!", ifp->if_xname);
2515                         }
2516                         if_printf(ifp, "Could not map %dth RX descriptor "
2517                                   "chain DMA memory!\n", i);
2518                         bus_dmamem_free(sc->rx_bd_chain_tag,
2519                                         sc->rx_bd_chain[i],
2520                                         sc->rx_bd_chain_map[i]);
2521                         sc->rx_bd_chain[i] = NULL;
2522                         return rc;
2523                 }
2524
2525                 sc->rx_bd_chain_paddr[i] = busaddr;
2526                 /* DRC - Fix for 64 bit systems. */
2527                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2528                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2529         }
2530
2531         /* Create a DMA tag for RX mbufs. */
2532         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2533                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2534                                 NULL, NULL,
2535                                 MCLBYTES, 1, MCLBYTES,
2536                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2537                                 BUS_DMA_WAITOK,
2538                                 &sc->rx_mbuf_tag);
2539         if (rc != 0) {
2540                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2541                 return rc;
2542         }
2543
2544         /* Create tmp DMA map for RX mbuf clusters. */
2545         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2546                                &sc->rx_mbuf_tmpmap);
2547         if (rc != 0) {
2548                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2549                 sc->rx_mbuf_tag = NULL;
2550
2551                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2552                 return rc;
2553         }
2554
2555         /* Create DMA maps for the RX mbuf clusters. */
2556         for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2557                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2558                                        &sc->rx_mbuf_map[i]);
2559                 if (rc != 0) {
2560                         for (j = 0; j < i; ++j) {
2561                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2562                                                    sc->rx_mbuf_map[j]);
2563                         }
2564                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2565                         sc->rx_mbuf_tag = NULL;
2566
2567                         if_printf(ifp, "Unable to create "
2568                                   "%dth RX mbuf DMA map!\n", i);
2569                         return rc;
2570                 }
2571         }
2572         return 0;
2573 }
2574
2575
2576 /****************************************************************************/
2577 /* Firmware synchronization.                                                */
2578 /*                                                                          */
2579 /* Before performing certain events such as a chip reset, synchronize with  */
2580 /* the firmware first.                                                      */
2581 /*                                                                          */
2582 /* Returns:                                                                 */
2583 /*   0 for success, positive value for failure.                             */
2584 /****************************************************************************/
2585 static int
2586 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2587 {
2588         int i, rc = 0;
2589         uint32_t val;
2590
2591         /* Don't waste any time if we've timed out before. */
2592         if (sc->bce_fw_timed_out)
2593                 return EBUSY;
2594
2595         /* Increment the message sequence number. */
2596         sc->bce_fw_wr_seq++;
2597         msg_data |= sc->bce_fw_wr_seq;
2598
2599         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2600
2601         /* Send the message to the bootcode driver mailbox. */
2602         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2603
2604         /* Wait for the bootcode to acknowledge the message. */
2605         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2606                 /* Check for a response in the bootcode firmware mailbox. */
2607                 val = bce_shmem_rd(sc, BCE_FW_MB);
2608                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2609                         break;
2610                 DELAY(1000);
2611         }
2612
2613         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2614         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2615             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2616                 if_printf(&sc->arpcom.ac_if,
2617                           "Firmware synchronization timeout! "
2618                           "msg_data = 0x%08X\n", msg_data);
2619
2620                 msg_data &= ~BCE_DRV_MSG_CODE;
2621                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2622
2623                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2624
2625                 sc->bce_fw_timed_out = 1;
2626                 rc = EBUSY;
2627         }
2628         return rc;
2629 }
2630
2631
2632 /****************************************************************************/
2633 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2634 /*                                                                          */
2635 /* Returns:                                                                 */
2636 /*   Nothing.                                                               */
2637 /****************************************************************************/
2638 static void
2639 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2640                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2641 {
2642         int i;
2643         uint32_t val;
2644
2645         for (i = 0; i < rv2p_code_len; i += 8) {
2646                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2647                 rv2p_code++;
2648                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2649                 rv2p_code++;
2650
2651                 if (rv2p_proc == RV2P_PROC1) {
2652                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2653                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2654                 } else {
2655                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2656                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2657                 }
2658         }
2659
2660         /* Reset the processor, un-stall is done later. */
2661         if (rv2p_proc == RV2P_PROC1)
2662                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2663         else
2664                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2665 }
2666
2667
2668 /****************************************************************************/
2669 /* Load RISC processor firmware.                                            */
2670 /*                                                                          */
2671 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2672 /* associated with a particular processor.                                  */
2673 /*                                                                          */
2674 /* Returns:                                                                 */
2675 /*   Nothing.                                                               */
2676 /****************************************************************************/
2677 static void
2678 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2679                 struct fw_info *fw)
2680 {
2681         uint32_t offset;
2682         int j;
2683
2684         bce_halt_cpu(sc, cpu_reg);
2685
2686         /* Load the Text area. */
2687         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2688         if (fw->text) {
2689                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2690                         REG_WR_IND(sc, offset, fw->text[j]);
2691         }
2692
2693         /* Load the Data area. */
2694         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2695         if (fw->data) {
2696                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2697                         REG_WR_IND(sc, offset, fw->data[j]);
2698         }
2699
2700         /* Load the SBSS area. */
2701         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2702         if (fw->sbss) {
2703                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2704                         REG_WR_IND(sc, offset, fw->sbss[j]);
2705         }
2706
2707         /* Load the BSS area. */
2708         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2709         if (fw->bss) {
2710                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2711                         REG_WR_IND(sc, offset, fw->bss[j]);
2712         }
2713
2714         /* Load the Read-Only area. */
2715         offset = cpu_reg->spad_base +
2716                 (fw->rodata_addr - cpu_reg->mips_view_base);
2717         if (fw->rodata) {
2718                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2719                         REG_WR_IND(sc, offset, fw->rodata[j]);
2720         }
2721
2722         /* Clear the pre-fetch instruction and set the FW start address. */
2723         REG_WR_IND(sc, cpu_reg->inst, 0);
2724         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2725 }
2726
2727
2728 /****************************************************************************/
2729 /* Starts the RISC processor.                                               */
2730 /*                                                                          */
2731 /* Assumes the CPU starting address has already been set.                   */
2732 /*                                                                          */
2733 /* Returns:                                                                 */
2734 /*   Nothing.                                                               */
2735 /****************************************************************************/
2736 static void
2737 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2738 {
2739         uint32_t val;
2740
2741         /* Start the CPU. */
2742         val = REG_RD_IND(sc, cpu_reg->mode);
2743         val &= ~cpu_reg->mode_value_halt;
2744         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2745         REG_WR_IND(sc, cpu_reg->mode, val);
2746 }
2747
2748
2749 /****************************************************************************/
2750 /* Halts the RISC processor.                                                */
2751 /*                                                                          */
2752 /* Returns:                                                                 */
2753 /*   Nothing.                                                               */
2754 /****************************************************************************/
2755 static void
2756 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2757 {
2758         uint32_t val;
2759
2760         /* Halt the CPU. */
2761         val = REG_RD_IND(sc, cpu_reg->mode);
2762         val |= cpu_reg->mode_value_halt;
2763         REG_WR_IND(sc, cpu_reg->mode, val);
2764         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2765 }
2766
2767
2768 /****************************************************************************/
2769 /* Start the RX CPU.                                                        */
2770 /*                                                                          */
2771 /* Returns:                                                                 */
2772 /*   Nothing.                                                               */
2773 /****************************************************************************/
2774 static void
2775 bce_start_rxp_cpu(struct bce_softc *sc)
2776 {
2777         struct cpu_reg cpu_reg;
2778
2779         cpu_reg.mode = BCE_RXP_CPU_MODE;
2780         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2781         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2782         cpu_reg.state = BCE_RXP_CPU_STATE;
2783         cpu_reg.state_value_clear = 0xffffff;
2784         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2785         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2786         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2787         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2788         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2789         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2790         cpu_reg.mips_view_base = 0x8000000;
2791
2792         bce_start_cpu(sc, &cpu_reg);
2793 }
2794
2795
2796 /****************************************************************************/
2797 /* Initialize the RX CPU.                                                   */
2798 /*                                                                          */
2799 /* Returns:                                                                 */
2800 /*   Nothing.                                                               */
2801 /****************************************************************************/
2802 static void
2803 bce_init_rxp_cpu(struct bce_softc *sc)
2804 {
2805         struct cpu_reg cpu_reg;
2806         struct fw_info fw;
2807
2808         cpu_reg.mode = BCE_RXP_CPU_MODE;
2809         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2810         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2811         cpu_reg.state = BCE_RXP_CPU_STATE;
2812         cpu_reg.state_value_clear = 0xffffff;
2813         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2814         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2815         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2816         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2817         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2818         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2819         cpu_reg.mips_view_base = 0x8000000;
2820
2821         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2822             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2823                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2824                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2825                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2826                 fw.start_addr = bce_RXP_b09FwStartAddr;
2827
2828                 fw.text_addr = bce_RXP_b09FwTextAddr;
2829                 fw.text_len = bce_RXP_b09FwTextLen;
2830                 fw.text_index = 0;
2831                 fw.text = bce_RXP_b09FwText;
2832
2833                 fw.data_addr = bce_RXP_b09FwDataAddr;
2834                 fw.data_len = bce_RXP_b09FwDataLen;
2835                 fw.data_index = 0;
2836                 fw.data = bce_RXP_b09FwData;
2837
2838                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2839                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2840                 fw.sbss_index = 0;
2841                 fw.sbss = bce_RXP_b09FwSbss;
2842
2843                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2844                 fw.bss_len = bce_RXP_b09FwBssLen;
2845                 fw.bss_index = 0;
2846                 fw.bss = bce_RXP_b09FwBss;
2847
2848                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2849                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2850                 fw.rodata_index = 0;
2851                 fw.rodata = bce_RXP_b09FwRodata;
2852         } else {
2853                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2854                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2855                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2856                 fw.start_addr = bce_RXP_b06FwStartAddr;
2857
2858                 fw.text_addr = bce_RXP_b06FwTextAddr;
2859                 fw.text_len = bce_RXP_b06FwTextLen;
2860                 fw.text_index = 0;
2861                 fw.text = bce_RXP_b06FwText;
2862
2863                 fw.data_addr = bce_RXP_b06FwDataAddr;
2864                 fw.data_len = bce_RXP_b06FwDataLen;
2865                 fw.data_index = 0;
2866                 fw.data = bce_RXP_b06FwData;
2867
2868                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2869                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2870                 fw.sbss_index = 0;
2871                 fw.sbss = bce_RXP_b06FwSbss;
2872
2873                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2874                 fw.bss_len = bce_RXP_b06FwBssLen;
2875                 fw.bss_index = 0;
2876                 fw.bss = bce_RXP_b06FwBss;
2877
2878                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2879                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2880                 fw.rodata_index = 0;
2881                 fw.rodata = bce_RXP_b06FwRodata;
2882         }
2883
2884         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2885         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2886         /* Delay RXP start until initialization is complete. */
2887 }
2888
2889
2890 /****************************************************************************/
2891 /* Initialize the TX CPU.                                                   */
2892 /*                                                                          */
2893 /* Returns:                                                                 */
2894 /*   Nothing.                                                               */
2895 /****************************************************************************/
2896 static void
2897 bce_init_txp_cpu(struct bce_softc *sc)
2898 {
2899         struct cpu_reg cpu_reg;
2900         struct fw_info fw;
2901
2902         cpu_reg.mode = BCE_TXP_CPU_MODE;
2903         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2904         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2905         cpu_reg.state = BCE_TXP_CPU_STATE;
2906         cpu_reg.state_value_clear = 0xffffff;
2907         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2908         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2909         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2910         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2911         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2912         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2913         cpu_reg.mips_view_base = 0x8000000;
2914
2915         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2916             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2917                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2918                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2919                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2920                 fw.start_addr = bce_TXP_b09FwStartAddr;
2921
2922                 fw.text_addr = bce_TXP_b09FwTextAddr;
2923                 fw.text_len = bce_TXP_b09FwTextLen;
2924                 fw.text_index = 0;
2925                 fw.text = bce_TXP_b09FwText;
2926
2927                 fw.data_addr = bce_TXP_b09FwDataAddr;
2928                 fw.data_len = bce_TXP_b09FwDataLen;
2929                 fw.data_index = 0;
2930                 fw.data = bce_TXP_b09FwData;
2931
2932                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2933                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2934                 fw.sbss_index = 0;
2935                 fw.sbss = bce_TXP_b09FwSbss;
2936
2937                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2938                 fw.bss_len = bce_TXP_b09FwBssLen;
2939                 fw.bss_index = 0;
2940                 fw.bss = bce_TXP_b09FwBss;
2941
2942                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2943                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2944                 fw.rodata_index = 0;
2945                 fw.rodata = bce_TXP_b09FwRodata;
2946         } else {
2947                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2948                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2949                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2950                 fw.start_addr = bce_TXP_b06FwStartAddr;
2951
2952                 fw.text_addr = bce_TXP_b06FwTextAddr;
2953                 fw.text_len = bce_TXP_b06FwTextLen;
2954                 fw.text_index = 0;
2955                 fw.text = bce_TXP_b06FwText;
2956
2957                 fw.data_addr = bce_TXP_b06FwDataAddr;
2958                 fw.data_len = bce_TXP_b06FwDataLen;
2959                 fw.data_index = 0;
2960                 fw.data = bce_TXP_b06FwData;
2961
2962                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2963                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2964                 fw.sbss_index = 0;
2965                 fw.sbss = bce_TXP_b06FwSbss;
2966
2967                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2968                 fw.bss_len = bce_TXP_b06FwBssLen;
2969                 fw.bss_index = 0;
2970                 fw.bss = bce_TXP_b06FwBss;
2971
2972                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2973                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2974                 fw.rodata_index = 0;
2975                 fw.rodata = bce_TXP_b06FwRodata;
2976         }
2977
2978         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2979         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2980         bce_start_cpu(sc, &cpu_reg);
2981 }
2982
2983
2984 /****************************************************************************/
2985 /* Initialize the TPAT CPU.                                                 */
2986 /*                                                                          */
2987 /* Returns:                                                                 */
2988 /*   Nothing.                                                               */
2989 /****************************************************************************/
2990 static void
2991 bce_init_tpat_cpu(struct bce_softc *sc)
2992 {
2993         struct cpu_reg cpu_reg;
2994         struct fw_info fw;
2995
2996         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2997         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2998         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2999         cpu_reg.state = BCE_TPAT_CPU_STATE;
3000         cpu_reg.state_value_clear = 0xffffff;
3001         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
3002         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
3003         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
3004         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
3005         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
3006         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
3007         cpu_reg.mips_view_base = 0x8000000;
3008
3009         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3010             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3011                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
3012                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
3013                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
3014                 fw.start_addr = bce_TPAT_b09FwStartAddr;
3015
3016                 fw.text_addr = bce_TPAT_b09FwTextAddr;
3017                 fw.text_len = bce_TPAT_b09FwTextLen;
3018                 fw.text_index = 0;
3019                 fw.text = bce_TPAT_b09FwText;
3020
3021                 fw.data_addr = bce_TPAT_b09FwDataAddr;
3022                 fw.data_len = bce_TPAT_b09FwDataLen;
3023                 fw.data_index = 0;
3024                 fw.data = bce_TPAT_b09FwData;
3025
3026                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3027                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
3028                 fw.sbss_index = 0;
3029                 fw.sbss = bce_TPAT_b09FwSbss;
3030
3031                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
3032                 fw.bss_len = bce_TPAT_b09FwBssLen;
3033                 fw.bss_index = 0;
3034                 fw.bss = bce_TPAT_b09FwBss;
3035
3036                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3037                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
3038                 fw.rodata_index = 0;
3039                 fw.rodata = bce_TPAT_b09FwRodata;
3040         } else {
3041                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3042                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3043                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3044                 fw.start_addr = bce_TPAT_b06FwStartAddr;
3045
3046                 fw.text_addr = bce_TPAT_b06FwTextAddr;
3047                 fw.text_len = bce_TPAT_b06FwTextLen;
3048                 fw.text_index = 0;
3049                 fw.text = bce_TPAT_b06FwText;
3050
3051                 fw.data_addr = bce_TPAT_b06FwDataAddr;
3052                 fw.data_len = bce_TPAT_b06FwDataLen;
3053                 fw.data_index = 0;
3054                 fw.data = bce_TPAT_b06FwData;
3055
3056                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3057                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3058                 fw.sbss_index = 0;
3059                 fw.sbss = bce_TPAT_b06FwSbss;
3060
3061                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3062                 fw.bss_len = bce_TPAT_b06FwBssLen;
3063                 fw.bss_index = 0;
3064                 fw.bss = bce_TPAT_b06FwBss;
3065
3066                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3067                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3068                 fw.rodata_index = 0;
3069                 fw.rodata = bce_TPAT_b06FwRodata;
3070         }
3071
3072         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3073         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3074         bce_start_cpu(sc, &cpu_reg);
3075 }
3076
3077
3078 /****************************************************************************/
3079 /* Initialize the CP CPU.                                                   */
3080 /*                                                                          */
3081 /* Returns:                                                                 */
3082 /*   Nothing.                                                               */
3083 /****************************************************************************/
3084 static void
3085 bce_init_cp_cpu(struct bce_softc *sc)
3086 {
3087         struct cpu_reg cpu_reg;
3088         struct fw_info fw;
3089
3090         cpu_reg.mode = BCE_CP_CPU_MODE;
3091         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3092         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3093         cpu_reg.state = BCE_CP_CPU_STATE;
3094         cpu_reg.state_value_clear = 0xffffff;
3095         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3096         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3097         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3098         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3099         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3100         cpu_reg.spad_base = BCE_CP_SCRATCH;
3101         cpu_reg.mips_view_base = 0x8000000;
3102
3103         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3104             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3105                 fw.ver_major = bce_CP_b09FwReleaseMajor;
3106                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3107                 fw.ver_fix = bce_CP_b09FwReleaseFix;
3108                 fw.start_addr = bce_CP_b09FwStartAddr;
3109
3110                 fw.text_addr = bce_CP_b09FwTextAddr;
3111                 fw.text_len = bce_CP_b09FwTextLen;
3112                 fw.text_index = 0;
3113                 fw.text = bce_CP_b09FwText;
3114
3115                 fw.data_addr = bce_CP_b09FwDataAddr;
3116                 fw.data_len = bce_CP_b09FwDataLen;
3117                 fw.data_index = 0;
3118                 fw.data = bce_CP_b09FwData;
3119
3120                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3121                 fw.sbss_len = bce_CP_b09FwSbssLen;
3122                 fw.sbss_index = 0;
3123                 fw.sbss = bce_CP_b09FwSbss;
3124
3125                 fw.bss_addr = bce_CP_b09FwBssAddr;
3126                 fw.bss_len = bce_CP_b09FwBssLen;
3127                 fw.bss_index = 0;
3128                 fw.bss = bce_CP_b09FwBss;
3129
3130                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3131                 fw.rodata_len = bce_CP_b09FwRodataLen;
3132                 fw.rodata_index = 0;
3133                 fw.rodata = bce_CP_b09FwRodata;
3134         } else {
3135                 fw.ver_major = bce_CP_b06FwReleaseMajor;
3136                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3137                 fw.ver_fix = bce_CP_b06FwReleaseFix;
3138                 fw.start_addr = bce_CP_b06FwStartAddr;
3139
3140                 fw.text_addr = bce_CP_b06FwTextAddr;
3141                 fw.text_len = bce_CP_b06FwTextLen;
3142                 fw.text_index = 0;
3143                 fw.text = bce_CP_b06FwText;
3144
3145                 fw.data_addr = bce_CP_b06FwDataAddr;
3146                 fw.data_len = bce_CP_b06FwDataLen;
3147                 fw.data_index = 0;
3148                 fw.data = bce_CP_b06FwData;
3149
3150                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3151                 fw.sbss_len = bce_CP_b06FwSbssLen;
3152                 fw.sbss_index = 0;
3153                 fw.sbss = bce_CP_b06FwSbss;
3154
3155                 fw.bss_addr = bce_CP_b06FwBssAddr;
3156                 fw.bss_len = bce_CP_b06FwBssLen;
3157                 fw.bss_index = 0;
3158                 fw.bss = bce_CP_b06FwBss;
3159
3160                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3161                 fw.rodata_len = bce_CP_b06FwRodataLen;
3162                 fw.rodata_index = 0;
3163                 fw.rodata = bce_CP_b06FwRodata;
3164         }
3165
3166         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3167         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3168         bce_start_cpu(sc, &cpu_reg);
3169 }
3170
3171
3172 /****************************************************************************/
3173 /* Initialize the COM CPU.                                                 */
3174 /*                                                                          */
3175 /* Returns:                                                                 */
3176 /*   Nothing.                                                               */
3177 /****************************************************************************/
3178 static void
3179 bce_init_com_cpu(struct bce_softc *sc)
3180 {
3181         struct cpu_reg cpu_reg;
3182         struct fw_info fw;
3183
3184         cpu_reg.mode = BCE_COM_CPU_MODE;
3185         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3186         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3187         cpu_reg.state = BCE_COM_CPU_STATE;
3188         cpu_reg.state_value_clear = 0xffffff;
3189         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3190         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3191         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3192         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3193         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3194         cpu_reg.spad_base = BCE_COM_SCRATCH;
3195         cpu_reg.mips_view_base = 0x8000000;
3196
3197         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3198             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3199                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3200                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3201                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3202                 fw.start_addr = bce_COM_b09FwStartAddr;
3203
3204                 fw.text_addr = bce_COM_b09FwTextAddr;
3205                 fw.text_len = bce_COM_b09FwTextLen;
3206                 fw.text_index = 0;
3207                 fw.text = bce_COM_b09FwText;
3208
3209                 fw.data_addr = bce_COM_b09FwDataAddr;
3210                 fw.data_len = bce_COM_b09FwDataLen;
3211                 fw.data_index = 0;
3212                 fw.data = bce_COM_b09FwData;
3213
3214                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3215                 fw.sbss_len = bce_COM_b09FwSbssLen;
3216                 fw.sbss_index = 0;
3217                 fw.sbss = bce_COM_b09FwSbss;
3218
3219                 fw.bss_addr = bce_COM_b09FwBssAddr;
3220                 fw.bss_len = bce_COM_b09FwBssLen;
3221                 fw.bss_index = 0;
3222                 fw.bss = bce_COM_b09FwBss;
3223
3224                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3225                 fw.rodata_len = bce_COM_b09FwRodataLen;
3226                 fw.rodata_index = 0;
3227                 fw.rodata = bce_COM_b09FwRodata;
3228         } else {
3229                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3230                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3231                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3232                 fw.start_addr = bce_COM_b06FwStartAddr;
3233
3234                 fw.text_addr = bce_COM_b06FwTextAddr;
3235                 fw.text_len = bce_COM_b06FwTextLen;
3236                 fw.text_index = 0;
3237                 fw.text = bce_COM_b06FwText;
3238
3239                 fw.data_addr = bce_COM_b06FwDataAddr;
3240                 fw.data_len = bce_COM_b06FwDataLen;
3241                 fw.data_index = 0;
3242                 fw.data = bce_COM_b06FwData;
3243
3244                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3245                 fw.sbss_len = bce_COM_b06FwSbssLen;
3246                 fw.sbss_index = 0;
3247                 fw.sbss = bce_COM_b06FwSbss;
3248
3249                 fw.bss_addr = bce_COM_b06FwBssAddr;
3250                 fw.bss_len = bce_COM_b06FwBssLen;
3251                 fw.bss_index = 0;
3252                 fw.bss = bce_COM_b06FwBss;
3253
3254                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3255                 fw.rodata_len = bce_COM_b06FwRodataLen;
3256                 fw.rodata_index = 0;
3257                 fw.rodata = bce_COM_b06FwRodata;
3258         }
3259
3260         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3261         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3262         bce_start_cpu(sc, &cpu_reg);
3263 }
3264
3265
3266 /****************************************************************************/
3267 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3268 /*                                                                          */
3269 /* Loads the firmware for each CPU and starts the CPU.                      */
3270 /*                                                                          */
3271 /* Returns:                                                                 */
3272 /*   Nothing.                                                               */
3273 /****************************************************************************/
3274 static void
3275 bce_init_cpus(struct bce_softc *sc)
3276 {
3277         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3278             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3279                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3280                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3281                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3282                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3283                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3284                 } else {
3285                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3286                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3287                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3288                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3289                 }
3290         } else {
3291                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3292                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3293                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3294                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3295         }
3296
3297         bce_init_rxp_cpu(sc);
3298         bce_init_txp_cpu(sc);
3299         bce_init_tpat_cpu(sc);
3300         bce_init_com_cpu(sc);
3301         bce_init_cp_cpu(sc);
3302 }
3303
3304
3305 /****************************************************************************/
3306 /* Initialize context memory.                                               */
3307 /*                                                                          */
3308 /* Clears the memory associated with each Context ID (CID).                 */
3309 /*                                                                          */
3310 /* Returns:                                                                 */
3311 /*   Nothing.                                                               */
3312 /****************************************************************************/
3313 static int
3314 bce_init_ctx(struct bce_softc *sc)
3315 {
3316         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3317             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3318                 /* DRC: Replace this constant value with a #define. */
3319                 int i, retry_cnt = 10;
3320                 uint32_t val;
3321
3322                 /*
3323                  * BCM5709 context memory may be cached
3324                  * in host memory so prepare the host memory
3325                  * for access.
3326                  */
3327                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3328                     (1 << 12);
3329                 val |= (BCM_PAGE_BITS - 8) << 16;
3330                 REG_WR(sc, BCE_CTX_COMMAND, val);
3331
3332                 /* Wait for mem init command to complete. */
3333                 for (i = 0; i < retry_cnt; i++) {
3334                         val = REG_RD(sc, BCE_CTX_COMMAND);
3335                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3336                                 break;
3337                         DELAY(2);
3338                 }
3339                 if (i == retry_cnt) {
3340                         device_printf(sc->bce_dev,
3341                             "Context memory initialization failed!\n");
3342                         return ETIMEDOUT;
3343                 }
3344
3345                 for (i = 0; i < sc->ctx_pages; i++) {
3346                         int j;
3347
3348                         /*
3349                          * Set the physical address of the context
3350                          * memory cache.
3351                          */
3352                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3353                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3354                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3355                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3356                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3357                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3358                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3359
3360                         /*
3361                          * Verify that the context memory write was successful.
3362                          */
3363                         for (j = 0; j < retry_cnt; j++) {
3364                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3365                                 if ((val &
3366                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3367                                         break;
3368                                 DELAY(5);
3369                         }
3370                         if (j == retry_cnt) {
3371                                 device_printf(sc->bce_dev,
3372                                     "Failed to initialize context page!\n");
3373                                 return ETIMEDOUT;
3374                         }
3375                 }
3376         } else {
3377                 uint32_t vcid_addr, offset;
3378
3379                 /*
3380                  * For the 5706/5708, context memory is local to
3381                  * the controller, so initialize the controller
3382                  * context memory.
3383                  */
3384
3385                 vcid_addr = GET_CID_ADDR(96);
3386                 while (vcid_addr) {
3387                         vcid_addr -= PHY_CTX_SIZE;
3388
3389                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3390                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3391
3392                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3393                                 CTX_WR(sc, 0x00, offset, 0);
3394
3395                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3396                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3397                 }
3398         }
3399         return 0;
3400 }
3401
3402
3403 /****************************************************************************/
3404 /* Fetch the permanent MAC address of the controller.                       */
3405 /*                                                                          */
3406 /* Returns:                                                                 */
3407 /*   Nothing.                                                               */
3408 /****************************************************************************/
3409 static void
3410 bce_get_mac_addr(struct bce_softc *sc)
3411 {
3412         uint32_t mac_lo = 0, mac_hi = 0;
3413 #ifdef BCE_DEBUG
3414         char ethstr[ETHER_ADDRSTRLEN + 1];
3415 #endif
3416         /*
3417          * The NetXtreme II bootcode populates various NIC
3418          * power-on and runtime configuration items in a
3419          * shared memory area.  The factory configured MAC
3420          * address is available from both NVRAM and the
3421          * shared memory area so we'll read the value from
3422          * shared memory for speed.
3423          */
3424
3425         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3426         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3427
3428         if (mac_lo == 0 && mac_hi == 0) {
3429                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3430         } else {
3431                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3432                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3433                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3434                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3435                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3436                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3437         }
3438
3439         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %s\n",
3440             kether_ntoa(sc->eaddr, ethstr));
3441 }
3442
3443
3444 /****************************************************************************/
3445 /* Program the MAC address.                                                 */
3446 /*                                                                          */
3447 /* Returns:                                                                 */
3448 /*   Nothing.                                                               */
3449 /****************************************************************************/
3450 static void
3451 bce_set_mac_addr(struct bce_softc *sc)
3452 {
3453         const uint8_t *mac_addr = sc->eaddr;
3454 #ifdef BCE_DEBUG
3455         char ethstr[ETHER_ADDRSTRLEN + 1];
3456 #endif
3457         uint32_t val;
3458
3459         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %s\n",
3460             kether_ntoa(sc->eaddr, ethstr));
3461
3462         val = (mac_addr[0] << 8) | mac_addr[1];
3463         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3464
3465         val = (mac_addr[2] << 24) |
3466               (mac_addr[3] << 16) |
3467               (mac_addr[4] << 8) |
3468               mac_addr[5];
3469         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3470 }
3471
3472
3473 /****************************************************************************/
3474 /* Stop the controller.                                                     */
3475 /*                                                                          */
3476 /* Returns:                                                                 */
3477 /*   Nothing.                                                               */
3478 /****************************************************************************/
3479 static void
3480 bce_stop(struct bce_softc *sc)
3481 {
3482         struct ifnet *ifp = &sc->arpcom.ac_if;
3483
3484         ASSERT_SERIALIZED(ifp->if_serializer);
3485
3486         callout_stop(&sc->bce_tick_callout);
3487
3488         /* Disable the transmit/receive blocks. */
3489         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3490         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3491         DELAY(20);
3492
3493         bce_disable_intr(sc);
3494
3495         /* Free the RX lists. */
3496         bce_free_rx_chain(sc);
3497
3498         /* Free TX buffers. */
3499         bce_free_tx_chain(sc);
3500
3501         sc->bce_link = 0;
3502         sc->bce_coalchg_mask = 0;
3503
3504         ifp->if_flags &= ~IFF_RUNNING;
3505         ifq_clr_oactive(&ifp->if_snd);
3506         ifp->if_timer = 0;
3507 }
3508
3509
3510 static int
3511 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3512 {
3513         uint32_t val;
3514         int i, rc = 0;
3515
3516         /* Wait for pending PCI transactions to complete. */
3517         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3518                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3519                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3520                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3521                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3522         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3523         DELAY(5);
3524
3525         /* Disable DMA */
3526         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3527             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3528                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3529                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3530                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3531         }
3532
3533         /* Assume bootcode is running. */
3534         sc->bce_fw_timed_out = 0;
3535         sc->bce_drv_cardiac_arrest = 0;
3536
3537         /* Give the firmware a chance to prepare for the reset. */
3538         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3539         if (rc) {
3540                 if_printf(&sc->arpcom.ac_if,
3541                           "Firmware is not ready for reset\n");
3542                 return rc;
3543         }
3544
3545         /* Set a firmware reminder that this is a soft reset. */
3546         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3547             BCE_DRV_RESET_SIGNATURE_MAGIC);
3548
3549         /* Dummy read to force the chip to complete all current transactions. */
3550         val = REG_RD(sc, BCE_MISC_ID);
3551
3552         /* Chip reset. */
3553         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3554             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3555                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3556                 REG_RD(sc, BCE_MISC_COMMAND);
3557                 DELAY(5);
3558
3559                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3560                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3561
3562                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3563         } else {
3564                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3565                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3566                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3567                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3568
3569                 /* Allow up to 30us for reset to complete. */
3570                 for (i = 0; i < 10; i++) {
3571                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3572                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3573                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3574                                 break;
3575                         DELAY(10);
3576                 }
3577
3578                 /* Check that reset completed successfully. */
3579                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3580                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3581                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3582                         return EBUSY;
3583                 }
3584         }
3585
3586         /* Make sure byte swapping is properly configured. */
3587         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3588         if (val != 0x01020304) {
3589                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3590                 return ENODEV;
3591         }
3592
3593         /* Just completed a reset, assume that firmware is running again. */
3594         sc->bce_fw_timed_out = 0;
3595         sc->bce_drv_cardiac_arrest = 0;
3596
3597         /* Wait for the firmware to finish its initialization. */
3598         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3599         if (rc) {
3600                 if_printf(&sc->arpcom.ac_if,
3601                           "Firmware did not complete initialization!\n");
3602         }
3603         return rc;
3604 }
3605
3606
3607 static int
3608 bce_chipinit(struct bce_softc *sc)
3609 {
3610         uint32_t val;
3611         int rc = 0;
3612
3613         /* Make sure the interrupt is not active. */
3614         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3615         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3616
3617         /*
3618          * Initialize DMA byte/word swapping, configure the number of DMA
3619          * channels and PCI clock compensation delay.
3620          */
3621         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3622               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3623 #if BYTE_ORDER == BIG_ENDIAN
3624               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3625 #endif
3626               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3627               DMA_READ_CHANS << 12 |
3628               DMA_WRITE_CHANS << 16;
3629
3630         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3631
3632         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3633                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3634
3635         /*
3636          * This setting resolves a problem observed on certain Intel PCI
3637          * chipsets that cannot handle multiple outstanding DMA operations.
3638          * See errata E9_5706A1_65.
3639          */
3640         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3641             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3642             !(sc->bce_flags & BCE_PCIX_FLAG))
3643                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3644
3645         REG_WR(sc, BCE_DMA_CONFIG, val);
3646
3647         /* Enable the RX_V2P and Context state machines before access. */
3648         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3649                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3650                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3651                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3652
3653         /* Initialize context mapping and zero out the quick contexts. */
3654         rc = bce_init_ctx(sc);
3655         if (rc != 0)
3656                 return rc;
3657
3658         /* Initialize the on-boards CPUs */
3659         bce_init_cpus(sc);
3660
3661         /* Enable management frames (NC-SI) to flow to the MCP. */
3662         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3663                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3664                     BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3665                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3666         }
3667
3668         /* Prepare NVRAM for access. */
3669         rc = bce_init_nvram(sc);
3670         if (rc != 0)
3671                 return rc;
3672
3673         /* Set the kernel bypass block size */
3674         val = REG_RD(sc, BCE_MQ_CONFIG);
3675         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3676         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3677
3678         /* Enable bins used on the 5709/5716. */
3679         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3680             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3681                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3682                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3683                         val |= BCE_MQ_CONFIG_HALT_DIS;
3684         }
3685
3686         REG_WR(sc, BCE_MQ_CONFIG, val);
3687
3688         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3689         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3690         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3691
3692         /* Set the page size and clear the RV2P processor stall bits. */
3693         val = (BCM_PAGE_BITS - 8) << 24;
3694         REG_WR(sc, BCE_RV2P_CONFIG, val);
3695
3696         /* Configure page size. */
3697         val = REG_RD(sc, BCE_TBDR_CONFIG);
3698         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3699         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3700         REG_WR(sc, BCE_TBDR_CONFIG, val);
3701
3702         /* Set the perfect match control register to default. */
3703         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3704
3705         return 0;
3706 }
3707
3708
3709 /****************************************************************************/
3710 /* Initialize the controller in preparation to send/receive traffic.        */
3711 /*                                                                          */
3712 /* Returns:                                                                 */
3713 /*   0 for success, positive value for failure.                             */
3714 /****************************************************************************/
3715 static int
3716 bce_blockinit(struct bce_softc *sc)
3717 {
3718         uint32_t reg, val;
3719
3720         /* Load the hardware default MAC address. */
3721         bce_set_mac_addr(sc);
3722
3723         /* Set the Ethernet backoff seed value */
3724         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3725               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3726         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3727
3728         sc->last_status_idx = 0;
3729         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3730
3731         /* Set up link change interrupt generation. */
3732         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3733
3734         /* Program the physical address of the status block. */
3735         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3736         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3737
3738         /* Program the physical address of the statistics block. */
3739         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3740                BCE_ADDR_LO(sc->stats_block_paddr));
3741         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3742                BCE_ADDR_HI(sc->stats_block_paddr));
3743
3744         /* Program various host coalescing parameters. */
3745         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3746                (sc->bce_tx_quick_cons_trip_int << 16) |
3747                sc->bce_tx_quick_cons_trip);
3748         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3749                (sc->bce_rx_quick_cons_trip_int << 16) |
3750                sc->bce_rx_quick_cons_trip);
3751         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3752                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3753         REG_WR(sc, BCE_HC_TX_TICKS,
3754                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3755         REG_WR(sc, BCE_HC_RX_TICKS,
3756                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3757         REG_WR(sc, BCE_HC_COM_TICKS,
3758                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3759         REG_WR(sc, BCE_HC_CMD_TICKS,
3760                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3761         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3762         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3763
3764         val = BCE_HC_CONFIG_TX_TMR_MODE | BCE_HC_CONFIG_COLLECT_STATS;
3765         if (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) {
3766                 if (bootverbose)
3767                         if_printf(&sc->arpcom.ac_if, "oneshot MSI\n");
3768                 val |= BCE_HC_CONFIG_ONE_SHOT | BCE_HC_CONFIG_USE_INT_PARAM;
3769         }
3770         REG_WR(sc, BCE_HC_CONFIG, val);
3771
3772         /* Clear the internal statistics counters. */
3773         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3774
3775         /* Verify that bootcode is running. */
3776         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3777
3778         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3779                 if_printf(&sc->arpcom.ac_if,
3780                           "%s(%d): Simulating bootcode failure.\n",
3781                           __FILE__, __LINE__);
3782                 reg = 0);
3783
3784         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3785             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3786                 if_printf(&sc->arpcom.ac_if,
3787                           "Bootcode not running! Found: 0x%08X, "
3788                           "Expected: 08%08X\n",
3789                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3790                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3791                 return ENODEV;
3792         }
3793
3794         /* Enable DMA */
3795         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3796             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3797                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3798                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3799                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3800         }
3801
3802         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3803         bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3804
3805         /* Enable link state change interrupt generation. */
3806         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3807
3808         /* Enable the RXP. */
3809         bce_start_rxp_cpu(sc);
3810
3811         /* Disable management frames (NC-SI) from flowing to the MCP. */
3812         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3813                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3814                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3815                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3816         }
3817
3818         /* Enable all remaining blocks in the MAC. */
3819         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3820             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3821                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3822                     BCE_MISC_ENABLE_DEFAULT_XI);
3823         } else {
3824                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3825         }
3826         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3827         DELAY(20);
3828
3829         /* Save the current host coalescing block settings. */
3830         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3831
3832         return 0;
3833 }
3834
3835
3836 /****************************************************************************/
3837 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3838 /*                                                                          */
3839 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3840 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3841 /* necessary.                                                               */
3842 /*                                                                          */
3843 /* Returns:                                                                 */
3844 /*   0 for success, positive value for failure.                             */
3845 /****************************************************************************/
3846 static int
3847 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3848                uint32_t *prod_bseq, int init)
3849 {
3850         bus_dmamap_t map;
3851         bus_dma_segment_t seg;
3852         struct mbuf *m_new;
3853         int error, nseg;
3854 #ifdef BCE_DEBUG
3855         uint16_t debug_chain_prod = *chain_prod;
3856 #endif
3857
3858         /* Make sure the inputs are valid. */
3859         DBRUNIF((*chain_prod > MAX_RX_BD(sc)),
3860                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3861                           "RX producer out of range: 0x%04X > 0x%04X\n",
3862                           __FILE__, __LINE__,
3863                           *chain_prod, (uint16_t)MAX_RX_BD(sc)));
3864
3865         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3866                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3867
3868         DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3869                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3870                           "Simulating mbuf allocation failure.\n",
3871                           __FILE__, __LINE__);
3872                 sc->mbuf_alloc_failed++;
3873                 return ENOBUFS);
3874
3875         /* This is a new mbuf allocation. */
3876         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3877         if (m_new == NULL)
3878                 return ENOBUFS;
3879         DBRUNIF(1, sc->rx_mbuf_alloc++);
3880
3881         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3882
3883         /* Map the mbuf cluster into device memory. */
3884         error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3885                         sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3886                         BUS_DMA_NOWAIT);
3887         if (error) {
3888                 m_freem(m_new);
3889                 if (init) {
3890                         if_printf(&sc->arpcom.ac_if,
3891                                   "Error mapping mbuf into RX chain!\n");
3892                 }
3893                 DBRUNIF(1, sc->rx_mbuf_alloc--);
3894                 return error;
3895         }
3896
3897         if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3898                 bus_dmamap_unload(sc->rx_mbuf_tag,
3899                                   sc->rx_mbuf_map[*chain_prod]);
3900         }
3901
3902         map = sc->rx_mbuf_map[*chain_prod];
3903         sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3904         sc->rx_mbuf_tmpmap = map;
3905
3906         /* Watch for overflow. */
3907         DBRUNIF((sc->free_rx_bd > USABLE_RX_BD(sc)),
3908                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3909                           "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3910                           __FILE__, __LINE__, sc->free_rx_bd,
3911                           (uint16_t)USABLE_RX_BD(sc)));
3912
3913         /* Update some debug statistic counters */
3914         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3915                 sc->rx_low_watermark = sc->free_rx_bd);
3916         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3917
3918         /* Save the mbuf and update our counter. */
3919         sc->rx_mbuf_ptr[*chain_prod] = m_new;
3920         sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3921         sc->free_rx_bd--;
3922
3923         bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3924
3925         DBRUN(BCE_VERBOSE_RECV,
3926               bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3927
3928         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3929                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3930
3931         return 0;
3932 }
3933
3934
3935 static void
3936 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3937 {
3938         struct rx_bd *rxbd;
3939         bus_addr_t paddr;
3940         int len;
3941
3942         paddr = sc->rx_mbuf_paddr[chain_prod];
3943         len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3944
3945         /* Setup the rx_bd for the first segment. */
3946         rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3947
3948         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3949         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3950         rxbd->rx_bd_len = htole32(len);
3951         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3952         *prod_bseq += len;
3953
3954         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3955 }
3956
3957
3958 /****************************************************************************/
3959 /* Initialize the TX context memory.                                        */
3960 /*                                                                          */
3961 /* Returns:                                                                 */
3962 /*   Nothing                                                                */
3963 /****************************************************************************/
3964 static void
3965 bce_init_tx_context(struct bce_softc *sc)
3966 {
3967         uint32_t val;
3968
3969         /* Initialize the context ID for an L2 TX chain. */
3970         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3971             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3972                 /* Set the CID type to support an L2 connection. */
3973                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3974                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3975                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3976                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3977
3978                 /* Point the hardware to the first page in the chain. */
3979                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3980                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3981                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3982                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3983                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3984                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3985         } else {
3986                 /* Set the CID type to support an L2 connection. */
3987                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3988                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3989                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3990                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3991
3992                 /* Point the hardware to the first page in the chain. */
3993                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3994                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3995                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3996                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3997                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3998                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3999         }
4000 }
4001
4002
4003 /****************************************************************************/
4004 /* Allocate memory and initialize the TX data structures.                   */
4005 /*                                                                          */
4006 /* Returns:                                                                 */
4007 /*   0 for success, positive value for failure.                             */
4008 /****************************************************************************/
4009 static int
4010 bce_init_tx_chain(struct bce_softc *sc)
4011 {
4012         struct tx_bd *txbd;
4013         int i, rc = 0;
4014
4015         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4016
4017         /* Set the initial TX producer/consumer indices. */
4018         sc->tx_prod = 0;
4019         sc->tx_cons = 0;
4020         sc->tx_prod_bseq   = 0;
4021         sc->used_tx_bd = 0;
4022         sc->max_tx_bd = USABLE_TX_BD(sc);
4023         DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD(sc));
4024         DBRUNIF(1, sc->tx_full_count = 0);
4025
4026         /*
4027          * The NetXtreme II supports a linked-list structre called
4028          * a Buffer Descriptor Chain (or BD chain).  A BD chain
4029          * consists of a series of 1 or more chain pages, each of which
4030          * consists of a fixed number of BD entries.
4031          * The last BD entry on each page is a pointer to the next page
4032          * in the chain, and the last pointer in the BD chain
4033          * points back to the beginning of the chain.
4034          */
4035
4036         /* Set the TX next pointer chain entries. */
4037         for (i = 0; i < sc->tx_pages; i++) {
4038                 int j;
4039
4040                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
4041
4042                 /* Check if we've reached the last page. */
4043                 if (i == (sc->tx_pages - 1))
4044                         j = 0;
4045                 else
4046                         j = i + 1;
4047
4048                 txbd->tx_bd_haddr_hi =
4049                         htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
4050                 txbd->tx_bd_haddr_lo =
4051                         htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
4052         }
4053         bce_init_tx_context(sc);
4054
4055         return(rc);
4056 }
4057
4058
4059 /****************************************************************************/
4060 /* Free memory and clear the TX data structures.                            */
4061 /*                                                                          */
4062 /* Returns:                                                                 */
4063 /*   Nothing.                                                               */
4064 /****************************************************************************/
4065 static void
4066 bce_free_tx_chain(struct bce_softc *sc)
4067 {
4068         int i;
4069
4070         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4071
4072         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
4073         for (i = 0; i < TOTAL_TX_BD(sc); i++) {
4074                 if (sc->tx_mbuf_ptr[i] != NULL) {
4075                         bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
4076                         m_freem(sc->tx_mbuf_ptr[i]);
4077                         sc->tx_mbuf_ptr[i] = NULL;
4078                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4079                 }
4080         }
4081
4082         /* Clear each TX chain page. */
4083         for (i = 0; i < sc->tx_pages; i++)
4084                 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
4085         sc->used_tx_bd = 0;
4086
4087         /* Check if we lost any mbufs in the process. */
4088         DBRUNIF((sc->tx_mbuf_alloc),
4089                 if_printf(&sc->arpcom.ac_if,
4090                           "%s(%d): Memory leak! "
4091                           "Lost %d mbufs from tx chain!\n",
4092                           __FILE__, __LINE__, sc->tx_mbuf_alloc));
4093
4094         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4095 }
4096
4097
4098 /****************************************************************************/
4099 /* Initialize the RX context memory.                                        */
4100 /*                                                                          */
4101 /* Returns:                                                                 */
4102 /*   Nothing                                                                */
4103 /****************************************************************************/
4104 static void
4105 bce_init_rx_context(struct bce_softc *sc)
4106 {
4107         uint32_t val;
4108
4109         /* Initialize the context ID for an L2 RX chain. */
4110         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4111             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4112
4113         /*
4114          * Set the level for generating pause frames
4115          * when the number of available rx_bd's gets
4116          * too low (the low watermark) and the level
4117          * when pause frames can be stopped (the high
4118          * watermark).
4119          */
4120         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4121             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4122                 uint32_t lo_water, hi_water;
4123
4124                 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
4125                 hi_water = USABLE_RX_BD(sc) / 4;
4126
4127                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
4128                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
4129
4130                 if (hi_water > 0xf)
4131                         hi_water = 0xf;
4132                 else if (hi_water == 0)
4133                         lo_water = 0;
4134                 val |= lo_water |
4135                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
4136         }
4137
4138         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
4139
4140         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
4141         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4142             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4143                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
4144                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
4145         }
4146
4147         /* Point the hardware to the first page in the chain. */
4148         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
4149         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
4150         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
4151         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
4152 }
4153
4154
4155 /****************************************************************************/
4156 /* Allocate memory and initialize the RX data structures.                   */
4157 /*                                                                          */
4158 /* Returns:                                                                 */
4159 /*   0 for success, positive value for failure.                             */
4160 /****************************************************************************/
4161 static int
4162 bce_init_rx_chain(struct bce_softc *sc)
4163 {
4164         struct rx_bd *rxbd;
4165         int i, rc = 0;
4166         uint16_t prod, chain_prod;
4167         uint32_t prod_bseq;
4168
4169         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4170
4171         /* Initialize the RX producer and consumer indices. */
4172         sc->rx_prod = 0;
4173         sc->rx_cons = 0;
4174         sc->rx_prod_bseq = 0;
4175         sc->free_rx_bd = USABLE_RX_BD(sc);
4176         sc->max_rx_bd = USABLE_RX_BD(sc);
4177         DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD(sc));
4178         DBRUNIF(1, sc->rx_empty_count = 0);
4179
4180         /* Initialize the RX next pointer chain entries. */
4181         for (i = 0; i < sc->rx_pages; i++) {
4182                 int j;
4183
4184                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
4185
4186                 /* Check if we've reached the last page. */
4187                 if (i == (sc->rx_pages - 1))
4188                         j = 0;
4189                 else
4190                         j = i + 1;
4191
4192                 /* Setup the chain page pointers. */
4193                 rxbd->rx_bd_haddr_hi =
4194                         htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4195                 rxbd->rx_bd_haddr_lo =
4196                         htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4197         }
4198
4199         /* Allocate mbuf clusters for the rx_bd chain. */
4200         prod = prod_bseq = 0;
4201         while (prod < TOTAL_RX_BD(sc)) {
4202                 chain_prod = RX_CHAIN_IDX(sc, prod);
4203                 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
4204                         if_printf(&sc->arpcom.ac_if,
4205                                   "Error filling RX chain: rx_bd[0x%04X]!\n",
4206                                   chain_prod);
4207                         rc = ENOBUFS;
4208                         break;
4209                 }
4210                 prod = NEXT_RX_BD(prod);
4211         }
4212
4213         /* Save the RX chain producer index. */
4214         sc->rx_prod = prod;
4215         sc->rx_prod_bseq = prod_bseq;
4216
4217         /* Tell the chip about the waiting rx_bd's. */
4218         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4219             sc->rx_prod);
4220         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4221             sc->rx_prod_bseq);
4222
4223         bce_init_rx_context(sc);
4224
4225         return(rc);
4226 }
4227
4228
4229 /****************************************************************************/
4230 /* Free memory and clear the RX data structures.                            */
4231 /*                                                                          */
4232 /* Returns:                                                                 */
4233 /*   Nothing.                                                               */
4234 /****************************************************************************/
4235 static void
4236 bce_free_rx_chain(struct bce_softc *sc)
4237 {
4238         int i;
4239
4240         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4241
4242         /* Free any mbufs still in the RX mbuf chain. */
4243         for (i = 0; i < TOTAL_RX_BD(sc); i++) {
4244                 if (sc->rx_mbuf_ptr[i] != NULL) {
4245                         bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
4246                         m_freem(sc->rx_mbuf_ptr[i]);
4247                         sc->rx_mbuf_ptr[i] = NULL;
4248                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4249                 }
4250         }
4251
4252         /* Clear each RX chain page. */
4253         for (i = 0; i < sc->rx_pages; i++)
4254                 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4255
4256         /* Check if we lost any mbufs in the process. */
4257         DBRUNIF((sc->rx_mbuf_alloc),
4258                 if_printf(&sc->arpcom.ac_if,
4259                           "%s(%d): Memory leak! "
4260                           "Lost %d mbufs from rx chain!\n",
4261                           __FILE__, __LINE__, sc->rx_mbuf_alloc));
4262
4263         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4264 }
4265
4266
4267 /****************************************************************************/
4268 /* Set media options.                                                       */
4269 /*                                                                          */
4270 /* Returns:                                                                 */
4271 /*   0 for success, positive value for failure.                             */
4272 /****************************************************************************/
4273 static int
4274 bce_ifmedia_upd(struct ifnet *ifp)
4275 {
4276         struct bce_softc *sc = ifp->if_softc;
4277         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4278         int error = 0;
4279
4280         /*
4281          * 'mii' will be NULL, when this function is called on following
4282          * code path: bce_attach() -> bce_mgmt_init()
4283          */
4284         if (mii != NULL) {
4285                 /* Make sure the MII bus has been enumerated. */
4286                 sc->bce_link = 0;
4287                 if (mii->mii_instance) {
4288                         struct mii_softc *miisc;
4289
4290                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4291                                 mii_phy_reset(miisc);
4292                 }
4293                 error = mii_mediachg(mii);
4294         }
4295         return error;
4296 }
4297
4298
4299 /****************************************************************************/
4300 /* Reports current media status.                                            */
4301 /*                                                                          */
4302 /* Returns:                                                                 */
4303 /*   Nothing.                                                               */
4304 /****************************************************************************/
4305 static void
4306 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4307 {
4308         struct bce_softc *sc = ifp->if_softc;
4309         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4310
4311         mii_pollstat(mii);
4312         ifmr->ifm_active = mii->mii_media_active;
4313         ifmr->ifm_status = mii->mii_media_status;
4314 }
4315
4316
4317 /****************************************************************************/
4318 /* Handles PHY generated interrupt events.                                  */
4319 /*                                                                          */
4320 /* Returns:                                                                 */
4321 /*   Nothing.                                                               */
4322 /****************************************************************************/
4323 static void
4324 bce_phy_intr(struct bce_softc *sc)
4325 {
4326         uint32_t new_link_state, old_link_state;
4327         struct ifnet *ifp = &sc->arpcom.ac_if;
4328
4329         ASSERT_SERIALIZED(ifp->if_serializer);
4330
4331         new_link_state = sc->status_block->status_attn_bits &
4332                          STATUS_ATTN_BITS_LINK_STATE;
4333         old_link_state = sc->status_block->status_attn_bits_ack &
4334                          STATUS_ATTN_BITS_LINK_STATE;
4335
4336         /* Handle any changes if the link state has changed. */
4337         if (new_link_state != old_link_state) { /* XXX redundant? */
4338                 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4339
4340                 /* Update the status_attn_bits_ack field in the status block. */
4341                 if (new_link_state) {
4342                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4343                                STATUS_ATTN_BITS_LINK_STATE);
4344                         if (bootverbose)
4345                                 if_printf(ifp, "Link is now UP.\n");
4346                 } else {
4347                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4348                                STATUS_ATTN_BITS_LINK_STATE);
4349                         if (bootverbose)
4350                                 if_printf(ifp, "Link is now DOWN.\n");
4351                 }
4352
4353                 /*
4354                  * Assume link is down and allow tick routine to
4355                  * update the state based on the actual media state.
4356                  */
4357                 sc->bce_link = 0;
4358                 callout_stop(&sc->bce_tick_callout);
4359                 bce_tick_serialized(sc);
4360         }
4361
4362         /* Acknowledge the link change interrupt. */
4363         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4364 }
4365
4366
4367 /****************************************************************************/
4368 /* Reads the receive consumer value from the status block (skipping over    */
4369 /* chain page pointer if necessary).                                        */
4370 /*                                                                          */
4371 /* Returns:                                                                 */
4372 /*   hw_cons                                                                */
4373 /****************************************************************************/
4374 static __inline uint16_t
4375 bce_get_hw_rx_cons(struct bce_softc *sc)
4376 {
4377         uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4378
4379         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4380                 hw_cons++;
4381         return hw_cons;
4382 }
4383
4384
4385 /****************************************************************************/
4386 /* Handles received frame interrupt events.                                 */
4387 /*                                                                          */
4388 /* Returns:                                                                 */
4389 /*   Nothing.                                                               */
4390 /****************************************************************************/
4391 static void
4392 bce_rx_intr(struct bce_softc *sc, int count, uint16_t hw_cons)
4393 {
4394         struct ifnet *ifp = &sc->arpcom.ac_if;
4395         uint16_t sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4396         uint32_t sw_prod_bseq;
4397
4398         ASSERT_SERIALIZED(ifp->if_serializer);
4399
4400         /* Get working copies of the driver's view of the RX indices. */
4401         sw_cons = sc->rx_cons;
4402         sw_prod = sc->rx_prod;
4403         sw_prod_bseq = sc->rx_prod_bseq;
4404
4405         /* Scan through the receive chain as long as there is work to do. */
4406         while (sw_cons != hw_cons) {
4407                 struct mbuf *m = NULL;
4408                 struct l2_fhdr *l2fhdr = NULL;
4409                 unsigned int len;
4410                 uint32_t status = 0;
4411
4412 #ifdef IFPOLL_ENABLE
4413                 if (count >= 0 && count-- == 0)
4414                         break;
4415 #endif
4416
4417                 /*
4418                  * Convert the producer/consumer indices
4419                  * to an actual rx_bd index.
4420                  */
4421                 sw_chain_cons = RX_CHAIN_IDX(sc, sw_cons);
4422                 sw_chain_prod = RX_CHAIN_IDX(sc, sw_prod);
4423
4424                 sc->free_rx_bd++;
4425
4426                 /* The mbuf is stored with the last rx_bd entry of a packet. */
4427                 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4428                         if (sw_chain_cons != sw_chain_prod) {
4429                                 if_printf(ifp, "RX cons(%d) != prod(%d), "
4430                                           "drop!\n", sw_chain_cons,
4431                                           sw_chain_prod);
4432                                 ifp->if_ierrors++;
4433
4434                                 bce_setup_rxdesc_std(sc, sw_chain_cons,
4435                                                      &sw_prod_bseq);
4436                                 m = NULL;
4437                                 goto bce_rx_int_next_rx;
4438                         }
4439
4440                         /* Unmap the mbuf from DMA space. */
4441                         bus_dmamap_sync(sc->rx_mbuf_tag,
4442                                         sc->rx_mbuf_map[sw_chain_cons],
4443                                         BUS_DMASYNC_POSTREAD);
4444
4445                         /* Save the mbuf from the driver's chain. */
4446                         m = sc->rx_mbuf_ptr[sw_chain_cons];
4447
4448                         /*
4449                          * Frames received on the NetXteme II are prepended
4450                          * with an l2_fhdr structure which provides status
4451                          * information about the received frame (including
4452                          * VLAN tags and checksum info).  The frames are also
4453                          * automatically adjusted to align the IP header
4454                          * (i.e. two null bytes are inserted before the
4455                          * Ethernet header).  As a result the data DMA'd by
4456                          * the controller into the mbuf is as follows:
4457                          *
4458                          * +---------+-----+---------------------+-----+
4459                          * | l2_fhdr | pad | packet data         | FCS |
4460                          * +---------+-----+---------------------+-----+
4461                          *
4462                          * The l2_fhdr needs to be checked and skipped and the
4463                          * FCS needs to be stripped before sending the packet
4464                          * up the stack.
4465                          */
4466                         l2fhdr = mtod(m, struct l2_fhdr *);
4467
4468                         len = l2fhdr->l2_fhdr_pkt_len;
4469                         status = l2fhdr->l2_fhdr_status;
4470
4471                         len -= ETHER_CRC_LEN;
4472
4473                         /* Check the received frame for errors. */
4474                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
4475                                       L2_FHDR_ERRORS_PHY_DECODE |
4476                                       L2_FHDR_ERRORS_ALIGNMENT |
4477                                       L2_FHDR_ERRORS_TOO_SHORT |
4478                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
4479                                 ifp->if_ierrors++;
4480
4481                                 /* Reuse the mbuf for a new frame. */
4482                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4483                                                      &sw_prod_bseq);
4484                                 m = NULL;
4485                                 goto bce_rx_int_next_rx;
4486                         }
4487
4488                         /*
4489                          * Get a new mbuf for the rx_bd.   If no new
4490                          * mbufs are available then reuse the current mbuf,
4491                          * log an ierror on the interface, and generate
4492                          * an error in the system log.
4493                          */
4494                         if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4495                                            &sw_prod_bseq, 0)) {
4496                                 ifp->if_ierrors++;
4497
4498                                 /* Try and reuse the exisitng mbuf. */
4499                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4500                                                      &sw_prod_bseq);
4501                                 m = NULL;
4502                                 goto bce_rx_int_next_rx;
4503                         }
4504
4505                         /*
4506                          * Skip over the l2_fhdr when passing
4507                          * the data up the stack.
4508                          */
4509                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4510
4511                         m->m_pkthdr.len = m->m_len = len;
4512                         m->m_pkthdr.rcvif = ifp;
4513
4514                         /* Validate the checksum if offload enabled. */
4515                         if (ifp->if_capenable & IFCAP_RXCSUM) {
4516                                 /* Check for an IP datagram. */
4517                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4518                                         m->m_pkthdr.csum_flags |=
4519                                                 CSUM_IP_CHECKED;
4520
4521                                         /* Check if the IP checksum is valid. */
4522                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
4523                                              0xffff) == 0) {
4524                                                 m->m_pkthdr.csum_flags |=
4525                                                         CSUM_IP_VALID;
4526                                         }
4527                                 }
4528
4529                                 /* Check for a valid TCP/UDP frame. */
4530                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4531                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
4532
4533                                         /* Check for a good TCP/UDP checksum. */
4534                                         if ((status &
4535                                              (L2_FHDR_ERRORS_TCP_XSUM |
4536                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4537                                                 m->m_pkthdr.csum_data =
4538                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
4539                                                 m->m_pkthdr.csum_flags |=
4540                                                         CSUM_DATA_VALID |
4541                                                         CSUM_PSEUDO_HDR;
4542                                         }
4543                                 }
4544                         }
4545
4546                         ifp->if_ipackets++;
4547 bce_rx_int_next_rx:
4548                         sw_prod = NEXT_RX_BD(sw_prod);
4549                 }
4550
4551                 sw_cons = NEXT_RX_BD(sw_cons);
4552
4553                 /* If we have a packet, pass it up the stack */
4554                 if (m) {
4555                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4556                                 m->m_flags |= M_VLANTAG;
4557                                 m->m_pkthdr.ether_vlantag =
4558                                         l2fhdr->l2_fhdr_vlan_tag;
4559                         }
4560                         ifp->if_input(ifp, m);
4561                 }
4562         }
4563
4564         sc->rx_cons = sw_cons;
4565         sc->rx_prod = sw_prod;
4566         sc->rx_prod_bseq = sw_prod_bseq;
4567
4568         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4569             sc->rx_prod);
4570         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4571             sc->rx_prod_bseq);
4572 }
4573
4574
4575 /****************************************************************************/
4576 /* Reads the transmit consumer value from the status block (skipping over   */
4577 /* chain page pointer if necessary).                                        */
4578 /*                                                                          */
4579 /* Returns:                                                                 */
4580 /*   hw_cons                                                                */
4581 /****************************************************************************/
4582 static __inline uint16_t
4583 bce_get_hw_tx_cons(struct bce_softc *sc)
4584 {
4585         uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4586
4587         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4588                 hw_cons++;
4589         return hw_cons;
4590 }
4591
4592
4593 /****************************************************************************/
4594 /* Handles transmit completion interrupt events.                            */
4595 /*                                                                          */
4596 /* Returns:                                                                 */
4597 /*   Nothing.                                                               */
4598 /****************************************************************************/
4599 static void
4600 bce_tx_intr(struct bce_softc *sc, uint16_t hw_tx_cons)
4601 {
4602         struct ifnet *ifp = &sc->arpcom.ac_if;
4603         uint16_t sw_tx_cons, sw_tx_chain_cons;
4604
4605         ASSERT_SERIALIZED(ifp->if_serializer);
4606
4607         /* Get the hardware's view of the TX consumer index. */
4608         sw_tx_cons = sc->tx_cons;
4609
4610         /* Cycle through any completed TX chain page entries. */
4611         while (sw_tx_cons != hw_tx_cons) {
4612                 sw_tx_chain_cons = TX_CHAIN_IDX(sc, sw_tx_cons);
4613
4614                 /*
4615                  * Free the associated mbuf. Remember
4616                  * that only the last tx_bd of a packet
4617                  * has an mbuf pointer and DMA map.
4618                  */
4619                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4620                         /* Unmap the mbuf. */
4621                         bus_dmamap_unload(sc->tx_mbuf_tag,
4622                                           sc->tx_mbuf_map[sw_tx_chain_cons]);
4623
4624                         /* Free the mbuf. */
4625                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4626                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4627
4628                         ifp->if_opackets++;
4629                 }
4630
4631                 sc->used_tx_bd--;
4632                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4633         }
4634
4635         if (sc->used_tx_bd == 0) {
4636                 /* Clear the TX timeout timer. */
4637                 ifp->if_timer = 0;
4638         }
4639
4640         /* Clear the tx hardware queue full flag. */
4641         if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE)
4642                 ifq_clr_oactive(&ifp->if_snd);
4643         sc->tx_cons = sw_tx_cons;
4644 }
4645
4646
4647 /****************************************************************************/
4648 /* Disables interrupt generation.                                           */
4649 /*                                                                          */
4650 /* Returns:                                                                 */
4651 /*   Nothing.                                                               */
4652 /****************************************************************************/
4653 static void
4654 bce_disable_intr(struct bce_softc *sc)
4655 {
4656         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4657         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4658
4659         callout_stop(&sc->bce_ckmsi_callout);
4660         sc->bce_msi_maylose = FALSE;
4661         sc->bce_check_rx_cons = 0;
4662         sc->bce_check_tx_cons = 0;
4663         sc->bce_check_status_idx = 0xffff;
4664
4665         sc->bce_npoll.ifpc_stcount = 0;
4666
4667         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4668 }
4669
4670
4671 /****************************************************************************/
4672 /* Enables interrupt generation.                                            */
4673 /*                                                                          */
4674 /* Returns:                                                                 */
4675 /*   Nothing.                                                               */
4676 /****************************************************************************/
4677 static void
4678 bce_enable_intr(struct bce_softc *sc)
4679 {
4680         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4681
4682         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4683                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4684                BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4685         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4686                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4687
4688         REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4689
4690         if (sc->bce_flags & BCE_CHECK_MSI_FLAG) {
4691                 sc->bce_msi_maylose = FALSE;
4692                 sc->bce_check_rx_cons = 0;
4693                 sc->bce_check_tx_cons = 0;
4694                 sc->bce_check_status_idx = 0xffff;
4695
4696                 if (bootverbose)
4697                         if_printf(&sc->arpcom.ac_if, "check msi\n");
4698
4699                 callout_reset_bycpu(&sc->bce_ckmsi_callout, BCE_MSI_CKINTVL,
4700                     bce_check_msi, sc, sc->bce_intr_cpuid);
4701         }
4702 }
4703
4704
4705 /****************************************************************************/
4706 /* Reenables interrupt generation during interrupt handling.                */
4707 /*                                                                          */
4708 /* Returns:                                                                 */
4709 /*   Nothing.                                                               */
4710 /****************************************************************************/
4711 static void
4712 bce_reenable_intr(struct bce_softc *sc)
4713 {
4714         if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
4715                 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4716                        BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4717                        BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4718         }
4719         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4720                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4721 }
4722
4723
4724 /****************************************************************************/
4725 /* Handles controller initialization.                                       */
4726 /*                                                                          */
4727 /* Returns:                                                                 */
4728 /*   Nothing.                                                               */
4729 /****************************************************************************/
4730 static void
4731 bce_init(void *xsc)
4732 {
4733         struct bce_softc *sc = xsc;
4734         struct ifnet *ifp = &sc->arpcom.ac_if;
4735         uint32_t ether_mtu;
4736         int error;
4737
4738         ASSERT_SERIALIZED(ifp->if_serializer);
4739
4740         /* Check if the driver is still running and bail out if it is. */
4741         if (ifp->if_flags & IFF_RUNNING)
4742                 return;
4743
4744         bce_stop(sc);
4745
4746         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4747         if (error) {
4748                 if_printf(ifp, "Controller reset failed!\n");
4749                 goto back;
4750         }
4751
4752         error = bce_chipinit(sc);
4753         if (error) {
4754                 if_printf(ifp, "Controller initialization failed!\n");
4755                 goto back;
4756         }
4757
4758         error = bce_blockinit(sc);
4759         if (error) {
4760                 if_printf(ifp, "Block initialization failed!\n");
4761                 goto back;
4762         }
4763
4764         /* Load our MAC address. */
4765         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4766         bce_set_mac_addr(sc);
4767
4768         /* Calculate and program the Ethernet MTU size. */
4769         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4770
4771         DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4772
4773         /*
4774          * Program the mtu, enabling jumbo frame
4775          * support if necessary.  Also set the mbuf
4776          * allocation count for RX frames.
4777          */
4778         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4779 #ifdef notyet
4780                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4781                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4782                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4783                 sc->mbuf_alloc_size = MJUM9BYTES;
4784 #else
4785                 panic("jumbo buffer is not supported yet");
4786 #endif
4787         } else {
4788                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4789                 sc->mbuf_alloc_size = MCLBYTES;
4790         }
4791
4792         /* Calculate the RX Ethernet frame size for rx_bd's. */
4793         sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4794
4795         DBPRINT(sc, BCE_INFO,
4796                 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4797                 "max_frame_size = %d\n",
4798                 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4799                 sc->max_frame_size);
4800
4801         /* Program appropriate promiscuous/multicast filtering. */
4802         bce_set_rx_mode(sc);
4803
4804         /* Init RX buffer descriptor chain. */
4805         bce_init_rx_chain(sc);  /* XXX return value */
4806
4807         /* Init TX buffer descriptor chain. */
4808         bce_init_tx_chain(sc);  /* XXX return value */
4809
4810 #ifdef IFPOLL_ENABLE
4811         /* Disable interrupts if we are polling. */
4812         if (ifp->if_flags & IFF_NPOLLING) {
4813                 bce_disable_intr(sc);
4814
4815                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4816                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4817                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4818                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4819         } else
4820 #endif
4821         /* Enable host interrupts. */
4822         bce_enable_intr(sc);
4823
4824         bce_ifmedia_upd(ifp);
4825
4826         ifp->if_flags |= IFF_RUNNING;
4827         ifq_clr_oactive(&ifp->if_snd);
4828
4829         callout_reset_bycpu(&sc->bce_tick_callout, hz, bce_tick, sc,
4830             sc->bce_intr_cpuid);
4831 back:
4832         if (error)
4833                 bce_stop(sc);
4834 }
4835
4836
4837 /****************************************************************************/
4838 /* Initialize the controller just enough so that any management firmware    */
4839 /* running on the device will continue to operate corectly.                 */
4840 /*                                                                          */
4841 /* Returns:                                                                 */
4842 /*   Nothing.                                                               */
4843 /****************************************************************************/
4844 static void
4845 bce_mgmt_init(struct bce_softc *sc)
4846 {
4847         struct ifnet *ifp = &sc->arpcom.ac_if;
4848
4849         /* Bail out if management firmware is not running. */
4850         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4851                 return;
4852
4853         /* Enable all critical blocks in the MAC. */
4854         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4855             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4856                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4857                     BCE_MISC_ENABLE_DEFAULT_XI);
4858         } else {
4859                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4860         }
4861         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4862         DELAY(20);
4863
4864         bce_ifmedia_upd(ifp);
4865 }
4866
4867
4868 /****************************************************************************/
4869 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4870 /* memory visible to the controller.                                        */
4871 /*                                                                          */
4872 /* Returns:                                                                 */
4873 /*   0 for success, positive value for failure.                             */
4874 /****************************************************************************/
4875 static int
4876 bce_encap(struct bce_softc *sc, struct mbuf **m_head, int *nsegs_used)
4877 {
4878         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4879         bus_dmamap_t map, tmp_map;
4880         struct mbuf *m0 = *m_head;
4881         struct tx_bd *txbd = NULL;
4882         uint16_t vlan_tag = 0, flags = 0, mss = 0;
4883         uint16_t chain_prod, chain_prod_start, prod;
4884         uint32_t prod_bseq;
4885         int i, error, maxsegs, nsegs;
4886
4887         /* Transfer any checksum offload flags to the bd. */
4888         if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
4889                 error = bce_tso_setup(sc, m_head, &flags, &mss);
4890                 if (error)
4891                         return ENOBUFS;
4892                 m0 = *m_head;
4893         } else if (m0->m_pkthdr.csum_flags & BCE_CSUM_FEATURES) {
4894                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4895                         flags |= TX_BD_FLAGS_IP_CKSUM;
4896                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4897                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4898         }
4899
4900         /* Transfer any VLAN tags to the bd. */
4901         if (m0->m_flags & M_VLANTAG) {
4902                 flags |= TX_BD_FLAGS_VLAN_TAG;
4903                 vlan_tag = m0->m_pkthdr.ether_vlantag;
4904         }
4905
4906         prod = sc->tx_prod;
4907         chain_prod_start = chain_prod = TX_CHAIN_IDX(sc, prod);
4908
4909         /* Map the mbuf into DMAable memory. */
4910         map = sc->tx_mbuf_map[chain_prod_start];
4911
4912         maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4913         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4914                 ("not enough segments %d", maxsegs));
4915         if (maxsegs > BCE_MAX_SEGMENTS)
4916                 maxsegs = BCE_MAX_SEGMENTS;
4917
4918         /* Map the mbuf into our DMA address space. */
4919         error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4920                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4921         if (error)
4922                 goto back;
4923         bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4924
4925         *nsegs_used += nsegs;
4926
4927         /* Reset m0 */
4928         m0 = *m_head;
4929
4930         /* prod points to an empty tx_bd at this point. */
4931         prod_bseq  = sc->tx_prod_bseq;
4932
4933         /*
4934          * Cycle through each mbuf segment that makes up
4935          * the outgoing frame, gathering the mapping info
4936          * for that segment and creating a tx_bd to for
4937          * the mbuf.
4938          */
4939         for (i = 0; i < nsegs; i++) {
4940                 chain_prod = TX_CHAIN_IDX(sc, prod);
4941                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4942
4943                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4944                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4945                 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
4946                     htole16(segs[i].ds_len);
4947                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4948                 txbd->tx_bd_flags = htole16(flags);
4949
4950                 prod_bseq += segs[i].ds_len;
4951                 if (i == 0)
4952                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4953                 prod = NEXT_TX_BD(prod);
4954         }
4955
4956         /* Set the END flag on the last TX buffer descriptor. */
4957         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4958
4959         /*
4960          * Ensure that the mbuf pointer for this transmission
4961          * is placed at the array index of the last
4962          * descriptor in this chain.  This is done
4963          * because a single map is used for all
4964          * segments of the mbuf and we don't want to
4965          * unload the map before all of the segments
4966          * have been freed.
4967          */
4968         sc->tx_mbuf_ptr[chain_prod] = m0;
4969
4970         tmp_map = sc->tx_mbuf_map[chain_prod];
4971         sc->tx_mbuf_map[chain_prod] = map;
4972         sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4973
4974         sc->used_tx_bd += nsegs;
4975
4976         /* prod points to the next free tx_bd at this point. */
4977         sc->tx_prod = prod;
4978         sc->tx_prod_bseq = prod_bseq;
4979 back:
4980         if (error) {
4981                 m_freem(*m_head);
4982                 *m_head = NULL;
4983         }
4984         return error;
4985 }
4986
4987
4988 /****************************************************************************/
4989 /* Main transmit routine when called from another routine with a lock.      */
4990 /*                                                                          */
4991 /* Returns:                                                                 */
4992 /*   Nothing.                                                               */
4993 /****************************************************************************/
4994 static void
4995 bce_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
4996 {
4997         struct bce_softc *sc = ifp->if_softc;
4998         int count = 0;
4999
5000         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
5001         ASSERT_SERIALIZED(ifp->if_serializer);
5002
5003         /* If there's no link or the transmit queue is empty then just exit. */
5004         if (!sc->bce_link) {
5005                 ifq_purge(&ifp->if_snd);
5006                 return;
5007         }
5008
5009         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
5010                 return;
5011
5012         for (;;) {
5013                 struct mbuf *m_head;
5014
5015                 /*
5016                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
5017                  * unlikely to fail.
5018                  */
5019                 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
5020                         ifq_set_oactive(&ifp->if_snd);
5021                         break;
5022                 }
5023
5024                 /* Check for any frames to send. */
5025                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
5026                 if (m_head == NULL)
5027                         break;
5028
5029                 /*
5030                  * Pack the data into the transmit ring. If we
5031                  * don't have room, place the mbuf back at the
5032                  * head of the queue and set the OACTIVE flag
5033                  * to wait for the NIC to drain the chain.
5034                  */
5035                 if (bce_encap(sc, &m_head, &count)) {
5036                         ifp->if_oerrors++;
5037                         if (sc->used_tx_bd == 0) {
5038                                 continue;
5039                         } else {
5040                                 ifq_set_oactive(&ifp->if_snd);
5041                                 break;
5042                         }
5043                 }
5044
5045                 if (count >= sc->tx_wreg) {
5046                         /* Start the transmit. */
5047                         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) +
5048                             BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5049                         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
5050                             BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5051                         count = 0;
5052                 }
5053
5054                 /* Send a copy of the frame to any BPF listeners. */
5055                 ETHER_BPF_MTAP(ifp, m_head);
5056
5057                 /* Set the tx timeout. */
5058                 ifp->if_timer = BCE_TX_TIMEOUT;
5059         }
5060         if (count > 0) {
5061                 /* Start the transmit. */
5062                 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX,
5063                     sc->tx_prod);
5064                 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ,
5065                     sc->tx_prod_bseq);
5066         }
5067 }
5068
5069
5070 /****************************************************************************/
5071 /* Handles any IOCTL calls from the operating system.                       */
5072 /*                                                                          */
5073 /* Returns:                                                                 */
5074 /*   0 for success, positive value for failure.                             */
5075 /****************************************************************************/
5076 static int
5077 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
5078 {
5079         struct bce_softc *sc = ifp->if_softc;
5080         struct ifreq *ifr = (struct ifreq *)data;
5081         struct mii_data *mii;
5082         int mask, error = 0;
5083
5084         ASSERT_SERIALIZED(ifp->if_serializer);
5085
5086         switch(command) {
5087         case SIOCSIFMTU:
5088                 /* Check that the MTU setting is supported. */
5089                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
5090 #ifdef notyet
5091                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
5092 #else
5093                     ifr->ifr_mtu > ETHERMTU
5094 #endif
5095                    ) {
5096                         error = EINVAL;
5097                         break;
5098                 }
5099
5100                 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5101
5102                 ifp->if_mtu = ifr->ifr_mtu;
5103                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5104                 bce_init(sc);
5105                 break;
5106
5107         case SIOCSIFFLAGS:
5108                 if (ifp->if_flags & IFF_UP) {
5109                         if (ifp->if_flags & IFF_RUNNING) {
5110                                 mask = ifp->if_flags ^ sc->bce_if_flags;
5111
5112                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5113                                         bce_set_rx_mode(sc);
5114                         } else {
5115                                 bce_init(sc);
5116                         }
5117                 } else if (ifp->if_flags & IFF_RUNNING) {
5118                         bce_stop(sc);
5119
5120                         /* If MFW is running, restart the controller a bit. */
5121                         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5122                                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5123                                 bce_chipinit(sc);
5124                                 bce_mgmt_init(sc);
5125                         }
5126                 }
5127                 sc->bce_if_flags = ifp->if_flags;
5128                 break;
5129
5130         case SIOCADDMULTI:
5131         case SIOCDELMULTI:
5132                 if (ifp->if_flags & IFF_RUNNING)
5133                         bce_set_rx_mode(sc);
5134                 break;
5135
5136         case SIOCSIFMEDIA:
5137         case SIOCGIFMEDIA:
5138                 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5139                         sc->bce_phy_flags);
5140                 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5141
5142                 mii = device_get_softc(sc->bce_miibus);
5143                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5144                 break;
5145
5146         case SIOCSIFCAP:
5147                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5148                 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5149                         (uint32_t) mask);
5150
5151                 if (mask & IFCAP_HWCSUM) {
5152                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5153                         if (ifp->if_capenable & IFCAP_TXCSUM)
5154                                 ifp->if_hwassist |= BCE_CSUM_FEATURES;
5155                         else
5156                                 ifp->if_hwassist &= ~BCE_CSUM_FEATURES;
5157                 }
5158                 if (mask & IFCAP_TSO) {
5159                         ifp->if_capenable ^= IFCAP_TSO;
5160                         if (ifp->if_capenable & IFCAP_TSO)
5161                                 ifp->if_hwassist |= CSUM_TSO;
5162                         else
5163                                 ifp->if_hwassist &= ~CSUM_TSO;
5164                 }
5165                 break;
5166
5167         default:
5168                 error = ether_ioctl(ifp, command, data);
5169                 break;
5170         }
5171         return error;
5172 }
5173
5174
5175 /****************************************************************************/
5176 /* Transmit timeout handler.                                                */
5177 /*                                                                          */
5178 /* Returns:                                                                 */
5179 /*   Nothing.                                                               */
5180 /****************************************************************************/
5181 static void
5182 bce_watchdog(struct ifnet *ifp)
5183 {
5184         struct bce_softc *sc = ifp->if_softc;
5185
5186         ASSERT_SERIALIZED(ifp->if_serializer);
5187
5188         DBRUN(BCE_VERBOSE_SEND,
5189               bce_dump_driver_state(sc);
5190               bce_dump_status_block(sc));
5191
5192         /*
5193          * If we are in this routine because of pause frames, then
5194          * don't reset the hardware.
5195          */
5196         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5197                 return;
5198
5199         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5200
5201         /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5202
5203         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5204         bce_init(sc);
5205
5206         ifp->if_oerrors++;
5207
5208         if (!ifq_is_empty(&ifp->if_snd))
5209                 if_devstart(ifp);
5210 }
5211
5212
5213 #ifdef IFPOLL_ENABLE
5214
5215 static void
5216 bce_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
5217 {
5218         struct bce_softc *sc = ifp->if_softc;
5219         struct status_block *sblk = sc->status_block;
5220         uint16_t hw_tx_cons, hw_rx_cons;
5221
5222         ASSERT_SERIALIZED(ifp->if_serializer);
5223
5224         /*
5225          * Save the status block index value for use when enabling
5226          * the interrupt.
5227          */
5228         sc->last_status_idx = sblk->status_idx;
5229
5230         /* Make sure status index is extracted before rx/tx cons */
5231         cpu_lfence();
5232
5233         if (sc->bce_npoll.ifpc_stcount-- == 0) {
5234                 uint32_t status_attn_bits;
5235
5236                 sc->bce_npoll.ifpc_stcount = sc->bce_npoll.ifpc_stfrac;
5237
5238                 status_attn_bits = sblk->status_attn_bits;
5239
5240                 /* Was it a link change interrupt? */
5241                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5242                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5243                         bce_phy_intr(sc);
5244
5245                 /*
5246                  * Clear any transient status updates during link state change.
5247                  */
5248                 REG_WR(sc, BCE_HC_COMMAND,
5249                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5250                 REG_RD(sc, BCE_HC_COMMAND);
5251
5252                 /*
5253                  * If any other attention is asserted then the chip is toast.
5254                  */
5255                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5256                      (sblk->status_attn_bits_ack &
5257                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5258                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5259                                   sblk->status_attn_bits);
5260                         bce_init(sc);
5261                         return;
5262                 }
5263         }
5264
5265         hw_rx_cons = bce_get_hw_rx_cons(sc);
5266         hw_tx_cons = bce_get_hw_tx_cons(sc);
5267
5268         /* Check for any completed RX frames. */
5269         if (hw_rx_cons != sc->rx_cons)
5270                 bce_rx_intr(sc, count, hw_rx_cons);
5271
5272         /* Check for any completed TX frames. */
5273         if (hw_tx_cons != sc->tx_cons)
5274                 bce_tx_intr(sc, hw_tx_cons);
5275
5276         if (sc->bce_coalchg_mask)
5277                 bce_coal_change(sc);
5278
5279         /* Check for new frames to transmit. */
5280         if (!ifq_is_empty(&ifp->if_snd))
5281                 if_devstart(ifp);
5282 }
5283
5284 static void
5285 bce_npoll(struct ifnet *ifp, struct ifpoll_info *info)
5286 {
5287         struct bce_softc *sc = ifp->if_softc;
5288
5289         ASSERT_SERIALIZED(ifp->if_serializer);
5290
5291         if (info != NULL) {
5292                 int cpuid = sc->bce_npoll.ifpc_cpuid;
5293
5294                 info->ifpi_rx[cpuid].poll_func = bce_npoll_compat;
5295                 info->ifpi_rx[cpuid].arg = NULL;
5296                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
5297
5298                 if (ifp->if_flags & IFF_RUNNING) {
5299                         bce_disable_intr(sc);
5300
5301                         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5302                                (1 << 16) | sc->bce_rx_quick_cons_trip);
5303                         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5304                                (1 << 16) | sc->bce_tx_quick_cons_trip);
5305                 }
5306                 ifq_set_cpuid(&ifp->if_snd, cpuid);
5307         } else {
5308                 if (ifp->if_flags & IFF_RUNNING) {
5309                         bce_enable_intr(sc);
5310
5311                         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5312                                (sc->bce_tx_quick_cons_trip_int << 16) |
5313                                sc->bce_tx_quick_cons_trip);
5314                         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5315                                (sc->bce_rx_quick_cons_trip_int << 16) |
5316                                sc->bce_rx_quick_cons_trip);
5317                 }
5318                 ifq_set_cpuid(&ifp->if_snd, sc->bce_intr_cpuid);
5319         }
5320 }
5321
5322 #endif  /* IFPOLL_ENABLE */
5323
5324
5325 /*
5326  * Interrupt handler.
5327  */
5328 /****************************************************************************/
5329 /* Main interrupt entry point.  Verifies that the controller generated the  */
5330 /* interrupt and then calls a separate routine for handle the various       */
5331 /* interrupt causes (PHY, TX, RX).                                          */
5332 /*                                                                          */
5333 /* Returns:                                                                 */
5334 /*   0 for success, positive value for failure.                             */
5335 /****************************************************************************/
5336 static void
5337 bce_intr(struct bce_softc *sc)
5338 {
5339         struct ifnet *ifp = &sc->arpcom.ac_if;
5340         struct status_block *sblk;
5341         uint16_t hw_rx_cons, hw_tx_cons;
5342         uint32_t status_attn_bits;
5343
5344         ASSERT_SERIALIZED(ifp->if_serializer);
5345
5346         sblk = sc->status_block;
5347
5348         /*
5349          * Save the status block index value for use during
5350          * the next interrupt.
5351          */
5352         sc->last_status_idx = sblk->status_idx;
5353
5354         /* Make sure status index is extracted before rx/tx cons */
5355         cpu_lfence();
5356
5357         /* Check if the hardware has finished any work. */
5358         hw_rx_cons = bce_get_hw_rx_cons(sc);
5359         hw_tx_cons = bce_get_hw_tx_cons(sc);
5360
5361         status_attn_bits = sblk->status_attn_bits;
5362
5363         /* Was it a link change interrupt? */
5364         if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5365             (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5366                 bce_phy_intr(sc);
5367
5368                 /*
5369                  * Clear any transient status updates during link state
5370                  * change.
5371                  */
5372                 REG_WR(sc, BCE_HC_COMMAND,
5373                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5374                 REG_RD(sc, BCE_HC_COMMAND);
5375         }
5376
5377         /*
5378          * If any other attention is asserted then
5379          * the chip is toast.
5380          */
5381         if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5382             (sblk->status_attn_bits_ack & ~STATUS_ATTN_BITS_LINK_STATE)) {
5383                 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5384                           sblk->status_attn_bits);
5385                 bce_init(sc);
5386                 return;
5387         }
5388
5389         /* Check for any completed RX frames. */
5390         if (hw_rx_cons != sc->rx_cons)
5391                 bce_rx_intr(sc, -1, hw_rx_cons);
5392
5393         /* Check for any completed TX frames. */
5394         if (hw_tx_cons != sc->tx_cons)
5395                 bce_tx_intr(sc, hw_tx_cons);
5396
5397         /* Re-enable interrupts. */
5398         bce_reenable_intr(sc);
5399
5400         if (sc->bce_coalchg_mask)
5401                 bce_coal_change(sc);
5402
5403         /* Handle any frames that arrived while handling the interrupt. */
5404         if (!ifq_is_empty(&ifp->if_snd))
5405                 if_devstart(ifp);
5406 }
5407
5408 static void
5409 bce_intr_legacy(void *xsc)
5410 {
5411         struct bce_softc *sc = xsc;
5412         struct status_block *sblk;
5413
5414         sblk = sc->status_block;
5415
5416         /*
5417          * If the hardware status block index matches the last value
5418          * read by the driver and we haven't asserted our interrupt
5419          * then there's nothing to do.
5420          */
5421         if (sblk->status_idx == sc->last_status_idx &&
5422             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5423              BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5424                 return;
5425
5426         /* Ack the interrupt and stop others from occuring. */
5427         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5428                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5429                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5430
5431         /*
5432          * Read back to deassert IRQ immediately to avoid too
5433          * many spurious interrupts.
5434          */
5435         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
5436
5437         bce_intr(sc);
5438 }
5439
5440 static void
5441 bce_intr_msi(void *xsc)
5442 {
5443         struct bce_softc *sc = xsc;
5444
5445         /* Ack the interrupt and stop others from occuring. */
5446         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5447                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5448                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5449
5450         bce_intr(sc);
5451 }
5452
5453 static void
5454 bce_intr_msi_oneshot(void *xsc)
5455 {
5456         bce_intr(xsc);
5457 }
5458
5459
5460 /****************************************************************************/
5461 /* Programs the various packet receive modes (broadcast and multicast).     */
5462 /*                                                                          */
5463 /* Returns:                                                                 */
5464 /*   Nothing.                                                               */
5465 /****************************************************************************/
5466 static void
5467 bce_set_rx_mode(struct bce_softc *sc)
5468 {
5469         struct ifnet *ifp = &sc->arpcom.ac_if;
5470         struct ifmultiaddr *ifma;
5471         uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5472         uint32_t rx_mode, sort_mode;
5473         int h, i;
5474
5475         ASSERT_SERIALIZED(ifp->if_serializer);
5476
5477         /* Initialize receive mode default settings. */
5478         rx_mode = sc->rx_mode &
5479                   ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5480                     BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5481         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5482
5483         /*
5484          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5485          * be enbled.
5486          */
5487         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5488             !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5489                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5490
5491         /*
5492          * Check for promiscuous, all multicast, or selected
5493          * multicast address filtering.
5494          */
5495         if (ifp->if_flags & IFF_PROMISC) {
5496                 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5497
5498                 /* Enable promiscuous mode. */
5499                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5500                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5501         } else if (ifp->if_flags & IFF_ALLMULTI) {
5502                 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5503
5504                 /* Enable all multicast addresses. */
5505                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5506                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5507                                0xffffffff);
5508                 }
5509                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5510         } else {
5511                 /* Accept one or more multicast(s). */
5512                 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5513
5514                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5515                         if (ifma->ifma_addr->sa_family != AF_LINK)
5516                                 continue;
5517                         h = ether_crc32_le(
5518                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5519                             ETHER_ADDR_LEN) & 0xFF;
5520                         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5521                 }
5522
5523                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5524                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5525                                hashes[i]);
5526                 }
5527                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5528         }
5529
5530         /* Only make changes if the recive mode has actually changed. */
5531         if (rx_mode != sc->rx_mode) {
5532                 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5533                         rx_mode);
5534
5535                 sc->rx_mode = rx_mode;
5536                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5537         }
5538
5539         /* Disable and clear the exisitng sort before enabling a new sort. */
5540         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5541         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5542         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5543 }
5544
5545
5546 /****************************************************************************/
5547 /* Called periodically to updates statistics from the controllers           */
5548 /* statistics block.                                                        */
5549 /*                                                                          */
5550 /* Returns:                                                                 */
5551 /*   Nothing.                                                               */
5552 /****************************************************************************/
5553 static void
5554 bce_stats_update(struct bce_softc *sc)
5555 {
5556         struct ifnet *ifp = &sc->arpcom.ac_if;
5557         struct statistics_block *stats = sc->stats_block;
5558
5559         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5560
5561         ASSERT_SERIALIZED(ifp->if_serializer);
5562
5563         /*
5564          * Certain controllers don't report carrier sense errors correctly.
5565          * See errata E11_5708CA0_1165.
5566          */
5567         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5568             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5569                 ifp->if_oerrors +=
5570                         (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5571         }
5572
5573         /*
5574          * Update the sysctl statistics from the hardware statistics.
5575          */
5576         sc->stat_IfHCInOctets =
5577                 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5578                  (uint64_t)stats->stat_IfHCInOctets_lo;
5579
5580         sc->stat_IfHCInBadOctets =
5581                 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5582                  (uint64_t)stats->stat_IfHCInBadOctets_lo;
5583
5584         sc->stat_IfHCOutOctets =
5585                 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5586                  (uint64_t)stats->stat_IfHCOutOctets_lo;
5587
5588         sc->stat_IfHCOutBadOctets =
5589                 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5590                  (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5591
5592         sc->stat_IfHCInUcastPkts =
5593                 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5594                  (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5595
5596         sc->stat_IfHCInMulticastPkts =
5597                 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5598                  (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5599
5600         sc->stat_IfHCInBroadcastPkts =
5601                 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5602                  (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5603
5604         sc->stat_IfHCOutUcastPkts =
5605                 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5606                  (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5607
5608         sc->stat_IfHCOutMulticastPkts =
5609                 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5610                  (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5611
5612         sc->stat_IfHCOutBroadcastPkts =
5613                 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5614                  (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5615
5616         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5617                 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5618
5619         sc->stat_Dot3StatsCarrierSenseErrors =
5620                 stats->stat_Dot3StatsCarrierSenseErrors;
5621
5622         sc->stat_Dot3StatsFCSErrors =
5623                 stats->stat_Dot3StatsFCSErrors;
5624
5625         sc->stat_Dot3StatsAlignmentErrors =
5626                 stats->stat_Dot3StatsAlignmentErrors;
5627
5628         sc->stat_Dot3StatsSingleCollisionFrames =
5629                 stats->stat_Dot3StatsSingleCollisionFrames;
5630
5631         sc->stat_Dot3StatsMultipleCollisionFrames =
5632                 stats->stat_Dot3StatsMultipleCollisionFrames;
5633
5634         sc->stat_Dot3StatsDeferredTransmissions =
5635                 stats->stat_Dot3StatsDeferredTransmissions;
5636
5637         sc->stat_Dot3StatsExcessiveCollisions =
5638                 stats->stat_Dot3StatsExcessiveCollisions;
5639
5640         sc->stat_Dot3StatsLateCollisions =
5641                 stats->stat_Dot3StatsLateCollisions;
5642
5643         sc->stat_EtherStatsCollisions =
5644                 stats->stat_EtherStatsCollisions;
5645
5646         sc->stat_EtherStatsFragments =
5647                 stats->stat_EtherStatsFragments;
5648
5649         sc->stat_EtherStatsJabbers =
5650                 stats->stat_EtherStatsJabbers;
5651
5652         sc->stat_EtherStatsUndersizePkts =
5653                 stats->stat_EtherStatsUndersizePkts;
5654
5655         sc->stat_EtherStatsOverrsizePkts =
5656                 stats->stat_EtherStatsOverrsizePkts;
5657
5658         sc->stat_EtherStatsPktsRx64Octets =
5659                 stats->stat_EtherStatsPktsRx64Octets;
5660
5661         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5662                 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5663
5664         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5665                 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5666
5667         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5668                 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5669
5670         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5671                 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5672
5673         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5674                 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5675
5676         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5677                 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5678
5679         sc->stat_EtherStatsPktsTx64Octets =
5680                 stats->stat_EtherStatsPktsTx64Octets;
5681
5682         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5683                 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5684
5685         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5686                 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5687
5688         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5689                 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5690
5691         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5692                 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5693
5694         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5695                 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5696
5697         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5698                 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5699
5700         sc->stat_XonPauseFramesReceived =
5701                 stats->stat_XonPauseFramesReceived;
5702
5703         sc->stat_XoffPauseFramesReceived =
5704                 stats->stat_XoffPauseFramesReceived;
5705
5706         sc->stat_OutXonSent =
5707                 stats->stat_OutXonSent;
5708
5709         sc->stat_OutXoffSent =
5710                 stats->stat_OutXoffSent;
5711
5712         sc->stat_FlowControlDone =
5713                 stats->stat_FlowControlDone;
5714
5715         sc->stat_MacControlFramesReceived =
5716                 stats->stat_MacControlFramesReceived;
5717
5718         sc->stat_XoffStateEntered =
5719                 stats->stat_XoffStateEntered;
5720
5721         sc->stat_IfInFramesL2FilterDiscards =
5722                 stats->stat_IfInFramesL2FilterDiscards;
5723
5724         sc->stat_IfInRuleCheckerDiscards =
5725                 stats->stat_IfInRuleCheckerDiscards;
5726
5727         sc->stat_IfInFTQDiscards =
5728                 stats->stat_IfInFTQDiscards;
5729
5730         sc->stat_IfInMBUFDiscards =
5731                 stats->stat_IfInMBUFDiscards;
5732
5733         sc->stat_IfInRuleCheckerP4Hit =
5734                 stats->stat_IfInRuleCheckerP4Hit;
5735
5736         sc->stat_CatchupInRuleCheckerDiscards =
5737                 stats->stat_CatchupInRuleCheckerDiscards;
5738
5739         sc->stat_CatchupInFTQDiscards =
5740                 stats->stat_CatchupInFTQDiscards;
5741
5742         sc->stat_CatchupInMBUFDiscards =
5743                 stats->stat_CatchupInMBUFDiscards;
5744
5745         sc->stat_CatchupInRuleCheckerP4Hit =
5746                 stats->stat_CatchupInRuleCheckerP4Hit;
5747
5748         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5749
5750         /*
5751          * Update the interface statistics from the
5752          * hardware statistics.
5753          */
5754         ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5755
5756         ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5757             (u_long)sc->stat_EtherStatsOverrsizePkts +
5758             (u_long)sc->stat_IfInMBUFDiscards +
5759             (u_long)sc->stat_Dot3StatsAlignmentErrors +
5760             (u_long)sc->stat_Dot3StatsFCSErrors +
5761             (u_long)sc->stat_IfInRuleCheckerDiscards +
5762             (u_long)sc->stat_IfInFTQDiscards +
5763             (u_long)sc->com_no_buffers;
5764
5765         ifp->if_oerrors =
5766             (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5767             (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5768             (u_long)sc->stat_Dot3StatsLateCollisions;
5769
5770         DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5771 }
5772
5773
5774 /****************************************************************************/
5775 /* Periodic function to notify the bootcode that the driver is still        */
5776 /* present.                                                                 */
5777 /*                                                                          */
5778 /* Returns:                                                                 */
5779 /*   Nothing.                                                               */
5780 /****************************************************************************/
5781 static void
5782 bce_pulse(void *xsc)
5783 {
5784         struct bce_softc *sc = xsc;
5785         struct ifnet *ifp = &sc->arpcom.ac_if;
5786         uint32_t msg;
5787
5788         lwkt_serialize_enter(ifp->if_serializer);
5789
5790         /* Tell the firmware that the driver is still running. */
5791         msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5792         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
5793
5794         /* Update the bootcode condition. */
5795         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
5796
5797         /* Report whether the bootcode still knows the driver is running. */
5798         if (!sc->bce_drv_cardiac_arrest) {
5799                 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
5800                         sc->bce_drv_cardiac_arrest = 1;
5801                         if_printf(ifp, "Bootcode lost the driver pulse! "
5802                             "(bc_state = 0x%08X)\n", sc->bc_state);
5803                 }
5804         } else {
5805                 /*
5806                  * Not supported by all bootcode versions.
5807                  * (v5.0.11+ and v5.2.1+)  Older bootcode
5808                  * will require the driver to reset the
5809                  * controller to clear this condition.
5810                  */
5811                 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
5812                         sc->bce_drv_cardiac_arrest = 0;
5813                         if_printf(ifp, "Bootcode found the driver pulse! "
5814                             "(bc_state = 0x%08X)\n", sc->bc_state);
5815                 }
5816         }
5817
5818         /* Schedule the next pulse. */
5819         callout_reset_bycpu(&sc->bce_pulse_callout, hz, bce_pulse, sc,
5820             sc->bce_intr_cpuid);
5821
5822         lwkt_serialize_exit(ifp->if_serializer);
5823 }
5824
5825
5826 /****************************************************************************/
5827 /* Periodic function to check whether MSI is lost                           */
5828 /*                                                                          */
5829 /* Returns:                                                                 */
5830 /*   Nothing.                                                               */
5831 /****************************************************************************/
5832 static void
5833 bce_check_msi(void *xsc)
5834 {
5835         struct bce_softc *sc = xsc;
5836         struct ifnet *ifp = &sc->arpcom.ac_if;
5837         struct status_block *sblk = sc->status_block;
5838
5839         lwkt_serialize_enter(ifp->if_serializer);
5840
5841         KKASSERT(mycpuid == sc->bce_intr_cpuid);
5842
5843         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
5844                 lwkt_serialize_exit(ifp->if_serializer);
5845                 return;
5846         }
5847
5848         if (bce_get_hw_rx_cons(sc) != sc->rx_cons ||
5849             bce_get_hw_tx_cons(sc) != sc->tx_cons ||
5850             (sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5851             (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5852                 if (sc->bce_check_rx_cons == sc->rx_cons &&
5853                     sc->bce_check_tx_cons == sc->tx_cons &&
5854                     sc->bce_check_status_idx == sc->last_status_idx) {
5855                         uint32_t msi_ctrl;
5856
5857                         if (!sc->bce_msi_maylose) {
5858                                 sc->bce_msi_maylose = TRUE;
5859                                 goto done;
5860                         }
5861
5862                         msi_ctrl = REG_RD(sc, BCE_PCICFG_MSI_CONTROL);
5863                         if (msi_ctrl & BCE_PCICFG_MSI_CONTROL_ENABLE) {
5864                                 if (bootverbose)
5865                                         if_printf(ifp, "lost MSI\n");
5866
5867                                 REG_WR(sc, BCE_PCICFG_MSI_CONTROL,
5868                                     msi_ctrl & ~BCE_PCICFG_MSI_CONTROL_ENABLE);
5869                                 REG_WR(sc, BCE_PCICFG_MSI_CONTROL, msi_ctrl);
5870
5871                                 bce_intr_msi(sc);
5872                         } else if (bootverbose) {
5873                                 if_printf(ifp, "MSI may be lost\n");
5874                         }
5875                 }
5876         }
5877         sc->bce_msi_maylose = FALSE;
5878         sc->bce_check_rx_cons = sc->rx_cons;
5879         sc->bce_check_tx_cons = sc->tx_cons;
5880         sc->bce_check_status_idx = sc->last_status_idx;
5881
5882 done:
5883         callout_reset(&sc->bce_ckmsi_callout, BCE_MSI_CKINTVL,
5884             bce_check_msi, sc);
5885         lwkt_serialize_exit(ifp->if_serializer);
5886 }
5887
5888
5889 /****************************************************************************/
5890 /* Periodic function to perform maintenance tasks.                          */
5891 /*                                                                          */
5892 /* Returns:                                                                 */
5893 /*   Nothing.                                                               */
5894 /****************************************************************************/
5895 static void
5896 bce_tick_serialized(struct bce_softc *sc)
5897 {
5898         struct ifnet *ifp = &sc->arpcom.ac_if;
5899         struct mii_data *mii;
5900
5901         ASSERT_SERIALIZED(ifp->if_serializer);
5902
5903         /* Update the statistics from the hardware statistics block. */
5904         bce_stats_update(sc);
5905
5906         /* Schedule the next tick. */
5907         callout_reset_bycpu(&sc->bce_tick_callout, hz, bce_tick, sc,
5908             sc->bce_intr_cpuid);
5909
5910         /* If link is up already up then we're done. */
5911         if (sc->bce_link)
5912                 return;
5913
5914         mii = device_get_softc(sc->bce_miibus);
5915         mii_tick(mii);
5916
5917         /* Check if the link has come up. */
5918         if ((mii->mii_media_status & IFM_ACTIVE) &&
5919             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5920                 sc->bce_link++;
5921                 /* Now that link is up, handle any outstanding TX traffic. */
5922                 if (!ifq_is_empty(&ifp->if_snd))
5923                         if_devstart(ifp);
5924         }
5925 }
5926
5927
5928 static void
5929 bce_tick(void *xsc)
5930 {
5931         struct bce_softc *sc = xsc;
5932         struct ifnet *ifp = &sc->arpcom.ac_if;
5933
5934         lwkt_serialize_enter(ifp->if_serializer);
5935         bce_tick_serialized(sc);
5936         lwkt_serialize_exit(ifp->if_serializer);
5937 }
5938
5939
5940 #ifdef BCE_DEBUG
5941 /****************************************************************************/
5942 /* Allows the driver state to be dumped through the sysctl interface.       */
5943 /*                                                                          */
5944 /* Returns:                                                                 */
5945 /*   0 for success, positive value for failure.                             */
5946 /****************************************************************************/
5947 static int
5948 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5949 {
5950         int error;
5951         int result;
5952         struct bce_softc *sc;
5953
5954         result = -1;
5955         error = sysctl_handle_int(oidp, &result, 0, req);
5956
5957         if (error || !req->newptr)
5958                 return (error);
5959
5960         if (result == 1) {
5961                 sc = (struct bce_softc *)arg1;
5962                 bce_dump_driver_state(sc);
5963         }
5964
5965         return error;
5966 }
5967
5968
5969 /****************************************************************************/
5970 /* Allows the hardware state to be dumped through the sysctl interface.     */
5971 /*                                                                          */
5972 /* Returns:                                                                 */
5973 /*   0 for success, positive value for failure.                             */
5974 /****************************************************************************/
5975 static int
5976 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5977 {
5978         int error;
5979         int result;
5980         struct bce_softc *sc;
5981
5982         result = -1;
5983         error = sysctl_handle_int(oidp, &result, 0, req);
5984
5985         if (error || !req->newptr)
5986                 return (error);
5987
5988         if (result == 1) {
5989                 sc = (struct bce_softc *)arg1;
5990                 bce_dump_hw_state(sc);
5991         }
5992
5993         return error;
5994 }
5995
5996
5997 /****************************************************************************/
5998 /* Provides a sysctl interface to allows dumping the RX chain.              */
5999 /*                                                                          */
6000 /* Returns:                                                                 */
6001 /*   0 for success, positive value for failure.                             */
6002 /****************************************************************************/
6003 static int
6004 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
6005 {
6006         int error;
6007         int result;
6008         struct bce_softc *sc;
6009
6010         result = -1;
6011         error = sysctl_handle_int(oidp, &result, 0, req);
6012
6013         if (error || !req->newptr)
6014                 return (error);
6015
6016         if (result == 1) {
6017                 sc = (struct bce_softc *)arg1;
6018                 bce_dump_rx_chain(sc, 0, USABLE_RX_BD(sc));
6019         }
6020
6021         return error;
6022 }
6023
6024
6025 /****************************************************************************/
6026 /* Provides a sysctl interface to allows dumping the TX chain.              */
6027 /*                                                                          */
6028 /* Returns:                                                                 */
6029 /*   0 for success, positive value for failure.                             */
6030 /****************************************************************************/
6031 static int
6032 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
6033 {
6034         int error;
6035         int result;
6036         struct bce_softc *sc;
6037
6038         result = -1;
6039         error = sysctl_handle_int(oidp, &result, 0, req);
6040
6041         if (error || !req->newptr)
6042                 return (error);
6043
6044         if (result == 1) {
6045                 sc = (struct bce_softc *)arg1;
6046                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD(sc));
6047         }
6048
6049         return error;
6050 }
6051
6052
6053 /****************************************************************************/
6054 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
6055 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
6056 /*                                                                          */
6057 /* Returns:                                                                 */
6058 /*   0 for success, positive value for failure.                             */
6059 /****************************************************************************/
6060 static int
6061 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6062 {
6063         struct bce_softc *sc;
6064         int error;
6065         uint32_t val, result;
6066
6067         result = -1;
6068         error = sysctl_handle_int(oidp, &result, 0, req);
6069         if (error || (req->newptr == NULL))
6070                 return (error);
6071
6072         /* Make sure the register is accessible. */
6073         if (result < 0x8000) {
6074                 sc = (struct bce_softc *)arg1;
6075                 val = REG_RD(sc, result);
6076                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6077                           result, val);
6078         } else if (result < 0x0280000) {
6079                 sc = (struct bce_softc *)arg1;
6080                 val = REG_RD_IND(sc, result);
6081                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6082                           result, val);
6083         }
6084         return (error);
6085 }
6086
6087
6088 /****************************************************************************/
6089 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
6090 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
6091 /*                                                                          */
6092 /* Returns:                                                                 */
6093 /*   0 for success, positive value for failure.                             */
6094 /****************************************************************************/
6095 static int
6096 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
6097 {
6098         struct bce_softc *sc;
6099         device_t dev;
6100         int error, result;
6101         uint16_t val;
6102
6103         result = -1;
6104         error = sysctl_handle_int(oidp, &result, 0, req);
6105         if (error || (req->newptr == NULL))
6106                 return (error);
6107
6108         /* Make sure the register is accessible. */
6109         if (result < 0x20) {
6110                 sc = (struct bce_softc *)arg1;
6111                 dev = sc->bce_dev;
6112                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
6113                 if_printf(&sc->arpcom.ac_if,
6114                           "phy 0x%02X = 0x%04X\n", result, val);
6115         }
6116         return (error);
6117 }
6118
6119
6120 /****************************************************************************/
6121 /* Provides a sysctl interface to forcing the driver to dump state and      */
6122 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
6123 /*                                                                          */
6124 /* Returns:                                                                 */
6125 /*   0 for success, positive value for failure.                             */
6126 /****************************************************************************/
6127 static int
6128 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
6129 {
6130         int error;
6131         int result;
6132         struct bce_softc *sc;
6133
6134         result = -1;
6135         error = sysctl_handle_int(oidp, &result, 0, req);
6136
6137         if (error || !req->newptr)
6138                 return (error);
6139
6140         if (result == 1) {
6141                 sc = (struct bce_softc *)arg1;
6142                 bce_breakpoint(sc);
6143         }
6144
6145         return error;
6146 }
6147 #endif
6148
6149
6150 /****************************************************************************/
6151 /* Adds any sysctl parameters for tuning or debugging purposes.             */
6152 /*                                                                          */
6153 /* Returns:                                                                 */
6154 /*   0 for success, positive value for failure.                             */
6155 /****************************************************************************/
6156 static void
6157 bce_add_sysctls(struct bce_softc *sc)
6158 {
6159         struct sysctl_ctx_list *ctx;
6160         struct sysctl_oid_list *children;
6161
6162         sysctl_ctx_init(&sc->bce_sysctl_ctx);
6163         sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
6164                                               SYSCTL_STATIC_CHILDREN(_hw),
6165                                               OID_AUTO,
6166                                               device_get_nameunit(sc->bce_dev),
6167                                               CTLFLAG_RD, 0, "");
6168         if (sc->bce_sysctl_tree == NULL) {
6169                 device_printf(sc->bce_dev, "can't add sysctl node\n");
6170                 return;
6171         }
6172
6173         ctx = &sc->bce_sysctl_ctx;
6174         children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
6175
6176         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
6177                         CTLTYPE_INT | CTLFLAG_RW,
6178                         sc, 0, bce_sysctl_tx_bds_int, "I",
6179                         "Send max coalesced BD count during interrupt");
6180         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
6181                         CTLTYPE_INT | CTLFLAG_RW,
6182                         sc, 0, bce_sysctl_tx_bds, "I",
6183                         "Send max coalesced BD count");
6184         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
6185                         CTLTYPE_INT | CTLFLAG_RW,
6186                         sc, 0, bce_sysctl_tx_ticks_int, "I",
6187                         "Send coalescing ticks during interrupt");
6188         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
6189                         CTLTYPE_INT | CTLFLAG_RW,
6190                         sc, 0, bce_sysctl_tx_ticks, "I",
6191                         "Send coalescing ticks");
6192
6193         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
6194                         CTLTYPE_INT | CTLFLAG_RW,
6195                         sc, 0, bce_sysctl_rx_bds_int, "I",
6196                         "Receive max coalesced BD count during interrupt");
6197         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
6198                         CTLTYPE_INT | CTLFLAG_RW,
6199                         sc, 0, bce_sysctl_rx_bds, "I",
6200                         "Receive max coalesced BD count");
6201         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
6202                         CTLTYPE_INT | CTLFLAG_RW,
6203                         sc, 0, bce_sysctl_rx_ticks_int, "I",
6204                         "Receive coalescing ticks during interrupt");
6205         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
6206                         CTLTYPE_INT | CTLFLAG_RW,
6207                         sc, 0, bce_sysctl_rx_ticks, "I",
6208                         "Receive coalescing ticks");
6209
6210         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_pages",
6211                 CTLFLAG_RD, &sc->rx_pages, 0, "# of RX pages");
6212         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_pages",
6213                 CTLFLAG_RD, &sc->tx_pages, 0, "# of TX pages");
6214
6215         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_wreg",
6216                 CTLFLAG_RW, &sc->tx_wreg, 0,
6217                 "# segments before write to hardware registers");
6218
6219 #ifdef BCE_DEBUG
6220         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6221                 "rx_low_watermark",
6222                 CTLFLAG_RD, &sc->rx_low_watermark,
6223                 0, "Lowest level of free rx_bd's");
6224
6225         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6226                 "rx_empty_count",
6227                 CTLFLAG_RD, &sc->rx_empty_count,
6228                 0, "Number of times the RX chain was empty");
6229
6230         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6231                 "tx_hi_watermark",
6232                 CTLFLAG_RD, &sc->tx_hi_watermark,
6233                 0, "Highest level of used tx_bd's");
6234
6235         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6236                 "tx_full_count",
6237                 CTLFLAG_RD, &sc->tx_full_count,
6238                 0, "Number of times the TX chain was full");
6239
6240         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6241                 "l2fhdr_status_errors",
6242                 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6243                 0, "l2_fhdr status errors");
6244
6245         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6246                 "unexpected_attentions",
6247                 CTLFLAG_RD, &sc->unexpected_attentions,
6248                 0, "unexpected attentions");
6249
6250         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6251                 "lost_status_block_updates",
6252                 CTLFLAG_RD, &sc->lost_status_block_updates,
6253                 0, "lost status block updates");
6254
6255         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6256                 "mbuf_alloc_failed",
6257                 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6258                 0, "mbuf cluster allocation failures");
6259 #endif
6260
6261         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6262                 "stat_IfHCInOctets",
6263                 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6264                 "Bytes received");
6265
6266         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6267                 "stat_IfHCInBadOctets",
6268                 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6269                 "Bad bytes received");
6270
6271         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6272                 "stat_IfHCOutOctets",
6273                 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6274                 "Bytes sent");
6275
6276         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6277                 "stat_IfHCOutBadOctets",
6278                 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6279                 "Bad bytes sent");
6280
6281         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6282                 "stat_IfHCInUcastPkts",
6283                 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6284                 "Unicast packets received");
6285
6286         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6287                 "stat_IfHCInMulticastPkts",
6288                 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6289                 "Multicast packets received");
6290
6291         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6292                 "stat_IfHCInBroadcastPkts",
6293                 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6294                 "Broadcast packets received");
6295
6296         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6297                 "stat_IfHCOutUcastPkts",
6298                 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6299                 "Unicast packets sent");
6300
6301         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6302                 "stat_IfHCOutMulticastPkts",
6303                 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6304                 "Multicast packets sent");
6305
6306         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6307                 "stat_IfHCOutBroadcastPkts",
6308                 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6309                 "Broadcast packets sent");
6310
6311         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6312                 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6313                 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6314                 0, "Internal MAC transmit errors");
6315
6316         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6317                 "stat_Dot3StatsCarrierSenseErrors",
6318                 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6319                 0, "Carrier sense errors");
6320
6321         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6322                 "stat_Dot3StatsFCSErrors",
6323                 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6324                 0, "Frame check sequence errors");
6325
6326         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6327                 "stat_Dot3StatsAlignmentErrors",
6328                 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6329                 0, "Alignment errors");
6330
6331         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6332                 "stat_Dot3StatsSingleCollisionFrames",
6333                 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6334                 0, "Single Collision Frames");
6335
6336         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6337                 "stat_Dot3StatsMultipleCollisionFrames",
6338                 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6339                 0, "Multiple Collision Frames");
6340
6341         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6342                 "stat_Dot3StatsDeferredTransmissions",
6343                 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6344                 0, "Deferred Transmissions");
6345
6346         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6347                 "stat_Dot3StatsExcessiveCollisions",
6348                 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6349                 0, "Excessive Collisions");
6350
6351         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6352                 "stat_Dot3StatsLateCollisions",
6353                 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6354                 0, "Late Collisions");
6355
6356         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6357                 "stat_EtherStatsCollisions",
6358                 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6359                 0, "Collisions");
6360
6361         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6362                 "stat_EtherStatsFragments",
6363                 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6364                 0, "Fragments");
6365
6366         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6367                 "stat_EtherStatsJabbers",
6368                 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6369                 0, "Jabbers");
6370
6371         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6372                 "stat_EtherStatsUndersizePkts",
6373                 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6374                 0, "Undersize packets");
6375
6376         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6377                 "stat_EtherStatsOverrsizePkts",
6378                 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6379                 0, "stat_EtherStatsOverrsizePkts");
6380
6381         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6382                 "stat_EtherStatsPktsRx64Octets",
6383                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6384                 0, "Bytes received in 64 byte packets");
6385
6386         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6387                 "stat_EtherStatsPktsRx65Octetsto127Octets",
6388                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6389                 0, "Bytes received in 65 to 127 byte packets");
6390
6391         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6392                 "stat_EtherStatsPktsRx128Octetsto255Octets",
6393                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6394                 0, "Bytes received in 128 to 255 byte packets");
6395
6396         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6397                 "stat_EtherStatsPktsRx256Octetsto511Octets",
6398                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6399                 0, "Bytes received in 256 to 511 byte packets");
6400
6401         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6402                 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6403                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6404                 0, "Bytes received in 512 to 1023 byte packets");
6405
6406         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6407                 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6408                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6409                 0, "Bytes received in 1024 t0 1522 byte packets");
6410
6411         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6412                 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6413                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6414                 0, "Bytes received in 1523 to 9022 byte packets");
6415
6416         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6417                 "stat_EtherStatsPktsTx64Octets",
6418                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6419                 0, "Bytes sent in 64 byte packets");
6420
6421         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6422                 "stat_EtherStatsPktsTx65Octetsto127Octets",
6423                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6424                 0, "Bytes sent in 65 to 127 byte packets");
6425
6426         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6427                 "stat_EtherStatsPktsTx128Octetsto255Octets",
6428                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6429                 0, "Bytes sent in 128 to 255 byte packets");
6430
6431         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6432                 "stat_EtherStatsPktsTx256Octetsto511Octets",
6433                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6434                 0, "Bytes sent in 256 to 511 byte packets");
6435
6436         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6437                 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6438                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6439                 0, "Bytes sent in 512 to 1023 byte packets");
6440
6441         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6442                 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6443                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6444                 0, "Bytes sent in 1024 to 1522 byte packets");
6445
6446         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6447                 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6448                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6449                 0, "Bytes sent in 1523 to 9022 byte packets");
6450
6451         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6452                 "stat_XonPauseFramesReceived",
6453                 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6454                 0, "XON pause frames receved");
6455
6456         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6457                 "stat_XoffPauseFramesReceived",
6458                 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6459                 0, "XOFF pause frames received");
6460
6461         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6462                 "stat_OutXonSent",
6463                 CTLFLAG_RD, &sc->stat_OutXonSent,
6464                 0, "XON pause frames sent");
6465
6466         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6467                 "stat_OutXoffSent",
6468                 CTLFLAG_RD, &sc->stat_OutXoffSent,
6469                 0, "XOFF pause frames sent");
6470
6471         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6472                 "stat_FlowControlDone",
6473                 CTLFLAG_RD, &sc->stat_FlowControlDone,
6474                 0, "Flow control done");
6475
6476         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6477                 "stat_MacControlFramesReceived",
6478                 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6479                 0, "MAC control frames received");
6480
6481         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6482                 "stat_XoffStateEntered",
6483                 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6484                 0, "XOFF state entered");
6485
6486         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6487                 "stat_IfInFramesL2FilterDiscards",
6488                 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6489                 0, "Received L2 packets discarded");
6490
6491         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6492                 "stat_IfInRuleCheckerDiscards",
6493                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6494                 0, "Received packets discarded by rule");
6495
6496         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6497                 "stat_IfInFTQDiscards",
6498                 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6499                 0, "Received packet FTQ discards");
6500
6501         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6502                 "stat_IfInMBUFDiscards",
6503                 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6504                 0, "Received packets discarded due to lack of controller buffer memory");
6505
6506         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6507                 "stat_IfInRuleCheckerP4Hit",
6508                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6509                 0, "Received packets rule checker hits");
6510
6511         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6512                 "stat_CatchupInRuleCheckerDiscards",
6513                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6514                 0, "Received packets discarded in Catchup path");
6515
6516         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6517                 "stat_CatchupInFTQDiscards",
6518                 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6519                 0, "Received packets discarded in FTQ in Catchup path");
6520
6521         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6522                 "stat_CatchupInMBUFDiscards",
6523                 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6524                 0, "Received packets discarded in controller buffer memory in Catchup path");
6525
6526         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6527                 "stat_CatchupInRuleCheckerP4Hit",
6528                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6529                 0, "Received packets rule checker hits in Catchup path");
6530
6531         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6532                 "com_no_buffers",
6533                 CTLFLAG_RD, &sc->com_no_buffers,
6534                 0, "Valid packets received but no RX buffers available");
6535
6536 #ifdef BCE_DEBUG
6537         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6538                 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6539                 (void *)sc, 0,
6540                 bce_sysctl_driver_state, "I", "Drive state information");
6541
6542         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6543                 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6544                 (void *)sc, 0,
6545                 bce_sysctl_hw_state, "I", "Hardware state information");
6546
6547         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6548                 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6549                 (void *)sc, 0,
6550                 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6551
6552         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6553                 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6554                 (void *)sc, 0,
6555                 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6556
6557         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6558                 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6559                 (void *)sc, 0,
6560                 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6561
6562         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6563                 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6564                 (void *)sc, 0,
6565                 bce_sysctl_reg_read, "I", "Register read");
6566
6567         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6568                 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6569                 (void *)sc, 0,
6570                 bce_sysctl_phy_read, "I", "PHY register read");
6571
6572 #endif
6573
6574 }
6575
6576
6577 /****************************************************************************/
6578 /* BCE Debug Routines                                                       */
6579 /****************************************************************************/
6580 #ifdef BCE_DEBUG
6581
6582 /****************************************************************************/
6583 /* Freezes the controller to allow for a cohesive state dump.               */
6584 /*                                                                          */
6585 /* Returns:                                                                 */
6586 /*   Nothing.                                                               */
6587 /****************************************************************************/
6588 static void
6589 bce_freeze_controller(struct bce_softc *sc)
6590 {
6591         uint32_t val;
6592
6593         val = REG_RD(sc, BCE_MISC_COMMAND);
6594         val |= BCE_MISC_COMMAND_DISABLE_ALL;
6595         REG_WR(sc, BCE_MISC_COMMAND, val);
6596 }
6597
6598
6599 /****************************************************************************/
6600 /* Unfreezes the controller after a freeze operation.  This may not always  */
6601 /* work and the controller will require a reset!                            */
6602 /*                                                                          */
6603 /* Returns:                                                                 */
6604 /*   Nothing.                                                               */
6605 /****************************************************************************/
6606 static void
6607 bce_unfreeze_controller(struct bce_softc *sc)
6608 {
6609         uint32_t val;
6610
6611         val = REG_RD(sc, BCE_MISC_COMMAND);
6612         val |= BCE_MISC_COMMAND_ENABLE_ALL;
6613         REG_WR(sc, BCE_MISC_COMMAND, val);
6614 }
6615
6616
6617 /****************************************************************************/
6618 /* Prints out information about an mbuf.                                    */
6619 /*                                                                          */
6620 /* Returns:                                                                 */
6621 /*   Nothing.                                                               */
6622 /****************************************************************************/
6623 static void
6624 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6625 {
6626         struct ifnet *ifp = &sc->arpcom.ac_if;
6627         uint32_t val_hi, val_lo;
6628         struct mbuf *mp = m;
6629
6630         if (m == NULL) {
6631                 /* Index out of range. */
6632                 if_printf(ifp, "mbuf: null pointer\n");
6633                 return;
6634         }
6635
6636         while (mp) {
6637                 val_hi = BCE_ADDR_HI(mp);
6638                 val_lo = BCE_ADDR_LO(mp);
6639                 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6640                           "m_flags = ( ", val_hi, val_lo, mp->m_len);
6641
6642                 if (mp->m_flags & M_EXT)
6643                         kprintf("M_EXT ");
6644                 if (mp->m_flags & M_PKTHDR)
6645                         kprintf("M_PKTHDR ");
6646                 if (mp->m_flags & M_EOR)
6647                         kprintf("M_EOR ");
6648 #ifdef M_RDONLY
6649                 if (mp->m_flags & M_RDONLY)
6650                         kprintf("M_RDONLY ");
6651 #endif
6652
6653                 val_hi = BCE_ADDR_HI(mp->m_data);
6654                 val_lo = BCE_ADDR_LO(mp->m_data);
6655                 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6656
6657                 if (mp->m_flags & M_PKTHDR) {
6658                         if_printf(ifp, "- m_pkthdr: flags = ( ");
6659                         if (mp->m_flags & M_BCAST)
6660                                 kprintf("M_BCAST ");
6661                         if (mp->m_flags & M_MCAST)
6662                                 kprintf("M_MCAST ");
6663                         if (mp->m_flags & M_FRAG)
6664                                 kprintf("M_FRAG ");
6665                         if (mp->m_flags & M_FIRSTFRAG)
6666                                 kprintf("M_FIRSTFRAG ");
6667                         if (mp->m_flags & M_LASTFRAG)
6668                                 kprintf("M_LASTFRAG ");
6669 #ifdef M_VLANTAG
6670                         if (mp->m_flags & M_VLANTAG)
6671                                 kprintf("M_VLANTAG ");
6672 #endif
6673 #ifdef M_PROMISC
6674                         if (mp->m_flags & M_PROMISC)
6675                                 kprintf("M_PROMISC ");
6676 #endif
6677                         kprintf(") csum_flags = ( ");
6678                         if (mp->m_pkthdr.csum_flags & CSUM_IP)
6679                                 kprintf("CSUM_IP ");
6680                         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6681                                 kprintf("CSUM_TCP ");
6682                         if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6683                                 kprintf("CSUM_UDP ");
6684                         if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6685                                 kprintf("CSUM_IP_FRAGS ");
6686                         if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6687                                 kprintf("CSUM_FRAGMENT ");
6688 #ifdef CSUM_TSO
6689                         if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6690                                 kprintf("CSUM_TSO ");
6691 #endif
6692                         if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6693                                 kprintf("CSUM_IP_CHECKED ");
6694                         if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6695                                 kprintf("CSUM_IP_VALID ");
6696                         if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6697                                 kprintf("CSUM_DATA_VALID ");
6698                         kprintf(")\n");
6699                 }
6700
6701                 if (mp->m_flags & M_EXT) {
6702                         val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6703                         val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6704                         if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6705                                   "ext_size = %d\n",
6706                                   val_hi, val_lo, mp->m_ext.ext_size);
6707                 }
6708                 mp = mp->m_next;
6709         }
6710 }
6711
6712
6713 /****************************************************************************/
6714 /* Prints out the mbufs in the RX mbuf chain.                               */
6715 /*                                                                          */
6716 /* Returns:                                                                 */
6717 /*   Nothing.                                                               */
6718 /****************************************************************************/
6719 static void
6720 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6721 {
6722         struct ifnet *ifp = &sc->arpcom.ac_if;
6723         int i;
6724
6725         if_printf(ifp,
6726         "----------------------------"
6727         "  rx mbuf data  "
6728         "----------------------------\n");
6729
6730         for (i = 0; i < count; i++) {
6731                 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6732                 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6733                 chain_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(chain_prod));
6734         }
6735
6736         if_printf(ifp,
6737         "----------------------------"
6738         "----------------"
6739         "----------------------------\n");
6740 }
6741
6742
6743 /****************************************************************************/
6744 /* Prints out a tx_bd structure.                                            */
6745 /*                                                                          */
6746 /* Returns:                                                                 */
6747 /*   Nothing.                                                               */
6748 /****************************************************************************/
6749 static void
6750 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6751 {
6752         struct ifnet *ifp = &sc->arpcom.ac_if;
6753
6754         if (idx > MAX_TX_BD(sc)) {
6755                 /* Index out of range. */
6756                 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6757         } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6758                 /* TX Chain page pointer. */
6759                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6760                           "chain page pointer\n",
6761                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6762         } else {
6763                 /* Normal tx_bd entry. */
6764                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6765                           "nbytes = 0x%08X, "
6766                           "vlan tag= 0x%04X, flags = 0x%04X (",
6767                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6768                           txbd->tx_bd_mss_nbytes,
6769                           txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6770
6771                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6772                         kprintf(" CONN_FAULT");
6773
6774                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6775                         kprintf(" TCP_UDP_CKSUM");
6776
6777                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6778                         kprintf(" IP_CKSUM");
6779
6780                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6781                         kprintf("  VLAN");
6782
6783                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6784                         kprintf(" COAL_NOW");
6785
6786                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6787                         kprintf(" DONT_GEN_CRC");
6788
6789                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6790                         kprintf(" START");
6791
6792                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6793                         kprintf(" END");
6794
6795                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6796                         kprintf(" LSO");
6797
6798                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6799                         kprintf(" OPTION_WORD");
6800
6801                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6802                         kprintf(" FLAGS");
6803
6804                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6805                         kprintf(" SNAP");
6806
6807                 kprintf(" )\n");
6808         }
6809 }
6810
6811
6812 /****************************************************************************/
6813 /* Prints out a rx_bd structure.                                            */
6814 /*                                                                          */
6815 /* Returns:                                                                 */
6816 /*   Nothing.                                                               */
6817 /****************************************************************************/
6818 static void
6819 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6820 {
6821         struct ifnet *ifp = &sc->arpcom.ac_if;
6822
6823         if (idx > MAX_RX_BD(sc)) {
6824                 /* Index out of range. */
6825                 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6826         } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6827                 /* TX Chain page pointer. */
6828                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6829                           "chain page pointer\n",
6830                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6831         } else {
6832                 /* Normal tx_bd entry. */
6833                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6834                           "nbytes = 0x%08X, flags = 0x%08X\n",
6835                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6836                           rxbd->rx_bd_len, rxbd->rx_bd_flags);
6837         }
6838 }
6839
6840
6841 /****************************************************************************/
6842 /* Prints out a l2_fhdr structure.                                          */
6843 /*                                                                          */
6844 /* Returns:                                                                 */
6845 /*   Nothing.                                                               */
6846 /****************************************************************************/
6847 static void
6848 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6849 {
6850         if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6851                   "pkt_len = 0x%04X, vlan = 0x%04x, "
6852                   "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6853                   idx, l2fhdr->l2_fhdr_status,
6854                   l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6855                   l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6856 }
6857
6858
6859 /****************************************************************************/
6860 /* Prints out the tx chain.                                                 */
6861 /*                                                                          */
6862 /* Returns:                                                                 */
6863 /*   Nothing.                                                               */
6864 /****************************************************************************/
6865 static void
6866 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6867 {
6868         struct ifnet *ifp = &sc->arpcom.ac_if;
6869         int i;
6870
6871         /* First some info about the tx_bd chain structure. */
6872         if_printf(ifp,
6873         "----------------------------"
6874         "  tx_bd  chain  "
6875         "----------------------------\n");
6876
6877         if_printf(ifp, "page size      = 0x%08X, "
6878                   "tx chain pages        = 0x%08X\n",
6879                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->tx_pages);
6880
6881         if_printf(ifp, "tx_bd per page = 0x%08X, "
6882                   "usable tx_bd per page = 0x%08X\n",
6883                   (uint32_t)TOTAL_TX_BD_PER_PAGE,
6884                   (uint32_t)USABLE_TX_BD_PER_PAGE);
6885
6886         if_printf(ifp, "total tx_bd    = 0x%08X\n", (uint32_t)TOTAL_TX_BD(sc));
6887
6888         if_printf(ifp,
6889         "----------------------------"
6890         "  tx_bd data    "
6891         "----------------------------\n");
6892
6893         /* Now print out the tx_bd's themselves. */
6894         for (i = 0; i < count; i++) {
6895                 struct tx_bd *txbd;
6896
6897                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6898                 bce_dump_txbd(sc, tx_prod, txbd);
6899                 tx_prod = TX_CHAIN_IDX(sc, NEXT_TX_BD(tx_prod));
6900         }
6901
6902         if_printf(ifp,
6903         "----------------------------"
6904         "----------------"
6905         "----------------------------\n");
6906 }
6907
6908
6909 /****************************************************************************/
6910 /* Prints out the rx chain.                                                 */
6911 /*                                                                          */
6912 /* Returns:                                                                 */
6913 /*   Nothing.                                                               */
6914 /****************************************************************************/
6915 static void
6916 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6917 {
6918         struct ifnet *ifp = &sc->arpcom.ac_if;
6919         int i;
6920
6921         /* First some info about the tx_bd chain structure. */
6922         if_printf(ifp,
6923         "----------------------------"
6924         "  rx_bd  chain  "
6925         "----------------------------\n");
6926
6927         if_printf(ifp, "page size      = 0x%08X, "
6928                   "rx chain pages        = 0x%08X\n",
6929                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->rx_pages);
6930
6931         if_printf(ifp, "rx_bd per page = 0x%08X, "
6932                   "usable rx_bd per page = 0x%08X\n",
6933                   (uint32_t)TOTAL_RX_BD_PER_PAGE,
6934                   (uint32_t)USABLE_RX_BD_PER_PAGE);
6935
6936         if_printf(ifp, "total rx_bd    = 0x%08X\n", (uint32_t)TOTAL_RX_BD(sc));
6937
6938         if_printf(ifp,
6939         "----------------------------"
6940         "   rx_bd data   "
6941         "----------------------------\n");
6942
6943         /* Now print out the rx_bd's themselves. */
6944         for (i = 0; i < count; i++) {
6945                 struct rx_bd *rxbd;
6946
6947                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6948                 bce_dump_rxbd(sc, rx_prod, rxbd);
6949                 rx_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(rx_prod));
6950         }
6951
6952         if_printf(ifp,
6953         "----------------------------"
6954         "----------------"
6955         "----------------------------\n");
6956 }
6957
6958
6959 /****************************************************************************/
6960 /* Prints out the status block from host memory.                            */
6961 /*                                                                          */
6962 /* Returns:                                                                 */
6963 /*   Nothing.                                                               */
6964 /****************************************************************************/
6965 static void
6966 bce_dump_status_block(struct bce_softc *sc)
6967 {
6968         struct status_block *sblk = sc->status_block;
6969         struct ifnet *ifp = &sc->arpcom.ac_if;
6970
6971         if_printf(ifp,
6972         "----------------------------"
6973         "  Status Block  "
6974         "----------------------------\n");
6975
6976         if_printf(ifp, "    0x%08X - attn_bits\n", sblk->status_attn_bits);
6977
6978         if_printf(ifp, "    0x%08X - attn_bits_ack\n",
6979                   sblk->status_attn_bits_ack);
6980
6981         if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6982             sblk->status_rx_quick_consumer_index0,
6983             (uint16_t)RX_CHAIN_IDX(sc, sblk->status_rx_quick_consumer_index0));
6984
6985         if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6986             sblk->status_tx_quick_consumer_index0,
6987             (uint16_t)TX_CHAIN_IDX(sc, sblk->status_tx_quick_consumer_index0));
6988
6989         if_printf(ifp, "        0x%04X - status_idx\n", sblk->status_idx);
6990
6991         /* Theses indices are not used for normal L2 drivers. */
6992         if (sblk->status_rx_quick_consumer_index1) {
6993                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6994                 sblk->status_rx_quick_consumer_index1,
6995                 (uint16_t)RX_CHAIN_IDX(sc,
6996                     sblk->status_rx_quick_consumer_index1));
6997         }
6998
6999         if (sblk->status_tx_quick_consumer_index1) {
7000                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
7001                 sblk->status_tx_quick_consumer_index1,
7002                 (uint16_t)TX_CHAIN_IDX(sc,
7003                     sblk->status_tx_quick_consumer_index1));
7004         }
7005
7006         if (sblk->status_rx_quick_consumer_index2) {
7007                 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
7008                 sblk->status_rx_quick_consumer_index2,
7009                 (uint16_t)RX_CHAIN_IDX(sc,
7010                     sblk->status_rx_quick_consumer_index2));
7011         }
7012
7013         if (sblk->status_tx_quick_consumer_index2) {
7014                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
7015                 sblk->status_tx_quick_consumer_index2,
7016                 (uint16_t)TX_CHAIN_IDX(sc,
7017                     sblk->status_tx_quick_consumer_index2));
7018         }
7019
7020         if (sblk->status_rx_quick_consumer_index3) {
7021                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
7022                 sblk->status_rx_quick_consumer_index3,
7023                 (uint16_t)RX_CHAIN_IDX(sc,
7024                     sblk->status_rx_quick_consumer_index3));
7025         }
7026
7027         if (sblk->status_tx_quick_consumer_index3) {
7028                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
7029                 sblk->status_tx_quick_consumer_index3,
7030                 (uint16_t)TX_CHAIN_IDX(sc,
7031                     sblk->status_tx_quick_consumer_index3));
7032         }
7033
7034         if (sblk->status_rx_quick_consumer_index4 ||
7035             sblk->status_rx_quick_consumer_index5) {
7036                 if_printf(ifp, "rx_cons4  = 0x%08X, rx_cons5      = 0x%08X\n",
7037                           sblk->status_rx_quick_consumer_index4,
7038                           sblk->status_rx_quick_consumer_index5);
7039         }
7040
7041         if (sblk->status_rx_quick_consumer_index6 ||
7042             sblk->status_rx_quick_consumer_index7) {
7043                 if_printf(ifp, "rx_cons6  = 0x%08X, rx_cons7      = 0x%08X\n",
7044                           sblk->status_rx_quick_consumer_index6,
7045                           sblk->status_rx_quick_consumer_index7);
7046         }
7047
7048         if (sblk->status_rx_quick_consumer_index8 ||
7049             sblk->status_rx_quick_consumer_index9) {
7050                 if_printf(ifp, "rx_cons8  = 0x%08X, rx_cons9      = 0x%08X\n",
7051                           sblk->status_rx_quick_consumer_index8,
7052                           sblk->status_rx_quick_consumer_index9);
7053         }
7054
7055         if (sblk->status_rx_quick_consumer_index10 ||
7056             sblk->status_rx_quick_consumer_index11) {
7057                 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11     = 0x%08X\n",
7058                           sblk->status_rx_quick_consumer_index10,
7059                           sblk->status_rx_quick_consumer_index11);
7060         }
7061
7062         if (sblk->status_rx_quick_consumer_index12 ||
7063             sblk->status_rx_quick_consumer_index13) {
7064                 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13     = 0x%08X\n",
7065                           sblk->status_rx_quick_consumer_index12,
7066                           sblk->status_rx_quick_consumer_index13);
7067         }
7068
7069         if (sblk->status_rx_quick_consumer_index14 ||
7070             sblk->status_rx_quick_consumer_index15) {
7071                 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15     = 0x%08X\n",
7072                           sblk->status_rx_quick_consumer_index14,
7073                           sblk->status_rx_quick_consumer_index15);
7074         }
7075
7076         if (sblk->status_completion_producer_index ||
7077             sblk->status_cmd_consumer_index) {
7078                 if_printf(ifp, "com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
7079                           sblk->status_completion_producer_index,
7080                           sblk->status_cmd_consumer_index);
7081         }
7082
7083         if_printf(ifp,
7084         "----------------------------"
7085         "----------------"
7086         "----------------------------\n");
7087 }
7088
7089
7090 /****************************************************************************/
7091 /* Prints out the statistics block.                                         */
7092 /*                                                                          */
7093 /* Returns:                                                                 */
7094 /*   Nothing.                                                               */
7095 /****************************************************************************/
7096 static void
7097 bce_dump_stats_block(struct bce_softc *sc)
7098 {
7099         struct statistics_block *sblk = sc->stats_block;
7100         struct ifnet *ifp = &sc->arpcom.ac_if;
7101
7102         if_printf(ifp,
7103         "---------------"
7104         " Stats Block  (All Stats Not Shown Are 0) "
7105         "---------------\n");
7106
7107         if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
7108                 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
7109                           sblk->stat_IfHCInOctets_hi,
7110                           sblk->stat_IfHCInOctets_lo);
7111         }
7112
7113         if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
7114                 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
7115                           sblk->stat_IfHCInBadOctets_hi,
7116                           sblk->stat_IfHCInBadOctets_lo);
7117         }
7118
7119         if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
7120                 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
7121                           sblk->stat_IfHCOutOctets_hi,
7122                           sblk->stat_IfHCOutOctets_lo);
7123         }
7124
7125         if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
7126                 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
7127                           sblk->stat_IfHCOutBadOctets_hi,
7128                           sblk->stat_IfHCOutBadOctets_lo);
7129         }
7130
7131         if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
7132                 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
7133                           sblk->stat_IfHCInUcastPkts_hi,
7134                           sblk->stat_IfHCInUcastPkts_lo);
7135         }
7136
7137         if (sblk->stat_IfHCInBroadcastPkts_hi ||
7138             sblk->stat_IfHCInBroadcastPkts_lo) {
7139                 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
7140                           sblk->stat_IfHCInBroadcastPkts_hi,
7141                           sblk->stat_IfHCInBroadcastPkts_lo);
7142         }
7143
7144         if (sblk->stat_IfHCInMulticastPkts_hi ||
7145             sblk->stat_IfHCInMulticastPkts_lo) {
7146                 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
7147                           sblk->stat_IfHCInMulticastPkts_hi,
7148                           sblk->stat_IfHCInMulticastPkts_lo);
7149         }
7150
7151         if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
7152                 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
7153                           sblk->stat_IfHCOutUcastPkts_hi,
7154                           sblk->stat_IfHCOutUcastPkts_lo);
7155         }
7156
7157         if (sblk->stat_IfHCOutBroadcastPkts_hi ||
7158             sblk->stat_IfHCOutBroadcastPkts_lo) {
7159                 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
7160                           sblk->stat_IfHCOutBroadcastPkts_hi,
7161                           sblk->stat_IfHCOutBroadcastPkts_lo);
7162         }
7163
7164         if (sblk->stat_IfHCOutMulticastPkts_hi ||
7165             sblk->stat_IfHCOutMulticastPkts_lo) {
7166                 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
7167                           sblk->stat_IfHCOutMulticastPkts_hi,
7168                           sblk->stat_IfHCOutMulticastPkts_lo);
7169         }
7170
7171         if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
7172                 if_printf(ifp, "         0x%08X : "
7173                 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
7174                 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
7175         }
7176
7177         if (sblk->stat_Dot3StatsCarrierSenseErrors) {
7178                 if_printf(ifp, "         0x%08X : "
7179                           "Dot3StatsCarrierSenseErrors\n",
7180                           sblk->stat_Dot3StatsCarrierSenseErrors);
7181         }
7182
7183         if (sblk->stat_Dot3StatsFCSErrors) {
7184                 if_printf(ifp, "         0x%08X : Dot3StatsFCSErrors\n",
7185                           sblk->stat_Dot3StatsFCSErrors);
7186         }
7187
7188         if (sblk->stat_Dot3StatsAlignmentErrors) {
7189                 if_printf(ifp, "         0x%08X : Dot3StatsAlignmentErrors\n",
7190                           sblk->stat_Dot3StatsAlignmentErrors);
7191         }
7192
7193         if (sblk->stat_Dot3StatsSingleCollisionFrames) {
7194                 if_printf(ifp, "         0x%08X : "
7195                           "Dot3StatsSingleCollisionFrames\n",
7196                           sblk->stat_Dot3StatsSingleCollisionFrames);
7197         }
7198
7199         if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
7200                 if_printf(ifp, "         0x%08X : "
7201                           "Dot3StatsMultipleCollisionFrames\n",
7202                           sblk->stat_Dot3StatsMultipleCollisionFrames);
7203         }
7204
7205         if (sblk->stat_Dot3StatsDeferredTransmissions) {
7206                 if_printf(ifp, "         0x%08X : "
7207                           "Dot3StatsDeferredTransmissions\n",
7208                           sblk->stat_Dot3StatsDeferredTransmissions);
7209         }
7210
7211         if (sblk->stat_Dot3StatsExcessiveCollisions) {
7212                 if_printf(ifp, "         0x%08X : "
7213                           "Dot3StatsExcessiveCollisions\n",
7214                           sblk->stat_Dot3StatsExcessiveCollisions);
7215         }
7216
7217         if (sblk->stat_Dot3StatsLateCollisions) {
7218                 if_printf(ifp, "         0x%08X : Dot3StatsLateCollisions\n",
7219                           sblk->stat_Dot3StatsLateCollisions);
7220         }
7221
7222         if (sblk->stat_EtherStatsCollisions) {
7223                 if_printf(ifp, "         0x%08X : EtherStatsCollisions\n",
7224                           sblk->stat_EtherStatsCollisions);
7225         }
7226
7227         if (sblk->stat_EtherStatsFragments)  {
7228                 if_printf(ifp, "         0x%08X : EtherStatsFragments\n",
7229                           sblk->stat_EtherStatsFragments);
7230         }
7231
7232         if (sblk->stat_EtherStatsJabbers) {
7233                 if_printf(ifp, "         0x%08X : EtherStatsJabbers\n",
7234                           sblk->stat_EtherStatsJabbers);
7235         }
7236
7237         if (sblk->stat_EtherStatsUndersizePkts) {
7238                 if_printf(ifp, "         0x%08X : EtherStatsUndersizePkts\n",
7239                           sblk->stat_EtherStatsUndersizePkts);
7240         }
7241
7242         if (sblk->stat_EtherStatsOverrsizePkts) {
7243                 if_printf(ifp, "         0x%08X : EtherStatsOverrsizePkts\n",
7244                           sblk->stat_EtherStatsOverrsizePkts);
7245         }
7246
7247         if (sblk->stat_EtherStatsPktsRx64Octets) {
7248                 if_printf(ifp, "         0x%08X : EtherStatsPktsRx64Octets\n",
7249                           sblk->stat_EtherStatsPktsRx64Octets);
7250         }
7251
7252         if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7253                 if_printf(ifp, "         0x%08X : "
7254                           "EtherStatsPktsRx65Octetsto127Octets\n",
7255                           sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7256         }
7257
7258         if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7259                 if_printf(ifp, "         0x%08X : "
7260                           "EtherStatsPktsRx128Octetsto255Octets\n",
7261                           sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7262         }
7263
7264         if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7265                 if_printf(ifp, "         0x%08X : "
7266                           "EtherStatsPktsRx256Octetsto511Octets\n",
7267                           sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7268         }
7269
7270         if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7271                 if_printf(ifp, "         0x%08X : "
7272                           "EtherStatsPktsRx512Octetsto1023Octets\n",
7273                           sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7274         }
7275
7276         if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7277                 if_printf(ifp, "         0x%08X : "
7278                           "EtherStatsPktsRx1024Octetsto1522Octets\n",
7279                           sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7280         }
7281
7282         if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7283                 if_printf(ifp, "         0x%08X : "
7284                           "EtherStatsPktsRx1523Octetsto9022Octets\n",
7285                           sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7286         }
7287
7288         if (sblk->stat_EtherStatsPktsTx64Octets) {
7289                 if_printf(ifp, "         0x%08X : EtherStatsPktsTx64Octets\n",
7290                           sblk->stat_EtherStatsPktsTx64Octets);
7291         }
7292
7293         if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7294                 if_printf(ifp, "         0x%08X : "
7295                           "EtherStatsPktsTx65Octetsto127Octets\n",
7296                           sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7297         }
7298
7299         if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7300                 if_printf(ifp, "         0x%08X : "
7301                           "EtherStatsPktsTx128Octetsto255Octets\n",
7302                           sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7303         }
7304
7305         if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7306                 if_printf(ifp, "         0x%08X : "
7307                           "EtherStatsPktsTx256Octetsto511Octets\n",
7308                           sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7309         }
7310
7311         if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7312                 if_printf(ifp, "         0x%08X : "
7313                           "EtherStatsPktsTx512Octetsto1023Octets\n",
7314                           sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7315         }
7316
7317         if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7318                 if_printf(ifp, "         0x%08X : "
7319                           "EtherStatsPktsTx1024Octetsto1522Octets\n",
7320                           sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7321         }
7322
7323         if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7324                 if_printf(ifp, "         0x%08X : "
7325                           "EtherStatsPktsTx1523Octetsto9022Octets\n",
7326                           sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7327         }
7328
7329         if (sblk->stat_XonPauseFramesReceived) {
7330                 if_printf(ifp, "         0x%08X : XonPauseFramesReceived\n",
7331                           sblk->stat_XonPauseFramesReceived);
7332         }
7333
7334         if (sblk->stat_XoffPauseFramesReceived) {
7335                 if_printf(ifp, "          0x%08X : XoffPauseFramesReceived\n",
7336                           sblk->stat_XoffPauseFramesReceived);
7337         }
7338
7339         if (sblk->stat_OutXonSent) {
7340                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7341                           sblk->stat_OutXonSent);
7342         }
7343
7344         if (sblk->stat_OutXoffSent) {
7345                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7346                           sblk->stat_OutXoffSent);
7347         }
7348
7349         if (sblk->stat_FlowControlDone) {
7350                 if_printf(ifp, "         0x%08X : FlowControlDone\n",
7351                           sblk->stat_FlowControlDone);
7352         }
7353
7354         if (sblk->stat_MacControlFramesReceived) {
7355                 if_printf(ifp, "         0x%08X : MacControlFramesReceived\n",
7356                           sblk->stat_MacControlFramesReceived);
7357         }
7358
7359         if (sblk->stat_XoffStateEntered) {
7360                 if_printf(ifp, "         0x%08X : XoffStateEntered\n",
7361                           sblk->stat_XoffStateEntered);
7362         }
7363
7364         if (sblk->stat_IfInFramesL2FilterDiscards) {
7365                 if_printf(ifp, "         0x%08X : IfInFramesL2FilterDiscards\n",                          sblk->stat_IfInFramesL2FilterDiscards);
7366         }
7367
7368         if (sblk->stat_IfInRuleCheckerDiscards) {
7369                 if_printf(ifp, "         0x%08X : IfInRuleCheckerDiscards\n",
7370                           sblk->stat_IfInRuleCheckerDiscards);
7371         }
7372
7373         if (sblk->stat_IfInFTQDiscards) {
7374                 if_printf(ifp, "         0x%08X : IfInFTQDiscards\n",
7375                           sblk->stat_IfInFTQDiscards);
7376         }
7377
7378         if (sblk->stat_IfInMBUFDiscards) {
7379                 if_printf(ifp, "         0x%08X : IfInMBUFDiscards\n",
7380                           sblk->stat_IfInMBUFDiscards);
7381         }
7382
7383         if (sblk->stat_IfInRuleCheckerP4Hit) {
7384                 if_printf(ifp, "         0x%08X : IfInRuleCheckerP4Hit\n",
7385                           sblk->stat_IfInRuleCheckerP4Hit);
7386         }
7387
7388         if (sblk->stat_CatchupInRuleCheckerDiscards) {
7389                 if_printf(ifp, "         0x%08X : "
7390                           "CatchupInRuleCheckerDiscards\n",
7391                           sblk->stat_CatchupInRuleCheckerDiscards);
7392         }
7393
7394         if (sblk->stat_CatchupInFTQDiscards) {
7395                 if_printf(ifp, "         0x%08X : CatchupInFTQDiscards\n",
7396                           sblk->stat_CatchupInFTQDiscards);
7397         }
7398
7399         if (sblk->stat_CatchupInMBUFDiscards) {
7400                 if_printf(ifp, "         0x%08X : CatchupInMBUFDiscards\n",
7401                           sblk->stat_CatchupInMBUFDiscards);
7402         }
7403
7404         if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7405                 if_printf(ifp, "         0x%08X : CatchupInRuleCheckerP4Hit\n",
7406                           sblk->stat_CatchupInRuleCheckerP4Hit);
7407         }
7408
7409         if_printf(ifp,
7410         "----------------------------"
7411         "----------------"
7412         "----------------------------\n");
7413 }
7414
7415
7416 /****************************************************************************/
7417 /* Prints out a summary of the driver state.                                */
7418 /*                                                                          */
7419 /* Returns:                                                                 */
7420 /*   Nothing.                                                               */
7421 /****************************************************************************/
7422 static void
7423 bce_dump_driver_state(struct bce_softc *sc)
7424 {
7425         struct ifnet *ifp = &sc->arpcom.ac_if;
7426         uint32_t val_hi, val_lo;
7427
7428         if_printf(ifp,
7429         "-----------------------------"
7430         " Driver State "
7431         "-----------------------------\n");
7432
7433         val_hi = BCE_ADDR_HI(sc);
7434         val_lo = BCE_ADDR_LO(sc);
7435         if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7436                   "virtual address\n", val_hi, val_lo);
7437
7438         val_hi = BCE_ADDR_HI(sc->status_block);
7439         val_lo = BCE_ADDR_LO(sc->status_block);
7440         if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7441                   "virtual address\n", val_hi, val_lo);
7442
7443         val_hi = BCE_ADDR_HI(sc->stats_block);
7444         val_lo = BCE_ADDR_LO(sc->stats_block);
7445         if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7446                   "virtual address\n", val_hi, val_lo);
7447
7448         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7449         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7450         if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7451                   "virtual address\n", val_hi, val_lo);
7452
7453         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7454         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7455         if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7456                   "virtual address\n", val_hi, val_lo);
7457
7458         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7459         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7460         if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7461                   "virtual address\n", val_hi, val_lo);
7462
7463         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7464         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7465         if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7466                   "virtual address\n", val_hi, val_lo);
7467
7468         if_printf(ifp, "         0x%08X - (sc->interrupts_generated) "
7469                   "h/w intrs\n", sc->interrupts_generated);
7470
7471         if_printf(ifp, "         0x%08X - (sc->rx_interrupts) "
7472                   "rx interrupts handled\n", sc->rx_interrupts);
7473
7474         if_printf(ifp, "         0x%08X - (sc->tx_interrupts) "
7475                   "tx interrupts handled\n", sc->tx_interrupts);
7476
7477         if_printf(ifp, "         0x%08X - (sc->last_status_idx) "
7478                   "status block index\n", sc->last_status_idx);
7479
7480         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_prod) "
7481                   "tx producer index\n",
7482                   sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_prod));
7483
7484         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_cons) "
7485                   "tx consumer index\n",
7486                   sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_cons));
7487
7488         if_printf(ifp, "         0x%08X - (sc->tx_prod_bseq) "
7489                   "tx producer bseq index\n", sc->tx_prod_bseq);
7490
7491         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_prod) "
7492                   "rx producer index\n",
7493                   sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_prod));
7494
7495         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_cons) "
7496                   "rx consumer index\n",
7497                   sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_cons));
7498
7499         if_printf(ifp, "         0x%08X - (sc->rx_prod_bseq) "
7500                   "rx producer bseq index\n", sc->rx_prod_bseq);
7501
7502         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7503                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7504
7505         if_printf(ifp, "         0x%08X - (sc->free_rx_bd) "
7506                   "free rx_bd's\n", sc->free_rx_bd);
7507
7508         if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7509                   "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7510
7511         if_printf(ifp, "         0x%08X - (sc->txmbuf_alloc) "
7512                   "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7513
7514         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7515                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7516
7517         if_printf(ifp, "         0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7518                   sc->used_tx_bd);
7519
7520         if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7521                   sc->tx_hi_watermark, sc->max_tx_bd);
7522
7523         if_printf(ifp, "         0x%08X - (sc->mbuf_alloc_failed) "
7524                   "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7525
7526         if_printf(ifp,
7527         "----------------------------"
7528         "----------------"
7529         "----------------------------\n");
7530 }
7531
7532
7533 /****************************************************************************/
7534 /* Prints out the hardware state through a summary of important registers,  */
7535 /* followed by a complete register dump.                                    */
7536 /*                                                                          */
7537 /* Returns:                                                                 */
7538 /*   Nothing.                                                               */
7539 /****************************************************************************/
7540 static void
7541 bce_dump_hw_state(struct bce_softc *sc)
7542 {
7543         struct ifnet *ifp = &sc->arpcom.ac_if;
7544         uint32_t val1;
7545         int i;
7546
7547         if_printf(ifp,
7548         "----------------------------"
7549         " Hardware State "
7550         "----------------------------\n");
7551
7552         if_printf(ifp, "%s - bootcode version\n", sc->bce_bc_ver);
7553
7554         val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7555         if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7556                   val1, BCE_MISC_ENABLE_STATUS_BITS);
7557
7558         val1 = REG_RD(sc, BCE_DMA_STATUS);
7559         if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7560
7561         val1 = REG_RD(sc, BCE_CTX_STATUS);
7562         if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7563
7564         val1 = REG_RD(sc, BCE_EMAC_STATUS);
7565         if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7566                   val1, BCE_EMAC_STATUS);
7567
7568         val1 = REG_RD(sc, BCE_RPM_STATUS);
7569         if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7570
7571         val1 = REG_RD(sc, BCE_TBDR_STATUS);
7572         if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7573                   val1, BCE_TBDR_STATUS);
7574
7575         val1 = REG_RD(sc, BCE_TDMA_STATUS);
7576         if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7577                   val1, BCE_TDMA_STATUS);
7578
7579         val1 = REG_RD(sc, BCE_HC_STATUS);
7580         if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7581
7582         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7583         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7584                   val1, BCE_TXP_CPU_STATE);
7585
7586         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7587         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7588                   val1, BCE_TPAT_CPU_STATE);
7589
7590         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7591         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7592                   val1, BCE_RXP_CPU_STATE);
7593
7594         val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7595         if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7596                   val1, BCE_COM_CPU_STATE);
7597
7598         val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7599         if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7600                   val1, BCE_MCP_CPU_STATE);
7601
7602         val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7603         if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7604                   val1, BCE_CP_CPU_STATE);
7605
7606         if_printf(ifp,
7607         "----------------------------"
7608         "----------------"
7609         "----------------------------\n");
7610
7611         if_printf(ifp,
7612         "----------------------------"
7613         " Register  Dump "
7614         "----------------------------\n");
7615
7616         for (i = 0x400; i < 0x8000; i += 0x10) {
7617                 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7618                           REG_RD(sc, i),
7619                           REG_RD(sc, i + 0x4),
7620                           REG_RD(sc, i + 0x8),
7621                           REG_RD(sc, i + 0xc));
7622         }
7623
7624         if_printf(ifp,
7625         "----------------------------"
7626         "----------------"
7627         "----------------------------\n");
7628 }
7629
7630
7631 /****************************************************************************/
7632 /* Prints out the TXP state.                                                */
7633 /*                                                                          */
7634 /* Returns:                                                                 */
7635 /*   Nothing.                                                               */
7636 /****************************************************************************/
7637 static void
7638 bce_dump_txp_state(struct bce_softc *sc)
7639 {
7640         struct ifnet *ifp = &sc->arpcom.ac_if;
7641         uint32_t val1;
7642         int i;
7643
7644         if_printf(ifp,
7645         "----------------------------"
7646         "   TXP  State   "
7647         "----------------------------\n");
7648
7649         val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7650         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7651                   val1, BCE_TXP_CPU_MODE);
7652
7653         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7654         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7655                   val1, BCE_TXP_CPU_STATE);
7656
7657         val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7658         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7659                   val1, BCE_TXP_CPU_EVENT_MASK);
7660
7661         if_printf(ifp,
7662         "----------------------------"
7663         " Register  Dump "
7664         "----------------------------\n");
7665
7666         for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7667                 /* Skip the big blank spaces */
7668                 if (i < 0x454000 && i > 0x5ffff) {
7669                         if_printf(ifp, "0x%04X: "
7670                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7671                                   REG_RD_IND(sc, i),
7672                                   REG_RD_IND(sc, i + 0x4),
7673                                   REG_RD_IND(sc, i + 0x8),
7674                                   REG_RD_IND(sc, i + 0xc));
7675                 }
7676         }
7677
7678         if_printf(ifp,
7679         "----------------------------"
7680         "----------------"
7681         "----------------------------\n");
7682 }
7683
7684
7685 /****************************************************************************/
7686 /* Prints out the RXP state.                                                */
7687 /*                                                                          */
7688 /* Returns:                                                                 */
7689 /*   Nothing.                                                               */
7690 /****************************************************************************/
7691 static void
7692 bce_dump_rxp_state(struct bce_softc *sc)
7693 {
7694         struct ifnet *ifp = &sc->arpcom.ac_if;
7695         uint32_t val1;
7696         int i;
7697
7698         if_printf(ifp,
7699         "----------------------------"
7700         "   RXP  State   "
7701         "----------------------------\n");
7702
7703         val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7704         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7705                   val1, BCE_RXP_CPU_MODE);
7706
7707         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7708         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7709                   val1, BCE_RXP_CPU_STATE);
7710
7711         val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7712         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7713                   val1, BCE_RXP_CPU_EVENT_MASK);
7714
7715         if_printf(ifp,
7716         "----------------------------"
7717         " Register  Dump "
7718         "----------------------------\n");
7719
7720         for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7721                 /* Skip the big blank sapces */
7722                 if (i < 0xc5400 || i > 0xdffff) {
7723                         if_printf(ifp, "0x%04X: "
7724                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7725                                   REG_RD_IND(sc, i),
7726                                   REG_RD_IND(sc, i + 0x4),
7727                                   REG_RD_IND(sc, i + 0x8),
7728                                   REG_RD_IND(sc, i + 0xc));
7729                 }
7730         }
7731
7732         if_printf(ifp,
7733         "----------------------------"
7734         "----------------"
7735         "----------------------------\n");
7736 }
7737
7738
7739 /****************************************************************************/
7740 /* Prints out the TPAT state.                                               */
7741 /*                                                                          */
7742 /* Returns:                                                                 */
7743 /*   Nothing.                                                               */
7744 /****************************************************************************/
7745 static void
7746 bce_dump_tpat_state(struct bce_softc *sc)
7747 {
7748         struct ifnet *ifp = &sc->arpcom.ac_if;
7749         uint32_t val1;
7750         int i;
7751
7752         if_printf(ifp,
7753         "----------------------------"
7754         "   TPAT State   "
7755         "----------------------------\n");
7756
7757         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7758         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7759                   val1, BCE_TPAT_CPU_MODE);
7760
7761         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7762         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7763                   val1, BCE_TPAT_CPU_STATE);
7764
7765         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7766         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7767                   val1, BCE_TPAT_CPU_EVENT_MASK);
7768
7769         if_printf(ifp,
7770         "----------------------------"
7771         " Register  Dump "
7772         "----------------------------\n");
7773
7774         for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7775                 /* Skip the big blank spaces */
7776                 if (i < 0x854000 && i > 0x9ffff) {
7777                         if_printf(ifp, "0x%04X: "
7778                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7779                                   REG_RD_IND(sc, i),
7780                                   REG_RD_IND(sc, i + 0x4),
7781                                   REG_RD_IND(sc, i + 0x8),
7782                                   REG_RD_IND(sc, i + 0xc));
7783                 }
7784         }
7785
7786         if_printf(ifp,
7787         "----------------------------"
7788         "----------------"
7789         "----------------------------\n");
7790 }
7791
7792
7793 /****************************************************************************/
7794 /* Prints out the driver state and then enters the debugger.                */
7795 /*                                                                          */
7796 /* Returns:                                                                 */
7797 /*   Nothing.                                                               */
7798 /****************************************************************************/
7799 static void
7800 bce_breakpoint(struct bce_softc *sc)
7801 {
7802 #if 0
7803         bce_freeze_controller(sc);
7804 #endif
7805
7806         bce_dump_driver_state(sc);
7807         bce_dump_status_block(sc);
7808         bce_dump_tx_chain(sc, 0, TOTAL_TX_BD(sc));
7809         bce_dump_hw_state(sc);
7810         bce_dump_txp_state(sc);
7811
7812 #if 0
7813         bce_unfreeze_controller(sc);
7814 #endif
7815
7816         /* Call the debugger. */
7817         breakpoint();
7818 }
7819
7820 #endif  /* BCE_DEBUG */
7821
7822 static int
7823 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7824 {
7825         struct bce_softc *sc = arg1;
7826
7827         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7828                         &sc->bce_tx_quick_cons_trip_int,
7829                         BCE_COALMASK_TX_BDS_INT);
7830 }
7831
7832 static int
7833 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7834 {
7835         struct bce_softc *sc = arg1;
7836
7837         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7838                         &sc->bce_tx_quick_cons_trip,
7839                         BCE_COALMASK_TX_BDS);
7840 }
7841
7842 static int
7843 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7844 {
7845         struct bce_softc *sc = arg1;
7846
7847         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7848                         &sc->bce_tx_ticks_int,
7849                         BCE_COALMASK_TX_TICKS_INT);
7850 }
7851
7852 static int
7853 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7854 {
7855         struct bce_softc *sc = arg1;
7856
7857         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7858                         &sc->bce_tx_ticks,
7859                         BCE_COALMASK_TX_TICKS);
7860 }
7861
7862 static int
7863 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7864 {
7865         struct bce_softc *sc = arg1;
7866
7867         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7868                         &sc->bce_rx_quick_cons_trip_int,
7869                         BCE_COALMASK_RX_BDS_INT);
7870 }
7871
7872 static int
7873 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7874 {
7875         struct bce_softc *sc = arg1;
7876
7877         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7878                         &sc->bce_rx_quick_cons_trip,
7879                         BCE_COALMASK_RX_BDS);
7880 }
7881
7882 static int
7883 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7884 {
7885         struct bce_softc *sc = arg1;
7886
7887         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7888                         &sc->bce_rx_ticks_int,
7889                         BCE_COALMASK_RX_TICKS_INT);
7890 }
7891
7892 static int
7893 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7894 {
7895         struct bce_softc *sc = arg1;
7896
7897         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7898                         &sc->bce_rx_ticks,
7899                         BCE_COALMASK_RX_TICKS);
7900 }
7901
7902 static int
7903 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7904                        uint32_t coalchg_mask)
7905 {
7906         struct bce_softc *sc = arg1;
7907         struct ifnet *ifp = &sc->arpcom.ac_if;
7908         int error = 0, v;
7909
7910         lwkt_serialize_enter(ifp->if_serializer);
7911
7912         v = *coal;
7913         error = sysctl_handle_int(oidp, &v, 0, req);
7914         if (!error && req->newptr != NULL) {
7915                 if (v < 0) {
7916                         error = EINVAL;
7917                 } else {
7918                         *coal = v;
7919                         sc->bce_coalchg_mask |= coalchg_mask;
7920                 }
7921         }
7922
7923         lwkt_serialize_exit(ifp->if_serializer);
7924         return error;
7925 }
7926
7927 static void
7928 bce_coal_change(struct bce_softc *sc)
7929 {
7930         struct ifnet *ifp = &sc->arpcom.ac_if;
7931
7932         ASSERT_SERIALIZED(ifp->if_serializer);
7933
7934         if ((ifp->if_flags & IFF_RUNNING) == 0) {
7935                 sc->bce_coalchg_mask = 0;
7936                 return;
7937         }
7938
7939         if (sc->bce_coalchg_mask &
7940             (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7941                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7942                        (sc->bce_tx_quick_cons_trip_int << 16) |
7943                        sc->bce_tx_quick_cons_trip);
7944                 if (bootverbose) {
7945                         if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7946                                   sc->bce_tx_quick_cons_trip,
7947                                   sc->bce_tx_quick_cons_trip_int);
7948                 }
7949         }
7950
7951         if (sc->bce_coalchg_mask &
7952             (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7953                 REG_WR(sc, BCE_HC_TX_TICKS,
7954                        (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7955                 if (bootverbose) {
7956                         if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7957                                   sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7958                 }
7959         }
7960
7961         if (sc->bce_coalchg_mask &
7962             (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7963                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7964                        (sc->bce_rx_quick_cons_trip_int << 16) |
7965                        sc->bce_rx_quick_cons_trip);
7966                 if (bootverbose) {
7967                         if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7968                                   sc->bce_rx_quick_cons_trip,
7969                                   sc->bce_rx_quick_cons_trip_int);
7970                 }
7971         }
7972
7973         if (sc->bce_coalchg_mask &
7974             (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7975                 REG_WR(sc, BCE_HC_RX_TICKS,
7976                        (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7977                 if (bootverbose) {
7978                         if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7979                                   sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7980                 }
7981         }
7982
7983         sc->bce_coalchg_mask = 0;
7984 }
7985
7986 static int
7987 bce_tso_setup(struct bce_softc *sc, struct mbuf **mp,
7988     uint16_t *flags0, uint16_t *mss0)
7989 {
7990         struct mbuf *m;
7991         uint16_t flags;
7992         int thoff, iphlen, hoff;
7993
7994         m = *mp;
7995         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
7996
7997         hoff = m->m_pkthdr.csum_lhlen;
7998         iphlen = m->m_pkthdr.csum_iphlen;
7999         thoff = m->m_pkthdr.csum_thlen;
8000
8001         KASSERT(hoff >= sizeof(struct ether_header),
8002             ("invalid ether header len %d", hoff));
8003         KASSERT(iphlen >= sizeof(struct ip),
8004             ("invalid ip header len %d", iphlen));
8005         KASSERT(thoff >= sizeof(struct tcphdr),
8006             ("invalid tcp header len %d", thoff));
8007
8008         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
8009                 m = m_pullup(m, hoff + iphlen + thoff);
8010                 if (m == NULL) {
8011                         *mp = NULL;
8012                         return ENOBUFS;
8013                 }
8014                 *mp = m;
8015         }
8016
8017         /* Set the LSO flag in the TX BD */
8018         flags = TX_BD_FLAGS_SW_LSO;
8019
8020         /* Set the length of IP + TCP options (in 32 bit words) */
8021         flags |= (((iphlen + thoff -
8022             sizeof(struct ip) - sizeof(struct tcphdr)) >> 2) << 8);
8023
8024         *mss0 = htole16(m->m_pkthdr.tso_segsz);
8025         *flags0 = flags;
8026
8027         return 0;
8028 }