2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
5 * Copyright (c) 2004, Scott Long <scottl@kfreebsd.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $FreeBSD: src/sys/i386/pci/pci_cfgreg.c,v 1.124.2.2.6.1 2009/04/15 03:14:26 kensmith Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/thread2.h>
38 #include <sys/spinlock.h>
39 #include <sys/spinlock2.h>
40 #include <sys/queue.h>
41 #include <bus/pci/pcivar.h>
42 #include <bus/pci/pcireg.h>
43 #include "pci_cfgreg.h"
44 #include <machine/pc/bios.h>
46 #include <machine/smp.h>
50 #include <vm/vm_param.h>
51 #include <vm/vm_kern.h>
52 #include <vm/vm_extern.h>
54 #include <machine/pmap.h>
56 #if defined(__DragonFly__)
57 #define mtx_init(a, b, c, d) spin_init(a)
58 #define mtx_lock_spin(a) spin_lock_wr(a)
59 #define mtx_unlock_spin(a) spin_unlock_wr(a)
62 #define PRVERB(a) do { \
68 struct pcie_cfg_elem {
69 TAILQ_ENTRY(pcie_cfg_elem) elem;
81 static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
82 static uint32_t pciebar;
85 #if defined(__DragonFly__)
86 static struct spinlock pcicfg_mtx;
88 static struct mtx pcicfg_mtx;
91 static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
92 static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
93 static int pcireg_cfgopen(void);
95 static int pciereg_cfgopen(void);
96 static int pciereg_cfgread(int bus, int slot, int func, int reg,
98 static void pciereg_cfgwrite(int bus, int slot, int func, int reg,
102 * Some BIOS writers seem to want to ignore the spec and put
103 * 0 in the intline rather than 255 to indicate none. Some use
104 * numbers in the range 128-254 to indicate something strange and
105 * apparently undocumented anywhere. Assume these are completely bogus
106 * and map them to 255, which means "none".
109 pci_i386_map_intline(int line)
111 if (line == 0 || line >= 128)
112 return (PCI_INVALID_IRQ);
119 pcibios_get_version(void)
121 struct bios_regs args;
123 if (PCIbios.ventry == 0) {
124 PRVERB(("pcibios: No call entry point\n"));
127 args.eax = PCIBIOS_BIOS_PRESENT;
128 if (bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL))) {
129 PRVERB(("pcibios: BIOS_PRESENT call failed\n"));
132 if (args.edx != 0x20494350) {
133 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n"));
136 return (args.ebx & 0xffff);
142 * Initialise access to PCI configuration space
147 static int opened = 0;
156 if (pcireg_cfgopen() == 0)
160 v = pcibios_get_version();
162 PRVERB(("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
164 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
167 /* $PIR requires PCI BIOS 2.10 or greater. */
172 * Grope around in the PCI config space to see if this is a
173 * chipset that is capable of doing memory-mapped config cycles.
174 * This also implies that it can do PCIe extended config cycles.
177 /* Check for supported chipsets */
178 vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
179 did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
181 if (did == 0x3590 || did == 0x3592) {
182 /* Intel 7520 or 7320 */
183 pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
185 } else if (did == 0x2580 || did == 0x2584) {
186 /* Intel 915 or 925 */
187 pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
198 * Read configuration space register
201 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
208 * If we are using the APIC, the contents of the intline
209 * register will probably be wrong (since they are set up for
210 * use with the PIC. Rather than rewrite these registers
211 * (maybe that would be smarter) we trap attempts to read them
212 * and translate to our private vector numbers.
214 if ((reg == PCIR_INTLINE) && (bytes == 1)) {
216 pin = pcireg_cfgread(bus, slot, func, PCIR_INTPIN, 1);
217 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
222 airq = pci_apic_irq(bus, slot, pin);
224 /* PCI specific entry found in MP table */
226 undirect_pci_irq(line);
230 * PCI interrupts might be redirected to the
231 * ISA bus according to some MP tables. Use the
232 * same methods as used by the ISA devices
233 * devices to find the proper IOAPIC int pin.
235 airq = isa_apic_irq(line);
236 if ((airq >= 0) && (airq != line)) {
237 /* XXX: undirect_pci_irq() ? */
238 undirect_isa_irq(line);
247 * Some BIOS writers seem to want to ignore the spec and put
248 * 0 in the intline rather than 255 to indicate none. The rest of
249 * the code uses 255 as an invalid IRQ.
251 if (reg == PCIR_INTLINE && bytes == 1) {
252 line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
253 return (pci_i386_map_intline(line));
256 return (pcireg_cfgread(bus, slot, func, reg, bytes));
260 * Write configuration space register
263 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
266 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
270 * Configuration space access using direct register operations
273 /* enable configuration space accesses and return data port address */
275 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
280 if (arch_i386_is_xbox) {
282 * The Xbox MCPX chipset is a derivative of the nForce 1
283 * chipset. It almost has the same bus layout; some devices
284 * cannot be used, because they have been removed.
288 * Devices 00:00.1 and 00:00.2 used to be memory controllers on
289 * the nForce chipset, but on the Xbox, using them will lockup
292 if (bus == 0 && slot == 0 && (func == 1 || func == 2))
296 * Bus 1 only contains a VGA controller at 01:00.0. When you try
297 * to probe beyond that device, you only get garbage, which
298 * could cause lockups.
300 if (bus == 1 && (slot != 0 || func != 0))
304 * Bus 2 used to contain the AGP controller, but the Xbox MCPX
305 * doesn't have one. Probing it can cause lockups.
312 if (bus <= PCI_BUSMAX
314 && func <= PCI_FUNCMAX
317 && (unsigned) bytes <= 4
318 && (reg & (bytes - 1)) == 0) {
321 outl(CONF1_ADDR_PORT, (1 << 31)
322 | (bus << 16) | (slot << 11)
323 | (func << 8) | (reg & ~0x03));
324 dataport = CONF1_DATA_PORT + (reg & 0x03);
327 outb(CONF2_ENABLE_PORT, 0xf0 | (func << 1));
328 outb(CONF2_FORWARD_PORT, bus);
329 dataport = 0xc000 | (slot << 8) | reg;
336 /* disable configuration space accesses */
343 * Do nothing for the config mechanism 1 case.
344 * Writing a 0 to the address port can apparently
345 * confuse some bridges and cause spurious
350 outb(CONF2_ENABLE_PORT, 0);
356 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
361 if (cfgmech == CFGMECH_PCIE) {
362 data = pciereg_cfgread(bus, slot, func, reg, bytes);
366 mtx_lock_spin(&pcicfg_mtx);
367 port = pci_cfgenable(bus, slot, func, reg, bytes);
382 mtx_unlock_spin(&pcicfg_mtx);
387 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
391 if (cfgmech == CFGMECH_PCIE) {
392 pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
396 mtx_lock_spin(&pcicfg_mtx);
397 port = pci_cfgenable(bus, slot, func, reg, bytes);
412 mtx_unlock_spin(&pcicfg_mtx);
415 /* check whether the configuration mechanism has been correctly identified */
417 pci_cfgcheck(int maxdev)
425 kprintf("pci_cfgcheck:\tdevice ");
427 for (device = 0; device < maxdev; device++) {
429 kprintf("%d ", device);
431 port = pci_cfgenable(0, device, 0, 0, 4);
433 if (id == 0 || id == 0xffffffff)
436 port = pci_cfgenable(0, device, 0, 8, 4);
437 class = inl(port) >> 8;
439 kprintf("[class=%06x] ", class);
440 if (class == 0 || (class & 0xf870ff) != 0)
443 port = pci_cfgenable(0, device, 0, 14, 1);
446 kprintf("[hdr=%02x] ", header);
447 if ((header & 0x7e) != 0)
451 kprintf("is there (id=%08x)\n", id);
457 kprintf("-- nothing found\n");
466 uint32_t mode1res, oldval1;
467 uint8_t mode2res, oldval2;
469 /* Check for type #1 first. */
470 oldval1 = inl(CONF1_ADDR_PORT);
473 kprintf("pci_open(1):\tmode 1 addr port (0x0cf8) is 0x%08x\n",
480 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
482 mode1res = inl(CONF1_ADDR_PORT);
483 outl(CONF1_ADDR_PORT, oldval1);
486 kprintf("pci_open(1a):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
490 if (pci_cfgcheck(32))
494 outl(CONF1_ADDR_PORT, CONF1_ENABLE_CHK1);
495 mode1res = inl(CONF1_ADDR_PORT);
496 outl(CONF1_ADDR_PORT, oldval1);
499 kprintf("pci_open(1b):\tmode1res=0x%08x (0x%08lx)\n", mode1res,
502 if ((mode1res & CONF1_ENABLE_MSK1) == CONF1_ENABLE_RES1) {
503 if (pci_cfgcheck(32))
507 /* Type #1 didn't work, so try type #2. */
508 oldval2 = inb(CONF2_ENABLE_PORT);
511 kprintf("pci_open(2):\tmode 2 enable port (0x0cf8) is 0x%02x\n",
515 if ((oldval2 & 0xf0) == 0) {
520 outb(CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
521 mode2res = inb(CONF2_ENABLE_PORT);
522 outb(CONF2_ENABLE_PORT, oldval2);
525 kprintf("pci_open(2a):\tmode2res=0x%02x (0x%02x)\n",
526 mode2res, CONF2_ENABLE_CHK);
528 if (mode2res == CONF2_ENABLE_RES) {
530 kprintf("pci_open(2a):\tnow trying mechanism 2\n");
532 if (pci_cfgcheck(16))
537 /* Nothing worked, so punt. */
538 cfgmech = CFGMECH_NONE;
544 pciereg_cfgopen(void)
547 struct pcie_cfg_list *pcielist;
548 struct pcie_cfg_elem *pcie_array, *elem;
556 kprintf("Setting up PCIe mappings for BAR 0x%x\n", pciebar);
559 SLIST_FOREACH(pc, &cpuhead, pc_allcpu)
563 pcie_array = kmalloc(sizeof(struct pcie_cfg_elem) * PCIE_CACHE,
565 if (pcie_array == NULL)
568 va = kmem_alloc_nofault(&kernel_map, PCIE_CACHE * PAGE_SIZE);
570 kfree(pcie_array, M_DEVBUF);
575 pcielist = &pcie_list[pc->pc_cpuid];
577 pcielist = &pcie_list[0];
579 TAILQ_INIT(pcielist);
580 for (i = 0; i < PCIE_CACHE; i++) {
581 elem = &pcie_array[i];
582 elem->vapage = va + (i * PAGE_SIZE);
584 TAILQ_INSERT_HEAD(pcielist, elem, elem);
589 cfgmech = CFGMECH_PCIE;
592 #else /* !PCIE_CFG_MECH */
594 #endif /* PCIE_CFG_MECH */
597 #define PCIE_PADDR(bar, reg, bus, slot, func) \
599 (((bus) & 0xff) << 20) | \
600 (((slot) & 0x1f) << 15) | \
601 (((func) & 0x7) << 12) | \
605 * Find an element in the cache that matches the physical page desired, or
606 * create a new mapping from the least recently used element.
607 * A very simple LRU algorithm is used here, does it need to be more
610 static __inline struct pcie_cfg_elem *
611 pciereg_findelem(vm_paddr_t papage)
613 struct pcie_cfg_list *pcielist;
614 struct pcie_cfg_elem *elem;
615 pcielist = &pcie_list[mycpuid];
616 TAILQ_FOREACH(elem, pcielist, elem) {
617 if (elem->papage == papage)
622 elem = TAILQ_LAST(pcielist, pcie_cfg_list);
623 if (elem->papage != 0) {
624 pmap_kremove(elem->vapage);
625 cpu_invlpg(&elem->vapage);
627 pmap_kenter(elem->vapage, papage);
628 elem->papage = papage;
631 if (elem != TAILQ_FIRST(pcielist)) {
632 TAILQ_REMOVE(pcielist, elem, elem);
633 TAILQ_INSERT_HEAD(pcielist, elem, elem);
639 pciereg_cfgread(int bus, int slot, int func, int reg, int bytes)
641 struct pcie_cfg_elem *elem;
642 volatile vm_offset_t va;
643 vm_paddr_t pa, papage;
647 pa = PCIE_PADDR(pciebar, reg, bus, slot, func);
648 papage = pa & ~PAGE_MASK;
649 elem = pciereg_findelem(papage);
650 va = elem->vapage | (pa & PAGE_MASK);
654 data = *(volatile uint32_t *)(va);
657 data = *(volatile uint16_t *)(va);
660 data = *(volatile uint8_t *)(va);
663 panic("pciereg_cfgread: invalid width");
671 pciereg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
673 struct pcie_cfg_elem *elem;
674 volatile vm_offset_t va;
675 vm_paddr_t pa, papage;
678 pa = PCIE_PADDR(pciebar, reg, bus, slot, func);
679 papage = pa & ~PAGE_MASK;
680 elem = pciereg_findelem(papage);
681 va = elem->vapage | (pa & PAGE_MASK);
685 *(volatile uint32_t *)(va) = data;
688 *(volatile uint16_t *)(va) = data;
691 *(volatile uint8_t *)(va) = data;
694 panic("pciereg_cfgwrite: invalid width");