bce: Set RX interrupt rate ~6000Hz
[dragonfly.git] / sys / dev / netif / bce / if_bce.c
1 /*-
2  * Copyright (c) 2006-2007 Broadcom Corporation
3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15  *    may be used to endorse or promote products derived from this software
16  *    without specific prior written consent.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28  * THE POSSIBILITY OF SUCH DAMAGE.
29  *
30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
31  */
32
33 /*
34  * The following controllers are supported by this driver:
35  *   BCM5706C A2, A3
36  *   BCM5706S A2, A3
37  *   BCM5708C B1, B2
38  *   BCM5708S B1, B2
39  *   BCM5709C A1, C0
40  *   BCM5716  C0
41  *
42  * The following controllers are not supported by this driver:
43  *   BCM5706C A0, A1
44  *   BCM5706S A0, A1
45  *   BCM5708C A0, B0
46  *   BCM5708S A0, B0
47  *   BCM5709C A0, B0, B1
48  *   BCM5709S A0, A1, B0, B1, B2, C0
49  */
50
51 #include "opt_bce.h"
52 #include "opt_polling.h"
53
54 #include <sys/param.h>
55 #include <sys/bus.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
59 #include <sys/mbuf.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
62 #ifdef BCE_DEBUG
63 #include <sys/random.h>
64 #endif
65 #include <sys/rman.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
70
71 #include <net/bpf.h>
72 #include <net/ethernet.h>
73 #include <net/if.h>
74 #include <net/if_arp.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/ifq_var.h>
79 #include <net/vlan/if_vlan_var.h>
80 #include <net/vlan/if_vlan_ether.h>
81
82 #include <dev/netif/mii_layer/mii.h>
83 #include <dev/netif/mii_layer/miivar.h>
84 #include <dev/netif/mii_layer/brgphyreg.h>
85
86 #include <bus/pci/pcireg.h>
87 #include <bus/pci/pcivar.h>
88
89 #include "miibus_if.h"
90
91 #include <dev/netif/bce/if_bcereg.h>
92 #include <dev/netif/bce/if_bcefw.h>
93
94 /****************************************************************************/
95 /* BCE Debug Options                                                        */
96 /****************************************************************************/
97 #ifdef BCE_DEBUG
98
99 static uint32_t bce_debug = BCE_WARN;
100
101 /*
102  *          0 = Never             
103  *          1 = 1 in 2,147,483,648
104  *        256 = 1 in     8,388,608
105  *       2048 = 1 in     1,048,576
106  *      65536 = 1 in        32,768
107  *    1048576 = 1 in         2,048
108  *  268435456 = 1 in             8
109  *  536870912 = 1 in             4
110  * 1073741824 = 1 in             2
111  *
112  * bce_debug_l2fhdr_status_check:
113  *     How often the l2_fhdr frame error check will fail.
114  *
115  * bce_debug_unexpected_attention:
116  *     How often the unexpected attention check will fail.
117  *
118  * bce_debug_mbuf_allocation_failure:
119  *     How often to simulate an mbuf allocation failure.
120  *
121  * bce_debug_dma_map_addr_failure:
122  *     How often to simulate a DMA mapping failure.
123  *
124  * bce_debug_bootcode_running_failure:
125  *     How often to simulate a bootcode failure.
126  */
127 static int      bce_debug_l2fhdr_status_check = 0;
128 static int      bce_debug_unexpected_attention = 0;
129 static int      bce_debug_mbuf_allocation_failure = 0;
130 static int      bce_debug_dma_map_addr_failure = 0;
131 static int      bce_debug_bootcode_running_failure = 0;
132
133 #endif  /* BCE_DEBUG */
134
135
136 /****************************************************************************/
137 /* PCI Device ID Table                                                      */
138 /*                                                                          */
139 /* Used by bce_probe() to identify the devices supported by this driver.    */
140 /****************************************************************************/
141 #define BCE_DEVDESC_MAX         64
142
143 static struct bce_type bce_devs[] = {
144         /* BCM5706C Controllers and OEM boards. */
145         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
146                 "HP NC370T Multifunction Gigabit Server Adapter" },
147         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
148                 "HP NC370i Multifunction Gigabit Server Adapter" },
149         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
150                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
151         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
152                 "HP NC371i Multifunction Gigabit Server Adapter" },
153         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
154                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
155
156         /* BCM5706S controllers and OEM boards. */
157         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
158                 "HP NC370F Multifunction Gigabit Server Adapter" },
159         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
160                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
161
162         /* BCM5708C controllers and OEM boards. */
163         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
164                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
165         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
166                 "HP NC373i Multifunction Gigabit Server Adapter" },
167         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
168                 "HP NC374m PCIe Multifunction Adapter" },
169         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
170                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
171
172         /* BCM5708S controllers and OEM boards. */
173         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
174                 "HP NC373m Multifunction Gigabit Server Adapter" },
175         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
176                 "HP NC373i Multifunction Gigabit Server Adapter" },
177         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
178                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
179         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
180                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
181
182         /* BCM5709C controllers and OEM boards. */
183         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
184                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
185         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
186                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
187         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
188                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
189
190         /* BCM5709S controllers and OEM boards. */
191         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
192                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
193         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
194                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
195         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
196                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
197
198         /* BCM5716 controllers and OEM boards. */
199         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
200                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
201
202         { 0, 0, 0, 0, NULL }
203 };
204
205
206 /****************************************************************************/
207 /* Supported Flash NVRAM device data.                                       */
208 /****************************************************************************/
209 static const struct flash_spec flash_table[] =
210 {
211 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
212 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
213
214         /* Slow EEPROM */
215         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
216          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
217          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
218          "EEPROM - slow"},
219         /* Expansion entry 0001 */
220         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
221          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
222          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
223          "Entry 0001"},
224         /* Saifun SA25F010 (non-buffered flash) */
225         /* strap, cfg1, & write1 need updates */
226         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
227          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
228          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
229          "Non-buffered flash (128kB)"},
230         /* Saifun SA25F020 (non-buffered flash) */
231         /* strap, cfg1, & write1 need updates */
232         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
233          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
234          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
235          "Non-buffered flash (256kB)"},
236         /* Expansion entry 0100 */
237         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
238          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
239          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
240          "Entry 0100"},
241         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
242         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
243          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
244          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
245          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
246         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
247         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
248          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
249          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
250          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
251         /* Saifun SA25F005 (non-buffered flash) */
252         /* strap, cfg1, & write1 need updates */
253         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
254          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
255          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
256          "Non-buffered flash (64kB)"},
257         /* Fast EEPROM */
258         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
259          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
260          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
261          "EEPROM - fast"},
262         /* Expansion entry 1001 */
263         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
264          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
265          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
266          "Entry 1001"},
267         /* Expansion entry 1010 */
268         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
269          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
270          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
271          "Entry 1010"},
272         /* ATMEL AT45DB011B (buffered flash) */
273         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
274          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
275          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
276          "Buffered flash (128kB)"},
277         /* Expansion entry 1100 */
278         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
279          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
280          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
281          "Entry 1100"},
282         /* Expansion entry 1101 */
283         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
284          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
285          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
286          "Entry 1101"},
287         /* Ateml Expansion entry 1110 */
288         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
289          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
290          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
291          "Entry 1110 (Atmel)"},
292         /* ATMEL AT45DB021B (buffered flash) */
293         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
294          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
295          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
296          "Buffered flash (256kB)"},
297 };
298
299 /*
300  * The BCM5709 controllers transparently handle the
301  * differences between Atmel 264 byte pages and all
302  * flash devices which use 256 byte pages, so no
303  * logical-to-physical mapping is required in the
304  * driver.
305  */
306 static struct flash_spec flash_5709 = {
307         .flags          = BCE_NV_BUFFERED,
308         .page_bits      = BCM5709_FLASH_PAGE_BITS,
309         .page_size      = BCM5709_FLASH_PAGE_SIZE,
310         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
311         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
312         .name           = "5709/5716 buffered flash (256kB)",
313 };
314
315
316 /****************************************************************************/
317 /* DragonFly device entry points.                                           */
318 /****************************************************************************/
319 static int      bce_probe(device_t);
320 static int      bce_attach(device_t);
321 static int      bce_detach(device_t);
322 static void     bce_shutdown(device_t);
323
324 /****************************************************************************/
325 /* BCE Debug Data Structure Dump Routines                                   */
326 /****************************************************************************/
327 #ifdef BCE_DEBUG
328 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
329 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
330 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
331 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
332 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
333 static void     bce_dump_l2fhdr(struct bce_softc *, int,
334                                 struct l2_fhdr *) __unused;
335 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
336 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
337 static void     bce_dump_status_block(struct bce_softc *);
338 static void     bce_dump_driver_state(struct bce_softc *);
339 static void     bce_dump_stats_block(struct bce_softc *) __unused;
340 static void     bce_dump_hw_state(struct bce_softc *);
341 static void     bce_dump_txp_state(struct bce_softc *);
342 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
343 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
344 static void     bce_freeze_controller(struct bce_softc *) __unused;
345 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
346 static void     bce_breakpoint(struct bce_softc *);
347 #endif  /* BCE_DEBUG */
348
349
350 /****************************************************************************/
351 /* BCE Register/Memory Access Routines                                      */
352 /****************************************************************************/
353 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
354 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
355 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
356 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
357 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
358 static int      bce_miibus_read_reg(device_t, int, int);
359 static int      bce_miibus_write_reg(device_t, int, int, int);
360 static void     bce_miibus_statchg(device_t);
361
362
363 /****************************************************************************/
364 /* BCE NVRAM Access Routines                                                */
365 /****************************************************************************/
366 static int      bce_acquire_nvram_lock(struct bce_softc *);
367 static int      bce_release_nvram_lock(struct bce_softc *);
368 static void     bce_enable_nvram_access(struct bce_softc *);
369 static void     bce_disable_nvram_access(struct bce_softc *);
370 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
371                                      uint32_t);
372 static int      bce_init_nvram(struct bce_softc *);
373 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
374 static int      bce_nvram_test(struct bce_softc *);
375
376 /****************************************************************************/
377 /* BCE DMA Allocate/Free Routines                                           */
378 /****************************************************************************/
379 static int      bce_dma_alloc(struct bce_softc *);
380 static void     bce_dma_free(struct bce_softc *);
381 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
382
383 /****************************************************************************/
384 /* BCE Firmware Synchronization and Load                                    */
385 /****************************************************************************/
386 static int      bce_fw_sync(struct bce_softc *, uint32_t);
387 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
388                                  uint32_t, uint32_t);
389 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
390                                 struct fw_info *);
391 static void     bce_start_cpu(struct bce_softc *, struct cpu_reg *);
392 static void     bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
393 static void     bce_start_rxp_cpu(struct bce_softc *);
394 static void     bce_init_rxp_cpu(struct bce_softc *);
395 static void     bce_init_txp_cpu(struct bce_softc *);
396 static void     bce_init_tpat_cpu(struct bce_softc *);
397 static void     bce_init_cp_cpu(struct bce_softc *);
398 static void     bce_init_com_cpu(struct bce_softc *);
399 static void     bce_init_cpus(struct bce_softc *);
400
401 static void     bce_stop(struct bce_softc *);
402 static int      bce_reset(struct bce_softc *, uint32_t);
403 static int      bce_chipinit(struct bce_softc *);
404 static int      bce_blockinit(struct bce_softc *);
405 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
406                                uint32_t *, int);
407 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
408 static void     bce_probe_pci_caps(struct bce_softc *);
409 static void     bce_print_adapter_info(struct bce_softc *);
410 static void     bce_get_media(struct bce_softc *);
411
412 static void     bce_init_tx_context(struct bce_softc *);
413 static int      bce_init_tx_chain(struct bce_softc *);
414 static void     bce_init_rx_context(struct bce_softc *);
415 static int      bce_init_rx_chain(struct bce_softc *);
416 static void     bce_free_rx_chain(struct bce_softc *);
417 static void     bce_free_tx_chain(struct bce_softc *);
418
419 static int      bce_encap(struct bce_softc *, struct mbuf **);
420 static void     bce_start(struct ifnet *);
421 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
422 static void     bce_watchdog(struct ifnet *);
423 static int      bce_ifmedia_upd(struct ifnet *);
424 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
425 static void     bce_init(void *);
426 static void     bce_mgmt_init(struct bce_softc *);
427
428 static int      bce_init_ctx(struct bce_softc *);
429 static void     bce_get_mac_addr(struct bce_softc *);
430 static void     bce_set_mac_addr(struct bce_softc *);
431 static void     bce_phy_intr(struct bce_softc *);
432 static void     bce_rx_intr(struct bce_softc *, int, uint16_t);
433 static void     bce_tx_intr(struct bce_softc *, uint16_t);
434 static void     bce_disable_intr(struct bce_softc *);
435 static void     bce_enable_intr(struct bce_softc *);
436 static void     bce_reenable_intr(struct bce_softc *);
437
438 #ifdef DEVICE_POLLING
439 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
440 #endif
441 static void     bce_intr(struct bce_softc *);
442 static void     bce_intr_legacy(void *);
443 static void     bce_intr_msi(void *);
444 static void     bce_intr_msi_oneshot(void *);
445 static void     bce_set_rx_mode(struct bce_softc *);
446 static void     bce_stats_update(struct bce_softc *);
447 static void     bce_tick(void *);
448 static void     bce_tick_serialized(struct bce_softc *);
449 static void     bce_pulse(void *);
450 static void     bce_pulse_check_msi(struct bce_softc *);
451 static void     bce_add_sysctls(struct bce_softc *);
452
453 static void     bce_coal_change(struct bce_softc *);
454 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
455 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
456 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
457 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
458 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
459 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
460 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
461 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
462 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
463                                        uint32_t *, uint32_t);
464
465 /*
466  * NOTE:
467  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
468  * takes 1023 as the TX ticks limit.  However, using 1023 will
469  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
470  * there is _no_ network activity on the NIC.
471  */
472 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
473 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
474 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
475 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
476 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
477 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
478 static uint32_t bce_rx_ticks_int = 150;         /* bcm: 18 */
479 static uint32_t bce_rx_ticks = 150;             /* bcm: 18 */
480
481 static int      bce_msi_enable = 1;
482
483 static int      bce_rx_pages = RX_PAGES_DEFAULT;
484 static int      bce_tx_pages = TX_PAGES_DEFAULT;
485
486 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
487 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
488 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
489 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
490 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
491 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
492 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
493 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
494 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
495 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
496 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
497
498 /****************************************************************************/
499 /* DragonFly device dispatch table.                                         */
500 /****************************************************************************/
501 static device_method_t bce_methods[] = {
502         /* Device interface */
503         DEVMETHOD(device_probe,         bce_probe),
504         DEVMETHOD(device_attach,        bce_attach),
505         DEVMETHOD(device_detach,        bce_detach),
506         DEVMETHOD(device_shutdown,      bce_shutdown),
507
508         /* bus interface */
509         DEVMETHOD(bus_print_child,      bus_generic_print_child),
510         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
511
512         /* MII interface */
513         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
514         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
515         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
516
517         { 0, 0 }
518 };
519
520 static driver_t bce_driver = {
521         "bce",
522         bce_methods,
523         sizeof(struct bce_softc)
524 };
525
526 static devclass_t bce_devclass;
527
528
529 DECLARE_DUMMY_MODULE(if_bce);
530 MODULE_DEPEND(bce, miibus, 1, 1, 1);
531 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
532 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
533
534
535 /****************************************************************************/
536 /* Device probe function.                                                   */
537 /*                                                                          */
538 /* Compares the device to the driver's list of supported devices and        */
539 /* reports back to the OS whether this is the right driver for the device.  */
540 /*                                                                          */
541 /* Returns:                                                                 */
542 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
543 /****************************************************************************/
544 static int
545 bce_probe(device_t dev)
546 {
547         struct bce_type *t;
548         uint16_t vid, did, svid, sdid;
549
550         /* Get the data for the device to be probed. */
551         vid  = pci_get_vendor(dev);
552         did  = pci_get_device(dev);
553         svid = pci_get_subvendor(dev);
554         sdid = pci_get_subdevice(dev);
555
556         /* Look through the list of known devices for a match. */
557         for (t = bce_devs; t->bce_name != NULL; ++t) {
558                 if (vid == t->bce_vid && did == t->bce_did && 
559                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
560                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
561                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
562                         char *descbuf;
563
564                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
565
566                         /* Print out the device identity. */
567                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
568                                   t->bce_name,
569                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
570
571                         device_set_desc_copy(dev, descbuf);
572                         kfree(descbuf, M_TEMP);
573                         return 0;
574                 }
575         }
576         return ENXIO;
577 }
578
579
580 /****************************************************************************/
581 /* PCI Capabilities Probe Function.                                         */
582 /*                                                                          */
583 /* Walks the PCI capabiites list for the device to find what features are   */
584 /* supported.                                                               */
585 /*                                                                          */
586 /* Returns:                                                                 */
587 /*   None.                                                                  */
588 /****************************************************************************/
589 static void
590 bce_print_adapter_info(struct bce_softc *sc)
591 {
592         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
593
594         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
595                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
596
597         /* Bus info. */
598         if (sc->bce_flags & BCE_PCIE_FLAG) {
599                 kprintf("Bus (PCIe x%d, ", sc->link_width);
600                 switch (sc->link_speed) {
601                 case 1:
602                         kprintf("2.5Gbps); ");
603                         break;
604                 case 2:
605                         kprintf("5Gbps); ");
606                         break;
607                 default:
608                         kprintf("Unknown link speed); ");
609                         break;
610                 }
611         } else {
612                 kprintf("Bus (PCI%s, %s, %dMHz); ",
613                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
614                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
615                     sc->bus_speed_mhz);
616         }
617
618         /* Firmware version and device features. */
619         kprintf("B/C (%s)", sc->bce_bc_ver);
620
621         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
622             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
623                 kprintf("; Flags(");
624                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
625                         kprintf("MFW[%s]", sc->bce_mfw_ver);
626                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
627                         kprintf(" 2.5G");
628                 kprintf(")");
629         }
630         kprintf("\n");
631 }
632
633
634 /****************************************************************************/
635 /* PCI Capabilities Probe Function.                                         */
636 /*                                                                          */
637 /* Walks the PCI capabiites list for the device to find what features are   */
638 /* supported.                                                               */
639 /*                                                                          */
640 /* Returns:                                                                 */
641 /*   None.                                                                  */
642 /****************************************************************************/
643 static void
644 bce_probe_pci_caps(struct bce_softc *sc)
645 {
646         device_t dev = sc->bce_dev;
647         uint8_t ptr;
648
649         if (pci_is_pcix(dev))
650                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
651
652         ptr = pci_get_pciecap_ptr(dev);
653         if (ptr) {
654                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
655
656                 sc->link_speed = link_status & 0xf;
657                 sc->link_width = (link_status >> 4) & 0x3f;
658                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
659                 sc->bce_flags |= BCE_PCIE_FLAG;
660         }
661 }
662
663
664 /****************************************************************************/
665 /* Device attach function.                                                  */
666 /*                                                                          */
667 /* Allocates device resources, performs secondary chip identification,      */
668 /* resets and initializes the hardware, and initializes driver instance     */
669 /* variables.                                                               */
670 /*                                                                          */
671 /* Returns:                                                                 */
672 /*   0 on success, positive value on failure.                               */
673 /****************************************************************************/
674 static int
675 bce_attach(device_t dev)
676 {
677         struct bce_softc *sc = device_get_softc(dev);
678         struct ifnet *ifp = &sc->arpcom.ac_if;
679         uint32_t val;
680         u_int irq_flags;
681         void (*irq_handle)(void *);
682         int rid, rc = 0;
683         int i, j;
684         struct mii_probe_args mii_args;
685         uintptr_t mii_priv = 0;
686
687         sc->bce_dev = dev;
688         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
689
690         pci_enable_busmaster(dev);
691
692         bce_probe_pci_caps(sc);
693
694         /* Allocate PCI memory resources. */
695         rid = PCIR_BAR(0);
696         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
697                                                  RF_ACTIVE | PCI_RF_DENSE);
698         if (sc->bce_res_mem == NULL) {
699                 device_printf(dev, "PCI memory allocation failed\n");
700                 return ENXIO;
701         }
702         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
703         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
704
705         /* Allocate PCI IRQ resources. */
706         sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
707             &sc->bce_irq_rid, &irq_flags);
708
709         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
710             &sc->bce_irq_rid, irq_flags);
711         if (sc->bce_res_irq == NULL) {
712                 device_printf(dev, "PCI map interrupt failed\n");
713                 rc = ENXIO;
714                 goto fail;
715         }
716
717         /*
718          * Configure byte swap and enable indirect register access.
719          * Rely on CPU to do target byte swapping on big endian systems.
720          * Access to registers outside of PCI configurtion space are not
721          * valid until this is done.
722          */
723         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
724                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
725                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
726
727         /* Save ASIC revsion info. */
728         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
729
730         /* Weed out any non-production controller revisions. */
731         switch (BCE_CHIP_ID(sc)) {
732         case BCE_CHIP_ID_5706_A0:
733         case BCE_CHIP_ID_5706_A1:
734         case BCE_CHIP_ID_5708_A0:
735         case BCE_CHIP_ID_5708_B0:
736         case BCE_CHIP_ID_5709_A0:
737         case BCE_CHIP_ID_5709_B0:
738         case BCE_CHIP_ID_5709_B1:
739 #ifdef foo
740         /* 5709C B2 seems to work fine */
741         case BCE_CHIP_ID_5709_B2:
742 #endif
743                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
744                               BCE_CHIP_ID(sc));
745                 rc = ENODEV;
746                 goto fail;
747         }
748
749         mii_priv |= BRGPHY_FLAG_WIRESPEED;
750         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
751                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax ||
752                     BCE_CHIP_REV(sc) == BCE_CHIP_REV_Bx)
753                         mii_priv |= BRGPHY_FLAG_NO_EARLYDAC;
754         } else {
755                 mii_priv |= BRGPHY_FLAG_BER_BUG;
756         }
757
758         if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
759                 irq_handle = bce_intr_legacy;
760         } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
761                 irq_handle = bce_intr_msi;
762                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
763                         irq_handle = bce_intr_msi_oneshot;
764                         sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
765                 }
766         } else {
767                 panic("%s: unsupported intr type %d",
768                     device_get_nameunit(dev), sc->bce_irq_type);
769         }
770
771         /*
772          * Find the base address for shared memory access.
773          * Newer versions of bootcode use a signature and offset
774          * while older versions use a fixed address.
775          */
776         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
777         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
778             BCE_SHM_HDR_SIGNATURE_SIG) {
779                 /* Multi-port devices use different offsets in shared memory. */
780                 sc->bce_shmem_base = REG_RD_IND(sc,
781                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
782         } else {
783                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
784         }
785         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
786
787         /* Fetch the bootcode revision. */
788         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
789         for (i = 0, j = 0; i < 3; i++) {
790                 uint8_t num;
791                 int k, skip0;
792
793                 num = (uint8_t)(val >> (24 - (i * 8)));
794                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
795                         if (num >= k || !skip0 || k == 1) {
796                                 sc->bce_bc_ver[j++] = (num / k) + '0';
797                                 skip0 = 0;
798                         }
799                 }
800                 if (i != 2)
801                         sc->bce_bc_ver[j++] = '.';
802         }
803
804         /* Check if any management firwmare is running. */
805         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
806         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
807                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
808
809                 /* Allow time for firmware to enter the running state. */
810                 for (i = 0; i < 30; i++) {
811                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
812                         if (val & BCE_CONDITION_MFW_RUN_MASK)
813                                 break;
814                         DELAY(10000);
815                 }
816         }
817
818         /* Check the current bootcode state. */
819         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
820             BCE_CONDITION_MFW_RUN_MASK;
821         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
822             val != BCE_CONDITION_MFW_RUN_NONE) {
823                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
824
825                 for (i = 0, j = 0; j < 3; j++) {
826                         val = bce_reg_rd_ind(sc, addr + j * 4);
827                         val = bswap32(val);
828                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
829                         i += 4;
830                 }
831         }
832
833         /* Get PCI bus information (speed and type). */
834         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
835         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
836                 uint32_t clkreg;
837
838                 sc->bce_flags |= BCE_PCIX_FLAG;
839
840                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
841                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
842                 switch (clkreg) {
843                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
844                         sc->bus_speed_mhz = 133;
845                         break;
846
847                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
848                         sc->bus_speed_mhz = 100;
849                         break;
850
851                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
852                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
853                         sc->bus_speed_mhz = 66;
854                         break;
855
856                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
857                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
858                         sc->bus_speed_mhz = 50;
859                         break;
860
861                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
862                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
863                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
864                         sc->bus_speed_mhz = 33;
865                         break;
866                 }
867         } else {
868                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
869                         sc->bus_speed_mhz = 66;
870                 else
871                         sc->bus_speed_mhz = 33;
872         }
873
874         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
875                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
876
877         /* Reset the controller. */
878         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
879         if (rc != 0)
880                 goto fail;
881
882         /* Initialize the controller. */
883         rc = bce_chipinit(sc);
884         if (rc != 0) {
885                 device_printf(dev, "Controller initialization failed!\n");
886                 goto fail;
887         }
888
889         /* Perform NVRAM test. */
890         rc = bce_nvram_test(sc);
891         if (rc != 0) {
892                 device_printf(dev, "NVRAM test failed!\n");
893                 goto fail;
894         }
895
896         /* Fetch the permanent Ethernet MAC address. */
897         bce_get_mac_addr(sc);
898
899         /*
900          * Trip points control how many BDs
901          * should be ready before generating an
902          * interrupt while ticks control how long
903          * a BD can sit in the chain before
904          * generating an interrupt.  Set the default 
905          * values for the RX and TX rings.
906          */
907
908 #ifdef BCE_DRBUG
909         /* Force more frequent interrupts. */
910         sc->bce_tx_quick_cons_trip_int = 1;
911         sc->bce_tx_quick_cons_trip     = 1;
912         sc->bce_tx_ticks_int           = 0;
913         sc->bce_tx_ticks               = 0;
914
915         sc->bce_rx_quick_cons_trip_int = 1;
916         sc->bce_rx_quick_cons_trip     = 1;
917         sc->bce_rx_ticks_int           = 0;
918         sc->bce_rx_ticks               = 0;
919 #else
920         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
921         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
922         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
923         sc->bce_tx_ticks               = bce_tx_ticks;
924
925         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
926         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
927         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
928         sc->bce_rx_ticks               = bce_rx_ticks;
929 #endif
930
931         /* Update statistics once every second. */
932         sc->bce_stats_ticks = 1000000 & 0xffff00;
933
934         /* Find the media type for the adapter. */
935         bce_get_media(sc);
936
937         /* Allocate DMA memory resources. */
938         rc = bce_dma_alloc(sc);
939         if (rc != 0) {
940                 device_printf(dev, "DMA resource allocation failed!\n");
941                 goto fail;
942         }
943
944         /* Initialize the ifnet interface. */
945         ifp->if_softc = sc;
946         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
947         ifp->if_ioctl = bce_ioctl;
948         ifp->if_start = bce_start;
949         ifp->if_init = bce_init;
950         ifp->if_watchdog = bce_watchdog;
951 #ifdef DEVICE_POLLING
952         ifp->if_poll = bce_poll;
953 #endif
954         ifp->if_mtu = ETHERMTU;
955         ifp->if_hwassist = BCE_IF_HWASSIST;
956         ifp->if_capabilities = BCE_IF_CAPABILITIES;
957         ifp->if_capenable = ifp->if_capabilities;
958         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD(sc));
959         ifq_set_ready(&ifp->if_snd);
960
961         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
962                 ifp->if_baudrate = IF_Gbps(2.5);
963         else
964                 ifp->if_baudrate = IF_Gbps(1);
965
966         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
967         sc->mbuf_alloc_size  = MCLBYTES;
968
969         /*
970          * Look for our PHY.
971          */
972         mii_probe_args_init(&mii_args, bce_ifmedia_upd, bce_ifmedia_sts);
973         mii_args.mii_probemask = 1 << sc->bce_phy_addr;
974         mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
975         mii_args.mii_priv = mii_priv;
976
977         rc = mii_probe(dev, &sc->bce_miibus, &mii_args);
978         if (rc != 0) {
979                 device_printf(dev, "PHY probe failed!\n");
980                 goto fail;
981         }
982
983         /* Attach to the Ethernet interface list. */
984         ether_ifattach(ifp, sc->eaddr, NULL);
985
986         callout_init_mp(&sc->bce_tick_callout);
987         callout_init_mp(&sc->bce_pulse_callout);
988
989         /* Hookup IRQ last. */
990         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
991                             &sc->bce_intrhand, ifp->if_serializer);
992         if (rc != 0) {
993                 device_printf(dev, "Failed to setup IRQ!\n");
994                 ether_ifdetach(ifp);
995                 goto fail;
996         }
997
998         ifp->if_cpuid = rman_get_cpuid(sc->bce_res_irq);
999         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1000
1001         /* Print some important debugging info. */
1002         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
1003
1004         /* Add the supported sysctls to the kernel. */
1005         bce_add_sysctls(sc);
1006
1007         /*
1008          * The chip reset earlier notified the bootcode that
1009          * a driver is present.  We now need to start our pulse
1010          * routine so that the bootcode is reminded that we're
1011          * still running.
1012          */
1013         bce_pulse(sc);
1014
1015         /* Get the firmware running so IPMI still works */
1016         bce_mgmt_init(sc);
1017
1018         if (bootverbose)
1019                 bce_print_adapter_info(sc);
1020
1021         return 0;
1022 fail:
1023         bce_detach(dev);
1024         return(rc);
1025 }
1026
1027
1028 /****************************************************************************/
1029 /* Device detach function.                                                  */
1030 /*                                                                          */
1031 /* Stops the controller, resets the controller, and releases resources.     */
1032 /*                                                                          */
1033 /* Returns:                                                                 */
1034 /*   0 on success, positive value on failure.                               */
1035 /****************************************************************************/
1036 static int
1037 bce_detach(device_t dev)
1038 {
1039         struct bce_softc *sc = device_get_softc(dev);
1040
1041         if (device_is_attached(dev)) {
1042                 struct ifnet *ifp = &sc->arpcom.ac_if;
1043                 uint32_t msg;
1044
1045                 /* Stop and reset the controller. */
1046                 lwkt_serialize_enter(ifp->if_serializer);
1047                 callout_stop(&sc->bce_pulse_callout);
1048                 bce_stop(sc);
1049                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1050                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1051                 else
1052                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1053                 bce_reset(sc, msg);
1054                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1055                 lwkt_serialize_exit(ifp->if_serializer);
1056
1057                 ether_ifdetach(ifp);
1058         }
1059
1060         /* If we have a child device on the MII bus remove it too. */
1061         if (sc->bce_miibus)
1062                 device_delete_child(dev, sc->bce_miibus);
1063         bus_generic_detach(dev);
1064
1065         if (sc->bce_res_irq != NULL) {
1066                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1067                     sc->bce_res_irq);
1068         }
1069
1070         if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1071                 pci_release_msi(dev);
1072
1073         if (sc->bce_res_mem != NULL) {
1074                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1075                                      sc->bce_res_mem);
1076         }
1077
1078         bce_dma_free(sc);
1079
1080         if (sc->bce_sysctl_tree != NULL)
1081                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1082
1083         return 0;
1084 }
1085
1086
1087 /****************************************************************************/
1088 /* Device shutdown function.                                                */
1089 /*                                                                          */
1090 /* Stops and resets the controller.                                         */
1091 /*                                                                          */
1092 /* Returns:                                                                 */
1093 /*   Nothing                                                                */
1094 /****************************************************************************/
1095 static void
1096 bce_shutdown(device_t dev)
1097 {
1098         struct bce_softc *sc = device_get_softc(dev);
1099         struct ifnet *ifp = &sc->arpcom.ac_if;
1100         uint32_t msg;
1101
1102         lwkt_serialize_enter(ifp->if_serializer);
1103         bce_stop(sc);
1104         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1105                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1106         else
1107                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1108         bce_reset(sc, msg);
1109         lwkt_serialize_exit(ifp->if_serializer);
1110 }
1111
1112
1113 /****************************************************************************/
1114 /* Indirect register read.                                                  */
1115 /*                                                                          */
1116 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1117 /* configuration space.  Using this mechanism avoids issues with posted     */
1118 /* reads but is much slower than memory-mapped I/O.                         */
1119 /*                                                                          */
1120 /* Returns:                                                                 */
1121 /*   The value of the register.                                             */
1122 /****************************************************************************/
1123 static uint32_t
1124 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1125 {
1126         device_t dev = sc->bce_dev;
1127
1128         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1129 #ifdef BCE_DEBUG
1130         {
1131                 uint32_t val;
1132                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1133                 DBPRINT(sc, BCE_EXCESSIVE,
1134                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1135                         __func__, offset, val);
1136                 return val;
1137         }
1138 #else
1139         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1140 #endif
1141 }
1142
1143
1144 /****************************************************************************/
1145 /* Indirect register write.                                                 */
1146 /*                                                                          */
1147 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1148 /* configuration space.  Using this mechanism avoids issues with posted     */
1149 /* writes but is muchh slower than memory-mapped I/O.                       */
1150 /*                                                                          */
1151 /* Returns:                                                                 */
1152 /*   Nothing.                                                               */
1153 /****************************************************************************/
1154 static void
1155 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1156 {
1157         device_t dev = sc->bce_dev;
1158
1159         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1160                 __func__, offset, val);
1161
1162         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1163         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1164 }
1165
1166
1167 /****************************************************************************/
1168 /* Shared memory write.                                                     */
1169 /*                                                                          */
1170 /* Writes NetXtreme II shared memory region.                                */
1171 /*                                                                          */
1172 /* Returns:                                                                 */
1173 /*   Nothing.                                                               */
1174 /****************************************************************************/
1175 static void
1176 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1177 {
1178         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1179 }
1180
1181
1182 /****************************************************************************/
1183 /* Shared memory read.                                                      */
1184 /*                                                                          */
1185 /* Reads NetXtreme II shared memory region.                                 */
1186 /*                                                                          */
1187 /* Returns:                                                                 */
1188 /*   The 32 bit value read.                                                 */
1189 /****************************************************************************/
1190 static u32
1191 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1192 {
1193         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1194 }
1195
1196
1197 /****************************************************************************/
1198 /* Context memory write.                                                    */
1199 /*                                                                          */
1200 /* The NetXtreme II controller uses context memory to track connection      */
1201 /* information for L2 and higher network protocols.                         */
1202 /*                                                                          */
1203 /* Returns:                                                                 */
1204 /*   Nothing.                                                               */
1205 /****************************************************************************/
1206 static void
1207 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1208     uint32_t ctx_val)
1209 {
1210         uint32_t idx, offset = ctx_offset + cid_addr;
1211         uint32_t val, retry_cnt = 5;
1212
1213         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1214             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1215                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1216                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1217
1218                 for (idx = 0; idx < retry_cnt; idx++) {
1219                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1220                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1221                                 break;
1222                         DELAY(5);
1223                 }
1224
1225                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1226                         device_printf(sc->bce_dev,
1227                             "Unable to write CTX memory: "
1228                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1229                             cid_addr, ctx_offset);
1230                 }
1231         } else {
1232                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1233                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1234         }
1235 }
1236
1237
1238 /****************************************************************************/
1239 /* PHY register read.                                                       */
1240 /*                                                                          */
1241 /* Implements register reads on the MII bus.                                */
1242 /*                                                                          */
1243 /* Returns:                                                                 */
1244 /*   The value of the register.                                             */
1245 /****************************************************************************/
1246 static int
1247 bce_miibus_read_reg(device_t dev, int phy, int reg)
1248 {
1249         struct bce_softc *sc = device_get_softc(dev);
1250         uint32_t val;
1251         int i;
1252
1253         /* Make sure we are accessing the correct PHY address. */
1254         KASSERT(phy == sc->bce_phy_addr,
1255             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1256
1257         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1258                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1259                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1260
1261                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1262                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1263
1264                 DELAY(40);
1265         }
1266
1267         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1268               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1269               BCE_EMAC_MDIO_COMM_START_BUSY;
1270         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1271
1272         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1273                 DELAY(10);
1274
1275                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1276                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1277                         DELAY(5);
1278
1279                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1280                         val &= BCE_EMAC_MDIO_COMM_DATA;
1281                         break;
1282                 }
1283         }
1284
1285         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1286                 if_printf(&sc->arpcom.ac_if,
1287                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1288                           phy, reg);
1289                 val = 0x0;
1290         } else {
1291                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1292         }
1293
1294         DBPRINT(sc, BCE_EXCESSIVE,
1295                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1296                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1297
1298         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1299                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1300                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1301
1302                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1303                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1304
1305                 DELAY(40);
1306         }
1307         return (val & 0xffff);
1308 }
1309
1310
1311 /****************************************************************************/
1312 /* PHY register write.                                                      */
1313 /*                                                                          */
1314 /* Implements register writes on the MII bus.                               */
1315 /*                                                                          */
1316 /* Returns:                                                                 */
1317 /*   The value of the register.                                             */
1318 /****************************************************************************/
1319 static int
1320 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1321 {
1322         struct bce_softc *sc = device_get_softc(dev);
1323         uint32_t val1;
1324         int i;
1325
1326         /* Make sure we are accessing the correct PHY address. */
1327         KASSERT(phy == sc->bce_phy_addr,
1328             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1329
1330         DBPRINT(sc, BCE_EXCESSIVE,
1331                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1332                 __func__, phy, (uint16_t)(reg & 0xffff),
1333                 (uint16_t)(val & 0xffff));
1334
1335         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1336                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1337                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1338
1339                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1340                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1341
1342                 DELAY(40);
1343         }
1344
1345         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1346                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1347                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1348         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1349
1350         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1351                 DELAY(10);
1352
1353                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1354                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1355                         DELAY(5);
1356                         break;
1357                 }
1358         }
1359
1360         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1361                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1362
1363         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1364                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1365                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1366
1367                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1368                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1369
1370                 DELAY(40);
1371         }
1372         return 0;
1373 }
1374
1375
1376 /****************************************************************************/
1377 /* MII bus status change.                                                   */
1378 /*                                                                          */
1379 /* Called by the MII bus driver when the PHY establishes link to set the    */
1380 /* MAC interface registers.                                                 */
1381 /*                                                                          */
1382 /* Returns:                                                                 */
1383 /*   Nothing.                                                               */
1384 /****************************************************************************/
1385 static void
1386 bce_miibus_statchg(device_t dev)
1387 {
1388         struct bce_softc *sc = device_get_softc(dev);
1389         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1390
1391         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1392                 mii->mii_media_active);
1393
1394 #ifdef BCE_DEBUG
1395         /* Decode the interface media flags. */
1396         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1397         switch(IFM_TYPE(mii->mii_media_active)) {
1398         case IFM_ETHER:
1399                 kprintf("Ethernet )");
1400                 break;
1401         default:
1402                 kprintf("Unknown )");
1403                 break;
1404         }
1405
1406         kprintf(" Media Options: ( ");
1407         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1408         case IFM_AUTO:
1409                 kprintf("Autoselect )");
1410                 break;
1411         case IFM_MANUAL:
1412                 kprintf("Manual )");
1413                 break;
1414         case IFM_NONE:
1415                 kprintf("None )");
1416                 break;
1417         case IFM_10_T:
1418                 kprintf("10Base-T )");
1419                 break;
1420         case IFM_100_TX:
1421                 kprintf("100Base-TX )");
1422                 break;
1423         case IFM_1000_SX:
1424                 kprintf("1000Base-SX )");
1425                 break;
1426         case IFM_1000_T:
1427                 kprintf("1000Base-T )");
1428                 break;
1429         default:
1430                 kprintf("Other )");
1431                 break;
1432         }
1433
1434         kprintf(" Global Options: (");
1435         if (mii->mii_media_active & IFM_FDX)
1436                 kprintf(" FullDuplex");
1437         if (mii->mii_media_active & IFM_HDX)
1438                 kprintf(" HalfDuplex");
1439         if (mii->mii_media_active & IFM_LOOP)
1440                 kprintf(" Loopback");
1441         if (mii->mii_media_active & IFM_FLAG0)
1442                 kprintf(" Flag0");
1443         if (mii->mii_media_active & IFM_FLAG1)
1444                 kprintf(" Flag1");
1445         if (mii->mii_media_active & IFM_FLAG2)
1446                 kprintf(" Flag2");
1447         kprintf(" )\n");
1448 #endif
1449
1450         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1451
1452         /*
1453          * Set MII or GMII interface based on the speed negotiated
1454          * by the PHY.
1455          */
1456         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 
1457             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1458                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1459                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1460         } else {
1461                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1462                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1463         }
1464
1465         /*
1466          * Set half or full duplex based on the duplicity negotiated
1467          * by the PHY.
1468          */
1469         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1470                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1471                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1472         } else {
1473                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1474                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1475         }
1476 }
1477
1478
1479 /****************************************************************************/
1480 /* Acquire NVRAM lock.                                                      */
1481 /*                                                                          */
1482 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1483 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1484 /* for use by the driver.                                                   */
1485 /*                                                                          */
1486 /* Returns:                                                                 */
1487 /*   0 on success, positive value on failure.                               */
1488 /****************************************************************************/
1489 static int
1490 bce_acquire_nvram_lock(struct bce_softc *sc)
1491 {
1492         uint32_t val;
1493         int j;
1494
1495         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1496
1497         /* Request access to the flash interface. */
1498         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1499         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1500                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1501                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1502                         break;
1503
1504                 DELAY(5);
1505         }
1506
1507         if (j >= NVRAM_TIMEOUT_COUNT) {
1508                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1509                 return EBUSY;
1510         }
1511         return 0;
1512 }
1513
1514
1515 /****************************************************************************/
1516 /* Release NVRAM lock.                                                      */
1517 /*                                                                          */
1518 /* When the caller is finished accessing NVRAM the lock must be released.   */
1519 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1520 /* for use by the driver.                                                   */
1521 /*                                                                          */
1522 /* Returns:                                                                 */
1523 /*   0 on success, positive value on failure.                               */
1524 /****************************************************************************/
1525 static int
1526 bce_release_nvram_lock(struct bce_softc *sc)
1527 {
1528         int j;
1529         uint32_t val;
1530
1531         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1532
1533         /*
1534          * Relinquish nvram interface.
1535          */
1536         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1537
1538         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1539                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1540                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1541                         break;
1542
1543                 DELAY(5);
1544         }
1545
1546         if (j >= NVRAM_TIMEOUT_COUNT) {
1547                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1548                 return EBUSY;
1549         }
1550         return 0;
1551 }
1552
1553
1554 /****************************************************************************/
1555 /* Enable NVRAM access.                                                     */
1556 /*                                                                          */
1557 /* Before accessing NVRAM for read or write operations the caller must      */
1558 /* enabled NVRAM access.                                                    */
1559 /*                                                                          */
1560 /* Returns:                                                                 */
1561 /*   Nothing.                                                               */
1562 /****************************************************************************/
1563 static void
1564 bce_enable_nvram_access(struct bce_softc *sc)
1565 {
1566         uint32_t val;
1567
1568         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1569
1570         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1571         /* Enable both bits, even on read. */
1572         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1573                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1574 }
1575
1576
1577 /****************************************************************************/
1578 /* Disable NVRAM access.                                                    */
1579 /*                                                                          */
1580 /* When the caller is finished accessing NVRAM access must be disabled.     */
1581 /*                                                                          */
1582 /* Returns:                                                                 */
1583 /*   Nothing.                                                               */
1584 /****************************************************************************/
1585 static void
1586 bce_disable_nvram_access(struct bce_softc *sc)
1587 {
1588         uint32_t val;
1589
1590         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1591
1592         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1593
1594         /* Disable both bits, even after read. */
1595         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1596                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1597 }
1598
1599
1600 /****************************************************************************/
1601 /* Read a dword (32 bits) from NVRAM.                                       */
1602 /*                                                                          */
1603 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1604 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1605 /*                                                                          */
1606 /* Returns:                                                                 */
1607 /*   0 on success and the 32 bit value read, positive value on failure.     */
1608 /****************************************************************************/
1609 static int
1610 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1611                      uint32_t cmd_flags)
1612 {
1613         uint32_t cmd;
1614         int i, rc = 0;
1615
1616         /* Build the command word. */
1617         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1618
1619         /* Calculate the offset for buffered flash. */
1620         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1621                 offset = ((offset / sc->bce_flash_info->page_size) <<
1622                           sc->bce_flash_info->page_bits) +
1623                          (offset % sc->bce_flash_info->page_size);
1624         }
1625
1626         /*
1627          * Clear the DONE bit separately, set the address to read,
1628          * and issue the read.
1629          */
1630         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1631         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1632         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1633
1634         /* Wait for completion. */
1635         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1636                 uint32_t val;
1637
1638                 DELAY(5);
1639
1640                 val = REG_RD(sc, BCE_NVM_COMMAND);
1641                 if (val & BCE_NVM_COMMAND_DONE) {
1642                         val = REG_RD(sc, BCE_NVM_READ);
1643
1644                         val = be32toh(val);
1645                         memcpy(ret_val, &val, 4);
1646                         break;
1647                 }
1648         }
1649
1650         /* Check for errors. */
1651         if (i >= NVRAM_TIMEOUT_COUNT) {
1652                 if_printf(&sc->arpcom.ac_if,
1653                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1654                           offset);
1655                 rc = EBUSY;
1656         }
1657         return rc;
1658 }
1659
1660
1661 /****************************************************************************/
1662 /* Initialize NVRAM access.                                                 */
1663 /*                                                                          */
1664 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1665 /* access that device.                                                      */
1666 /*                                                                          */
1667 /* Returns:                                                                 */
1668 /*   0 on success, positive value on failure.                               */
1669 /****************************************************************************/
1670 static int
1671 bce_init_nvram(struct bce_softc *sc)
1672 {
1673         uint32_t val;
1674         int j, entry_count, rc = 0;
1675         const struct flash_spec *flash;
1676
1677         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1678
1679         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1680             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1681                 sc->bce_flash_info = &flash_5709;
1682                 goto bce_init_nvram_get_flash_size;
1683         }
1684
1685         /* Determine the selected interface. */
1686         val = REG_RD(sc, BCE_NVM_CFG1);
1687
1688         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1689
1690         /*
1691          * Flash reconfiguration is required to support additional
1692          * NVRAM devices not directly supported in hardware.
1693          * Check if the flash interface was reconfigured
1694          * by the bootcode.
1695          */
1696
1697         if (val & 0x40000000) {
1698                 /* Flash interface reconfigured by bootcode. */
1699
1700                 DBPRINT(sc, BCE_INFO_LOAD, 
1701                         "%s(): Flash WAS reconfigured.\n", __func__);
1702
1703                 for (j = 0, flash = flash_table; j < entry_count;
1704                      j++, flash++) {
1705                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1706                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1707                                 sc->bce_flash_info = flash;
1708                                 break;
1709                         }
1710                 }
1711         } else {
1712                 /* Flash interface not yet reconfigured. */
1713                 uint32_t mask;
1714
1715                 DBPRINT(sc, BCE_INFO_LOAD, 
1716                         "%s(): Flash was NOT reconfigured.\n", __func__);
1717
1718                 if (val & (1 << 23))
1719                         mask = FLASH_BACKUP_STRAP_MASK;
1720                 else
1721                         mask = FLASH_STRAP_MASK;
1722
1723                 /* Look for the matching NVRAM device configuration data. */
1724                 for (j = 0, flash = flash_table; j < entry_count;
1725                      j++, flash++) {
1726                         /* Check if the device matches any of the known devices. */
1727                         if ((val & mask) == (flash->strapping & mask)) {
1728                                 /* Found a device match. */
1729                                 sc->bce_flash_info = flash;
1730
1731                                 /* Request access to the flash interface. */
1732                                 rc = bce_acquire_nvram_lock(sc);
1733                                 if (rc != 0)
1734                                         return rc;
1735
1736                                 /* Reconfigure the flash interface. */
1737                                 bce_enable_nvram_access(sc);
1738                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1739                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1740                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1741                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1742                                 bce_disable_nvram_access(sc);
1743                                 bce_release_nvram_lock(sc);
1744                                 break;
1745                         }
1746                 }
1747         }
1748
1749         /* Check if a matching device was found. */
1750         if (j == entry_count) {
1751                 sc->bce_flash_info = NULL;
1752                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1753                 return ENODEV;
1754         }
1755
1756 bce_init_nvram_get_flash_size:
1757         /* Write the flash config data to the shared memory interface. */
1758         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1759             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1760         if (val)
1761                 sc->bce_flash_size = val;
1762         else
1763                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1764
1765         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1766                 __func__, sc->bce_flash_info->total_size);
1767
1768         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1769
1770         return rc;
1771 }
1772
1773
1774 /****************************************************************************/
1775 /* Read an arbitrary range of data from NVRAM.                              */
1776 /*                                                                          */
1777 /* Prepares the NVRAM interface for access and reads the requested data     */
1778 /* into the supplied buffer.                                                */
1779 /*                                                                          */
1780 /* Returns:                                                                 */
1781 /*   0 on success and the data read, positive value on failure.             */
1782 /****************************************************************************/
1783 static int
1784 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1785                int buf_size)
1786 {
1787         uint32_t cmd_flags, offset32, len32, extra;
1788         int rc = 0;
1789
1790         if (buf_size == 0)
1791                 return 0;
1792
1793         /* Request access to the flash interface. */
1794         rc = bce_acquire_nvram_lock(sc);
1795         if (rc != 0)
1796                 return rc;
1797
1798         /* Enable access to flash interface */
1799         bce_enable_nvram_access(sc);
1800
1801         len32 = buf_size;
1802         offset32 = offset;
1803         extra = 0;
1804
1805         cmd_flags = 0;
1806
1807         /* XXX should we release nvram lock if read_dword() fails? */
1808         if (offset32 & 3) {
1809                 uint8_t buf[4];
1810                 uint32_t pre_len;
1811
1812                 offset32 &= ~3;
1813                 pre_len = 4 - (offset & 3);
1814
1815                 if (pre_len >= len32) {
1816                         pre_len = len32;
1817                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1818                 } else {
1819                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1820                 }
1821
1822                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1823                 if (rc)
1824                         return rc;
1825
1826                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1827
1828                 offset32 += 4;
1829                 ret_buf += pre_len;
1830                 len32 -= pre_len;
1831         }
1832
1833         if (len32 & 3) {
1834                 extra = 4 - (len32 & 3);
1835                 len32 = (len32 + 4) & ~3;
1836         }
1837
1838         if (len32 == 4) {
1839                 uint8_t buf[4];
1840
1841                 if (cmd_flags)
1842                         cmd_flags = BCE_NVM_COMMAND_LAST;
1843                 else
1844                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1845                                     BCE_NVM_COMMAND_LAST;
1846
1847                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1848
1849                 memcpy(ret_buf, buf, 4 - extra);
1850         } else if (len32 > 0) {
1851                 uint8_t buf[4];
1852
1853                 /* Read the first word. */
1854                 if (cmd_flags)
1855                         cmd_flags = 0;
1856                 else
1857                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1858
1859                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1860
1861                 /* Advance to the next dword. */
1862                 offset32 += 4;
1863                 ret_buf += 4;
1864                 len32 -= 4;
1865
1866                 while (len32 > 4 && rc == 0) {
1867                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1868
1869                         /* Advance to the next dword. */
1870                         offset32 += 4;
1871                         ret_buf += 4;
1872                         len32 -= 4;
1873                 }
1874
1875                 if (rc)
1876                         goto bce_nvram_read_locked_exit;
1877
1878                 cmd_flags = BCE_NVM_COMMAND_LAST;
1879                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1880
1881                 memcpy(ret_buf, buf, 4 - extra);
1882         }
1883
1884 bce_nvram_read_locked_exit:
1885         /* Disable access to flash interface and release the lock. */
1886         bce_disable_nvram_access(sc);
1887         bce_release_nvram_lock(sc);
1888
1889         return rc;
1890 }
1891
1892
1893 /****************************************************************************/
1894 /* Verifies that NVRAM is accessible and contains valid data.               */
1895 /*                                                                          */
1896 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1897 /* correct.                                                                 */
1898 /*                                                                          */
1899 /* Returns:                                                                 */
1900 /*   0 on success, positive value on failure.                               */
1901 /****************************************************************************/
1902 static int
1903 bce_nvram_test(struct bce_softc *sc)
1904 {
1905         uint32_t buf[BCE_NVRAM_SIZE / 4];
1906         uint32_t magic, csum;
1907         uint8_t *data = (uint8_t *)buf;
1908         int rc = 0;
1909
1910         /*
1911          * Check that the device NVRAM is valid by reading
1912          * the magic value at offset 0.
1913          */
1914         rc = bce_nvram_read(sc, 0, data, 4);
1915         if (rc != 0)
1916                 return rc;
1917
1918         magic = be32toh(buf[0]);
1919         if (magic != BCE_NVRAM_MAGIC) {
1920                 if_printf(&sc->arpcom.ac_if,
1921                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1922                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1923                 return ENODEV;
1924         }
1925
1926         /*
1927          * Verify that the device NVRAM includes valid
1928          * configuration data.
1929          */
1930         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1931         if (rc != 0)
1932                 return rc;
1933
1934         csum = ether_crc32_le(data, 0x100);
1935         if (csum != BCE_CRC32_RESIDUAL) {
1936                 if_printf(&sc->arpcom.ac_if,
1937                           "Invalid Manufacturing Information NVRAM CRC! "
1938                           "Expected: 0x%08X, Found: 0x%08X\n",
1939                           BCE_CRC32_RESIDUAL, csum);
1940                 return ENODEV;
1941         }
1942
1943         csum = ether_crc32_le(data + 0x100, 0x100);
1944         if (csum != BCE_CRC32_RESIDUAL) {
1945                 if_printf(&sc->arpcom.ac_if,
1946                           "Invalid Feature Configuration Information "
1947                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1948                           BCE_CRC32_RESIDUAL, csum);
1949                 rc = ENODEV;
1950         }
1951         return rc;
1952 }
1953
1954
1955 /****************************************************************************/
1956 /* Identifies the current media type of the controller and sets the PHY     */
1957 /* address.                                                                 */
1958 /*                                                                          */
1959 /* Returns:                                                                 */
1960 /*   Nothing.                                                               */
1961 /****************************************************************************/
1962 static void
1963 bce_get_media(struct bce_softc *sc)
1964 {
1965         uint32_t val;
1966
1967         sc->bce_phy_addr = 1;
1968
1969         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1970             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1971                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1972                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1973                 uint32_t strap;
1974
1975                 /*
1976                  * The BCM5709S is software configurable
1977                  * for Copper or SerDes operation.
1978                  */
1979                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1980                         return;
1981                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1982                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1983                         return;
1984                 }
1985
1986                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1987                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1988                 } else {
1989                         strap =
1990                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1991                 }
1992
1993                 if (pci_get_function(sc->bce_dev) == 0) {
1994                         switch (strap) {
1995                         case 0x4:
1996                         case 0x5:
1997                         case 0x6:
1998                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1999                                 break;
2000                         }
2001                 } else {
2002                         switch (strap) {
2003                         case 0x1:
2004                         case 0x2:
2005                         case 0x4:
2006                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2007                                 break;
2008                         }
2009                 }
2010         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
2011                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2012         }
2013
2014         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2015                 sc->bce_flags |= BCE_NO_WOL_FLAG;
2016                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2017                         sc->bce_phy_addr = 2;
2018                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2019                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2020                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2021                 }
2022         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2023             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2024                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2025         }
2026 }
2027
2028
2029 /****************************************************************************/
2030 /* Free any DMA memory owned by the driver.                                 */
2031 /*                                                                          */
2032 /* Scans through each data structre that requires DMA memory and frees      */
2033 /* the memory if allocated.                                                 */
2034 /*                                                                          */
2035 /* Returns:                                                                 */
2036 /*   Nothing.                                                               */
2037 /****************************************************************************/
2038 static void
2039 bce_dma_free(struct bce_softc *sc)
2040 {
2041         int i;
2042
2043         /* Destroy the status block. */
2044         if (sc->status_tag != NULL) {
2045                 if (sc->status_block != NULL) {
2046                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2047                         bus_dmamem_free(sc->status_tag, sc->status_block,
2048                                         sc->status_map);
2049                 }
2050                 bus_dma_tag_destroy(sc->status_tag);
2051         }
2052
2053         /* Destroy the statistics block. */
2054         if (sc->stats_tag != NULL) {
2055                 if (sc->stats_block != NULL) {
2056                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2057                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2058                                         sc->stats_map);
2059                 }
2060                 bus_dma_tag_destroy(sc->stats_tag);
2061         }
2062
2063         /* Destroy the CTX DMA stuffs. */
2064         if (sc->ctx_tag != NULL) {
2065                 for (i = 0; i < sc->ctx_pages; i++) {
2066                         if (sc->ctx_block[i] != NULL) {
2067                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2068                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2069                                                 sc->ctx_map[i]);
2070                         }
2071                 }
2072                 bus_dma_tag_destroy(sc->ctx_tag);
2073         }
2074
2075         /* Destroy the TX buffer descriptor DMA stuffs. */
2076         if (sc->tx_bd_chain_tag != NULL) {
2077                 for (i = 0; i < sc->tx_pages; i++) {
2078                         if (sc->tx_bd_chain[i] != NULL) {
2079                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2080                                                   sc->tx_bd_chain_map[i]);
2081                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2082                                                 sc->tx_bd_chain[i],
2083                                                 sc->tx_bd_chain_map[i]);
2084                         }
2085                 }
2086                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2087         }
2088
2089         /* Destroy the RX buffer descriptor DMA stuffs. */
2090         if (sc->rx_bd_chain_tag != NULL) {
2091                 for (i = 0; i < sc->rx_pages; i++) {
2092                         if (sc->rx_bd_chain[i] != NULL) {
2093                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2094                                                   sc->rx_bd_chain_map[i]);
2095                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2096                                                 sc->rx_bd_chain[i],
2097                                                 sc->rx_bd_chain_map[i]);
2098                         }
2099                 }
2100                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2101         }
2102
2103         /* Destroy the TX mbuf DMA stuffs. */
2104         if (sc->tx_mbuf_tag != NULL) {
2105                 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2106                         /* Must have been unloaded in bce_stop() */
2107                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2108                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2109                                            sc->tx_mbuf_map[i]);
2110                 }
2111                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2112         }
2113
2114         /* Destroy the RX mbuf DMA stuffs. */
2115         if (sc->rx_mbuf_tag != NULL) {
2116                 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2117                         /* Must have been unloaded in bce_stop() */
2118                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2119                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2120                                            sc->rx_mbuf_map[i]);
2121                 }
2122                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2123                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2124         }
2125
2126         /* Destroy the parent tag */
2127         if (sc->parent_tag != NULL)
2128                 bus_dma_tag_destroy(sc->parent_tag);
2129
2130         if (sc->tx_bd_chain_map != NULL)
2131                 kfree(sc->tx_bd_chain_map, M_DEVBUF);
2132         if (sc->tx_bd_chain != NULL)
2133                 kfree(sc->tx_bd_chain, M_DEVBUF);
2134         if (sc->tx_bd_chain_paddr != NULL)
2135                 kfree(sc->tx_bd_chain_paddr, M_DEVBUF);
2136
2137         if (sc->rx_bd_chain_map != NULL)
2138                 kfree(sc->rx_bd_chain_map, M_DEVBUF);
2139         if (sc->rx_bd_chain != NULL)
2140                 kfree(sc->rx_bd_chain, M_DEVBUF);
2141         if (sc->rx_bd_chain_paddr != NULL)
2142                 kfree(sc->rx_bd_chain_paddr, M_DEVBUF);
2143
2144         if (sc->tx_mbuf_map != NULL)
2145                 kfree(sc->tx_mbuf_map, M_DEVBUF);
2146         if (sc->tx_mbuf_ptr != NULL)
2147                 kfree(sc->tx_mbuf_ptr, M_DEVBUF);
2148
2149         if (sc->rx_mbuf_map != NULL)
2150                 kfree(sc->rx_mbuf_map, M_DEVBUF);
2151         if (sc->rx_mbuf_ptr != NULL)
2152                 kfree(sc->rx_mbuf_ptr, M_DEVBUF);
2153         if (sc->rx_mbuf_paddr != NULL)
2154                 kfree(sc->rx_mbuf_paddr, M_DEVBUF);
2155 }
2156
2157
2158 /****************************************************************************/
2159 /* Get DMA memory from the OS.                                              */
2160 /*                                                                          */
2161 /* Validates that the OS has provided DMA buffers in response to a          */
2162 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2163 /* When the callback is used the OS will return 0 for the mapping function  */
2164 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2165 /* failures back to the caller.                                             */
2166 /*                                                                          */
2167 /* Returns:                                                                 */
2168 /*   Nothing.                                                               */
2169 /****************************************************************************/
2170 static void
2171 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2172 {
2173         bus_addr_t *busaddr = arg;
2174
2175         /*
2176          * Simulate a mapping failure.
2177          * XXX not correct.
2178          */
2179         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2180                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2181                         __FILE__, __LINE__);
2182                 error = ENOMEM);
2183                 
2184         /* Check for an error and signal the caller that an error occurred. */
2185         if (error)
2186                 return;
2187
2188         KASSERT(nseg == 1, ("only one segment is allowed"));
2189         *busaddr = segs->ds_addr;
2190 }
2191
2192
2193 /****************************************************************************/
2194 /* Allocate any DMA memory needed by the driver.                            */
2195 /*                                                                          */
2196 /* Allocates DMA memory needed for the various global structures needed by  */
2197 /* hardware.                                                                */
2198 /*                                                                          */
2199 /* Memory alignment requirements:                                           */
2200 /* -----------------+----------+----------+----------+----------+           */
2201 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2202 /* -----------------+----------+----------+----------+----------+           */
2203 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2204 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2205 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2206 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2207 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2208 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2209 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2210 /* -----------------+----------+----------+----------+----------+           */
2211 /*                                                                          */
2212 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2213 /*                                                                          */
2214 /* Returns:                                                                 */
2215 /*   0 for success, positive value for failure.                             */
2216 /****************************************************************************/
2217 static int
2218 bce_dma_alloc(struct bce_softc *sc)
2219 {
2220         struct ifnet *ifp = &sc->arpcom.ac_if;
2221         int i, j, rc = 0, pages;
2222         bus_addr_t busaddr, max_busaddr;
2223         bus_size_t status_align, stats_align;
2224
2225         pages = device_getenv_int(sc->bce_dev, "rx_pages", bce_rx_pages);
2226         if (pages <= 0 || pages > RX_PAGES_MAX || !powerof2(pages)) {
2227                 device_printf(sc->bce_dev, "invalid # of RX pages\n");
2228                 pages = RX_PAGES_DEFAULT;
2229         }
2230         sc->rx_pages = pages;
2231
2232         pages = device_getenv_int(sc->bce_dev, "tx_pages", bce_tx_pages);
2233         if (pages <= 0 || pages > TX_PAGES_MAX || !powerof2(pages)) {
2234                 device_printf(sc->bce_dev, "invalid # of TX pages\n");
2235                 pages = TX_PAGES_DEFAULT;
2236         }
2237         sc->tx_pages = pages;
2238
2239         sc->tx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->tx_pages,
2240             M_DEVBUF, M_WAITOK | M_ZERO);
2241         sc->tx_bd_chain = kmalloc(sizeof(struct tx_bd *) * sc->tx_pages,
2242             M_DEVBUF, M_WAITOK | M_ZERO);
2243         sc->tx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->tx_pages,
2244             M_DEVBUF, M_WAITOK | M_ZERO);
2245
2246         sc->rx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->rx_pages,
2247             M_DEVBUF, M_WAITOK | M_ZERO);
2248         sc->rx_bd_chain = kmalloc(sizeof(struct rx_bd *) * sc->rx_pages,
2249             M_DEVBUF, M_WAITOK | M_ZERO);
2250         sc->rx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->rx_pages,
2251             M_DEVBUF, M_WAITOK | M_ZERO);
2252
2253         sc->tx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_TX_BD(sc),
2254             M_DEVBUF, M_WAITOK | M_ZERO);
2255         sc->tx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_TX_BD(sc),
2256             M_DEVBUF, M_WAITOK | M_ZERO);
2257
2258         sc->rx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_RX_BD(sc),
2259             M_DEVBUF, M_WAITOK | M_ZERO);
2260         sc->rx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_RX_BD(sc),
2261             M_DEVBUF, M_WAITOK | M_ZERO);
2262         sc->rx_mbuf_paddr = kmalloc(sizeof(bus_addr_t) * TOTAL_RX_BD(sc),
2263             M_DEVBUF, M_WAITOK | M_ZERO);
2264
2265         /*
2266          * The embedded PCIe to PCI-X bridge (EPB) 
2267          * in the 5708 cannot address memory above 
2268          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 
2269          */
2270         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2271                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2272         else
2273                 max_busaddr = BUS_SPACE_MAXADDR;
2274
2275         /*
2276          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2277          */
2278         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2279             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2280                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2281                 if (sc->ctx_pages == 0)
2282                         sc->ctx_pages = 1;
2283                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2284                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2285                             sc->ctx_pages);
2286                         return ENOMEM;
2287                 }
2288                 status_align = 16;
2289                 stats_align = 16;
2290         } else {
2291                 status_align = 8;
2292                 stats_align = 8;
2293         }
2294
2295         /*
2296          * Allocate the parent bus DMA tag appropriate for PCI.
2297          */
2298         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2299                                 max_busaddr, BUS_SPACE_MAXADDR,
2300                                 NULL, NULL,
2301                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2302                                 BUS_SPACE_MAXSIZE_32BIT,
2303                                 0, &sc->parent_tag);
2304         if (rc != 0) {
2305                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2306                 return rc;
2307         }
2308
2309         /*
2310          * Allocate status block.
2311          */
2312         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2313                                 status_align, BCE_STATUS_BLK_SZ,
2314                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2315                                 &sc->status_tag, &sc->status_map,
2316                                 &sc->status_block_paddr);
2317         if (sc->status_block == NULL) {
2318                 if_printf(ifp, "Could not allocate status block!\n");
2319                 return ENOMEM;
2320         }
2321
2322         /*
2323          * Allocate statistics block.
2324          */
2325         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2326                                 stats_align, BCE_STATS_BLK_SZ,
2327                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2328                                 &sc->stats_tag, &sc->stats_map,
2329                                 &sc->stats_block_paddr);
2330         if (sc->stats_block == NULL) {
2331                 if_printf(ifp, "Could not allocate statistics block!\n");
2332                 return ENOMEM;
2333         }
2334
2335         /*
2336          * Allocate context block, if needed
2337          */
2338         if (sc->ctx_pages != 0) {
2339                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2340                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2341                                         NULL, NULL,
2342                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2343                                         0, &sc->ctx_tag);
2344                 if (rc != 0) {
2345                         if_printf(ifp, "Could not allocate "
2346                                   "context block DMA tag!\n");
2347                         return rc;
2348                 }
2349
2350                 for (i = 0; i < sc->ctx_pages; i++) {
2351                         rc = bus_dmamem_alloc(sc->ctx_tag,
2352                                               (void **)&sc->ctx_block[i],
2353                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2354                                               BUS_DMA_COHERENT,
2355                                               &sc->ctx_map[i]);
2356                         if (rc != 0) {
2357                                 if_printf(ifp, "Could not allocate %dth context "
2358                                           "DMA memory!\n", i);
2359                                 return rc;
2360                         }
2361
2362                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2363                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2364                                              bce_dma_map_addr, &busaddr,
2365                                              BUS_DMA_WAITOK);
2366                         if (rc != 0) {
2367                                 if (rc == EINPROGRESS) {
2368                                         panic("%s coherent memory loading "
2369                                               "is still in progress!", ifp->if_xname);
2370                                 }
2371                                 if_printf(ifp, "Could not map %dth context "
2372                                           "DMA memory!\n", i);
2373                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2374                                                 sc->ctx_map[i]);
2375                                 sc->ctx_block[i] = NULL;
2376                                 return rc;
2377                         }
2378                         sc->ctx_paddr[i] = busaddr;
2379                 }
2380         }
2381
2382         /*
2383          * Create a DMA tag for the TX buffer descriptor chain,
2384          * allocate and clear the  memory, and fetch the
2385          * physical address of the block.
2386          */
2387         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2388                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2389                                 NULL, NULL,
2390                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2391                                 0, &sc->tx_bd_chain_tag);
2392         if (rc != 0) {
2393                 if_printf(ifp, "Could not allocate "
2394                           "TX descriptor chain DMA tag!\n");
2395                 return rc;
2396         }
2397
2398         for (i = 0; i < sc->tx_pages; i++) {
2399                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2400                                       (void **)&sc->tx_bd_chain[i],
2401                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2402                                       BUS_DMA_COHERENT,
2403                                       &sc->tx_bd_chain_map[i]);
2404                 if (rc != 0) {
2405                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2406                                   "chain DMA memory!\n", i);
2407                         return rc;
2408                 }
2409
2410                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2411                                      sc->tx_bd_chain_map[i],
2412                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2413                                      bce_dma_map_addr, &busaddr,
2414                                      BUS_DMA_WAITOK);
2415                 if (rc != 0) {
2416                         if (rc == EINPROGRESS) {
2417                                 panic("%s coherent memory loading "
2418                                       "is still in progress!", ifp->if_xname);
2419                         }
2420                         if_printf(ifp, "Could not map %dth TX descriptor "
2421                                   "chain DMA memory!\n", i);
2422                         bus_dmamem_free(sc->tx_bd_chain_tag,
2423                                         sc->tx_bd_chain[i],
2424                                         sc->tx_bd_chain_map[i]);
2425                         sc->tx_bd_chain[i] = NULL;
2426                         return rc;
2427                 }
2428
2429                 sc->tx_bd_chain_paddr[i] = busaddr;
2430                 /* DRC - Fix for 64 bit systems. */
2431                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 
2432                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2433         }
2434
2435         /* Create a DMA tag for TX mbufs. */
2436         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2437                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2438                                 NULL, NULL,
2439                                 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2440                                 BCE_MAX_SEGMENTS, MCLBYTES,
2441                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2442                                 BUS_DMA_ONEBPAGE,
2443                                 &sc->tx_mbuf_tag);
2444         if (rc != 0) {
2445                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2446                 return rc;
2447         }
2448
2449         /* Create DMA maps for the TX mbufs clusters. */
2450         for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2451                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2452                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2453                                        &sc->tx_mbuf_map[i]);
2454                 if (rc != 0) {
2455                         for (j = 0; j < i; ++j) {
2456                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2457                                                    sc->tx_mbuf_map[i]);
2458                         }
2459                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2460                         sc->tx_mbuf_tag = NULL;
2461
2462                         if_printf(ifp, "Unable to create "
2463                                   "%dth TX mbuf DMA map!\n", i);
2464                         return rc;
2465                 }
2466         }
2467
2468         /*
2469          * Create a DMA tag for the RX buffer descriptor chain,
2470          * allocate and clear the  memory, and fetch the physical
2471          * address of the blocks.
2472          */
2473         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2474                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2475                                 NULL, NULL,
2476                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2477                                 0, &sc->rx_bd_chain_tag);
2478         if (rc != 0) {
2479                 if_printf(ifp, "Could not allocate "
2480                           "RX descriptor chain DMA tag!\n");
2481                 return rc;
2482         }
2483
2484         for (i = 0; i < sc->rx_pages; i++) {
2485                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2486                                       (void **)&sc->rx_bd_chain[i],
2487                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2488                                       BUS_DMA_COHERENT,
2489                                       &sc->rx_bd_chain_map[i]);
2490                 if (rc != 0) {
2491                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2492                                   "chain DMA memory!\n", i);
2493                         return rc;
2494                 }
2495
2496                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2497                                      sc->rx_bd_chain_map[i],
2498                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2499                                      bce_dma_map_addr, &busaddr,
2500                                      BUS_DMA_WAITOK);
2501                 if (rc != 0) {
2502                         if (rc == EINPROGRESS) {
2503                                 panic("%s coherent memory loading "
2504                                       "is still in progress!", ifp->if_xname);
2505                         }
2506                         if_printf(ifp, "Could not map %dth RX descriptor "
2507                                   "chain DMA memory!\n", i);
2508                         bus_dmamem_free(sc->rx_bd_chain_tag,
2509                                         sc->rx_bd_chain[i],
2510                                         sc->rx_bd_chain_map[i]);
2511                         sc->rx_bd_chain[i] = NULL;
2512                         return rc;
2513                 }
2514
2515                 sc->rx_bd_chain_paddr[i] = busaddr;
2516                 /* DRC - Fix for 64 bit systems. */
2517                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2518                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2519         }
2520
2521         /* Create a DMA tag for RX mbufs. */
2522         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2523                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2524                                 NULL, NULL,
2525                                 MCLBYTES, 1, MCLBYTES,
2526                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2527                                 BUS_DMA_WAITOK,
2528                                 &sc->rx_mbuf_tag);
2529         if (rc != 0) {
2530                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2531                 return rc;
2532         }
2533
2534         /* Create tmp DMA map for RX mbuf clusters. */
2535         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2536                                &sc->rx_mbuf_tmpmap);
2537         if (rc != 0) {
2538                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2539                 sc->rx_mbuf_tag = NULL;
2540
2541                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2542                 return rc;
2543         }
2544
2545         /* Create DMA maps for the RX mbuf clusters. */
2546         for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2547                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2548                                        &sc->rx_mbuf_map[i]);
2549                 if (rc != 0) {
2550                         for (j = 0; j < i; ++j) {
2551                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2552                                                    sc->rx_mbuf_map[j]);
2553                         }
2554                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2555                         sc->rx_mbuf_tag = NULL;
2556
2557                         if_printf(ifp, "Unable to create "
2558                                   "%dth RX mbuf DMA map!\n", i);
2559                         return rc;
2560                 }
2561         }
2562         return 0;
2563 }
2564
2565
2566 /****************************************************************************/
2567 /* Firmware synchronization.                                                */
2568 /*                                                                          */
2569 /* Before performing certain events such as a chip reset, synchronize with  */
2570 /* the firmware first.                                                      */
2571 /*                                                                          */
2572 /* Returns:                                                                 */
2573 /*   0 for success, positive value for failure.                             */
2574 /****************************************************************************/
2575 static int
2576 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2577 {
2578         int i, rc = 0;
2579         uint32_t val;
2580
2581         /* Don't waste any time if we've timed out before. */
2582         if (sc->bce_fw_timed_out)
2583                 return EBUSY;
2584
2585         /* Increment the message sequence number. */
2586         sc->bce_fw_wr_seq++;
2587         msg_data |= sc->bce_fw_wr_seq;
2588
2589         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2590
2591         /* Send the message to the bootcode driver mailbox. */
2592         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2593
2594         /* Wait for the bootcode to acknowledge the message. */
2595         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2596                 /* Check for a response in the bootcode firmware mailbox. */
2597                 val = bce_shmem_rd(sc, BCE_FW_MB);
2598                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2599                         break;
2600                 DELAY(1000);
2601         }
2602
2603         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2604         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2605             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2606                 if_printf(&sc->arpcom.ac_if,
2607                           "Firmware synchronization timeout! "
2608                           "msg_data = 0x%08X\n", msg_data);
2609
2610                 msg_data &= ~BCE_DRV_MSG_CODE;
2611                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2612
2613                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2614
2615                 sc->bce_fw_timed_out = 1;
2616                 rc = EBUSY;
2617         }
2618         return rc;
2619 }
2620
2621
2622 /****************************************************************************/
2623 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2624 /*                                                                          */
2625 /* Returns:                                                                 */
2626 /*   Nothing.                                                               */
2627 /****************************************************************************/
2628 static void
2629 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2630                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2631 {
2632         int i;
2633         uint32_t val;
2634
2635         for (i = 0; i < rv2p_code_len; i += 8) {
2636                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2637                 rv2p_code++;
2638                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2639                 rv2p_code++;
2640
2641                 if (rv2p_proc == RV2P_PROC1) {
2642                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2643                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2644                 } else {
2645                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2646                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2647                 }
2648         }
2649
2650         /* Reset the processor, un-stall is done later. */
2651         if (rv2p_proc == RV2P_PROC1)
2652                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2653         else
2654                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2655 }
2656
2657
2658 /****************************************************************************/
2659 /* Load RISC processor firmware.                                            */
2660 /*                                                                          */
2661 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2662 /* associated with a particular processor.                                  */
2663 /*                                                                          */
2664 /* Returns:                                                                 */
2665 /*   Nothing.                                                               */
2666 /****************************************************************************/
2667 static void
2668 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2669                 struct fw_info *fw)
2670 {
2671         uint32_t offset;
2672         int j;
2673
2674         bce_halt_cpu(sc, cpu_reg);
2675
2676         /* Load the Text area. */
2677         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2678         if (fw->text) {
2679                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2680                         REG_WR_IND(sc, offset, fw->text[j]);
2681         }
2682
2683         /* Load the Data area. */
2684         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2685         if (fw->data) {
2686                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2687                         REG_WR_IND(sc, offset, fw->data[j]);
2688         }
2689
2690         /* Load the SBSS area. */
2691         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2692         if (fw->sbss) {
2693                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2694                         REG_WR_IND(sc, offset, fw->sbss[j]);
2695         }
2696
2697         /* Load the BSS area. */
2698         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2699         if (fw->bss) {
2700                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2701                         REG_WR_IND(sc, offset, fw->bss[j]);
2702         }
2703
2704         /* Load the Read-Only area. */
2705         offset = cpu_reg->spad_base +
2706                 (fw->rodata_addr - cpu_reg->mips_view_base);
2707         if (fw->rodata) {
2708                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2709                         REG_WR_IND(sc, offset, fw->rodata[j]);
2710         }
2711
2712         /* Clear the pre-fetch instruction and set the FW start address. */
2713         REG_WR_IND(sc, cpu_reg->inst, 0);
2714         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2715 }
2716
2717
2718 /****************************************************************************/
2719 /* Starts the RISC processor.                                               */
2720 /*                                                                          */
2721 /* Assumes the CPU starting address has already been set.                   */
2722 /*                                                                          */
2723 /* Returns:                                                                 */
2724 /*   Nothing.                                                               */
2725 /****************************************************************************/
2726 static void
2727 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2728 {
2729         uint32_t val;
2730
2731         /* Start the CPU. */
2732         val = REG_RD_IND(sc, cpu_reg->mode);
2733         val &= ~cpu_reg->mode_value_halt;
2734         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2735         REG_WR_IND(sc, cpu_reg->mode, val);
2736 }
2737
2738
2739 /****************************************************************************/
2740 /* Halts the RISC processor.                                                */
2741 /*                                                                          */
2742 /* Returns:                                                                 */
2743 /*   Nothing.                                                               */
2744 /****************************************************************************/
2745 static void
2746 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2747 {
2748         uint32_t val;
2749
2750         /* Halt the CPU. */
2751         val = REG_RD_IND(sc, cpu_reg->mode);
2752         val |= cpu_reg->mode_value_halt;
2753         REG_WR_IND(sc, cpu_reg->mode, val);
2754         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2755 }
2756
2757
2758 /****************************************************************************/
2759 /* Start the RX CPU.                                                        */
2760 /*                                                                          */
2761 /* Returns:                                                                 */
2762 /*   Nothing.                                                               */
2763 /****************************************************************************/
2764 static void
2765 bce_start_rxp_cpu(struct bce_softc *sc)
2766 {
2767         struct cpu_reg cpu_reg;
2768
2769         cpu_reg.mode = BCE_RXP_CPU_MODE;
2770         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2771         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2772         cpu_reg.state = BCE_RXP_CPU_STATE;
2773         cpu_reg.state_value_clear = 0xffffff;
2774         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2775         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2776         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2777         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2778         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2779         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2780         cpu_reg.mips_view_base = 0x8000000;
2781
2782         bce_start_cpu(sc, &cpu_reg);
2783 }
2784
2785
2786 /****************************************************************************/
2787 /* Initialize the RX CPU.                                                   */
2788 /*                                                                          */
2789 /* Returns:                                                                 */
2790 /*   Nothing.                                                               */
2791 /****************************************************************************/
2792 static void
2793 bce_init_rxp_cpu(struct bce_softc *sc)
2794 {
2795         struct cpu_reg cpu_reg;
2796         struct fw_info fw;
2797
2798         cpu_reg.mode = BCE_RXP_CPU_MODE;
2799         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2800         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2801         cpu_reg.state = BCE_RXP_CPU_STATE;
2802         cpu_reg.state_value_clear = 0xffffff;
2803         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2804         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2805         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2806         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2807         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2808         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2809         cpu_reg.mips_view_base = 0x8000000;
2810
2811         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2812             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2813                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2814                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2815                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2816                 fw.start_addr = bce_RXP_b09FwStartAddr;
2817
2818                 fw.text_addr = bce_RXP_b09FwTextAddr;
2819                 fw.text_len = bce_RXP_b09FwTextLen;
2820                 fw.text_index = 0;
2821                 fw.text = bce_RXP_b09FwText;
2822
2823                 fw.data_addr = bce_RXP_b09FwDataAddr;
2824                 fw.data_len = bce_RXP_b09FwDataLen;
2825                 fw.data_index = 0;
2826                 fw.data = bce_RXP_b09FwData;
2827
2828                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2829                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2830                 fw.sbss_index = 0;
2831                 fw.sbss = bce_RXP_b09FwSbss;
2832
2833                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2834                 fw.bss_len = bce_RXP_b09FwBssLen;
2835                 fw.bss_index = 0;
2836                 fw.bss = bce_RXP_b09FwBss;
2837
2838                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2839                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2840                 fw.rodata_index = 0;
2841                 fw.rodata = bce_RXP_b09FwRodata;
2842         } else {
2843                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2844                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2845                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2846                 fw.start_addr = bce_RXP_b06FwStartAddr;
2847
2848                 fw.text_addr = bce_RXP_b06FwTextAddr;
2849                 fw.text_len = bce_RXP_b06FwTextLen;
2850                 fw.text_index = 0;
2851                 fw.text = bce_RXP_b06FwText;
2852
2853                 fw.data_addr = bce_RXP_b06FwDataAddr;
2854                 fw.data_len = bce_RXP_b06FwDataLen;
2855                 fw.data_index = 0;
2856                 fw.data = bce_RXP_b06FwData;
2857
2858                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2859                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2860                 fw.sbss_index = 0;
2861                 fw.sbss = bce_RXP_b06FwSbss;
2862
2863                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2864                 fw.bss_len = bce_RXP_b06FwBssLen;
2865                 fw.bss_index = 0;
2866                 fw.bss = bce_RXP_b06FwBss;
2867
2868                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2869                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2870                 fw.rodata_index = 0;
2871                 fw.rodata = bce_RXP_b06FwRodata;
2872         }
2873
2874         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2875         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2876         /* Delay RXP start until initialization is complete. */
2877 }
2878
2879
2880 /****************************************************************************/
2881 /* Initialize the TX CPU.                                                   */
2882 /*                                                                          */
2883 /* Returns:                                                                 */
2884 /*   Nothing.                                                               */
2885 /****************************************************************************/
2886 static void
2887 bce_init_txp_cpu(struct bce_softc *sc)
2888 {
2889         struct cpu_reg cpu_reg;
2890         struct fw_info fw;
2891
2892         cpu_reg.mode = BCE_TXP_CPU_MODE;
2893         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2894         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2895         cpu_reg.state = BCE_TXP_CPU_STATE;
2896         cpu_reg.state_value_clear = 0xffffff;
2897         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2898         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2899         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2900         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2901         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2902         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2903         cpu_reg.mips_view_base = 0x8000000;
2904
2905         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2906             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2907                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2908                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2909                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2910                 fw.start_addr = bce_TXP_b09FwStartAddr;
2911
2912                 fw.text_addr = bce_TXP_b09FwTextAddr;
2913                 fw.text_len = bce_TXP_b09FwTextLen;
2914                 fw.text_index = 0;
2915                 fw.text = bce_TXP_b09FwText;
2916
2917                 fw.data_addr = bce_TXP_b09FwDataAddr;
2918                 fw.data_len = bce_TXP_b09FwDataLen;
2919                 fw.data_index = 0;
2920                 fw.data = bce_TXP_b09FwData;
2921
2922                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2923                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2924                 fw.sbss_index = 0;
2925                 fw.sbss = bce_TXP_b09FwSbss;
2926
2927                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2928                 fw.bss_len = bce_TXP_b09FwBssLen;
2929                 fw.bss_index = 0;
2930                 fw.bss = bce_TXP_b09FwBss;
2931
2932                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2933                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2934                 fw.rodata_index = 0;
2935                 fw.rodata = bce_TXP_b09FwRodata;
2936         } else {
2937                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2938                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2939                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2940                 fw.start_addr = bce_TXP_b06FwStartAddr;
2941
2942                 fw.text_addr = bce_TXP_b06FwTextAddr;
2943                 fw.text_len = bce_TXP_b06FwTextLen;
2944                 fw.text_index = 0;
2945                 fw.text = bce_TXP_b06FwText;
2946
2947                 fw.data_addr = bce_TXP_b06FwDataAddr;
2948                 fw.data_len = bce_TXP_b06FwDataLen;
2949                 fw.data_index = 0;
2950                 fw.data = bce_TXP_b06FwData;
2951
2952                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2953                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2954                 fw.sbss_index = 0;
2955                 fw.sbss = bce_TXP_b06FwSbss;
2956
2957                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2958                 fw.bss_len = bce_TXP_b06FwBssLen;
2959                 fw.bss_index = 0;
2960                 fw.bss = bce_TXP_b06FwBss;
2961
2962                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2963                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2964                 fw.rodata_index = 0;
2965                 fw.rodata = bce_TXP_b06FwRodata;
2966         }
2967
2968         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2969         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2970         bce_start_cpu(sc, &cpu_reg);
2971 }
2972
2973
2974 /****************************************************************************/
2975 /* Initialize the TPAT CPU.                                                 */
2976 /*                                                                          */
2977 /* Returns:                                                                 */
2978 /*   Nothing.                                                               */
2979 /****************************************************************************/
2980 static void
2981 bce_init_tpat_cpu(struct bce_softc *sc)
2982 {
2983         struct cpu_reg cpu_reg;
2984         struct fw_info fw;
2985
2986         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2987         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2988         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2989         cpu_reg.state = BCE_TPAT_CPU_STATE;
2990         cpu_reg.state_value_clear = 0xffffff;
2991         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2992         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2993         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2994         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2995         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2996         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2997         cpu_reg.mips_view_base = 0x8000000;
2998
2999         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3000             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3001                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
3002                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
3003                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
3004                 fw.start_addr = bce_TPAT_b09FwStartAddr;
3005
3006                 fw.text_addr = bce_TPAT_b09FwTextAddr;
3007                 fw.text_len = bce_TPAT_b09FwTextLen;
3008                 fw.text_index = 0;
3009                 fw.text = bce_TPAT_b09FwText;
3010
3011                 fw.data_addr = bce_TPAT_b09FwDataAddr;
3012                 fw.data_len = bce_TPAT_b09FwDataLen;
3013                 fw.data_index = 0;
3014                 fw.data = bce_TPAT_b09FwData;
3015
3016                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3017                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
3018                 fw.sbss_index = 0;
3019                 fw.sbss = bce_TPAT_b09FwSbss;
3020
3021                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
3022                 fw.bss_len = bce_TPAT_b09FwBssLen;
3023                 fw.bss_index = 0;
3024                 fw.bss = bce_TPAT_b09FwBss;
3025
3026                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3027                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
3028                 fw.rodata_index = 0;
3029                 fw.rodata = bce_TPAT_b09FwRodata;
3030         } else {
3031                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3032                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3033                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3034                 fw.start_addr = bce_TPAT_b06FwStartAddr;
3035
3036                 fw.text_addr = bce_TPAT_b06FwTextAddr;
3037                 fw.text_len = bce_TPAT_b06FwTextLen;
3038                 fw.text_index = 0;
3039                 fw.text = bce_TPAT_b06FwText;
3040
3041                 fw.data_addr = bce_TPAT_b06FwDataAddr;
3042                 fw.data_len = bce_TPAT_b06FwDataLen;
3043                 fw.data_index = 0;
3044                 fw.data = bce_TPAT_b06FwData;
3045
3046                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3047                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3048                 fw.sbss_index = 0;
3049                 fw.sbss = bce_TPAT_b06FwSbss;
3050
3051                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3052                 fw.bss_len = bce_TPAT_b06FwBssLen;
3053                 fw.bss_index = 0;
3054                 fw.bss = bce_TPAT_b06FwBss;
3055
3056                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3057                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3058                 fw.rodata_index = 0;
3059                 fw.rodata = bce_TPAT_b06FwRodata;
3060         }
3061
3062         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3063         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3064         bce_start_cpu(sc, &cpu_reg);
3065 }
3066
3067
3068 /****************************************************************************/
3069 /* Initialize the CP CPU.                                                   */
3070 /*                                                                          */
3071 /* Returns:                                                                 */
3072 /*   Nothing.                                                               */
3073 /****************************************************************************/
3074 static void
3075 bce_init_cp_cpu(struct bce_softc *sc)
3076 {
3077         struct cpu_reg cpu_reg;
3078         struct fw_info fw;
3079
3080         cpu_reg.mode = BCE_CP_CPU_MODE;
3081         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3082         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3083         cpu_reg.state = BCE_CP_CPU_STATE;
3084         cpu_reg.state_value_clear = 0xffffff;
3085         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3086         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3087         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3088         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3089         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3090         cpu_reg.spad_base = BCE_CP_SCRATCH;
3091         cpu_reg.mips_view_base = 0x8000000;
3092
3093         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3094             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3095                 fw.ver_major = bce_CP_b09FwReleaseMajor;
3096                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3097                 fw.ver_fix = bce_CP_b09FwReleaseFix;
3098                 fw.start_addr = bce_CP_b09FwStartAddr;
3099
3100                 fw.text_addr = bce_CP_b09FwTextAddr;
3101                 fw.text_len = bce_CP_b09FwTextLen;
3102                 fw.text_index = 0;
3103                 fw.text = bce_CP_b09FwText;
3104
3105                 fw.data_addr = bce_CP_b09FwDataAddr;
3106                 fw.data_len = bce_CP_b09FwDataLen;
3107                 fw.data_index = 0;
3108                 fw.data = bce_CP_b09FwData;
3109
3110                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3111                 fw.sbss_len = bce_CP_b09FwSbssLen;
3112                 fw.sbss_index = 0;
3113                 fw.sbss = bce_CP_b09FwSbss;
3114
3115                 fw.bss_addr = bce_CP_b09FwBssAddr;
3116                 fw.bss_len = bce_CP_b09FwBssLen;
3117                 fw.bss_index = 0;
3118                 fw.bss = bce_CP_b09FwBss;
3119
3120                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3121                 fw.rodata_len = bce_CP_b09FwRodataLen;
3122                 fw.rodata_index = 0;
3123                 fw.rodata = bce_CP_b09FwRodata;
3124         } else {
3125                 fw.ver_major = bce_CP_b06FwReleaseMajor;
3126                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3127                 fw.ver_fix = bce_CP_b06FwReleaseFix;
3128                 fw.start_addr = bce_CP_b06FwStartAddr;
3129
3130                 fw.text_addr = bce_CP_b06FwTextAddr;
3131                 fw.text_len = bce_CP_b06FwTextLen;
3132                 fw.text_index = 0;
3133                 fw.text = bce_CP_b06FwText;
3134
3135                 fw.data_addr = bce_CP_b06FwDataAddr;
3136                 fw.data_len = bce_CP_b06FwDataLen;
3137                 fw.data_index = 0;
3138                 fw.data = bce_CP_b06FwData;
3139
3140                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3141                 fw.sbss_len = bce_CP_b06FwSbssLen;
3142                 fw.sbss_index = 0;
3143                 fw.sbss = bce_CP_b06FwSbss;
3144
3145                 fw.bss_addr = bce_CP_b06FwBssAddr;
3146                 fw.bss_len = bce_CP_b06FwBssLen;
3147                 fw.bss_index = 0;
3148                 fw.bss = bce_CP_b06FwBss;
3149
3150                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3151                 fw.rodata_len = bce_CP_b06FwRodataLen;
3152                 fw.rodata_index = 0;
3153                 fw.rodata = bce_CP_b06FwRodata;
3154         }
3155
3156         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3157         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3158         bce_start_cpu(sc, &cpu_reg);
3159 }
3160
3161
3162 /****************************************************************************/
3163 /* Initialize the COM CPU.                                                 */
3164 /*                                                                          */
3165 /* Returns:                                                                 */
3166 /*   Nothing.                                                               */
3167 /****************************************************************************/
3168 static void
3169 bce_init_com_cpu(struct bce_softc *sc)
3170 {
3171         struct cpu_reg cpu_reg;
3172         struct fw_info fw;
3173
3174         cpu_reg.mode = BCE_COM_CPU_MODE;
3175         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3176         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3177         cpu_reg.state = BCE_COM_CPU_STATE;
3178         cpu_reg.state_value_clear = 0xffffff;
3179         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3180         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3181         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3182         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3183         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3184         cpu_reg.spad_base = BCE_COM_SCRATCH;
3185         cpu_reg.mips_view_base = 0x8000000;
3186
3187         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3188             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3189                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3190                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3191                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3192                 fw.start_addr = bce_COM_b09FwStartAddr;
3193
3194                 fw.text_addr = bce_COM_b09FwTextAddr;
3195                 fw.text_len = bce_COM_b09FwTextLen;
3196                 fw.text_index = 0;
3197                 fw.text = bce_COM_b09FwText;
3198
3199                 fw.data_addr = bce_COM_b09FwDataAddr;
3200                 fw.data_len = bce_COM_b09FwDataLen;
3201                 fw.data_index = 0;
3202                 fw.data = bce_COM_b09FwData;
3203
3204                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3205                 fw.sbss_len = bce_COM_b09FwSbssLen;
3206                 fw.sbss_index = 0;
3207                 fw.sbss = bce_COM_b09FwSbss;
3208
3209                 fw.bss_addr = bce_COM_b09FwBssAddr;
3210                 fw.bss_len = bce_COM_b09FwBssLen;
3211                 fw.bss_index = 0;
3212                 fw.bss = bce_COM_b09FwBss;
3213
3214                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3215                 fw.rodata_len = bce_COM_b09FwRodataLen;
3216                 fw.rodata_index = 0;
3217                 fw.rodata = bce_COM_b09FwRodata;
3218         } else {
3219                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3220                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3221                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3222                 fw.start_addr = bce_COM_b06FwStartAddr;
3223
3224                 fw.text_addr = bce_COM_b06FwTextAddr;
3225                 fw.text_len = bce_COM_b06FwTextLen;
3226                 fw.text_index = 0;
3227                 fw.text = bce_COM_b06FwText;
3228
3229                 fw.data_addr = bce_COM_b06FwDataAddr;
3230                 fw.data_len = bce_COM_b06FwDataLen;
3231                 fw.data_index = 0;
3232                 fw.data = bce_COM_b06FwData;
3233
3234                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3235                 fw.sbss_len = bce_COM_b06FwSbssLen;
3236                 fw.sbss_index = 0;
3237                 fw.sbss = bce_COM_b06FwSbss;
3238
3239                 fw.bss_addr = bce_COM_b06FwBssAddr;
3240                 fw.bss_len = bce_COM_b06FwBssLen;
3241                 fw.bss_index = 0;
3242                 fw.bss = bce_COM_b06FwBss;
3243
3244                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3245                 fw.rodata_len = bce_COM_b06FwRodataLen;
3246                 fw.rodata_index = 0;
3247                 fw.rodata = bce_COM_b06FwRodata;
3248         }
3249
3250         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3251         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3252         bce_start_cpu(sc, &cpu_reg);
3253 }
3254
3255
3256 /****************************************************************************/
3257 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3258 /*                                                                          */
3259 /* Loads the firmware for each CPU and starts the CPU.                      */
3260 /*                                                                          */
3261 /* Returns:                                                                 */
3262 /*   Nothing.                                                               */
3263 /****************************************************************************/
3264 static void
3265 bce_init_cpus(struct bce_softc *sc)
3266 {
3267         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3268             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3269                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3270                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3271                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3272                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3273                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3274                 } else {
3275                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3276                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3277                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3278                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3279                 }
3280         } else {
3281                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3282                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3283                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3284                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3285         }
3286
3287         bce_init_rxp_cpu(sc);
3288         bce_init_txp_cpu(sc);
3289         bce_init_tpat_cpu(sc);
3290         bce_init_com_cpu(sc);
3291         bce_init_cp_cpu(sc);
3292 }
3293
3294
3295 /****************************************************************************/
3296 /* Initialize context memory.                                               */
3297 /*                                                                          */
3298 /* Clears the memory associated with each Context ID (CID).                 */
3299 /*                                                                          */
3300 /* Returns:                                                                 */
3301 /*   Nothing.                                                               */
3302 /****************************************************************************/
3303 static int
3304 bce_init_ctx(struct bce_softc *sc)
3305 {
3306         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3307             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3308                 /* DRC: Replace this constant value with a #define. */
3309                 int i, retry_cnt = 10;
3310                 uint32_t val;
3311
3312                 /*
3313                  * BCM5709 context memory may be cached
3314                  * in host memory so prepare the host memory
3315                  * for access.
3316                  */
3317                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3318                     (1 << 12);
3319                 val |= (BCM_PAGE_BITS - 8) << 16;
3320                 REG_WR(sc, BCE_CTX_COMMAND, val);
3321
3322                 /* Wait for mem init command to complete. */
3323                 for (i = 0; i < retry_cnt; i++) {
3324                         val = REG_RD(sc, BCE_CTX_COMMAND);
3325                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3326                                 break;
3327                         DELAY(2);
3328                 }
3329                 if (i == retry_cnt) {
3330                         device_printf(sc->bce_dev,
3331                             "Context memory initialization failed!\n");
3332                         return ETIMEDOUT;
3333                 }
3334
3335                 for (i = 0; i < sc->ctx_pages; i++) {
3336                         int j;
3337
3338                         /*
3339                          * Set the physical address of the context
3340                          * memory cache.
3341                          */
3342                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3343                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3344                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3345                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3346                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3347                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3348                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3349
3350                         /*
3351                          * Verify that the context memory write was successful.
3352                          */
3353                         for (j = 0; j < retry_cnt; j++) {
3354                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3355                                 if ((val &
3356                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3357                                         break;
3358                                 DELAY(5);
3359                         }
3360                         if (j == retry_cnt) {
3361                                 device_printf(sc->bce_dev,
3362                                     "Failed to initialize context page!\n");
3363                                 return ETIMEDOUT;
3364                         }
3365                 }
3366         } else {
3367                 uint32_t vcid_addr, offset;
3368
3369                 /*
3370                  * For the 5706/5708, context memory is local to
3371                  * the controller, so initialize the controller
3372                  * context memory.
3373                  */
3374
3375                 vcid_addr = GET_CID_ADDR(96);
3376                 while (vcid_addr) {
3377                         vcid_addr -= PHY_CTX_SIZE;
3378
3379                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3380                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3381
3382                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3383                                 CTX_WR(sc, 0x00, offset, 0);
3384
3385                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3386                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3387                 }
3388         }
3389         return 0;
3390 }
3391
3392
3393 /****************************************************************************/
3394 /* Fetch the permanent MAC address of the controller.                       */
3395 /*                                                                          */
3396 /* Returns:                                                                 */
3397 /*   Nothing.                                                               */
3398 /****************************************************************************/
3399 static void
3400 bce_get_mac_addr(struct bce_softc *sc)
3401 {
3402         uint32_t mac_lo = 0, mac_hi = 0;
3403
3404         /*
3405          * The NetXtreme II bootcode populates various NIC
3406          * power-on and runtime configuration items in a
3407          * shared memory area.  The factory configured MAC
3408          * address is available from both NVRAM and the
3409          * shared memory area so we'll read the value from
3410          * shared memory for speed.
3411          */
3412
3413         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3414         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3415
3416         if (mac_lo == 0 && mac_hi == 0) {
3417                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3418         } else {
3419                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3420                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3421                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3422                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3423                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3424                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3425         }
3426
3427         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3428 }
3429
3430
3431 /****************************************************************************/
3432 /* Program the MAC address.                                                 */
3433 /*                                                                          */
3434 /* Returns:                                                                 */
3435 /*   Nothing.                                                               */
3436 /****************************************************************************/
3437 static void
3438 bce_set_mac_addr(struct bce_softc *sc)
3439 {
3440         const uint8_t *mac_addr = sc->eaddr;
3441         uint32_t val;
3442
3443         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3444                 sc->eaddr, ":");
3445
3446         val = (mac_addr[0] << 8) | mac_addr[1];
3447         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3448
3449         val = (mac_addr[2] << 24) |
3450               (mac_addr[3] << 16) |
3451               (mac_addr[4] << 8) |
3452               mac_addr[5];
3453         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3454 }
3455
3456
3457 /****************************************************************************/
3458 /* Stop the controller.                                                     */
3459 /*                                                                          */
3460 /* Returns:                                                                 */
3461 /*   Nothing.                                                               */
3462 /****************************************************************************/
3463 static void
3464 bce_stop(struct bce_softc *sc)
3465 {
3466         struct ifnet *ifp = &sc->arpcom.ac_if;
3467
3468         ASSERT_SERIALIZED(ifp->if_serializer);
3469
3470         callout_stop(&sc->bce_tick_callout);
3471
3472         /* Disable the transmit/receive blocks. */
3473         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3474         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3475         DELAY(20);
3476
3477         bce_disable_intr(sc);
3478
3479         /* Free the RX lists. */
3480         bce_free_rx_chain(sc);
3481
3482         /* Free TX buffers. */
3483         bce_free_tx_chain(sc);
3484
3485         sc->bce_link = 0;
3486         sc->bce_coalchg_mask = 0;
3487
3488         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3489         ifp->if_timer = 0;
3490 }
3491
3492
3493 static int
3494 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3495 {
3496         uint32_t val;
3497         int i, rc = 0;
3498
3499         /* Wait for pending PCI transactions to complete. */
3500         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3501                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3502                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3503                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3504                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3505         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3506         DELAY(5);
3507
3508         /* Disable DMA */
3509         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3510             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3511                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3512                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3513                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3514         }
3515
3516         /* Assume bootcode is running. */
3517         sc->bce_fw_timed_out = 0;
3518         sc->bce_drv_cardiac_arrest = 0;
3519
3520         /* Give the firmware a chance to prepare for the reset. */
3521         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3522         if (rc) {
3523                 if_printf(&sc->arpcom.ac_if,
3524                           "Firmware is not ready for reset\n");
3525                 return rc;
3526         }
3527
3528         /* Set a firmware reminder that this is a soft reset. */
3529         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3530             BCE_DRV_RESET_SIGNATURE_MAGIC);
3531
3532         /* Dummy read to force the chip to complete all current transactions. */
3533         val = REG_RD(sc, BCE_MISC_ID);
3534
3535         /* Chip reset. */
3536         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3537             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3538                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3539                 REG_RD(sc, BCE_MISC_COMMAND);
3540                 DELAY(5);
3541
3542                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3543                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3544
3545                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3546         } else {
3547                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3548                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3549                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3550                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3551
3552                 /* Allow up to 30us for reset to complete. */
3553                 for (i = 0; i < 10; i++) {
3554                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3555                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3556                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3557                                 break;
3558                         DELAY(10);
3559                 }
3560
3561                 /* Check that reset completed successfully. */
3562                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3563                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3564                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3565                         return EBUSY;
3566                 }
3567         }
3568
3569         /* Make sure byte swapping is properly configured. */
3570         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3571         if (val != 0x01020304) {
3572                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3573                 return ENODEV;
3574         }
3575
3576         /* Just completed a reset, assume that firmware is running again. */
3577         sc->bce_fw_timed_out = 0;
3578         sc->bce_drv_cardiac_arrest = 0;
3579
3580         /* Wait for the firmware to finish its initialization. */
3581         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3582         if (rc) {
3583                 if_printf(&sc->arpcom.ac_if,
3584                           "Firmware did not complete initialization!\n");
3585         }
3586         return rc;
3587 }
3588
3589
3590 static int
3591 bce_chipinit(struct bce_softc *sc)
3592 {
3593         uint32_t val;
3594         int rc = 0;
3595
3596         /* Make sure the interrupt is not active. */
3597         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3598         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3599
3600         /*
3601          * Initialize DMA byte/word swapping, configure the number of DMA
3602          * channels and PCI clock compensation delay.
3603          */
3604         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3605               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3606 #if BYTE_ORDER == BIG_ENDIAN
3607               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3608 #endif
3609               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3610               DMA_READ_CHANS << 12 |
3611               DMA_WRITE_CHANS << 16;
3612
3613         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3614
3615         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3616                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3617
3618         /*
3619          * This setting resolves a problem observed on certain Intel PCI
3620          * chipsets that cannot handle multiple outstanding DMA operations.
3621          * See errata E9_5706A1_65.
3622          */
3623         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3624             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3625             !(sc->bce_flags & BCE_PCIX_FLAG))
3626                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3627
3628         REG_WR(sc, BCE_DMA_CONFIG, val);
3629
3630         /* Enable the RX_V2P and Context state machines before access. */
3631         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3632                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3633                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3634                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3635
3636         /* Initialize context mapping and zero out the quick contexts. */
3637         rc = bce_init_ctx(sc);
3638         if (rc != 0)
3639                 return rc;
3640
3641         /* Initialize the on-boards CPUs */
3642         bce_init_cpus(sc);
3643
3644         /* Enable management frames (NC-SI) to flow to the MCP. */
3645         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3646                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3647                     BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3648                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3649         }
3650
3651         /* Prepare NVRAM for access. */
3652         rc = bce_init_nvram(sc);
3653         if (rc != 0)
3654                 return rc;
3655
3656         /* Set the kernel bypass block size */
3657         val = REG_RD(sc, BCE_MQ_CONFIG);
3658         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3659         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3660
3661         /* Enable bins used on the 5709/5716. */
3662         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3663             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3664                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3665                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3666                         val |= BCE_MQ_CONFIG_HALT_DIS;
3667         }
3668
3669         REG_WR(sc, BCE_MQ_CONFIG, val);
3670
3671         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3672         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3673         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3674
3675         /* Set the page size and clear the RV2P processor stall bits. */
3676         val = (BCM_PAGE_BITS - 8) << 24;
3677         REG_WR(sc, BCE_RV2P_CONFIG, val);
3678
3679         /* Configure page size. */
3680         val = REG_RD(sc, BCE_TBDR_CONFIG);
3681         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3682         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3683         REG_WR(sc, BCE_TBDR_CONFIG, val);
3684