2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $
33 * $DragonFly: src/sys/dev/netif/dc/if_dc.c,v 1.45 2005/10/24 08:06:15 sephe Exp $
37 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143
38 * series chips and several workalikes including the following:
40 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com)
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
43 * ASIX Electronics AX88140A (www.asix.com.tw)
44 * ASIX Electronics AX88141 (www.asix.com.tw)
45 * ADMtek AL981 (www.admtek.com.tw)
46 * ADMtek AN985 (www.admtek.com.tw)
47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com)
48 * Accton EN1217 (www.accton.com)
49 * Conexant LANfinity (www.conexant.com)
51 * Datasheets for the 21143 are available at developer.intel.com.
52 * Datasheets for the clone parts can be found at their respective sites.
53 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.)
54 * The PNIC II is essentially a Macronix 98715A chip; the only difference
55 * worth noting is that its multicast hash table is only 128 bits wide
58 * Written by Bill Paul <wpaul@ee.columbia.edu>
59 * Electrical Engineering Department
60 * Columbia University, New York City
64 * The Intel 21143 is the successor to the DEC 21140. It is basically
65 * the same as the 21140 but with a few new features. The 21143 supports
66 * three kinds of media attachments:
68 * o MII port, for 10Mbps and 100Mbps support and NWAY
69 * autonegotiation provided by an external PHY.
70 * o SYM port, for symbol mode 100Mbps support.
74 * The 100Mbps SYM port and 10baseT port can be used together in
75 * combination with the internal NWAY support to create a 10/100
76 * autosensing configuration.
78 * Note that not all tulip workalikes are handled in this driver: we only
79 * deal with those which are relatively well behaved. The Winbond is
80 * handled separately due to its different register offsets and the
81 * special handling needed for its various bugs. The PNIC is handled
82 * here, but I'm not thrilled about it.
84 * All of the workalike chips use some form of MII transceiver support
85 * with the exception of the Macronix chips, which also have a SYM port.
86 * The ASIX AX88140A is also documented to have a SYM port, but all
87 * the cards I've seen use an MII transceiver, probably because the
88 * AX88140A doesn't support internal NWAY.
91 #include "opt_polling.h"
93 #include <sys/param.h>
94 #include <sys/systm.h>
95 #include <sys/sockio.h>
97 #include <sys/malloc.h>
98 #include <sys/kernel.h>
99 #include <sys/socket.h>
100 #include <sys/sysctl.h>
101 #include <sys/thread2.h>
104 #include <net/ifq_var.h>
105 #include <net/if_arp.h>
106 #include <net/ethernet.h>
107 #include <net/if_dl.h>
108 #include <net/if_media.h>
109 #include <net/if_types.h>
110 #include <net/vlan/if_vlan_var.h>
114 #include <vm/vm.h> /* for vtophys */
115 #include <vm/pmap.h> /* for vtophys */
116 #include <machine/bus_pio.h>
117 #include <machine/bus_memio.h>
118 #include <machine/bus.h>
119 #include <machine/resource.h>
121 #include <sys/rman.h>
123 #include "../mii_layer/mii.h"
124 #include "../mii_layer/miivar.h"
126 #include <bus/pci/pcireg.h>
127 #include <bus/pci/pcivar.h>
129 #define DC_USEIOSPACE
131 #include "if_dcreg.h"
133 /* "controller miibus0" required. See GENERIC if you get errors here. */
134 #include "miibus_if.h"
137 * Various supported device vendors/types and their names.
139 static const struct dc_type dc_devs[] = {
140 { DC_VENDORID_DEC, DC_DEVICEID_21143,
141 "Intel 21143 10/100BaseTX" },
142 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009,
143 "Davicom DM9009 10/100BaseTX" },
144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100,
145 "Davicom DM9100 10/100BaseTX" },
146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
147 "Davicom DM9102 10/100BaseTX" },
148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102,
149 "Davicom DM9102A 10/100BaseTX" },
150 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981,
151 "ADMtek AL981 10/100BaseTX" },
152 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985,
153 "ADMtek AN985 10/100BaseTX" },
154 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511,
155 "ADMtek ADM9511 10/100BaseTX" },
156 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513,
157 "ADMtek ADM9513 10/100BaseTX" },
158 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
159 "ASIX AX88140A 10/100BaseTX" },
160 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A,
161 "ASIX AX88141 10/100BaseTX" },
162 { DC_VENDORID_MX, DC_DEVICEID_98713,
163 "Macronix 98713 10/100BaseTX" },
164 { DC_VENDORID_MX, DC_DEVICEID_98713,
165 "Macronix 98713A 10/100BaseTX" },
166 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
167 "Compex RL100-TX 10/100BaseTX" },
168 { DC_VENDORID_CP, DC_DEVICEID_98713_CP,
169 "Compex RL100-TX 10/100BaseTX" },
170 { DC_VENDORID_MX, DC_DEVICEID_987x5,
171 "Macronix 98715/98715A 10/100BaseTX" },
172 { DC_VENDORID_MX, DC_DEVICEID_987x5,
173 "Macronix 98715AEC-C 10/100BaseTX" },
174 { DC_VENDORID_MX, DC_DEVICEID_987x5,
175 "Macronix 98725 10/100BaseTX" },
176 { DC_VENDORID_MX, DC_DEVICEID_98727,
177 "Macronix 98727/98732 10/100BaseTX" },
178 { DC_VENDORID_LO, DC_DEVICEID_82C115,
179 "LC82C115 PNIC II 10/100BaseTX" },
180 { DC_VENDORID_LO, DC_DEVICEID_82C168,
181 "82c168 PNIC 10/100BaseTX" },
182 { DC_VENDORID_LO, DC_DEVICEID_82C168,
183 "82c169 PNIC 10/100BaseTX" },
184 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217,
185 "Accton EN1217 10/100BaseTX" },
186 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242,
187 "Accton EN2242 MiniPCI 10/100BaseTX" },
188 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112,
189 "Conexant LANfinity MiniPCI 10/100BaseTX" },
190 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB,
191 "3Com OfficeConnect 10/100B" },
195 static int dc_probe (device_t);
196 static int dc_attach (device_t);
197 static int dc_detach (device_t);
198 static int dc_suspend (device_t);
199 static int dc_resume (device_t);
200 static void dc_acpi (device_t);
201 static const struct dc_type *dc_devtype (device_t);
202 static int dc_newbuf (struct dc_softc *, int, struct mbuf *);
203 static int dc_encap (struct dc_softc *, struct mbuf *,
205 static void dc_pnic_rx_bug_war (struct dc_softc *, int);
206 static int dc_rx_resync (struct dc_softc *);
207 static void dc_rxeof (struct dc_softc *);
208 static void dc_txeof (struct dc_softc *);
209 static void dc_tick (void *);
210 static void dc_tx_underrun (struct dc_softc *);
211 static void dc_intr (void *);
212 static void dc_start (struct ifnet *);
213 static int dc_ioctl (struct ifnet *, u_long, caddr_t,
215 #ifdef DEVICE_POLLING
216 static void dc_poll (struct ifnet *ifp, enum poll_cmd cmd,
219 static void dc_init (void *);
220 static void dc_stop (struct dc_softc *);
221 static void dc_watchdog (struct ifnet *);
222 static void dc_shutdown (device_t);
223 static int dc_ifmedia_upd (struct ifnet *);
224 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *);
226 static void dc_delay (struct dc_softc *);
227 static void dc_eeprom_idle (struct dc_softc *);
228 static void dc_eeprom_putbyte (struct dc_softc *, int);
229 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *);
230 static void dc_eeprom_getword_pnic
231 (struct dc_softc *, int, u_int16_t *);
232 static void dc_eeprom_width (struct dc_softc *);
233 static void dc_read_eeprom (struct dc_softc *, caddr_t, int,
236 static void dc_mii_writebit (struct dc_softc *, int);
237 static int dc_mii_readbit (struct dc_softc *);
238 static void dc_mii_sync (struct dc_softc *);
239 static void dc_mii_send (struct dc_softc *, u_int32_t, int);
240 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *);
241 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *);
242 static int dc_miibus_readreg (device_t, int, int);
243 static int dc_miibus_writereg (device_t, int, int, int);
244 static void dc_miibus_statchg (device_t);
245 static void dc_miibus_mediainit (device_t);
247 static u_int32_t dc_crc_mask (struct dc_softc *);
248 static void dc_setcfg (struct dc_softc *, int);
249 static void dc_setfilt_21143 (struct dc_softc *);
250 static void dc_setfilt_asix (struct dc_softc *);
251 static void dc_setfilt_admtek (struct dc_softc *);
253 static void dc_setfilt (struct dc_softc *);
255 static void dc_reset (struct dc_softc *);
256 static int dc_list_rx_init (struct dc_softc *);
257 static int dc_list_tx_init (struct dc_softc *);
259 static void dc_read_srom (struct dc_softc *, int);
260 static void dc_parse_21143_srom (struct dc_softc *);
261 static void dc_decode_leaf_sia (struct dc_softc *,
262 struct dc_eblock_sia *);
263 static void dc_decode_leaf_mii (struct dc_softc *,
264 struct dc_eblock_mii *);
265 static void dc_decode_leaf_sym (struct dc_softc *,
266 struct dc_eblock_sym *);
267 static void dc_apply_fixup (struct dc_softc *, int);
270 #define DC_RES SYS_RES_IOPORT
271 #define DC_RID DC_PCI_CFBIO
273 #define DC_RES SYS_RES_MEMORY
274 #define DC_RID DC_PCI_CFBMA
277 static device_method_t dc_methods[] = {
278 /* Device interface */
279 DEVMETHOD(device_probe, dc_probe),
280 DEVMETHOD(device_attach, dc_attach),
281 DEVMETHOD(device_detach, dc_detach),
282 DEVMETHOD(device_suspend, dc_suspend),
283 DEVMETHOD(device_resume, dc_resume),
284 DEVMETHOD(device_shutdown, dc_shutdown),
287 DEVMETHOD(bus_print_child, bus_generic_print_child),
288 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
291 DEVMETHOD(miibus_readreg, dc_miibus_readreg),
292 DEVMETHOD(miibus_writereg, dc_miibus_writereg),
293 DEVMETHOD(miibus_statchg, dc_miibus_statchg),
294 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit),
299 static driver_t dc_driver = {
302 sizeof(struct dc_softc)
305 static devclass_t dc_devclass;
308 static int dc_quick=1;
309 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW,
310 &dc_quick,0,"do not mdevget in dc driver");
313 DECLARE_DUMMY_MODULE(if_dc);
314 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, 0, 0);
315 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, 0, 0);
317 #define DC_SETBIT(sc, reg, x) \
318 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
320 #define DC_CLRBIT(sc, reg, x) \
321 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
323 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
324 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
327 dc_delay(struct dc_softc *sc)
331 for (idx = (300 / 33) + 1; idx > 0; idx--)
332 CSR_READ_4(sc, DC_BUSCTL);
336 dc_eeprom_width(struct dc_softc *sc)
340 /* Force EEPROM to idle state. */
343 /* Enter EEPROM access mode. */
344 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
346 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
348 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
350 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
355 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
357 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
359 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
361 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
365 for (i = 1; i <= 12; i++) {
366 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
368 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
369 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
373 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
377 /* Turn off EEPROM access mode. */
385 /* Enter EEPROM access mode. */
386 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
388 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
390 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
392 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
395 /* Turn off EEPROM access mode. */
400 dc_eeprom_idle(struct dc_softc *sc)
404 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
406 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
408 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
410 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
413 for (i = 0; i < 25; i++) {
414 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
416 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
420 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
422 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
424 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
430 * Send a read command and address to the EEPROM, check for ACK.
433 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
437 d = DC_EECMD_READ >> 6;
440 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
442 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
444 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
446 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
451 * Feed in each bit and strobe the clock.
453 for (i = sc->dc_romwidth; i--;) {
454 if (addr & (1 << i)) {
455 SIO_SET(DC_SIO_EE_DATAIN);
457 SIO_CLR(DC_SIO_EE_DATAIN);
460 SIO_SET(DC_SIO_EE_CLK);
462 SIO_CLR(DC_SIO_EE_CLK);
470 * Read a word of data stored in the EEPROM at address 'addr.'
471 * The PNIC 82c168/82c169 has its own non-standard way to read
475 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
480 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
482 for (i = 0; i < DC_TIMEOUT; i++) {
484 r = CSR_READ_4(sc, DC_SIO);
485 if (!(r & DC_PN_SIOCTL_BUSY)) {
486 *dest = (u_int16_t)(r & 0xFFFF);
495 * Read a word of data stored in the EEPROM at address 'addr.'
498 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
503 /* Force EEPROM to idle state. */
506 /* Enter EEPROM access mode. */
507 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
509 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
511 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
513 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
517 * Send address of word we want to read.
519 dc_eeprom_putbyte(sc, addr);
522 * Start reading bits from EEPROM.
524 for (i = 0x8000; i; i >>= 1) {
525 SIO_SET(DC_SIO_EE_CLK);
527 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
530 SIO_CLR(DC_SIO_EE_CLK);
534 /* Turn off EEPROM access mode. */
543 * Read a sequence of words from the EEPROM.
546 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap)
549 u_int16_t word = 0, *ptr;
551 for (i = 0; i < cnt; i++) {
553 dc_eeprom_getword_pnic(sc, off + i, &word);
555 dc_eeprom_getword(sc, off + i, &word);
556 ptr = (u_int16_t *)(dest + (i * 2));
567 * The following two routines are taken from the Macronix 98713
568 * Application Notes pp.19-21.
571 * Write a bit to the MII bus.
574 dc_mii_writebit(struct dc_softc *sc, int bit)
577 CSR_WRITE_4(sc, DC_SIO,
578 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT);
580 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
582 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
583 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
589 * Read a bit from the MII bus.
592 dc_mii_readbit(struct dc_softc *sc)
594 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
595 CSR_READ_4(sc, DC_SIO);
596 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
597 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
598 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
605 * Sync the PHYs by setting data bit and strobing the clock 32 times.
608 dc_mii_sync(struct dc_softc *sc)
612 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
614 for (i = 0; i < 32; i++)
615 dc_mii_writebit(sc, 1);
621 * Clock a series of bits through the MII.
624 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
628 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
629 dc_mii_writebit(sc, bits & i);
633 * Read an PHY register through the MII.
636 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
643 * Set up frame for RX.
645 frame->mii_stdelim = DC_MII_STARTDELIM;
646 frame->mii_opcode = DC_MII_READOP;
647 frame->mii_turnaround = 0;
656 * Send command/address info.
658 dc_mii_send(sc, frame->mii_stdelim, 2);
659 dc_mii_send(sc, frame->mii_opcode, 2);
660 dc_mii_send(sc, frame->mii_phyaddr, 5);
661 dc_mii_send(sc, frame->mii_regaddr, 5);
665 dc_mii_writebit(sc, 1);
666 dc_mii_writebit(sc, 0);
670 ack = dc_mii_readbit(sc);
673 * Now try reading data bits. If the ack failed, we still
674 * need to clock through 16 cycles to keep the PHY(s) in sync.
677 for(i = 0; i < 16; i++) {
683 for (i = 0x8000; i; i >>= 1) {
685 if (dc_mii_readbit(sc))
686 frame->mii_data |= i;
692 dc_mii_writebit(sc, 0);
693 dc_mii_writebit(sc, 0);
703 * Write to a PHY register through the MII.
706 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
711 * Set up frame for TX.
714 frame->mii_stdelim = DC_MII_STARTDELIM;
715 frame->mii_opcode = DC_MII_WRITEOP;
716 frame->mii_turnaround = DC_MII_TURNAROUND;
723 dc_mii_send(sc, frame->mii_stdelim, 2);
724 dc_mii_send(sc, frame->mii_opcode, 2);
725 dc_mii_send(sc, frame->mii_phyaddr, 5);
726 dc_mii_send(sc, frame->mii_regaddr, 5);
727 dc_mii_send(sc, frame->mii_turnaround, 2);
728 dc_mii_send(sc, frame->mii_data, 16);
731 dc_mii_writebit(sc, 0);
732 dc_mii_writebit(sc, 0);
740 dc_miibus_readreg(device_t dev, int phy, int reg)
742 struct dc_mii_frame frame;
744 int i, rval, phy_reg = 0;
746 sc = device_get_softc(dev);
747 bzero((char *)&frame, sizeof(frame));
750 * Note: both the AL981 and AN985 have internal PHYs,
751 * however the AL981 provides direct access to the PHY
752 * registers while the AN985 uses a serial MII interface.
753 * The AN985's MII interface is also buggy in that you
754 * can read from any MII address (0 to 31), but only address 1
755 * behaves normally. To deal with both cases, we pretend
756 * that the PHY is at MII address 1.
758 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
762 * Note: the ukphy probes of the RS7112 report a PHY at
763 * MII address 0 (possibly HomePNA?) and 1 (ethernet)
764 * so we only respond to correct one.
766 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
769 if (sc->dc_pmode != DC_PMODE_MII) {
770 if (phy == (MII_NPHY - 1)) {
774 * Fake something to make the probe
775 * code think there's a PHY here.
777 return(BMSR_MEDIAMASK);
781 return(DC_VENDORID_LO);
782 return(DC_VENDORID_DEC);
786 return(DC_DEVICEID_82C168);
787 return(DC_DEVICEID_21143);
797 if (DC_IS_PNIC(sc)) {
798 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
799 (phy << 23) | (reg << 18));
800 for (i = 0; i < DC_TIMEOUT; i++) {
802 rval = CSR_READ_4(sc, DC_PN_MII);
803 if (!(rval & DC_PN_MII_BUSY)) {
805 return(rval == 0xFFFF ? 0 : rval);
811 if (DC_IS_COMET(sc)) {
814 phy_reg = DC_AL_BMCR;
817 phy_reg = DC_AL_BMSR;
820 phy_reg = DC_AL_VENID;
823 phy_reg = DC_AL_DEVID;
826 phy_reg = DC_AL_ANAR;
829 phy_reg = DC_AL_LPAR;
832 phy_reg = DC_AL_ANER;
835 if_printf(&sc->arpcom.ac_if,
836 "phy_read: bad phy register %x\n", reg);
841 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
848 frame.mii_phyaddr = phy;
849 frame.mii_regaddr = reg;
850 if (sc->dc_type == DC_TYPE_98713) {
851 phy_reg = CSR_READ_4(sc, DC_NETCFG);
852 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
854 dc_mii_readreg(sc, &frame);
855 if (sc->dc_type == DC_TYPE_98713)
856 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
858 return(frame.mii_data);
862 dc_miibus_writereg(device_t dev, int phy, int reg, int data)
865 struct dc_mii_frame frame;
868 sc = device_get_softc(dev);
869 bzero((char *)&frame, sizeof(frame));
871 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
874 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
877 if (DC_IS_PNIC(sc)) {
878 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
879 (phy << 23) | (reg << 10) | data);
880 for (i = 0; i < DC_TIMEOUT; i++) {
881 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
887 if (DC_IS_COMET(sc)) {
890 phy_reg = DC_AL_BMCR;
893 phy_reg = DC_AL_BMSR;
896 phy_reg = DC_AL_VENID;
899 phy_reg = DC_AL_DEVID;
902 phy_reg = DC_AL_ANAR;
905 phy_reg = DC_AL_LPAR;
908 phy_reg = DC_AL_ANER;
911 if_printf(&sc->arpcom.ac_if,
912 "phy_write: bad phy register %x\n", reg);
917 CSR_WRITE_4(sc, phy_reg, data);
921 frame.mii_phyaddr = phy;
922 frame.mii_regaddr = reg;
923 frame.mii_data = data;
925 if (sc->dc_type == DC_TYPE_98713) {
926 phy_reg = CSR_READ_4(sc, DC_NETCFG);
927 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
929 dc_mii_writereg(sc, &frame);
930 if (sc->dc_type == DC_TYPE_98713)
931 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
937 dc_miibus_statchg(device_t dev)
940 struct mii_data *mii;
943 sc = device_get_softc(dev);
944 if (DC_IS_ADMTEK(sc))
947 mii = device_get_softc(sc->dc_miibus);
948 ifm = &mii->mii_media;
949 if (DC_IS_DAVICOM(sc) &&
950 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
951 dc_setcfg(sc, ifm->ifm_media);
952 sc->dc_if_media = ifm->ifm_media;
954 dc_setcfg(sc, mii->mii_media_active);
955 sc->dc_if_media = mii->mii_media_active;
962 * Special support for DM9102A cards with HomePNA PHYs. Note:
963 * with the Davicom DM9102A/DM9801 eval board that I have, it seems
964 * to be impossible to talk to the management interface of the DM9801
965 * PHY (its MDIO pin is not connected to anything). Consequently,
966 * the driver has to just 'know' about the additional mode and deal
967 * with it itself. *sigh*
970 dc_miibus_mediainit(device_t dev)
973 struct mii_data *mii;
977 rev = pci_get_revid(dev);
979 sc = device_get_softc(dev);
980 mii = device_get_softc(sc->dc_miibus);
981 ifm = &mii->mii_media;
983 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A)
984 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL);
989 #define DC_BITS_512 9
990 #define DC_BITS_128 7
994 dc_crc_mask(struct dc_softc *sc)
997 * The hash table on the PNIC II and the MX98715AEC-C/D/E
998 * chips is only 128 bits wide.
1000 if (sc->dc_flags & DC_128BIT_HASH)
1001 return ((1 << DC_BITS_128) - 1);
1003 /* The hash table on the MX98715BEC is only 64 bits wide. */
1004 if (sc->dc_flags & DC_64BIT_HASH)
1005 return ((1 << DC_BITS_64) - 1);
1007 return ((1 << DC_BITS_512) - 1);
1011 * 21143-style RX filter setup routine. Filter programming is done by
1012 * downloading a special setup frame into the TX engine. 21143, Macronix,
1013 * PNIC, PNIC II and Davicom chips are programmed this way.
1015 * We always program the chip using 'hash perfect' mode, i.e. one perfect
1016 * address (our node address) and a 512-bit hash filter for multicast
1017 * frames. We also sneak the broadcast address into the hash filter since
1021 dc_setfilt_21143(struct dc_softc *sc)
1023 struct dc_desc *sframe;
1024 u_int32_t h, crc_mask, *sp;
1025 struct ifmultiaddr *ifma;
1029 ifp = &sc->arpcom.ac_if;
1031 i = sc->dc_cdata.dc_tx_prod;
1032 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1033 sc->dc_cdata.dc_tx_cnt++;
1034 sframe = &sc->dc_ldata->dc_tx_list[i];
1035 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf;
1036 bzero((char *)sp, DC_SFRAME_LEN);
1038 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf);
1039 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK |
1040 DC_FILTER_HASHPERF | DC_TXCTL_FINT;
1042 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf;
1044 /* If we want promiscuous mode, set the allframes bit. */
1045 if (ifp->if_flags & IFF_PROMISC)
1046 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1048 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1050 if (ifp->if_flags & IFF_ALLMULTI)
1051 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1053 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1055 crc_mask = dc_crc_mask(sc);
1056 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1057 if (ifma->ifma_addr->sa_family != AF_LINK)
1060 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1061 ETHER_ADDR_LEN) & crc_mask;
1062 sp[h >> 4] |= 1 << (h & 0xF);
1065 if (ifp->if_flags & IFF_BROADCAST) {
1066 h = ether_crc32_le(ifp->if_broadcastaddr,
1067 ETHER_ADDR_LEN) & crc_mask;
1068 sp[h >> 4] |= 1 << (h & 0xF);
1071 /* Set our MAC address */
1072 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0];
1073 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1];
1074 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2];
1076 sframe->dc_status = DC_TXSTAT_OWN;
1077 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1080 * The PNIC takes an exceedingly long time to process its
1081 * setup frame; wait 10ms after posting the setup frame
1082 * before proceeding, just so it has time to swallow its
1093 dc_setfilt_admtek(struct dc_softc *sc)
1098 u_int32_t hashes[2] = { 0, 0 };
1099 struct ifmultiaddr *ifma;
1101 ifp = &sc->arpcom.ac_if;
1103 /* Init our MAC address */
1104 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1105 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1107 /* If we want promiscuous mode, set the allframes bit. */
1108 if (ifp->if_flags & IFF_PROMISC)
1109 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1111 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1113 if (ifp->if_flags & IFF_ALLMULTI)
1114 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1116 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1118 /* first, zot all the existing hash bits */
1119 CSR_WRITE_4(sc, DC_AL_MAR0, 0);
1120 CSR_WRITE_4(sc, DC_AL_MAR1, 0);
1123 * If we're already in promisc or allmulti mode, we
1124 * don't have to bother programming the multicast filter.
1126 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1129 /* now program new ones */
1130 if (DC_IS_CENTAUR(sc))
1131 crc_mask = dc_crc_mask(sc);
1134 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1135 if (ifma->ifma_addr->sa_family != AF_LINK)
1137 if (DC_IS_CENTAUR(sc)) {
1139 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1140 ETHER_ADDR_LEN) & crc_mask;
1143 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1145 h = (h >> 26) & crc_mask;
1148 hashes[0] |= (1 << h);
1150 hashes[1] |= (1 << (h - 32));
1153 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1154 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1160 dc_setfilt_asix(struct dc_softc *sc)
1164 u_int32_t hashes[2] = { 0, 0 };
1165 struct ifmultiaddr *ifma;
1167 ifp = &sc->arpcom.ac_if;
1169 /* Init our MAC address */
1170 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1171 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1172 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1173 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1174 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1175 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1177 /* If we want promiscuous mode, set the allframes bit. */
1178 if (ifp->if_flags & IFF_PROMISC)
1179 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1181 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1183 if (ifp->if_flags & IFF_ALLMULTI)
1184 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1186 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1189 * The ASIX chip has a special bit to enable reception
1190 * of broadcast frames.
1192 if (ifp->if_flags & IFF_BROADCAST)
1193 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1195 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1197 /* first, zot all the existing hash bits */
1198 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1199 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1200 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1201 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0);
1204 * If we're already in promisc or allmulti mode, we
1205 * don't have to bother programming the multicast filter.
1207 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI))
1210 /* now program new ones */
1211 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1212 if (ifma->ifma_addr->sa_family != AF_LINK)
1215 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1217 h = (h >> 26) & 0x3f;
1219 hashes[0] |= (1 << h);
1221 hashes[1] |= (1 << (h - 32));
1224 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1225 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1226 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1227 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1233 dc_setfilt(struct dc_softc *sc)
1235 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1236 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1237 dc_setfilt_21143(sc);
1240 dc_setfilt_asix(sc);
1242 if (DC_IS_ADMTEK(sc))
1243 dc_setfilt_admtek(sc);
1249 * In order to fiddle with the
1250 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
1251 * first have to put the transmit and/or receive logic in the idle state.
1254 dc_setcfg(struct dc_softc *sc, int media)
1259 if (IFM_SUBTYPE(media) == IFM_NONE)
1262 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1264 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1266 for (i = 0; i < DC_TIMEOUT; i++) {
1267 isr = CSR_READ_4(sc, DC_ISR);
1268 if ((isr & DC_ISR_TX_IDLE) &&
1269 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED ||
1270 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT))
1275 if (i == DC_TIMEOUT) {
1276 if_printf(&sc->arpcom.ac_if,
1277 "failed to force tx and rx to idle state\n");
1281 if (IFM_SUBTYPE(media) == IFM_100_TX) {
1282 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1283 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1284 if (sc->dc_pmode == DC_PMODE_MII) {
1287 if (DC_IS_INTEL(sc)) {
1288 /* there's a write enable bit here that reads as 1 */
1289 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1290 watchdogreg &= ~DC_WDOG_CTLWREN;
1291 watchdogreg |= DC_WDOG_JABBERDIS;
1292 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1294 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1296 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1297 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1298 if (sc->dc_type == DC_TYPE_98713)
1299 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1300 DC_NETCFG_SCRAMBLER));
1301 if (!DC_IS_DAVICOM(sc))
1302 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1303 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1304 if (DC_IS_INTEL(sc))
1305 dc_apply_fixup(sc, IFM_AUTO);
1307 if (DC_IS_PNIC(sc)) {
1308 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1309 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1310 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1312 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1313 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1314 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1315 if (DC_IS_INTEL(sc))
1317 (media & IFM_GMASK) == IFM_FDX ?
1318 IFM_100_TX|IFM_FDX : IFM_100_TX);
1322 if (IFM_SUBTYPE(media) == IFM_10_T) {
1323 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1324 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1325 if (sc->dc_pmode == DC_PMODE_MII) {
1328 /* there's a write enable bit here that reads as 1 */
1329 if (DC_IS_INTEL(sc)) {
1330 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1331 watchdogreg &= ~DC_WDOG_CTLWREN;
1332 watchdogreg |= DC_WDOG_JABBERDIS;
1333 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1335 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1337 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1338 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER));
1339 if (sc->dc_type == DC_TYPE_98713)
1340 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1341 if (!DC_IS_DAVICOM(sc))
1342 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1343 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1344 if (DC_IS_INTEL(sc))
1345 dc_apply_fixup(sc, IFM_AUTO);
1347 if (DC_IS_PNIC(sc)) {
1348 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1349 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1350 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1352 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1353 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1354 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1355 if (DC_IS_INTEL(sc)) {
1356 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1357 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1358 if ((media & IFM_GMASK) == IFM_FDX)
1359 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1361 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1362 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1363 DC_CLRBIT(sc, DC_10BTCTRL,
1364 DC_TCTL_AUTONEGENBL);
1366 (media & IFM_GMASK) == IFM_FDX ?
1367 IFM_10_T|IFM_FDX : IFM_10_T);
1374 * If this is a Davicom DM9102A card with a DM9801 HomePNA
1375 * PHY and we want HomePNA mode, set the portsel bit to turn
1376 * on the external MII port.
1378 if (DC_IS_DAVICOM(sc)) {
1379 if (IFM_SUBTYPE(media) == IFM_HPNA_1) {
1380 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1383 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1387 if ((media & IFM_GMASK) == IFM_FDX) {
1388 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1389 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1390 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1392 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1393 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1394 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1398 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1404 dc_reset(struct dc_softc *sc)
1408 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1410 for (i = 0; i < DC_TIMEOUT; i++) {
1412 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1416 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_CONEXANT(sc)) {
1418 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1422 if (i == DC_TIMEOUT)
1423 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
1425 /* Wait a little while for the chip to get its brains in order. */
1428 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1429 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1430 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1433 * Bring the SIA out of reset. In some cases, it looks
1434 * like failing to unreset the SIA soon enough gets it
1435 * into a state where it will never come out of reset
1436 * until we reset the whole chip again.
1438 if (DC_IS_INTEL(sc)) {
1439 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1440 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1441 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1447 static const struct dc_type *
1448 dc_devtype(device_t dev)
1450 const struct dc_type *t;
1455 while(t->dc_name != NULL) {
1456 if ((pci_get_vendor(dev) == t->dc_vid) &&
1457 (pci_get_device(dev) == t->dc_did)) {
1458 /* Check the PCI revision */
1459 rev = pci_get_revid(dev);
1460 if (t->dc_did == DC_DEVICEID_98713 &&
1461 rev >= DC_REVISION_98713A)
1463 if (t->dc_did == DC_DEVICEID_98713_CP &&
1464 rev >= DC_REVISION_98713A)
1466 if (t->dc_did == DC_DEVICEID_987x5 &&
1467 rev >= DC_REVISION_98715AEC_C)
1469 if (t->dc_did == DC_DEVICEID_987x5 &&
1470 rev >= DC_REVISION_98725)
1472 if (t->dc_did == DC_DEVICEID_AX88140A &&
1473 rev >= DC_REVISION_88141)
1475 if (t->dc_did == DC_DEVICEID_82C168 &&
1476 rev >= DC_REVISION_82C169)
1478 if (t->dc_did == DC_DEVICEID_DM9102 &&
1479 rev >= DC_REVISION_DM9102A)
1490 * Probe for a 21143 or clone chip. Check the PCI vendor and device
1491 * IDs against our list and return a device name if we find a match.
1492 * We do a little bit of extra work to identify the exact type of
1493 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID,
1494 * but different revision IDs. The same is true for 98715/98715A
1495 * chips and the 98725, as well as the ASIX and ADMtek chips. In some
1496 * cases, the exact chip revision affects driver behavior.
1499 dc_probe(device_t dev)
1501 const struct dc_type *t;
1503 t = dc_devtype(dev);
1505 struct dc_softc *sc = device_get_softc(dev);
1507 /* Need this info to decide on a chip type. */
1509 device_set_desc(dev, t->dc_name);
1517 dc_acpi(device_t dev)
1519 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1520 uint32_t iobase, membase, irq;
1521 struct dc_softc *sc;
1523 /* Save important PCI config data. */
1524 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4);
1525 membase = pci_read_config(dev, DC_PCI_CFBMA, 4);
1526 irq = pci_read_config(dev, DC_PCI_CFIT, 4);
1528 sc = device_get_softc(dev);
1529 /* Reset the power state. */
1530 if_printf(&sc->arpcom.ac_if,
1531 "chip is in D%d power mode "
1532 "-- setting to D0\n", pci_get_powerstate(dev));
1533 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1535 /* Restore PCI config data. */
1536 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4);
1537 pci_write_config(dev, DC_PCI_CFBMA, membase, 4);
1538 pci_write_config(dev, DC_PCI_CFIT, irq, 4);
1543 dc_apply_fixup(struct dc_softc *sc, int media)
1545 struct dc_mediainfo *m;
1553 if (m->dc_media == media)
1561 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) {
1562 reg = (p[0] | (p[1] << 8)) << 16;
1563 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1566 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) {
1567 reg = (p[0] | (p[1] << 8)) << 16;
1568 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1575 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1577 struct dc_mediainfo *m;
1579 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1580 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT){
1581 case DC_SIA_CODE_10BT:
1582 m->dc_media = IFM_10_T;
1585 case DC_SIA_CODE_10BT_FDX:
1586 m->dc_media = IFM_10_T|IFM_FDX;
1589 case DC_SIA_CODE_10B2:
1590 m->dc_media = IFM_10_2;
1593 case DC_SIA_CODE_10B5:
1594 m->dc_media = IFM_10_5;
1597 if (l->dc_sia_code & DC_SIA_CODE_EXT){
1600 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl;
1604 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl;
1607 m->dc_next = sc->dc_mi;
1610 sc->dc_pmode = DC_PMODE_SIA;
1616 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1618 struct dc_mediainfo *m;
1620 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1621 if (l->dc_sym_code == DC_SYM_CODE_100BT)
1622 m->dc_media = IFM_100_TX;
1624 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX)
1625 m->dc_media = IFM_100_TX|IFM_FDX;
1628 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl;
1630 m->dc_next = sc->dc_mi;
1633 sc->dc_pmode = DC_PMODE_SYM;
1639 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1642 struct dc_mediainfo *m;
1644 m = malloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO);
1645 /* We abuse IFM_AUTO to represent MII. */
1646 m->dc_media = IFM_AUTO;
1647 m->dc_gp_len = l->dc_gpr_len;
1650 p += sizeof(struct dc_eblock_mii);
1652 p += 2 * l->dc_gpr_len;
1653 m->dc_reset_len = *p;
1655 m->dc_reset_ptr = p;
1657 m->dc_next = sc->dc_mi;
1664 dc_read_srom(struct dc_softc *sc, int bits)
1669 sc->dc_srom = malloc(size, M_DEVBUF, M_INTWAIT);
1670 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0);
1674 dc_parse_21143_srom(struct dc_softc *sc)
1676 struct dc_leaf_hdr *lhdr;
1677 struct dc_eblock_hdr *hdr;
1683 loff = sc->dc_srom[27];
1684 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1687 ptr += sizeof(struct dc_leaf_hdr) - 1;
1689 * Look if we got a MII media block.
1691 for (i = 0; i < lhdr->dc_mcnt; i++) {
1692 hdr = (struct dc_eblock_hdr *)ptr;
1693 if (hdr->dc_type == DC_EBLOCK_MII)
1696 ptr += (hdr->dc_len & 0x7F);
1701 * Do the same thing again. Only use SIA and SYM media
1702 * blocks if no MII media block is available.
1705 ptr += sizeof(struct dc_leaf_hdr) - 1;
1706 for (i = 0; i < lhdr->dc_mcnt; i++) {
1707 hdr = (struct dc_eblock_hdr *)ptr;
1708 switch(hdr->dc_type) {
1710 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1714 dc_decode_leaf_sia(sc,
1715 (struct dc_eblock_sia *)hdr);
1719 dc_decode_leaf_sym(sc,
1720 (struct dc_eblock_sym *)hdr);
1723 /* Don't care. Yet. */
1726 ptr += (hdr->dc_len & 0x7F);
1734 * Attach the interface. Allocate softc structures, do ifmedia
1735 * setup and ethernet/BPF attach.
1738 dc_attach(device_t dev)
1741 u_char eaddr[ETHER_ADDR_LEN];
1743 struct dc_softc *sc;
1746 int error = 0, rid, mac_offset;
1748 sc = device_get_softc(dev);
1749 callout_init(&sc->dc_stat_timer);
1751 ifp = &sc->arpcom.ac_if;
1752 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1755 * Handle power management nonsense.
1760 * Map control/status registers.
1762 pci_enable_busmaster(dev);
1765 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE);
1767 if (sc->dc_res == NULL) {
1768 device_printf(dev, "couldn't map ports/memory\n");
1773 sc->dc_btag = rman_get_bustag(sc->dc_res);
1774 sc->dc_bhandle = rman_get_bushandle(sc->dc_res);
1776 /* Allocate interrupt */
1778 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1779 RF_SHAREABLE | RF_ACTIVE);
1781 if (sc->dc_irq == NULL) {
1782 device_printf(dev, "couldn't map interrupt\n");
1787 revision = pci_get_revid(dev);
1789 /* Get the eeprom width, but PNIC has diff eeprom */
1790 if (sc->dc_info->dc_did != DC_DEVICEID_82C168)
1791 dc_eeprom_width(sc);
1793 switch(sc->dc_info->dc_did) {
1794 case DC_DEVICEID_21143:
1795 sc->dc_type = DC_TYPE_21143;
1796 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1797 sc->dc_flags |= DC_REDUCED_MII_POLL;
1798 /* Save EEPROM contents so we can parse them later. */
1799 dc_read_srom(sc, sc->dc_romwidth);
1801 case DC_DEVICEID_DM9009:
1802 case DC_DEVICEID_DM9100:
1803 case DC_DEVICEID_DM9102:
1804 sc->dc_type = DC_TYPE_DM9102;
1805 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS;
1806 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD;
1807 sc->dc_flags |= DC_TX_ALIGN;
1808 sc->dc_pmode = DC_PMODE_MII;
1809 /* Increase the latency timer value. */
1810 command = pci_read_config(dev, DC_PCI_CFLT, 4);
1811 command &= 0xFFFF00FF;
1812 command |= 0x00008000;
1813 pci_write_config(dev, DC_PCI_CFLT, command, 4);
1815 case DC_DEVICEID_AL981:
1816 sc->dc_type = DC_TYPE_AL981;
1817 sc->dc_flags |= DC_TX_USE_TX_INTR;
1818 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1819 sc->dc_pmode = DC_PMODE_MII;
1820 dc_read_srom(sc, sc->dc_romwidth);
1822 case DC_DEVICEID_AN985:
1823 case DC_DEVICEID_ADM9511:
1824 case DC_DEVICEID_ADM9513:
1825 case DC_DEVICEID_EN2242:
1826 case DC_DEVICEID_3CSOHOB:
1827 sc->dc_type = DC_TYPE_AN985;
1828 sc->dc_flags |= DC_64BIT_HASH;
1829 sc->dc_flags |= DC_TX_USE_TX_INTR;
1830 sc->dc_flags |= DC_TX_ADMTEK_WAR;
1831 sc->dc_pmode = DC_PMODE_MII;
1833 case DC_DEVICEID_98713:
1834 case DC_DEVICEID_98713_CP:
1835 if (revision < DC_REVISION_98713A) {
1836 sc->dc_type = DC_TYPE_98713;
1838 if (revision >= DC_REVISION_98713A) {
1839 sc->dc_type = DC_TYPE_98713A;
1840 sc->dc_flags |= DC_21143_NWAY;
1842 sc->dc_flags |= DC_REDUCED_MII_POLL;
1843 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1845 case DC_DEVICEID_987x5:
1846 case DC_DEVICEID_EN1217:
1848 * Macronix MX98715AEC-C/D/E parts have only a
1849 * 128-bit hash table. We need to deal with these
1850 * in the same manner as the PNIC II so that we
1851 * get the right number of bits out of the
1854 if (revision >= DC_REVISION_98715AEC_C &&
1855 revision < DC_REVISION_98725)
1856 sc->dc_flags |= DC_128BIT_HASH;
1857 sc->dc_type = DC_TYPE_987x5;
1858 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1859 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1861 case DC_DEVICEID_98727:
1862 sc->dc_type = DC_TYPE_987x5;
1863 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR;
1864 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1866 case DC_DEVICEID_82C115:
1867 sc->dc_type = DC_TYPE_PNICII;
1868 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH;
1869 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY;
1871 case DC_DEVICEID_82C168:
1872 sc->dc_type = DC_TYPE_PNIC;
1873 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS;
1874 sc->dc_flags |= DC_PNIC_RX_BUG_WAR;
1875 sc->dc_pnic_rx_buf = malloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK);
1876 if (revision < DC_REVISION_82C169)
1877 sc->dc_pmode = DC_PMODE_SYM;
1879 case DC_DEVICEID_AX88140A:
1880 sc->dc_type = DC_TYPE_ASIX;
1881 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG;
1882 sc->dc_flags |= DC_REDUCED_MII_POLL;
1883 sc->dc_pmode = DC_PMODE_MII;
1885 case DC_DEVICEID_RS7112:
1886 sc->dc_type = DC_TYPE_CONEXANT;
1887 sc->dc_flags |= DC_TX_INTR_ALWAYS;
1888 sc->dc_flags |= DC_REDUCED_MII_POLL;
1889 sc->dc_pmode = DC_PMODE_MII;
1890 dc_read_srom(sc, sc->dc_romwidth);
1893 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did);
1897 /* Save the cache line size. */
1898 if (DC_IS_DAVICOM(sc))
1899 sc->dc_cachesize = 0;
1901 sc->dc_cachesize = pci_read_config(dev,
1902 DC_PCI_CFLT, 4) & 0xFF;
1904 /* Reset the adapter. */
1907 /* Take 21143 out of snooze mode */
1908 if (DC_IS_INTEL(sc)) {
1909 command = pci_read_config(dev, DC_PCI_CFDD, 4);
1910 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE);
1911 pci_write_config(dev, DC_PCI_CFDD, command, 4);
1915 * Try to learn something about the supported media.
1916 * We know that ASIX and ADMtek and Davicom devices
1917 * will *always* be using MII media, so that's a no-brainer.
1918 * The tricky ones are the Macronix/PNIC II and the
1921 if (DC_IS_INTEL(sc))
1922 dc_parse_21143_srom(sc);
1923 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
1924 if (sc->dc_type == DC_TYPE_98713)
1925 sc->dc_pmode = DC_PMODE_MII;
1927 sc->dc_pmode = DC_PMODE_SYM;
1928 } else if (!sc->dc_pmode)
1929 sc->dc_pmode = DC_PMODE_MII;
1932 * Get station address from the EEPROM.
1934 switch(sc->dc_type) {
1936 case DC_TYPE_98713A:
1938 case DC_TYPE_PNICII:
1939 dc_read_eeprom(sc, (caddr_t)&mac_offset,
1940 (DC_EE_NODEADDR_OFFSET / 2), 1, 0);
1941 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0);
1944 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1);
1946 case DC_TYPE_DM9102:
1949 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
1953 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0);
1954 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1);
1956 case DC_TYPE_CONEXANT:
1957 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6);
1960 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0);
1964 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF,
1965 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1967 if (sc->dc_ldata == NULL) {
1968 device_printf(dev, "no memory for list buffers!\n");
1973 bzero(sc->dc_ldata, sizeof(struct dc_list_data));
1976 ifp->if_mtu = ETHERMTU;
1977 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1978 ifp->if_ioctl = dc_ioctl;
1979 ifp->if_start = dc_start;
1980 #ifdef DEVICE_POLLING
1981 ifp->if_poll = dc_poll;
1983 ifp->if_watchdog = dc_watchdog;
1984 ifp->if_init = dc_init;
1985 ifp->if_baudrate = 10000000;
1986 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1);
1987 ifq_set_ready(&ifp->if_snd);
1990 * Do MII setup. If this is a 21143, check for a PHY on the
1991 * MII bus after applying any necessary fixups to twiddle the
1992 * GPIO bits. If we don't end up finding a PHY, restore the
1993 * old selection (SIA only or SIA/SYM) and attach the dcphy
1996 if (DC_IS_INTEL(sc)) {
1997 dc_apply_fixup(sc, IFM_AUTO);
1999 sc->dc_pmode = DC_PMODE_MII;
2002 error = mii_phy_probe(dev, &sc->dc_miibus,
2003 dc_ifmedia_upd, dc_ifmedia_sts);
2005 if (error && DC_IS_INTEL(sc)) {
2007 if (sc->dc_pmode != DC_PMODE_SIA)
2008 sc->dc_pmode = DC_PMODE_SYM;
2009 sc->dc_flags |= DC_21143_NWAY;
2010 mii_phy_probe(dev, &sc->dc_miibus,
2011 dc_ifmedia_upd, dc_ifmedia_sts);
2013 * For non-MII cards, we need to have the 21143
2014 * drive the LEDs. Except there are some systems
2015 * like the NEC VersaPro NoteBook PC which have no
2016 * LEDs, and twiddling these bits has adverse effects
2017 * on them. (I.e. you suddenly can't get a link.)
2019 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033)
2020 sc->dc_flags |= DC_TULIP_LEDS;
2025 device_printf(dev, "MII without any PHY!\n");
2031 * Call MI attach routine.
2033 ether_ifattach(ifp, eaddr);
2035 if (DC_IS_ADMTEK(sc)) {
2037 * Set automatic TX underrun recovery for the ADMtek chips
2039 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
2043 * Tell the upper layer(s) we support long frames.
2045 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2047 error = bus_setup_intr(dev, sc->dc_irq, 0,
2048 dc_intr, sc, &sc->dc_intrhand, NULL);
2050 ether_ifdetach(ifp);
2051 device_printf(dev, "couldn't set up irq\n");
2063 dc_detach(device_t dev)
2065 struct dc_softc *sc = device_get_softc(dev);
2066 struct ifnet *ifp = &sc->arpcom.ac_if;
2067 struct dc_mediainfo *m;
2071 if (device_is_attached(dev)) {
2073 ether_ifdetach(ifp);
2077 device_delete_child(dev, sc->dc_miibus);
2078 bus_generic_detach(dev);
2080 if (sc->dc_intrhand)
2081 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand);
2086 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq);
2088 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res);
2091 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF);
2092 if (sc->dc_pnic_rx_buf != NULL)
2093 free(sc->dc_pnic_rx_buf, M_DEVBUF);
2095 while(sc->dc_mi != NULL) {
2096 m = sc->dc_mi->dc_next;
2097 free(sc->dc_mi, M_DEVBUF);
2102 free(sc->dc_srom, M_DEVBUF);
2108 * Initialize the transmit descriptors.
2111 dc_list_tx_init(struct dc_softc *sc)
2113 struct dc_chain_data *cd;
2114 struct dc_list_data *ld;
2119 for (i = 0; i < DC_TX_LIST_CNT; i++) {
2120 if (i == (DC_TX_LIST_CNT - 1)) {
2121 ld->dc_tx_list[i].dc_next =
2122 vtophys(&ld->dc_tx_list[0]);
2124 ld->dc_tx_list[i].dc_next =
2125 vtophys(&ld->dc_tx_list[i + 1]);
2127 cd->dc_tx_chain[i] = NULL;
2128 ld->dc_tx_list[i].dc_data = 0;
2129 ld->dc_tx_list[i].dc_ctl = 0;
2132 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0;
2139 * Initialize the RX descriptors and allocate mbufs for them. Note that
2140 * we arrange the descriptors in a closed ring, so that the last descriptor
2141 * points back to the first.
2144 dc_list_rx_init(struct dc_softc *sc)
2146 struct dc_chain_data *cd;
2147 struct dc_list_data *ld;
2153 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2154 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
2156 if (i == (DC_RX_LIST_CNT - 1)) {
2157 ld->dc_rx_list[i].dc_next =
2158 vtophys(&ld->dc_rx_list[0]);
2160 ld->dc_rx_list[i].dc_next =
2161 vtophys(&ld->dc_rx_list[i + 1]);
2171 * Initialize an RX descriptor and attach an MBUF cluster.
2174 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m)
2176 struct mbuf *m_new = NULL;
2179 c = &sc->dc_ldata->dc_rx_list[i];
2182 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2185 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2188 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2189 m_new->m_data = m_new->m_ext.ext_buf;
2192 m_adj(m_new, sizeof(u_int64_t));
2195 * If this is a PNIC chip, zero the buffer. This is part
2196 * of the workaround for the receive bug in the 82c168 and
2199 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
2200 bzero((char *)mtod(m_new, char *), m_new->m_len);
2202 sc->dc_cdata.dc_rx_chain[i] = m_new;
2203 c->dc_data = vtophys(mtod(m_new, caddr_t));
2204 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN;
2205 c->dc_status = DC_RXSTAT_OWN;
2212 * The PNIC chip has a terrible bug in it that manifests itself during
2213 * periods of heavy activity. The exact mode of failure if difficult to
2214 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it
2215 * will happen on slow machines. The bug is that sometimes instead of
2216 * uploading one complete frame during reception, it uploads what looks
2217 * like the entire contents of its FIFO memory. The frame we want is at
2218 * the end of the whole mess, but we never know exactly how much data has
2219 * been uploaded, so salvaging the frame is hard.
2221 * There is only one way to do it reliably, and it's disgusting.
2222 * Here's what we know:
2224 * - We know there will always be somewhere between one and three extra
2225 * descriptors uploaded.
2227 * - We know the desired received frame will always be at the end of the
2228 * total data upload.
2230 * - We know the size of the desired received frame because it will be
2231 * provided in the length field of the status word in the last descriptor.
2233 * Here's what we do:
2235 * - When we allocate buffers for the receive ring, we bzero() them.
2236 * This means that we know that the buffer contents should be all
2237 * zeros, except for data uploaded by the chip.
2239 * - We also force the PNIC chip to upload frames that include the
2240 * ethernet CRC at the end.
2242 * - We gather all of the bogus frame data into a single buffer.
2244 * - We then position a pointer at the end of this buffer and scan
2245 * backwards until we encounter the first non-zero byte of data.
2246 * This is the end of the received frame. We know we will encounter
2247 * some data at the end of the frame because the CRC will always be
2248 * there, so even if the sender transmits a packet of all zeros,
2249 * we won't be fooled.
2251 * - We know the size of the actual received frame, so we subtract
2252 * that value from the current pointer location. This brings us
2253 * to the start of the actual received packet.
2255 * - We copy this into an mbuf and pass it on, along with the actual
2258 * The performance hit is tremendous, but it beats dropping frames all
2262 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG)
2264 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
2266 struct dc_desc *cur_rx;
2267 struct dc_desc *c = NULL;
2268 struct mbuf *m = NULL;
2271 u_int32_t rxstat = 0;
2273 i = sc->dc_pnic_rx_bug_save;
2274 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
2275 ptr = sc->dc_pnic_rx_buf;
2276 bzero(ptr, DC_RXLEN * 5);
2278 /* Copy all the bytes from the bogus buffers. */
2280 c = &sc->dc_ldata->dc_rx_list[i];
2281 rxstat = c->dc_status;
2282 m = sc->dc_cdata.dc_rx_chain[i];
2283 bcopy(mtod(m, char *), ptr, DC_RXLEN);
2285 /* If this is the last buffer, break out. */
2286 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG)
2288 dc_newbuf(sc, i, m);
2289 DC_INC(i, DC_RX_LIST_CNT);
2292 /* Find the length of the actual receive frame. */
2293 total_len = DC_RXBYTES(rxstat);
2295 /* Scan backwards until we hit a non-zero byte. */
2300 if ((uintptr_t)(ptr) & 0x3)
2303 /* Now find the start of the frame. */
2305 if (ptr < sc->dc_pnic_rx_buf)
2306 ptr = sc->dc_pnic_rx_buf;
2309 * Now copy the salvaged frame to the last mbuf and fake up
2310 * the status word to make it look like a successful
2313 dc_newbuf(sc, i, m);
2314 bcopy(ptr, mtod(m, char *), total_len);
2315 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG;
2321 * This routine searches the RX ring for dirty descriptors in the
2322 * event that the rxeof routine falls out of sync with the chip's
2323 * current descriptor pointer. This may happen sometimes as a result
2324 * of a "no RX buffer available" condition that happens when the chip
2325 * consumes all of the RX buffers before the driver has a chance to
2326 * process the RX ring. This routine may need to be called more than
2327 * once to bring the driver back in sync with the chip, however we
2328 * should still be getting RX DONE interrupts to drive the search
2329 * for new packets in the RX ring, so we should catch up eventually.
2332 dc_rx_resync(struct dc_softc *sc)
2335 struct dc_desc *cur_rx;
2337 pos = sc->dc_cdata.dc_rx_prod;
2339 for (i = 0; i < DC_RX_LIST_CNT; i++) {
2340 cur_rx = &sc->dc_ldata->dc_rx_list[pos];
2341 if (!(cur_rx->dc_status & DC_RXSTAT_OWN))
2343 DC_INC(pos, DC_RX_LIST_CNT);
2346 /* If the ring really is empty, then just return. */
2347 if (i == DC_RX_LIST_CNT)
2350 /* We've fallen behing the chip: catch it. */
2351 sc->dc_cdata.dc_rx_prod = pos;
2357 * A frame has been uploaded: pass the resulting mbuf chain up to
2358 * the higher level protocols.
2361 dc_rxeof(struct dc_softc *sc)
2365 struct dc_desc *cur_rx;
2366 int i, total_len = 0;
2369 ifp = &sc->arpcom.ac_if;
2370 i = sc->dc_cdata.dc_rx_prod;
2372 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) {
2374 #ifdef DEVICE_POLLING
2375 if (ifp->if_flags & IFF_POLLING) {
2376 if (sc->rxcycles <= 0)
2380 #endif /* DEVICE_POLLING */
2381 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2382 rxstat = cur_rx->dc_status;
2383 m = sc->dc_cdata.dc_rx_chain[i];
2384 total_len = DC_RXBYTES(rxstat);
2386 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2387 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) {
2388 if (rxstat & DC_RXSTAT_FIRSTFRAG)
2389 sc->dc_pnic_rx_bug_save = i;
2390 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) {
2391 DC_INC(i, DC_RX_LIST_CNT);
2394 dc_pnic_rx_bug_war(sc, i);
2395 rxstat = cur_rx->dc_status;
2396 total_len = DC_RXBYTES(rxstat);
2400 sc->dc_cdata.dc_rx_chain[i] = NULL;
2403 * If an error occurs, update stats, clear the
2404 * status word and leave the mbuf cluster in place:
2405 * it should simply get re-used next time this descriptor
2406 * comes up in the ring. However, don't report long
2407 * frames as errors since they could be vlans
2409 if ((rxstat & DC_RXSTAT_RXERR)){
2410 if (!(rxstat & DC_RXSTAT_GIANT) ||
2411 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE |
2412 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN |
2413 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) {
2415 if (rxstat & DC_RXSTAT_COLLSEEN)
2416 ifp->if_collisions++;
2417 dc_newbuf(sc, i, m);
2418 if (rxstat & DC_RXSTAT_CRCERR) {
2419 DC_INC(i, DC_RX_LIST_CNT);
2428 /* No errors; receive the packet. */
2429 total_len -= ETHER_CRC_LEN;
2433 * On the x86 we do not have alignment problems, so try to
2434 * allocate a new buffer for the receive ring, and pass up
2435 * the one where the packet is already, saving the expensive
2436 * copy done in m_devget().
2437 * If we are on an architecture with alignment problems, or
2438 * if the allocation fails, then use m_devget and leave the
2439 * existing buffer in the receive ring.
2441 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) {
2442 m->m_pkthdr.rcvif = ifp;
2443 m->m_pkthdr.len = m->m_len = total_len;
2444 DC_INC(i, DC_RX_LIST_CNT);
2450 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2451 total_len + ETHER_ALIGN, 0, ifp, NULL);
2452 dc_newbuf(sc, i, m);
2453 DC_INC(i, DC_RX_LIST_CNT);
2458 m_adj(m0, ETHER_ALIGN);
2463 (*ifp->if_input)(ifp, m);
2466 sc->dc_cdata.dc_rx_prod = i;
2470 * A frame was downloaded to the chip. It's safe for us to clean up
2475 dc_txeof(struct dc_softc *sc)
2477 struct dc_desc *cur_tx = NULL;
2481 ifp = &sc->arpcom.ac_if;
2484 * Go through our tx list and free mbufs for those
2485 * frames that have been transmitted.
2487 idx = sc->dc_cdata.dc_tx_cons;
2488 while(idx != sc->dc_cdata.dc_tx_prod) {
2491 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2492 txstat = cur_tx->dc_status;
2494 if (txstat & DC_TXSTAT_OWN)
2497 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) ||
2498 cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2499 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) {
2501 * Yes, the PNIC is so brain damaged
2502 * that it will sometimes generate a TX
2503 * underrun error while DMAing the RX
2504 * filter setup frame. If we detect this,
2505 * we have to send the setup frame again,
2506 * or else the filter won't be programmed
2509 if (DC_IS_PNIC(sc)) {
2510 if (txstat & DC_TXSTAT_ERRSUM)
2513 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2515 sc->dc_cdata.dc_tx_cnt--;
2516 DC_INC(idx, DC_TX_LIST_CNT);
2520 if (DC_IS_CONEXANT(sc)) {
2522 * For some reason Conexant chips like
2523 * setting the CARRLOST flag even when
2524 * the carrier is there. In CURRENT we
2525 * have the same problem for Xircom
2528 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2529 sc->dc_pmode == DC_PMODE_MII &&
2530 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2531 DC_TXSTAT_NOCARRIER)))
2532 txstat &= ~DC_TXSTAT_ERRSUM;
2534 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2535 sc->dc_pmode == DC_PMODE_MII &&
2536 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM|
2537 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST)))
2538 txstat &= ~DC_TXSTAT_ERRSUM;
2541 if (txstat & DC_TXSTAT_ERRSUM) {
2543 if (txstat & DC_TXSTAT_EXCESSCOLL)
2544 ifp->if_collisions++;
2545 if (txstat & DC_TXSTAT_LATECOLL)
2546 ifp->if_collisions++;
2547 if (!(txstat & DC_TXSTAT_UNDERRUN)) {
2553 ifp->if_collisions += (txstat & DC_TXSTAT_COLLCNT) >> 3;
2556 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) {
2557 m_freem(sc->dc_cdata.dc_tx_chain[idx]);
2558 sc->dc_cdata.dc_tx_chain[idx] = NULL;
2561 sc->dc_cdata.dc_tx_cnt--;
2562 DC_INC(idx, DC_TX_LIST_CNT);
2565 if (idx != sc->dc_cdata.dc_tx_cons) {
2566 /* some buffers have been freed */
2567 sc->dc_cdata.dc_tx_cons = idx;
2568 ifp->if_flags &= ~IFF_OACTIVE;
2570 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5;
2578 struct dc_softc *sc = xsc;
2579 struct ifnet *ifp = &sc->arpcom.ac_if;
2580 struct mii_data *mii;
2585 mii = device_get_softc(sc->dc_miibus);
2587 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2588 if (sc->dc_flags & DC_21143_NWAY) {
2589 r = CSR_READ_4(sc, DC_10BTSTAT);
2590 if (IFM_SUBTYPE(mii->mii_media_active) ==
2591 IFM_100_TX && (r & DC_TSTAT_LS100)) {
2595 if (IFM_SUBTYPE(mii->mii_media_active) ==
2596 IFM_10_T && (r & DC_TSTAT_LS10)) {
2600 if (sc->dc_link == 0)
2603 r = CSR_READ_4(sc, DC_ISR);
2604 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT &&
2605 sc->dc_cdata.dc_tx_cnt == 0) {
2607 if (!(mii->mii_media_status & IFM_ACTIVE))
2615 * When the init routine completes, we expect to be able to send
2616 * packets right away, and in fact the network code will send a
2617 * gratuitous ARP the moment the init routine marks the interface
2618 * as running. However, even though the MAC may have been initialized,
2619 * there may be a delay of a few seconds before the PHY completes
2620 * autonegotiation and the link is brought up. Any transmissions
2621 * made during that delay will be lost. Dealing with this is tricky:
2622 * we can't just pause in the init routine while waiting for the
2623 * PHY to come ready since that would bring the whole system to
2624 * a screeching halt for several seconds.
2626 * What we do here is prevent the TX start routine from sending
2627 * any packets until a link has been established. After the
2628 * interface has been initialized, the tick routine will poll
2629 * the state of the PHY until the IFM_ACTIVE flag is set. Until
2630 * that time, packets will stay in the send queue, and once the
2631 * link comes up, they will be flushed out to the wire.
2635 if (mii->mii_media_status & IFM_ACTIVE &&
2636 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2638 if (!ifq_is_empty(&ifp->if_snd))
2643 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2644 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc);
2646 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
2652 * A transmit underrun has occurred. Back off the transmit threshold,
2653 * or switch to store and forward mode if we have to.
2656 dc_tx_underrun(struct dc_softc *sc)
2661 if (DC_IS_DAVICOM(sc))
2664 if (DC_IS_INTEL(sc)) {
2666 * The real 21143 requires that the transmitter be idle
2667 * in order to change the transmit threshold or store
2668 * and forward state.
2670 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2672 for (i = 0; i < DC_TIMEOUT; i++) {
2673 isr = CSR_READ_4(sc, DC_ISR);
2674 if (isr & DC_ISR_TX_IDLE)
2678 if (i == DC_TIMEOUT) {
2679 if_printf(&sc->arpcom.ac_if,
2680 "failed to force tx to idle state\n");
2685 if_printf(&sc->arpcom.ac_if, "TX underrun -- ");
2686 sc->dc_txthresh += DC_TXTHRESH_INC;
2687 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2688 printf("using store and forward mode\n");
2689 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2691 printf("increasing TX threshold\n");
2692 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2693 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2696 if (DC_IS_INTEL(sc))
2697 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2702 #ifdef DEVICE_POLLING
2705 dc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2707 struct dc_softc *sc = ifp->if_softc;
2712 /* Disable interrupts */
2713 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2715 case POLL_DEREGISTER:
2716 /* Re-enable interrupts. */
2717 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2720 sc->rxcycles = count;
2723 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2726 case POLL_AND_CHECK_STATUS:
2727 sc->rxcycles = count;
2730 if ((ifp->if_flags & IFF_OACTIVE) == 0 && !ifq_is_empty(&ifp->if_snd))
2732 status = CSR_READ_4(sc, DC_ISR);
2733 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF|
2734 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN|
2738 /* ack what we have */
2739 CSR_WRITE_4(sc, DC_ISR, status);
2741 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) {
2742 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);
2743 ifp->if_ierrors += (r & 0xffff) + ((r >> 17) & 0x7ff);
2745 if (dc_rx_resync(sc))
2748 /* restart transmit unit if necessary */
2749 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt)
2750 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2752 if (status & DC_ISR_TX_UNDERRUN)
2755 if (status & DC_ISR_BUS_ERR) {
2756 if_printf(ifp, "dc_poll: bus error\n");
2763 #endif /* DEVICE_POLLING */
2768 struct dc_softc *sc;
2774 if (sc->suspended) {
2778 ifp = &sc->arpcom.ac_if;
2780 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)
2783 /* Suppress unwanted interrupts */
2784 if (!(ifp->if_flags & IFF_UP)) {
2785 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
2790 /* Disable interrupts. */
2791 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2793 while((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) {
2795 CSR_WRITE_4(sc, DC_ISR, status);
2797 if (status & DC_ISR_RX_OK) {
2799 curpkts = ifp->if_ipackets;
2801 if (curpkts == ifp->if_ipackets) {
2802 while(dc_rx_resync(sc))
2807 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF))
2810 if (status & DC_ISR_TX_IDLE) {
2812 if (sc->dc_cdata.dc_tx_cnt) {
2813 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2814 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2818 if (status & DC_ISR_TX_UNDERRUN)
2821 if ((status & DC_ISR_RX_WATDOGTIMEO)
2822 || (status & DC_ISR_RX_NOBUF)) {
2824 curpkts = ifp->if_ipackets;
2826 if (curpkts == ifp->if_ipackets) {
2827 while(dc_rx_resync(sc))
2832 if (status & DC_ISR_BUS_ERR) {
2838 /* Re-enable interrupts. */
2839 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2841 if (!ifq_is_empty(&ifp->if_snd))
2848 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2849 * pointers to the fragment pointers.
2852 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
2854 struct dc_desc *f = NULL;
2856 int frag, cur, cnt = 0;
2859 * Start packing the mbufs in this chain into
2860 * the fragment pointers. Stop when we run out
2861 * of fragments or hit the end of the mbuf chain.
2864 cur = frag = *txidx;
2866 for (m = m_head; m != NULL; m = m->m_next) {
2867 if (m->m_len != 0) {
2868 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
2869 if (*txidx != sc->dc_cdata.dc_tx_prod &&
2870 frag == (DC_TX_LIST_CNT - 1))
2873 if ((DC_TX_LIST_CNT -
2874 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5)
2877 f = &sc->dc_ldata->dc_tx_list[frag];
2878 f->dc_ctl = DC_TXCTL_TLINK | m->m_len;
2881 f->dc_ctl |= DC_TXCTL_FIRSTFRAG;
2883 f->dc_status = DC_TXSTAT_OWN;
2884 f->dc_data = vtophys(mtod(m, vm_offset_t));
2886 DC_INC(frag, DC_TX_LIST_CNT);
2894 sc->dc_cdata.dc_tx_cnt += cnt;
2895 sc->dc_cdata.dc_tx_chain[cur] = m_head;
2896 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG;
2897 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
2898 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT;
2899 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
2900 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
2901 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
2902 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT;
2903 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN;
2910 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2911 * to the mbuf data regions directly in the transmit lists. We also save a
2912 * copy of the pointers since the transmit list fragment pointers are
2913 * physical addresses.
2917 dc_start(struct ifnet *ifp)
2919 struct dc_softc *sc;
2920 struct mbuf *m_head = NULL, *m_new;
2921 int did_defrag, idx, need_trans;
2928 if (ifp->if_flags & IFF_OACTIVE)
2931 idx = sc->dc_cdata.dc_tx_prod;
2934 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) {
2936 m_head = ifq_poll(&ifp->if_snd);
2940 if (sc->dc_flags & DC_TX_COALESCE &&
2941 (m_head->m_next != NULL ||
2942 sc->dc_flags & DC_TX_ALIGN)){
2944 * Check first if coalescing allows us to queue
2945 * the packet. We don't want to loose it if
2946 * the TX queue is full.
2948 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) &&
2949 idx != sc->dc_cdata.dc_tx_prod &&
2950 idx == (DC_TX_LIST_CNT - 1)) {
2951 ifp->if_flags |= IFF_OACTIVE;
2954 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) {
2955 ifp->if_flags |= IFF_OACTIVE;
2959 /* only coalesce if have >1 mbufs */
2960 m_new = m_defrag_nofree(m_head, MB_DONTWAIT);
2961 if (m_new == NULL) {
2962 ifp->if_flags |= IFF_OACTIVE;
2970 if (dc_encap(sc, m_head, &idx)) {
2973 m_new = ifq_dequeue(&ifp->if_snd);
2976 ifp->if_flags |= IFF_OACTIVE;
2980 m_new = ifq_dequeue(&ifp->if_snd);
2986 * If there's a BPF listener, bounce a copy of this frame
2989 BPF_MTAP(ifp, m_head);
2991 if (sc->dc_flags & DC_TX_ONE) {
2992 ifp->if_flags |= IFF_OACTIVE;
3001 sc->dc_cdata.dc_tx_prod = idx;
3002 if (!(sc->dc_flags & DC_TX_POLL))
3003 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
3006 * Set a timeout in case the chip goes out to lunch.
3014 struct dc_softc *sc = xsc;
3015 struct ifnet *ifp = &sc->arpcom.ac_if;
3016 struct mii_data *mii;
3020 mii = device_get_softc(sc->dc_miibus);
3023 * Cancel pending I/O and free all RX/TX buffers.
3029 * Set cache alignment and burst length.
3031 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
3032 CSR_WRITE_4(sc, DC_BUSCTL, 0);
3034 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
3036 * Evenly share the bus between receive and transmit process.
3038 if (DC_IS_INTEL(sc))
3039 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
3040 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
3041 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
3043 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
3045 if (sc->dc_flags & DC_TX_POLL)
3046 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
3047 switch(sc->dc_cachesize) {
3049 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
3052 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
3055 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
3059 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
3063 if (sc->dc_flags & DC_TX_STORENFWD)
3064 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3066 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
3067 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3069 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
3070 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
3074 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
3075 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
3077 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
3079 * The app notes for the 98713 and 98715A say that
3080 * in order to have the chips operate properly, a magic
3081 * number must be written to CSR16. Macronix does not
3082 * document the meaning of these bits so there's no way
3083 * to know exactly what they do. The 98713 has a magic
3084 * number all its own; the rest all use a different one.
3086 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
3087 if (sc->dc_type == DC_TYPE_98713)
3088 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
3090 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
3093 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
3094 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
3096 /* Init circular RX list. */
3097 if (dc_list_rx_init(sc) == ENOBUFS) {
3098 if_printf(ifp, "initialization failed: no "
3099 "memory for rx buffers\n");
3106 * Init tx descriptors.
3108 dc_list_tx_init(sc);
3111 * Load the address of the RX list.
3113 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0]));
3114 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0]));
3117 * Enable interrupts.
3119 #ifdef DEVICE_POLLING
3121 * ... but only if we are not polling, and make sure they are off in
3122 * the case of polling. Some cards (e.g. fxp) turn interrupts on
3125 if (ifp->if_flags & IFF_POLLING)
3126 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3129 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
3130 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
3132 /* Enable transmitter. */
3133 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
3136 * If this is an Intel 21143 and we're not using the
3137 * MII port, program the LED control pins so we get
3138 * link and activity indications.
3140 if (sc->dc_flags & DC_TULIP_LEDS) {
3141 CSR_WRITE_4(sc, DC_WATCHDOG,
3142 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY);
3143 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
3147 * Load the RX/multicast filter. We do this sort of late
3148 * because the filter programming scheme on the 21143 and
3149 * some clones requires DMAing a setup frame via the TX
3150 * engine, and we need the transmitter enabled for that.
3154 /* Enable receiver. */
3155 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
3156 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
3159 dc_setcfg(sc, sc->dc_if_media);
3161 ifp->if_flags |= IFF_RUNNING;
3162 ifp->if_flags &= ~IFF_OACTIVE;
3166 /* Don't start the ticker if this is a homePNA link. */
3167 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1)
3170 if (sc->dc_flags & DC_21143_NWAY)
3171 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc);
3173 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc);
3180 * Set media options.
3183 dc_ifmedia_upd(struct ifnet *ifp)
3185 struct dc_softc *sc;
3186 struct mii_data *mii;
3187 struct ifmedia *ifm;
3190 mii = device_get_softc(sc->dc_miibus);
3192 ifm = &mii->mii_media;
3194 if (DC_IS_DAVICOM(sc) &&
3195 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1)
3196 dc_setcfg(sc, ifm->ifm_media);
3204 * Report current media status.
3207 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3209 struct dc_softc *sc;
3210 struct mii_data *mii;
3211 struct ifmedia *ifm;
3214 mii = device_get_softc(sc->dc_miibus);
3216 ifm = &mii->mii_media;
3217 if (DC_IS_DAVICOM(sc)) {
3218 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
3219 ifmr->ifm_active = ifm->ifm_media;
3220 ifmr->ifm_status = 0;
3224 ifmr->ifm_active = mii->mii_media_active;
3225 ifmr->ifm_status = mii->mii_media_status;
3231 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3233 struct dc_softc *sc = ifp->if_softc;
3234 struct ifreq *ifr = (struct ifreq *) data;
3235 struct mii_data *mii;
3242 if (ifp->if_flags & IFF_UP) {
3243 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) &
3244 (IFF_PROMISC | IFF_ALLMULTI);
3245 if (ifp->if_flags & IFF_RUNNING) {
3249 sc->dc_txthresh = 0;
3253 if (ifp->if_flags & IFF_RUNNING)
3256 sc->dc_if_flags = ifp->if_flags;
3266 mii = device_get_softc(sc->dc_miibus);
3267 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3270 error = ether_ioctl(ifp, command, data);
3280 dc_watchdog(struct ifnet *ifp)
3282 struct dc_softc *sc;
3287 if_printf(ifp, "watchdog timeout\n");
3293 if (!ifq_is_empty(&ifp->if_snd))
3300 * Stop the adapter and free any mbufs allocated to the
3304 dc_stop(struct dc_softc *sc)
3309 ifp = &sc->arpcom.ac_if;
3312 callout_stop(&sc->dc_stat_timer);
3314 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3316 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
3317 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3318 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3319 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3323 * Free data in the RX lists.
3325 for (i = 0; i < DC_RX_LIST_CNT; i++) {
3326 if (sc->dc_cdata.dc_rx_chain[i] != NULL) {
3327 m_freem(sc->dc_cdata.dc_rx_chain[i]);
3328 sc->dc_cdata.dc_rx_chain[i] = NULL;
3331 bzero((char *)&sc->dc_ldata->dc_rx_list,
3332 sizeof(sc->dc_ldata->dc_rx_list));
3335 * Free the TX list buffers.
3337 for (i = 0; i < DC_TX_LIST_CNT; i++) {
3338 if (sc->dc_cdata.dc_tx_chain[i] != NULL) {
3339 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl &
3341 !(sc->dc_ldata->dc_tx_list[i].dc_ctl &
3342 DC_TXCTL_LASTFRAG)) {
3343 sc->dc_cdata.dc_tx_chain[i] = NULL;
3346 m_freem(sc->dc_cdata.dc_tx_chain[i]);
3347 sc->dc_cdata.dc_tx_chain[i] = NULL;
3351 bzero((char *)&sc->dc_ldata->dc_tx_list,
3352 sizeof(sc->dc_ldata->dc_tx_list));
3358 * Stop all chip I/O so that the kernel's probe routines don't
3359 * get confused by errant DMAs when rebooting.
3362 dc_shutdown(device_t dev)
3364 struct dc_softc *sc;
3366 sc = device_get_softc(dev);
3374 * Device suspend routine. Stop the interface and save some PCI
3375 * settings in case the BIOS doesn't restore them properly on
3379 dc_suspend(device_t dev)
3381 struct dc_softc *sc = device_get_softc(dev);
3388 for (i = 0; i < 5; i++)
3389 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
3390 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
3391 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
3392 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3393 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3402 * Device resume routine. Restore some PCI settings in case the BIOS
3403 * doesn't, re-enable busmastering, and restart the interface if
3407 dc_resume(device_t dev)
3409 struct dc_softc *sc = device_get_softc(dev);
3410 struct ifnet *ifp = &sc->arpcom.ac_if;
3417 /* better way to do this? */
3418 for (i = 0; i < 5; i++)
3419 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3420 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3421 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3422 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3423 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3425 /* reenable busmastering */
3426 pci_enable_busmaster(dev);
3427 pci_enable_io(dev, DC_RES);
3429 /* reinitialize interface if necessary */
3430 if (ifp->if_flags & IFF_UP)