2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
4 * Copyright (c) 2008 The DragonFly Project.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the University of
18 * California, Berkeley and its contributors.
19 * 4. Neither the name of the University nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * $FreeBSD: src/sys/amd64/include/cpufunc.h,v 1.139 2004/01/28 23:53:04 peter Exp $
36 * $DragonFly: src/sys/cpu/amd64/include/cpufunc.h,v 1.3 2008/08/29 17:07:06 dillon Exp $
40 * Functions to provide access to special i386 instructions.
41 * This in included in sys/systm.h, and that file should be
42 * used in preference to this.
45 #ifndef _CPU_CPUFUNC_H_
46 #define _CPU_CPUFUNC_H_
48 #include <sys/cdefs.h>
49 #include <machine/psl.h>
52 struct region_descriptor;
55 #define readb(va) (*(volatile u_int8_t *) (va))
56 #define readw(va) (*(volatile u_int16_t *) (va))
57 #define readl(va) (*(volatile u_int32_t *) (va))
58 #define readq(va) (*(volatile u_int64_t *) (va))
60 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
61 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
62 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
63 #define writeq(va, d) (*(volatile u_int64_t *) (va) = (d))
68 #include <machine/lock.h> /* XXX */
74 __asm __volatile("int $3");
80 __asm __volatile("pause");
88 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
92 static __inline u_long
97 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
101 static __inline u_int
106 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
110 static __inline u_long
115 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
120 cpu_disable_intr(void)
122 __asm __volatile("cli" : : : "memory");
126 do_cpuid(u_int ax, u_int *p)
128 __asm __volatile("cpuid"
129 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
134 cpuid_count(u_int ax, u_int cx, u_int *p)
136 __asm __volatile("cpuid"
137 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
138 : "0" (ax), "c" (cx));
142 cpu_enable_intr(void)
144 __asm __volatile("sti");
148 * Cpu and compiler memory ordering fence. mfence ensures strong read and
151 * A serializing or fence instruction is required here. A locked bus
152 * cycle on data for which we already own cache mastership is the most
159 __asm __volatile("mfence" : : : "memory");
161 __asm __volatile("" : : : "memory");
166 * cpu_lfence() ensures strong read ordering for reads issued prior
167 * to the instruction verses reads issued afterwords.
169 * A serializing or fence instruction is required here. A locked bus
170 * cycle on data for which we already own cache mastership is the most
177 __asm __volatile("lfence" : : : "memory");
179 __asm __volatile("" : : : "memory");
184 * cpu_sfence() ensures strong write ordering for writes issued prior
185 * to the instruction verses writes issued afterwords. Writes are
186 * ordered on intel cpus so we do not actually have to do anything.
192 __asm __volatile("sfence" : : : "memory");
194 __asm __volatile("" : : : "memory");
199 * cpu_ccfence() prevents the compiler from reordering instructions, in
200 * particular stores, relative to the current cpu. Use cpu_sfence() if
201 * you need to guarentee ordering by both the compiler and by the cpu.
203 * This also prevents the compiler from caching memory loads into local
204 * variables across the routine.
209 __asm __volatile("" : : : "memory");
214 #define HAVE_INLINE_FFS
221 * Note that gcc-2's builtin ffs would be used if we didn't declare
222 * this inline or turn off the builtin. The builtin is faster but
223 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
226 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
228 /* Actually, the above is way out of date. The builtins use cmov etc */
229 return (__builtin_ffs(mask));
233 #define HAVE_INLINE_FFSL
238 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
241 #define HAVE_INLINE_FLS
246 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
249 #define HAVE_INLINE_FLSL
254 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
262 __asm __volatile("hlt");
266 * The following complications are to get around gcc not having a
267 * constraint letter for the range 0..255. We still put "d" in the
268 * constraint because "i" isn't a valid constraint when the port
269 * isn't constant. This only matters for -O0 because otherwise
270 * the non-working version gets optimized away.
272 * Use an expression-statement instead of a conditional expression
273 * because gcc-2.6.0 would promote the operands of the conditional
274 * and produce poor code for "if ((inb(var) & const1) == const2)".
276 * The unnecessary test `(port) < 0x10000' is to generate a warning if
277 * the `port' has type u_short or smaller. Such types are pessimal.
278 * This actually only works for signed types. The range check is
279 * careful to avoid generating warnings.
281 #define inb(port) __extension__ ({ \
283 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
284 && (port) < 0x10000) \
285 _data = inbc(port); \
287 _data = inbv(port); \
290 #define outb(port, data) ( \
291 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
292 && (port) < 0x10000 \
293 ? outbc(port, data) : outbv(port, data))
295 static __inline u_char
300 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
305 outbc(u_int port, u_char data)
307 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
310 static __inline u_char
315 * We use %%dx and not %1 here because i/o is done at %dx and not at
316 * %edx, while gcc generates inferior code (movw instead of movl)
317 * if we tell it to load (u_short) port.
319 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
323 static __inline u_int
328 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
333 insb(u_int port, void *addr, size_t cnt)
335 __asm __volatile("cld; rep; insb"
336 : "+D" (addr), "+c" (cnt)
342 insw(u_int port, void *addr, size_t cnt)
344 __asm __volatile("cld; rep; insw"
345 : "+D" (addr), "+c" (cnt)
351 insl(u_int port, void *addr, size_t cnt)
353 __asm __volatile("cld; rep; insl"
354 : "+D" (addr), "+c" (cnt)
362 __asm __volatile("invd");
368 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
369 * will cause the invl*() functions to be equivalent to the cpu_invl*()
373 void smp_invltlb(void);
375 #define smp_invltlb()
378 #ifndef _CPU_INVLPG_DEFINED
381 * Invalidate a patricular VA on this cpu only
384 cpu_invlpg(void *addr)
386 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
393 static __inline u_short
398 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
402 static __inline u_int
403 loadandclear(volatile u_int *addr)
407 __asm __volatile("xorl %0,%0; xchgl %1,%0"
408 : "=&r" (result) : "m" (*addr));
413 outbv(u_int port, u_char data)
417 * Use an unnecessary assignment to help gcc's register allocator.
418 * This make a large difference for gcc-1.40 and a tiny difference
419 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
420 * best results. gcc-2.6.0 can't handle this.
423 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
427 outl(u_int port, u_int data)
430 * outl() and outw() aren't used much so we haven't looked at
431 * possible micro-optimizations such as the unnecessary
432 * assignment for them.
434 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
438 outsb(u_int port, const void *addr, size_t cnt)
440 __asm __volatile("cld; rep; outsb"
441 : "+S" (addr), "+c" (cnt)
446 outsw(u_int port, const void *addr, size_t cnt)
448 __asm __volatile("cld; rep; outsw"
449 : "+S" (addr), "+c" (cnt)
454 outsl(u_int port, const void *addr, size_t cnt)
456 __asm __volatile("cld; rep; outsl"
457 : "+S" (addr), "+c" (cnt)
462 outw(u_int port, u_short data)
464 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
470 __asm __volatile("pause");
473 static __inline u_long
478 __asm __volatile("pushfq; popq %0" : "=r" (rf));
482 static __inline u_int64_t
487 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
488 return (low | ((u_int64_t)high << 32));
491 static __inline u_int64_t
496 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
497 return (low | ((u_int64_t)high << 32));
500 #define _RDTSC_SUPPORTED_
502 static __inline u_int64_t
507 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
508 return (low | ((u_int64_t)high << 32));
514 __asm __volatile("wbinvd");
518 write_rflags(u_long rf)
520 __asm __volatile("pushq %0; popfq" : : "r" (rf));
524 wrmsr(u_int msr, u_int64_t newval)
530 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
534 load_cr0(u_long data)
537 __asm __volatile("movq %0,%%cr0" : : "r" (data));
540 static __inline u_long
545 __asm __volatile("movq %%cr0,%0" : "=r" (data));
549 static __inline u_long
554 __asm __volatile("movq %%cr2,%0" : "=r" (data));
559 load_cr3(u_long data)
562 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
565 static __inline u_long
570 __asm __volatile("movq %%cr3,%0" : "=r" (data));
575 load_cr4(u_long data)
577 __asm __volatile("movq %0,%%cr4" : : "r" (data));
580 static __inline u_long
585 __asm __volatile("movq %%cr4,%0" : "=r" (data));
590 * Global TLB flush (except for thise for pages marked PG_G)
600 * TLB flush for an individual page (even if it has PG_G).
601 * Only works on 486+ CPUs (i386 does not have PG_G).
607 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
610 static __inline u_int
614 __asm __volatile("movl %%fs,%0" : "=rm" (sel));
618 static __inline u_int
622 __asm __volatile("movl %%gs,%0" : "=rm" (sel));
629 __asm __volatile("movl %0,%%ds" : : "rm" (sel));
635 __asm __volatile("movl %0,%%es" : : "rm" (sel));
639 /* This is defined in <machine/specialreg.h> but is too painful to get to */
641 #define MSR_FSBASE 0xc0000100
646 /* Preserve the fsbase value across the selector load */
647 __asm __volatile("rdmsr; movl %0,%%fs; wrmsr"
648 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
652 #define MSR_GSBASE 0xc0000101
658 * Preserve the gsbase value across the selector load.
659 * Note that we have to disable interrupts because the gsbase
660 * being trashed happens to be the kernel gsbase at the time.
662 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
663 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
666 /* Usable by userland */
670 __asm __volatile("movl %0,%%fs" : : "rm" (sel));
676 __asm __volatile("movl %0,%%gs" : : "rm" (sel));
680 /* void lidt(struct region_descriptor *addr); */
682 lidt(struct region_descriptor *addr)
684 __asm __volatile("lidt (%0)" : : "r" (addr));
687 /* void lldt(u_short sel); */
691 __asm __volatile("lldt %0" : : "r" (sel));
694 /* void ltr(u_short sel); */
698 __asm __volatile("ltr %0" : : "r" (sel));
701 static __inline u_int64_t
705 __asm __volatile("movq %%dr0,%0" : "=r" (data));
710 load_dr0(u_int64_t dr0)
712 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
715 static __inline u_int64_t
719 __asm __volatile("movq %%dr1,%0" : "=r" (data));
724 load_dr1(u_int64_t dr1)
726 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
729 static __inline u_int64_t
733 __asm __volatile("movq %%dr2,%0" : "=r" (data));
738 load_dr2(u_int64_t dr2)
740 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
743 static __inline u_int64_t
747 __asm __volatile("movq %%dr3,%0" : "=r" (data));
752 load_dr3(u_int64_t dr3)
754 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
757 static __inline u_int64_t
761 __asm __volatile("movq %%dr4,%0" : "=r" (data));
766 load_dr4(u_int64_t dr4)
768 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
771 static __inline u_int64_t
775 __asm __volatile("movq %%dr5,%0" : "=r" (data));
780 load_dr5(u_int64_t dr5)
782 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
785 static __inline u_int64_t
789 __asm __volatile("movq %%dr6,%0" : "=r" (data));
794 load_dr6(u_int64_t dr6)
796 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
799 static __inline u_int64_t
803 __asm __volatile("movq %%dr7,%0" : "=r" (data));
808 load_dr7(u_int64_t dr7)
810 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
813 static __inline register_t
818 rflags = read_rflags();
824 intr_restore(register_t rflags)
826 write_rflags(rflags);
829 #else /* !__GNUC__ */
831 int breakpoint(void);
832 void cpu_pause(void);
833 u_int bsfl(u_int mask);
834 u_int bsrl(u_int mask);
835 void cpu_disable_intr(void);
836 void cpu_enable_intr(void);
837 void cpu_invlpg(u_long addr);
838 void cpu_invlpg_range(u_long start, u_long end);
839 void do_cpuid(u_int ax, u_int *p);
841 u_char inb(u_int port);
842 u_int inl(u_int port);
843 void insb(u_int port, void *addr, size_t cnt);
844 void insl(u_int port, void *addr, size_t cnt);
845 void insw(u_int port, void *addr, size_t cnt);
847 void invlpg(u_int addr);
848 void invlpg_range(u_int start, u_int end);
849 void cpu_invltlb(void);
850 u_short inw(u_int port);
851 void load_cr0(u_int cr0);
852 void load_cr3(u_int cr3);
853 void load_cr4(u_int cr4);
854 void load_fs(u_int sel);
855 void load_gs(u_int sel);
856 struct region_descriptor;
857 void lidt(struct region_descriptor *addr);
858 void lldt(u_short sel);
859 void ltr(u_short sel);
860 void outb(u_int port, u_char data);
861 void outl(u_int port, u_int data);
862 void outsb(u_int port, void *addr, size_t cnt);
863 void outsl(u_int port, void *addr, size_t cnt);
864 void outsw(u_int port, void *addr, size_t cnt);
865 void outw(u_int port, u_short data);
866 void ia32_pause(void);
873 u_int64_t rdmsr(u_int msr);
874 u_int64_t rdpmc(u_int pmc);
875 u_int64_t rdtsc(void);
876 u_int read_rflags(void);
878 void write_rflags(u_int rf);
879 void wrmsr(u_int msr, u_int64_t newval);
880 u_int64_t rdr0(void);
881 void load_dr0(u_int64_t dr0);
882 u_int64_t rdr1(void);
883 void load_dr1(u_int64_t dr1);
884 u_int64_t rdr2(void);
885 void load_dr2(u_int64_t dr2);
886 u_int64_t rdr3(void);
887 void load_dr3(u_int64_t dr3);
888 u_int64_t rdr4(void);
889 void load_dr4(u_int64_t dr4);
890 u_int64_t rdr5(void);
891 void load_dr5(u_int64_t dr5);
892 u_int64_t rdr6(void);
893 void load_dr6(u_int64_t dr6);
894 u_int64_t rdr7(void);
895 void load_dr7(u_int64_t dr7);
896 register_t intr_disable(void);
897 void intr_restore(register_t rf);
899 #endif /* __GNUC__ */
901 void reset_dbregs(void);
905 #endif /* !_CPU_CPUFUNC_H_ */