2c05c3f0e72699e30e3b8d21b61b9a90d2f5923f
[dragonfly.git] / sys / dev / netif / bge / if_bge.c
1 /*
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34  */
35
36 /*
37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
38  * 
39  * Written by Bill Paul <wpaul@windriver.com>
40  * Senior Engineer, Wind River Systems
41  */
42
43 /*
44  * The Broadcom BCM5700 is based on technology originally developed by
45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49  * frames, highly configurable RX filtering, and 16 RX and TX queues
50  * (which, along with RX filter rules, can be used for QOS applications).
51  * Other features, such as TCP segmentation, may be available as part
52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53  * firmware images can be stored in hardware and need not be compiled
54  * into the driver.
55  *
56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
58  * 
59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61  * does not support external SSRAM.
62  *
63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
64  * brand name, which is functionally similar but lacks PCI-X support.
65  *
66  * Without external SSRAM, you can only have at most 4 TX rings,
67  * and the use of the mini RX ring is disabled. This seems to imply
68  * that these features are simply not available on the BCM5701. As a
69  * result, this driver does not implement any support for the mini RX
70  * ring.
71  */
72
73 #include "opt_polling.h"
74
75 #include <sys/param.h>
76 #include <sys/bus.h>
77 #include <sys/endian.h>
78 #include <sys/kernel.h>
79 #include <sys/ktr.h>
80 #include <sys/interrupt.h>
81 #include <sys/mbuf.h>
82 #include <sys/malloc.h>
83 #include <sys/queue.h>
84 #include <sys/rman.h>
85 #include <sys/serialize.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
89
90 #include <net/bpf.h>
91 #include <net/ethernet.h>
92 #include <net/if.h>
93 #include <net/if_arp.h>
94 #include <net/if_dl.h>
95 #include <net/if_media.h>
96 #include <net/if_types.h>
97 #include <net/ifq_var.h>
98 #include <net/vlan/if_vlan_var.h>
99 #include <net/vlan/if_vlan_ether.h>
100
101 #include <dev/netif/mii_layer/mii.h>
102 #include <dev/netif/mii_layer/miivar.h>
103 #include <dev/netif/mii_layer/brgphyreg.h>
104
105 #include <bus/pci/pcidevs.h>
106 #include <bus/pci/pcireg.h>
107 #include <bus/pci/pcivar.h>
108
109 #include <dev/netif/bge/if_bgereg.h>
110
111 /* "device miibus" required.  See GENERIC if you get errors here. */
112 #include "miibus_if.h"
113
114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
115 #define BGE_MIN_FRAME           60
116
117 static const struct bge_type bge_devs[] = {
118         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
119                 "3COM 3C996 Gigabit Ethernet" },
120
121         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
122                 "Alteon BCM5700 Gigabit Ethernet" },
123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
124                 "Alteon BCM5701 Gigabit Ethernet" },
125
126         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
127                 "Altima AC1000 Gigabit Ethernet" },
128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
129                 "Altima AC1002 Gigabit Ethernet" },
130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
131                 "Altima AC9100 Gigabit Ethernet" },
132
133         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
134                 "Apple BCM5701 Gigabit Ethernet" },
135
136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
137                 "Broadcom BCM5700 Gigabit Ethernet" },
138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
139                 "Broadcom BCM5701 Gigabit Ethernet" },
140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
141                 "Broadcom BCM5702 Gigabit Ethernet" },
142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
143                 "Broadcom BCM5702X Gigabit Ethernet" },
144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
145                 "Broadcom BCM5702 Gigabit Ethernet" },
146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
147                 "Broadcom BCM5703 Gigabit Ethernet" },
148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
149                 "Broadcom BCM5703X Gigabit Ethernet" },
150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
151                 "Broadcom BCM5703 Gigabit Ethernet" },
152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
153                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
155                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
159                 "Broadcom BCM5705 Gigabit Ethernet" },
160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
161                 "Broadcom BCM5705F Gigabit Ethernet" },
162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
163                 "Broadcom BCM5705K Gigabit Ethernet" },
164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
165                 "Broadcom BCM5705M Gigabit Ethernet" },
166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
167                 "Broadcom BCM5705M Gigabit Ethernet" },
168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
169                 "Broadcom BCM5714C Gigabit Ethernet" },
170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
171                 "Broadcom BCM5714S Gigabit Ethernet" },
172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
173                 "Broadcom BCM5715 Gigabit Ethernet" },
174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
175                 "Broadcom BCM5715S Gigabit Ethernet" },
176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
177                 "Broadcom BCM5720 Gigabit Ethernet" },
178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
179                 "Broadcom BCM5721 Gigabit Ethernet" },
180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
181                 "Broadcom BCM5722 Gigabit Ethernet" },
182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
183                 "Broadcom BCM5723 Gigabit Ethernet" },
184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
185                 "Broadcom BCM5750 Gigabit Ethernet" },
186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
187                 "Broadcom BCM5750M Gigabit Ethernet" },
188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
189                 "Broadcom BCM5751 Gigabit Ethernet" },
190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
191                 "Broadcom BCM5751F Gigabit Ethernet" },
192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
193                 "Broadcom BCM5751M Gigabit Ethernet" },
194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
195                 "Broadcom BCM5752 Gigabit Ethernet" },
196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
197                 "Broadcom BCM5752M Gigabit Ethernet" },
198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
199                 "Broadcom BCM5753 Gigabit Ethernet" },
200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
201                 "Broadcom BCM5753F Gigabit Ethernet" },
202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
203                 "Broadcom BCM5753M Gigabit Ethernet" },
204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
205                 "Broadcom BCM5754 Gigabit Ethernet" },
206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
207                 "Broadcom BCM5754M Gigabit Ethernet" },
208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
209                 "Broadcom BCM5755 Gigabit Ethernet" },
210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
211                 "Broadcom BCM5755M Gigabit Ethernet" },
212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
213                 "Broadcom BCM5756 Gigabit Ethernet" },
214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
215                 "Broadcom BCM5761 Gigabit Ethernet" },
216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
217                 "Broadcom BCM5761E Gigabit Ethernet" },
218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
219                 "Broadcom BCM5761S Gigabit Ethernet" },
220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
221                 "Broadcom BCM5761SE Gigabit Ethernet" },
222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
223                 "Broadcom BCM5764 Gigabit Ethernet" },
224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
225                 "Broadcom BCM5780 Gigabit Ethernet" },
226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
227                 "Broadcom BCM5780S Gigabit Ethernet" },
228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
229                 "Broadcom BCM5781 Gigabit Ethernet" },
230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
231                 "Broadcom BCM5782 Gigabit Ethernet" },
232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
233                 "Broadcom BCM5784 Gigabit Ethernet" },
234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
235                 "Broadcom BCM5785F Gigabit Ethernet" },
236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
237                 "Broadcom BCM5785G Gigabit Ethernet" },
238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
239                 "Broadcom BCM5786 Gigabit Ethernet" },
240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
241                 "Broadcom BCM5787 Gigabit Ethernet" },
242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
243                 "Broadcom BCM5787F Gigabit Ethernet" },
244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
245                 "Broadcom BCM5787M Gigabit Ethernet" },
246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
247                 "Broadcom BCM5788 Gigabit Ethernet" },
248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
249                 "Broadcom BCM5789 Gigabit Ethernet" },
250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
251                 "Broadcom BCM5901 Fast Ethernet" },
252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
253                 "Broadcom BCM5901A2 Fast Ethernet" },
254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
255                 "Broadcom BCM5903M Fast Ethernet" },
256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
257                 "Broadcom BCM5906 Fast Ethernet"},
258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
259                 "Broadcom BCM5906M Fast Ethernet"},
260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
261                 "Broadcom BCM57760 Gigabit Ethernet"},
262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
263                 "Broadcom BCM57780 Gigabit Ethernet"},
264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
265                 "Broadcom BCM57788 Gigabit Ethernet"},
266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
267                 "Broadcom BCM57790 Gigabit Ethernet"},
268         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
269                 "SysKonnect Gigabit Ethernet" },
270
271         { 0, 0, NULL }
272 };
273
274 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
275 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
276 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
277 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
278 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
279 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
280 #define BGE_IS_5788(sc)                 ((sc)->bge_flags & BGE_FLAG_5788)
281
282 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
283
284 static int      bge_probe(device_t);
285 static int      bge_attach(device_t);
286 static int      bge_detach(device_t);
287 static void     bge_txeof(struct bge_softc *, uint16_t);
288 static void     bge_rxeof(struct bge_softc *, uint16_t);
289
290 static void     bge_tick(void *);
291 static void     bge_stats_update(struct bge_softc *);
292 static void     bge_stats_update_regs(struct bge_softc *);
293 static struct mbuf *
294                 bge_defrag_shortdma(struct mbuf *);
295 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
296
297 #ifdef DEVICE_POLLING
298 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
299 #endif
300 static void     bge_intr(void *);
301 static void     bge_intr_status_tag(void *);
302 static void     bge_enable_intr(struct bge_softc *);
303 static void     bge_disable_intr(struct bge_softc *);
304 static void     bge_start(struct ifnet *);
305 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
306 static void     bge_init(void *);
307 static void     bge_stop(struct bge_softc *);
308 static void     bge_watchdog(struct ifnet *);
309 static void     bge_shutdown(device_t);
310 static int      bge_suspend(device_t);
311 static int      bge_resume(device_t);
312 static int      bge_ifmedia_upd(struct ifnet *);
313 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
314
315 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
316 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
317
318 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
319 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
320
321 static void     bge_setmulti(struct bge_softc *);
322 static void     bge_setpromisc(struct bge_softc *);
323
324 static int      bge_alloc_jumbo_mem(struct bge_softc *);
325 static void     bge_free_jumbo_mem(struct bge_softc *);
326 static struct bge_jslot
327                 *bge_jalloc(struct bge_softc *);
328 static void     bge_jfree(void *);
329 static void     bge_jref(void *);
330 static int      bge_newbuf_std(struct bge_softc *, int, int);
331 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
332 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
333 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
334 static int      bge_init_rx_ring_std(struct bge_softc *);
335 static void     bge_free_rx_ring_std(struct bge_softc *);
336 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
337 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
338 static void     bge_free_tx_ring(struct bge_softc *);
339 static int      bge_init_tx_ring(struct bge_softc *);
340
341 static int      bge_chipinit(struct bge_softc *);
342 static int      bge_blockinit(struct bge_softc *);
343 static void     bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
344
345 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
346 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
347 #ifdef notdef
348 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
349 #endif
350 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
351 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
352 static void     bge_writembx(struct bge_softc *, int, int);
353
354 static int      bge_miibus_readreg(device_t, int, int);
355 static int      bge_miibus_writereg(device_t, int, int, int);
356 static void     bge_miibus_statchg(device_t);
357 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
358 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
359 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
360 static void     bge_autopoll_link_upd(struct bge_softc *, uint32_t);
361
362 static void     bge_reset(struct bge_softc *);
363
364 static int      bge_dma_alloc(struct bge_softc *);
365 static void     bge_dma_free(struct bge_softc *);
366 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
367                                     bus_dma_tag_t *, bus_dmamap_t *,
368                                     void **, bus_addr_t *);
369 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
370
371 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
372 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
373 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
374 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
375
376 static void     bge_coal_change(struct bge_softc *);
377 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
378 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
379 static int      bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
380 static int      bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
381 static int      bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
382 static int      bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
383 static int      bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
384 static int      bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
385 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
386
387 /*
388  * Set following tunable to 1 for some IBM blade servers with the DNLK
389  * switch module. Auto negotiation is broken for those configurations.
390  */
391 static int      bge_fake_autoneg = 0;
392 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
393
394 #if !defined(KTR_IF_BGE)
395 #define KTR_IF_BGE      KTR_ALL
396 #endif
397 KTR_INFO_MASTER(if_bge);
398 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
399 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
400 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
401 #define logif(name)     KTR_LOG(if_bge_ ## name)
402
403 static device_method_t bge_methods[] = {
404         /* Device interface */
405         DEVMETHOD(device_probe,         bge_probe),
406         DEVMETHOD(device_attach,        bge_attach),
407         DEVMETHOD(device_detach,        bge_detach),
408         DEVMETHOD(device_shutdown,      bge_shutdown),
409         DEVMETHOD(device_suspend,       bge_suspend),
410         DEVMETHOD(device_resume,        bge_resume),
411
412         /* bus interface */
413         DEVMETHOD(bus_print_child,      bus_generic_print_child),
414         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
415
416         /* MII interface */
417         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
418         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
419         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
420
421         { 0, 0 }
422 };
423
424 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
425 static devclass_t bge_devclass;
426
427 DECLARE_DUMMY_MODULE(if_bge);
428 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
429 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
430
431 static uint32_t
432 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
433 {
434         device_t dev = sc->bge_dev;
435         uint32_t val;
436
437         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
438             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
439                 return 0;
440
441         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
442         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
443         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
444         return (val);
445 }
446
447 static void
448 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
449 {
450         device_t dev = sc->bge_dev;
451
452         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
453             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
454                 return;
455
456         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
457         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
458         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
459 }
460
461 #ifdef notdef
462 static uint32_t
463 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
464 {
465         device_t dev = sc->bge_dev;
466
467         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
468         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
469 }
470 #endif
471
472 static void
473 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
474 {
475         device_t dev = sc->bge_dev;
476
477         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
478         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
479 }
480
481 static void
482 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
483 {
484         CSR_WRITE_4(sc, off, val);
485 }
486
487 static void
488 bge_writembx(struct bge_softc *sc, int off, int val)
489 {
490         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
491                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
492
493         CSR_WRITE_4(sc, off, val);
494         if (sc->bge_mbox_reorder)
495                 CSR_READ_4(sc, off);
496 }
497
498 static uint8_t
499 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
500 {
501         uint32_t access, byte = 0;
502         int i;
503
504         /* Lock. */
505         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
506         for (i = 0; i < 8000; i++) {
507                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
508                         break;
509                 DELAY(20);
510         }
511         if (i == 8000)
512                 return (1);
513
514         /* Enable access. */
515         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
516         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
517
518         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
519         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
520         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
521                 DELAY(10);
522                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
523                         DELAY(10);
524                         break;
525                 }
526         }
527
528         if (i == BGE_TIMEOUT * 10) {
529                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
530                 return (1);
531         }
532
533         /* Get result. */
534         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
535
536         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
537
538         /* Disable access. */
539         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
540
541         /* Unlock. */
542         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
543         CSR_READ_4(sc, BGE_NVRAM_SWARB);
544
545         return (0);
546 }
547
548 /*
549  * Read a sequence of bytes from NVRAM.
550  */
551 static int
552 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
553 {
554         int err = 0, i;
555         uint8_t byte = 0;
556
557         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
558                 return (1);
559
560         for (i = 0; i < cnt; i++) {
561                 err = bge_nvram_getbyte(sc, off + i, &byte);
562                 if (err)
563                         break;
564                 *(dest + i) = byte;
565         }
566
567         return (err ? 1 : 0);
568 }
569
570 /*
571  * Read a byte of data stored in the EEPROM at address 'addr.' The
572  * BCM570x supports both the traditional bitbang interface and an
573  * auto access interface for reading the EEPROM. We use the auto
574  * access method.
575  */
576 static uint8_t
577 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
578 {
579         int i;
580         uint32_t byte = 0;
581
582         /*
583          * Enable use of auto EEPROM access so we can avoid
584          * having to use the bitbang method.
585          */
586         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
587
588         /* Reset the EEPROM, load the clock period. */
589         CSR_WRITE_4(sc, BGE_EE_ADDR,
590             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
591         DELAY(20);
592
593         /* Issue the read EEPROM command. */
594         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
595
596         /* Wait for completion */
597         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
598                 DELAY(10);
599                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
600                         break;
601         }
602
603         if (i == BGE_TIMEOUT) {
604                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
605                 return(1);
606         }
607
608         /* Get result. */
609         byte = CSR_READ_4(sc, BGE_EE_DATA);
610
611         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
612
613         return(0);
614 }
615
616 /*
617  * Read a sequence of bytes from the EEPROM.
618  */
619 static int
620 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
621 {
622         size_t i;
623         int err;
624         uint8_t byte;
625
626         for (byte = 0, err = 0, i = 0; i < len; i++) {
627                 err = bge_eeprom_getbyte(sc, off + i, &byte);
628                 if (err)
629                         break;
630                 *(dest + i) = byte;
631         }
632
633         return(err ? 1 : 0);
634 }
635
636 static int
637 bge_miibus_readreg(device_t dev, int phy, int reg)
638 {
639         struct bge_softc *sc = device_get_softc(dev);
640         uint32_t val;
641         int i;
642
643         KASSERT(phy == sc->bge_phyno,
644             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
645
646         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
647         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
648                 CSR_WRITE_4(sc, BGE_MI_MODE,
649                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
650                 DELAY(80);
651         }
652
653         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
654             BGE_MIPHY(phy) | BGE_MIREG(reg));
655
656         /* Poll for the PHY register access to complete. */
657         for (i = 0; i < BGE_TIMEOUT; i++) {
658                 DELAY(10);
659                 val = CSR_READ_4(sc, BGE_MI_COMM);
660                 if ((val & BGE_MICOMM_BUSY) == 0) {
661                         DELAY(5);
662                         val = CSR_READ_4(sc, BGE_MI_COMM);
663                         break;
664                 }
665         }
666         if (i == BGE_TIMEOUT) {
667                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
668                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
669                 val = 0;
670         }
671
672         /* Restore the autopoll bit if necessary. */
673         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
674                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
675                 DELAY(80);
676         }
677
678         if (val & BGE_MICOMM_READFAIL)
679                 return 0;
680
681         return (val & 0xFFFF);
682 }
683
684 static int
685 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
686 {
687         struct bge_softc *sc = device_get_softc(dev);
688         int i;
689
690         KASSERT(phy == sc->bge_phyno,
691             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
692
693         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
694             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
695                return 0;
696
697         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
698         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
699                 CSR_WRITE_4(sc, BGE_MI_MODE,
700                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
701                 DELAY(80);
702         }
703
704         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
705             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
706
707         for (i = 0; i < BGE_TIMEOUT; i++) {
708                 DELAY(10);
709                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
710                         DELAY(5);
711                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
712                         break;
713                 }
714         }
715         if (i == BGE_TIMEOUT) {
716                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
717                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
718         }
719
720         /* Restore the autopoll bit if necessary. */
721         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
722                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
723                 DELAY(80);
724         }
725
726         return 0;
727 }
728
729 static void
730 bge_miibus_statchg(device_t dev)
731 {
732         struct bge_softc *sc;
733         struct mii_data *mii;
734
735         sc = device_get_softc(dev);
736         mii = device_get_softc(sc->bge_miibus);
737
738         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
739             (IFM_ACTIVE | IFM_AVALID)) {
740                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
741                 case IFM_10_T:
742                 case IFM_100_TX:
743                         sc->bge_link = 1;
744                         break;
745                 case IFM_1000_T:
746                 case IFM_1000_SX:
747                 case IFM_2500_SX:
748                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
749                                 sc->bge_link = 1;
750                         else
751                                 sc->bge_link = 0;
752                         break;
753                 default:
754                         sc->bge_link = 0;
755                         break;
756                 }
757         } else {
758                 sc->bge_link = 0;
759         }
760         if (sc->bge_link == 0)
761                 return;
762
763         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
764         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
765             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
766                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
767         } else {
768                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
769         }
770
771         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
772                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
773         } else {
774                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
775         }
776 }
777
778 /*
779  * Memory management for jumbo frames.
780  */
781 static int
782 bge_alloc_jumbo_mem(struct bge_softc *sc)
783 {
784         struct ifnet *ifp = &sc->arpcom.ac_if;
785         struct bge_jslot *entry;
786         uint8_t *ptr;
787         bus_addr_t paddr;
788         int i, error;
789
790         /*
791          * Create tag for jumbo mbufs.
792          * This is really a bit of a kludge. We allocate a special
793          * jumbo buffer pool which (thanks to the way our DMA
794          * memory allocation works) will consist of contiguous
795          * pages. This means that even though a jumbo buffer might
796          * be larger than a page size, we don't really need to
797          * map it into more than one DMA segment. However, the
798          * default mbuf tag will result in multi-segment mappings,
799          * so we have to create a special jumbo mbuf tag that
800          * lets us get away with mapping the jumbo buffers as
801          * a single segment. I think eventually the driver should
802          * be changed so that it uses ordinary mbufs and cluster
803          * buffers, i.e. jumbo frames can span multiple DMA
804          * descriptors. But that's a project for another day.
805          */
806
807         /*
808          * Create DMA stuffs for jumbo RX ring.
809          */
810         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
811                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
812                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
813                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
814                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
815         if (error) {
816                 if_printf(ifp, "could not create jumbo RX ring\n");
817                 return error;
818         }
819
820         /*
821          * Create DMA stuffs for jumbo buffer block.
822          */
823         error = bge_dma_block_alloc(sc, BGE_JMEM,
824                                     &sc->bge_cdata.bge_jumbo_tag,
825                                     &sc->bge_cdata.bge_jumbo_map,
826                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
827                                     &paddr);
828         if (error) {
829                 if_printf(ifp, "could not create jumbo buffer\n");
830                 return error;
831         }
832
833         SLIST_INIT(&sc->bge_jfree_listhead);
834
835         /*
836          * Now divide it up into 9K pieces and save the addresses
837          * in an array. Note that we play an evil trick here by using
838          * the first few bytes in the buffer to hold the the address
839          * of the softc structure for this interface. This is because
840          * bge_jfree() needs it, but it is called by the mbuf management
841          * code which will not pass it to us explicitly.
842          */
843         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
844                 entry = &sc->bge_cdata.bge_jslots[i];
845                 entry->bge_sc = sc;
846                 entry->bge_buf = ptr;
847                 entry->bge_paddr = paddr;
848                 entry->bge_inuse = 0;
849                 entry->bge_slot = i;
850                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
851
852                 ptr += BGE_JLEN;
853                 paddr += BGE_JLEN;
854         }
855         return 0;
856 }
857
858 static void
859 bge_free_jumbo_mem(struct bge_softc *sc)
860 {
861         /* Destroy jumbo RX ring. */
862         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
863                            sc->bge_cdata.bge_rx_jumbo_ring_map,
864                            sc->bge_ldata.bge_rx_jumbo_ring);
865
866         /* Destroy jumbo buffer block. */
867         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
868                            sc->bge_cdata.bge_jumbo_map,
869                            sc->bge_ldata.bge_jumbo_buf);
870 }
871
872 /*
873  * Allocate a jumbo buffer.
874  */
875 static struct bge_jslot *
876 bge_jalloc(struct bge_softc *sc)
877 {
878         struct bge_jslot *entry;
879
880         lwkt_serialize_enter(&sc->bge_jslot_serializer);
881         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
882         if (entry) {
883                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
884                 entry->bge_inuse = 1;
885         } else {
886                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
887         }
888         lwkt_serialize_exit(&sc->bge_jslot_serializer);
889         return(entry);
890 }
891
892 /*
893  * Adjust usage count on a jumbo buffer.
894  */
895 static void
896 bge_jref(void *arg)
897 {
898         struct bge_jslot *entry = (struct bge_jslot *)arg;
899         struct bge_softc *sc = entry->bge_sc;
900
901         if (sc == NULL)
902                 panic("bge_jref: can't find softc pointer!");
903
904         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
905                 panic("bge_jref: asked to reference buffer "
906                     "that we don't manage!");
907         } else if (entry->bge_inuse == 0) {
908                 panic("bge_jref: buffer already free!");
909         } else {
910                 atomic_add_int(&entry->bge_inuse, 1);
911         }
912 }
913
914 /*
915  * Release a jumbo buffer.
916  */
917 static void
918 bge_jfree(void *arg)
919 {
920         struct bge_jslot *entry = (struct bge_jslot *)arg;
921         struct bge_softc *sc = entry->bge_sc;
922
923         if (sc == NULL)
924                 panic("bge_jfree: can't find softc pointer!");
925
926         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
927                 panic("bge_jfree: asked to free buffer that we don't manage!");
928         } else if (entry->bge_inuse == 0) {
929                 panic("bge_jfree: buffer already free!");
930         } else {
931                 /*
932                  * Possible MP race to 0, use the serializer.  The atomic insn
933                  * is still needed for races against bge_jref().
934                  */
935                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
936                 atomic_subtract_int(&entry->bge_inuse, 1);
937                 if (entry->bge_inuse == 0) {
938                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 
939                                           entry, jslot_link);
940                 }
941                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
942         }
943 }
944
945
946 /*
947  * Intialize a standard receive ring descriptor.
948  */
949 static int
950 bge_newbuf_std(struct bge_softc *sc, int i, int init)
951 {
952         struct mbuf *m_new = NULL;
953         bus_dma_segment_t seg;
954         bus_dmamap_t map;
955         int error, nsegs;
956
957         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
958         if (m_new == NULL)
959                 return ENOBUFS;
960         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
961
962         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
963                 m_adj(m_new, ETHER_ALIGN);
964
965         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
966                         sc->bge_cdata.bge_rx_tmpmap, m_new,
967                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
968         if (error) {
969                 m_freem(m_new);
970                 return error;
971         }
972
973         if (!init) {
974                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
975                                 sc->bge_cdata.bge_rx_std_dmamap[i],
976                                 BUS_DMASYNC_POSTREAD);
977                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
978                         sc->bge_cdata.bge_rx_std_dmamap[i]);
979         }
980
981         map = sc->bge_cdata.bge_rx_tmpmap;
982         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
983         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
984
985         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
986         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
987
988         bge_setup_rxdesc_std(sc, i);
989         return 0;
990 }
991
992 static void
993 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
994 {
995         struct bge_rxchain *rc;
996         struct bge_rx_bd *r;
997
998         rc = &sc->bge_cdata.bge_rx_std_chain[i];
999         r = &sc->bge_ldata.bge_rx_std_ring[i];
1000
1001         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1002         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1003         r->bge_len = rc->bge_mbuf->m_len;
1004         r->bge_idx = i;
1005         r->bge_flags = BGE_RXBDFLAG_END;
1006 }
1007
1008 /*
1009  * Initialize a jumbo receive ring descriptor. This allocates
1010  * a jumbo buffer from the pool managed internally by the driver.
1011  */
1012 static int
1013 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
1014 {
1015         struct mbuf *m_new = NULL;
1016         struct bge_jslot *buf;
1017         bus_addr_t paddr;
1018
1019         /* Allocate the mbuf. */
1020         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1021         if (m_new == NULL)
1022                 return ENOBUFS;
1023
1024         /* Allocate the jumbo buffer */
1025         buf = bge_jalloc(sc);
1026         if (buf == NULL) {
1027                 m_freem(m_new);
1028                 return ENOBUFS;
1029         }
1030
1031         /* Attach the buffer to the mbuf. */
1032         m_new->m_ext.ext_arg = buf;
1033         m_new->m_ext.ext_buf = buf->bge_buf;
1034         m_new->m_ext.ext_free = bge_jfree;
1035         m_new->m_ext.ext_ref = bge_jref;
1036         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1037
1038         m_new->m_flags |= M_EXT;
1039
1040         m_new->m_data = m_new->m_ext.ext_buf;
1041         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1042
1043         paddr = buf->bge_paddr;
1044         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1045                 m_adj(m_new, ETHER_ALIGN);
1046                 paddr += ETHER_ALIGN;
1047         }
1048
1049         /* Save necessary information */
1050         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1051         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1052
1053         /* Set up the descriptor. */
1054         bge_setup_rxdesc_jumbo(sc, i);
1055         return 0;
1056 }
1057
1058 static void
1059 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1060 {
1061         struct bge_rx_bd *r;
1062         struct bge_rxchain *rc;
1063
1064         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1065         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1066
1067         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1068         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1069         r->bge_len = rc->bge_mbuf->m_len;
1070         r->bge_idx = i;
1071         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1072 }
1073
1074 static int
1075 bge_init_rx_ring_std(struct bge_softc *sc)
1076 {
1077         int i, error;
1078
1079         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1080                 error = bge_newbuf_std(sc, i, 1);
1081                 if (error)
1082                         return error;
1083         };
1084
1085         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1086         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1087
1088         return(0);
1089 }
1090
1091 static void
1092 bge_free_rx_ring_std(struct bge_softc *sc)
1093 {
1094         int i;
1095
1096         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1097                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1098
1099                 if (rc->bge_mbuf != NULL) {
1100                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1101                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1102                         m_freem(rc->bge_mbuf);
1103                         rc->bge_mbuf = NULL;
1104                 }
1105                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1106                     sizeof(struct bge_rx_bd));
1107         }
1108 }
1109
1110 static int
1111 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1112 {
1113         struct bge_rcb *rcb;
1114         int i, error;
1115
1116         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1117                 error = bge_newbuf_jumbo(sc, i, 1);
1118                 if (error)
1119                         return error;
1120         };
1121
1122         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1123
1124         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1125         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1126         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1127
1128         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1129
1130         return(0);
1131 }
1132
1133 static void
1134 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1135 {
1136         int i;
1137
1138         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1139                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1140
1141                 if (rc->bge_mbuf != NULL) {
1142                         m_freem(rc->bge_mbuf);
1143                         rc->bge_mbuf = NULL;
1144                 }
1145                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1146                     sizeof(struct bge_rx_bd));
1147         }
1148 }
1149
1150 static void
1151 bge_free_tx_ring(struct bge_softc *sc)
1152 {
1153         int i;
1154
1155         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1156                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1157                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1158                                           sc->bge_cdata.bge_tx_dmamap[i]);
1159                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1160                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1161                 }
1162                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1163                     sizeof(struct bge_tx_bd));
1164         }
1165 }
1166
1167 static int
1168 bge_init_tx_ring(struct bge_softc *sc)
1169 {
1170         sc->bge_txcnt = 0;
1171         sc->bge_tx_saved_considx = 0;
1172         sc->bge_tx_prodidx = 0;
1173
1174         /* Initialize transmit producer index for host-memory send ring. */
1175         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1176
1177         /* 5700 b2 errata */
1178         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1179                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1180
1181         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1182         /* 5700 b2 errata */
1183         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1184                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1185
1186         return(0);
1187 }
1188
1189 static void
1190 bge_setmulti(struct bge_softc *sc)
1191 {
1192         struct ifnet *ifp;
1193         struct ifmultiaddr *ifma;
1194         uint32_t hashes[4] = { 0, 0, 0, 0 };
1195         int h, i;
1196
1197         ifp = &sc->arpcom.ac_if;
1198
1199         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1200                 for (i = 0; i < 4; i++)
1201                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1202                 return;
1203         }
1204
1205         /* First, zot all the existing filters. */
1206         for (i = 0; i < 4; i++)
1207                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1208
1209         /* Now program new ones. */
1210         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1211                 if (ifma->ifma_addr->sa_family != AF_LINK)
1212                         continue;
1213                 h = ether_crc32_le(
1214                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1215                     ETHER_ADDR_LEN) & 0x7f;
1216                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1217         }
1218
1219         for (i = 0; i < 4; i++)
1220                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1221 }
1222
1223 /*
1224  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1225  * self-test results.
1226  */
1227 static int
1228 bge_chipinit(struct bge_softc *sc)
1229 {
1230         int i;
1231         uint32_t dma_rw_ctl;
1232         uint16_t val;
1233
1234         /* Set endian type before we access any non-PCI registers. */
1235         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1236             BGE_INIT | sc->bge_pci_miscctl, 4);
1237
1238         /* Clear the MAC control register */
1239         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1240
1241         /*
1242          * Clear the MAC statistics block in the NIC's
1243          * internal memory.
1244          */
1245         for (i = BGE_STATS_BLOCK;
1246             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1247                 BGE_MEMWIN_WRITE(sc, i, 0);
1248
1249         for (i = BGE_STATUS_BLOCK;
1250             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1251                 BGE_MEMWIN_WRITE(sc, i, 0);
1252
1253         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1254                 /*
1255                  * Fix data corruption caused by non-qword write with WB.
1256                  * Fix master abort in PCI mode.
1257                  * Fix PCI latency timer.
1258                  */
1259                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1260                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1261                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1262         }
1263
1264         /* Set up the PCI DMA control register. */
1265         if (sc->bge_flags & BGE_FLAG_PCIE) {
1266                 /* PCI Express */
1267                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1268                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1269                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1270         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1271                 /* PCI-X bus */
1272                 if (BGE_IS_5714_FAMILY(sc)) {
1273                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1274                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1275                         /* XXX magic values, Broadcom-supplied Linux driver */
1276                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1277                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | 
1278                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1279                         } else {
1280                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1281                         }
1282                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1283                         /*
1284                          * In the BCM5703, the DMA read watermark should
1285                          * be set to less than or equal to the maximum
1286                          * memory read byte count of the PCI-X command
1287                          * register.
1288                          */
1289                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1290                             (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1291                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1292                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1293                         /*
1294                          * The 5704 uses a different encoding of read/write
1295                          * watermarks.
1296                          */
1297                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1298                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1299                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1300                 } else {
1301                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1302                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1303                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1304                             (0x0F);
1305                 }
1306
1307                 /*
1308                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1309                  * for hardware bugs.
1310                  */
1311                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1312                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1313                         uint32_t tmp;
1314
1315                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1316                         if (tmp == 0x6 || tmp == 0x7)
1317                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1318                 }
1319         } else {
1320                 /* Conventional PCI bus */
1321                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1322                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1323                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1324                     (0x0F);
1325         }
1326
1327         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1328             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1329             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1330                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1331         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1332
1333         /*
1334          * Set up general mode register.
1335          */
1336         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1337             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1338             BGE_MODECTL_TX_NO_PHDR_CSUM);
1339
1340         /*
1341          * BCM5701 B5 have a bug causing data corruption when using
1342          * 64-bit DMA reads, which can be terminated early and then
1343          * completed later as 32-bit accesses, in combination with
1344          * certain bridges.
1345          */
1346         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1347             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1348                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1349
1350         /*
1351          * Disable memory write invalidate.  Apparently it is not supported
1352          * properly by these devices.
1353          */
1354         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1355
1356         /* Set the timer prescaler (always 66Mhz) */
1357         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1358
1359         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1360                 DELAY(40);      /* XXX */
1361
1362                 /* Put PHY into ready state */
1363                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1364                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1365                 DELAY(40);
1366         }
1367
1368         return(0);
1369 }
1370
1371 static int
1372 bge_blockinit(struct bge_softc *sc)
1373 {
1374         struct bge_rcb *rcb;
1375         bus_size_t vrcb;
1376         bge_hostaddr taddr;
1377         uint32_t val;
1378         int i, limit;
1379
1380         /*
1381          * Initialize the memory window pointer register so that
1382          * we can access the first 32K of internal NIC RAM. This will
1383          * allow us to set up the TX send ring RCBs and the RX return
1384          * ring RCBs, plus other things which live in NIC memory.
1385          */
1386         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1387
1388         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1389
1390         if (!BGE_IS_5705_PLUS(sc)) {
1391                 /* Configure mbuf memory pool */
1392                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1393                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1394                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1395                 else
1396                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1397
1398                 /* Configure DMA resource pool */
1399                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1400                     BGE_DMA_DESCRIPTORS);
1401                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1402         }
1403
1404         /* Configure mbuf pool watermarks */
1405         if (!BGE_IS_5705_PLUS(sc)) {
1406                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1407                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1408                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1409         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1410                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1411                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1412                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1413         } else {
1414                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1415                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1416                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1417         }
1418
1419         /* Configure DMA resource watermarks */
1420         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1421         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1422
1423         /* Enable buffer manager */
1424         CSR_WRITE_4(sc, BGE_BMAN_MODE,
1425             BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1426
1427         /* Poll for buffer manager start indication */
1428         for (i = 0; i < BGE_TIMEOUT; i++) {
1429                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1430                         break;
1431                 DELAY(10);
1432         }
1433
1434         if (i == BGE_TIMEOUT) {
1435                 if_printf(&sc->arpcom.ac_if,
1436                           "buffer manager failed to start\n");
1437                 return(ENXIO);
1438         }
1439
1440         /* Enable flow-through queues */
1441         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1442         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1443
1444         /* Wait until queue initialization is complete */
1445         for (i = 0; i < BGE_TIMEOUT; i++) {
1446                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1447                         break;
1448                 DELAY(10);
1449         }
1450
1451         if (i == BGE_TIMEOUT) {
1452                 if_printf(&sc->arpcom.ac_if,
1453                           "flow-through queue init failed\n");
1454                 return(ENXIO);
1455         }
1456
1457         /*
1458          * Summary of rings supported by the controller:
1459          *
1460          * Standard Receive Producer Ring
1461          * - This ring is used to feed receive buffers for "standard"
1462          *   sized frames (typically 1536 bytes) to the controller.
1463          *
1464          * Jumbo Receive Producer Ring
1465          * - This ring is used to feed receive buffers for jumbo sized
1466          *   frames (i.e. anything bigger than the "standard" frames)
1467          *   to the controller.
1468          *
1469          * Mini Receive Producer Ring
1470          * - This ring is used to feed receive buffers for "mini"
1471          *   sized frames to the controller.
1472          * - This feature required external memory for the controller
1473          *   but was never used in a production system.  Should always
1474          *   be disabled.
1475          *
1476          * Receive Return Ring
1477          * - After the controller has placed an incoming frame into a
1478          *   receive buffer that buffer is moved into a receive return
1479          *   ring.  The driver is then responsible to passing the
1480          *   buffer up to the stack.  Many versions of the controller
1481          *   support multiple RR rings.
1482          *
1483          * Send Ring
1484          * - This ring is used for outgoing frames.  Many versions of
1485          *   the controller support multiple send rings.
1486          */
1487
1488         /* Initialize the standard receive producer ring control block. */
1489         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1490         rcb->bge_hostaddr.bge_addr_lo =
1491             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1492         rcb->bge_hostaddr.bge_addr_hi =
1493             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1494         if (BGE_IS_5705_PLUS(sc)) {
1495                 /*
1496                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1497                  * Bits 15-2 : Reserved (should be 0)
1498                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1499                  * Bit 0     : Reserved
1500                  */
1501                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1502         } else {
1503                 /*
1504                  * Ring size is always XXX entries
1505                  * Bits 31-16: Maximum RX frame size
1506                  * Bits 15-2 : Reserved (should be 0)
1507                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1508                  * Bit 0     : Reserved
1509                  */
1510                 rcb->bge_maxlen_flags =
1511                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1512         }
1513         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1514         /* Write the standard receive producer ring control block. */
1515         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1516         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1517         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1518         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1519         /* Reset the standard receive producer ring producer index. */
1520         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1521
1522         /*
1523          * Initialize the jumbo RX producer ring control
1524          * block.  We set the 'ring disabled' bit in the
1525          * flags field until we're actually ready to start
1526          * using this ring (i.e. once we set the MTU
1527          * high enough to require it).
1528          */
1529         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1530                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1531                 /* Get the jumbo receive producer ring RCB parameters. */
1532                 rcb->bge_hostaddr.bge_addr_lo =
1533                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1534                 rcb->bge_hostaddr.bge_addr_hi =
1535                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1536                 rcb->bge_maxlen_flags =
1537                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1538                     BGE_RCB_FLAG_RING_DISABLED);
1539                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1540                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1541                     rcb->bge_hostaddr.bge_addr_hi);
1542                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1543                     rcb->bge_hostaddr.bge_addr_lo);
1544                 /* Program the jumbo receive producer ring RCB parameters. */
1545                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1546                     rcb->bge_maxlen_flags);
1547                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1548                 /* Reset the jumbo receive producer ring producer index. */
1549                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1550         }
1551
1552         /* Disable the mini receive producer ring RCB. */
1553         if (BGE_IS_5700_FAMILY(sc)) {
1554                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1555                 rcb->bge_maxlen_flags =
1556                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1557                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1558                     rcb->bge_maxlen_flags);
1559                 /* Reset the mini receive producer ring producer index. */
1560                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1561         }
1562
1563         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1564         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1565             (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1566              sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1567              sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) {
1568                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1569                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1570         }
1571
1572         /*
1573          * The BD ring replenish thresholds control how often the
1574          * hardware fetches new BD's from the producer rings in host
1575          * memory.  Setting the value too low on a busy system can
1576          * starve the hardware and recue the throughpout.
1577          *
1578          * Set the BD ring replentish thresholds. The recommended
1579          * values are 1/8th the number of descriptors allocated to
1580          * each ring.
1581          */
1582         if (BGE_IS_5705_PLUS(sc))
1583                 val = 8;
1584         else
1585                 val = BGE_STD_RX_RING_CNT / 8;
1586         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1587         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1588                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1589                     BGE_JUMBO_RX_RING_CNT/8);
1590         }
1591
1592         /*
1593          * Disable all send rings by setting the 'ring disabled' bit
1594          * in the flags field of all the TX send ring control blocks,
1595          * located in NIC memory.
1596          */
1597         if (!BGE_IS_5705_PLUS(sc)) {
1598                 /* 5700 to 5704 had 16 send rings. */
1599                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1600         } else {
1601                 limit = 1;
1602         }
1603         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1604         for (i = 0; i < limit; i++) {
1605                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1606                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1607                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1608                 vrcb += sizeof(struct bge_rcb);
1609         }
1610
1611         /* Configure send ring RCB 0 (we use only the first ring) */
1612         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1613         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1614         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1615         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1616         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1617             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1618         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1619             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1620
1621         /*
1622          * Disable all receive return rings by setting the
1623          * 'ring diabled' bit in the flags field of all the receive
1624          * return ring control blocks, located in NIC memory.
1625          */
1626         if (!BGE_IS_5705_PLUS(sc))
1627                 limit = BGE_RX_RINGS_MAX;
1628         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1629                 limit = 4;
1630         else
1631                 limit = 1;
1632         /* Disable all receive return rings. */
1633         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1634         for (i = 0; i < limit; i++) {
1635                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1636                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1637                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1638                     BGE_RCB_FLAG_RING_DISABLED);
1639                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1640                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1641                     (i * (sizeof(uint64_t))), 0);
1642                 vrcb += sizeof(struct bge_rcb);
1643         }
1644
1645         /*
1646          * Set up receive return ring 0.  Note that the NIC address
1647          * for RX return rings is 0x0.  The return rings live entirely
1648          * within the host, so the nicaddr field in the RCB isn't used.
1649          */
1650         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1651         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1652         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1653         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1654         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1655         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1656             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1657
1658         /* Set random backoff seed for TX */
1659         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1660             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1661             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1662             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1663             BGE_TX_BACKOFF_SEED_MASK);
1664
1665         /* Set inter-packet gap */
1666         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1667
1668         /*
1669          * Specify which ring to use for packets that don't match
1670          * any RX rules.
1671          */
1672         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1673
1674         /*
1675          * Configure number of RX lists. One interrupt distribution
1676          * list, sixteen active lists, one bad frames class.
1677          */
1678         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1679
1680         /* Inialize RX list placement stats mask. */
1681         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1682         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1683
1684         /* Disable host coalescing until we get it set up */
1685         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1686
1687         /* Poll to make sure it's shut down. */
1688         for (i = 0; i < BGE_TIMEOUT; i++) {
1689                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1690                         break;
1691                 DELAY(10);
1692         }
1693
1694         if (i == BGE_TIMEOUT) {
1695                 if_printf(&sc->arpcom.ac_if,
1696                           "host coalescing engine failed to idle\n");
1697                 return(ENXIO);
1698         }
1699
1700         /* Set up host coalescing defaults */
1701         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1702         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1703         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds);
1704         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds);
1705         if (!BGE_IS_5705_PLUS(sc)) {
1706                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
1707                     sc->bge_rx_coal_ticks_int);
1708                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
1709                     sc->bge_tx_coal_ticks_int);
1710         }
1711         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int);
1712         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int);
1713
1714         /* Set up address of statistics block */
1715         if (!BGE_IS_5705_PLUS(sc)) {
1716                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1717                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1718                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1719                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1720
1721                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1722                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1723                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1724         }
1725
1726         /* Set up address of status block */
1727         bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1728         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1729             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1730         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1731             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1732
1733         /*
1734          * Set up status block partail update size.
1735          *
1736          * Because only single TX ring, RX produce ring and Rx return ring
1737          * are used, ask device to update only minimum part of status block
1738          * except for BCM5700 AX/BX, whose status block partial update size
1739          * can't be configured.
1740          */
1741         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1742             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1743                 /* XXX Actually reserved on BCM5700 AX/BX */
1744                 val = BGE_STATBLKSZ_FULL;
1745         } else {
1746                 val = BGE_STATBLKSZ_32BYTE;
1747         }
1748 #if 0
1749         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
1750                 val |= 0x00000200 | 0x00000400;
1751                 if_printf(&sc->arpcom.ac_if, "enable TMR\n");
1752         }
1753 #endif
1754
1755         /* Turn on host coalescing state machine */
1756         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1757
1758         /* Turn on RX BD completion state machine and enable attentions */
1759         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1760             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1761
1762         /* Turn on RX list placement state machine */
1763         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1764
1765         /* Turn on RX list selector state machine. */
1766         if (!BGE_IS_5705_PLUS(sc))
1767                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1768
1769         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1770             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1771             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1772             BGE_MACMODE_FRMHDR_DMA_ENB;
1773
1774         if (sc->bge_flags & BGE_FLAG_TBI)
1775                 val |= BGE_PORTMODE_TBI;
1776         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1777                 val |= BGE_PORTMODE_GMII;
1778         else
1779                 val |= BGE_PORTMODE_MII;
1780
1781         /* Turn on DMA, clear stats */
1782         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1783
1784         /* Set misc. local control, enable interrupts on attentions */
1785         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1786
1787 #ifdef notdef
1788         /* Assert GPIO pins for PHY reset */
1789         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1790             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1791         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1792             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1793 #endif
1794
1795         /* Turn on DMA completion state machine */
1796         if (!BGE_IS_5705_PLUS(sc))
1797                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1798
1799         /* Turn on write DMA state machine */
1800         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1801         if (BGE_IS_5755_PLUS(sc)) {
1802                 /* Enable host coalescing bug fix. */
1803                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1804         }
1805         if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1806                 /* Request larger DMA burst size to get better performance. */
1807                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1808         }
1809         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1810         DELAY(40);
1811
1812         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1813             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1814             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1815             sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1816                 /*
1817                  * Enable fix for read DMA FIFO overruns.
1818                  * The fix is to limit the number of RX BDs
1819                  * the hardware would fetch at a fime.
1820                  */
1821                 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1822                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1823                     val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1824         }
1825
1826         /* Turn on read DMA state machine */
1827         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1828         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1829             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1830             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1831                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1832                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1833                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1834         if (sc->bge_flags & BGE_FLAG_PCIE)
1835                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1836         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1837         DELAY(40);
1838
1839         /* Turn on RX data completion state machine */
1840         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1841
1842         /* Turn on RX BD initiator state machine */
1843         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1844
1845         /* Turn on RX data and RX BD initiator state machine */
1846         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1847
1848         /* Turn on Mbuf cluster free state machine */
1849         if (!BGE_IS_5705_PLUS(sc))
1850                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1851
1852         /* Turn on send BD completion state machine */
1853         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1854
1855         /* Turn on send data completion state machine */
1856         val = BGE_SDCMODE_ENABLE;
1857         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1858                 val |= BGE_SDCMODE_CDELAY; 
1859         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1860
1861         /* Turn on send data initiator state machine */
1862         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1863
1864         /* Turn on send BD initiator state machine */
1865         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1866
1867         /* Turn on send BD selector state machine */
1868         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1869
1870         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1871         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1872             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1873
1874         /* ack/clear link change events */
1875         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1876             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1877             BGE_MACSTAT_LINK_CHANGED);
1878         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1879
1880         /*
1881          * Enable attention when the link has changed state for
1882          * devices that use auto polling.
1883          */
1884         if (sc->bge_flags & BGE_FLAG_TBI) {
1885                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1886         } else {
1887                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1888                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1889                         DELAY(80);
1890                 }
1891                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1892                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1893                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1894                             BGE_EVTENB_MI_INTERRUPT);
1895                 }
1896         }
1897
1898         /*
1899          * Clear any pending link state attention.
1900          * Otherwise some link state change events may be lost until attention
1901          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1902          * It's not necessary on newer BCM chips - perhaps enabling link
1903          * state change attentions implies clearing pending attention.
1904          */
1905         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1906             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1907             BGE_MACSTAT_LINK_CHANGED);
1908
1909         /* Enable link state change attentions. */
1910         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1911
1912         return(0);
1913 }
1914
1915 /*
1916  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1917  * against our list and return its name if we find a match. Note
1918  * that since the Broadcom controller contains VPD support, we
1919  * can get the device name string from the controller itself instead
1920  * of the compiled-in string. This is a little slow, but it guarantees
1921  * we'll always announce the right product name.
1922  */
1923 static int
1924 bge_probe(device_t dev)
1925 {
1926         const struct bge_type *t;
1927         uint16_t product, vendor;
1928
1929         product = pci_get_device(dev);
1930         vendor = pci_get_vendor(dev);
1931
1932         for (t = bge_devs; t->bge_name != NULL; t++) {
1933                 if (vendor == t->bge_vid && product == t->bge_did)
1934                         break;
1935         }
1936         if (t->bge_name == NULL)
1937                 return(ENXIO);
1938
1939         device_set_desc(dev, t->bge_name);
1940         return(0);
1941 }
1942
1943 static int
1944 bge_attach(device_t dev)
1945 {
1946         struct ifnet *ifp;
1947         struct bge_softc *sc;
1948         uint32_t hwcfg = 0, misccfg;
1949         int error = 0, rid, capmask;
1950         uint8_t ether_addr[ETHER_ADDR_LEN];
1951         uint16_t product, vendor;
1952         driver_intr_t *intr_func;
1953
1954         sc = device_get_softc(dev);
1955         sc->bge_dev = dev;
1956         callout_init(&sc->bge_stat_timer);
1957         lwkt_serialize_init(&sc->bge_jslot_serializer);
1958
1959 #ifndef BURN_BRIDGES
1960         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1961                 uint32_t irq, mem;
1962
1963                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1964                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1965
1966                 device_printf(dev, "chip is in D%d power mode "
1967                     "-- setting to D0\n", pci_get_powerstate(dev));
1968
1969                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1970
1971                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1972                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1973         }
1974 #endif  /* !BURN_BRIDGE */
1975
1976         /*
1977          * Map control/status registers.
1978          */
1979         pci_enable_busmaster(dev);
1980
1981         rid = BGE_PCI_BAR0;
1982         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1983             RF_ACTIVE);
1984
1985         if (sc->bge_res == NULL) {
1986                 device_printf(dev, "couldn't map memory\n");
1987                 return ENXIO;
1988         }
1989
1990         sc->bge_btag = rman_get_bustag(sc->bge_res);
1991         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1992
1993         /* Save various chip information */
1994         sc->bge_chipid =
1995             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1996             BGE_PCIMISCCTL_ASICREV_SHIFT;
1997         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1998                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
1999         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2000         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2001
2002         /* Save chipset family. */
2003         switch (sc->bge_asicrev) {
2004         case BGE_ASICREV_BCM5755:
2005         case BGE_ASICREV_BCM5761:
2006         case BGE_ASICREV_BCM5784:
2007         case BGE_ASICREV_BCM5785:
2008         case BGE_ASICREV_BCM5787:
2009         case BGE_ASICREV_BCM57780:
2010             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2011                 BGE_FLAG_5705_PLUS;
2012             break;
2013
2014         case BGE_ASICREV_BCM5700:
2015         case BGE_ASICREV_BCM5701:
2016         case BGE_ASICREV_BCM5703:
2017         case BGE_ASICREV_BCM5704:
2018                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2019                 break;
2020
2021         case BGE_ASICREV_BCM5714_A0:
2022         case BGE_ASICREV_BCM5780:
2023         case BGE_ASICREV_BCM5714:
2024                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2025                 /* Fall through */
2026
2027         case BGE_ASICREV_BCM5750:
2028         case BGE_ASICREV_BCM5752:
2029         case BGE_ASICREV_BCM5906:
2030                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2031                 /* Fall through */
2032
2033         case BGE_ASICREV_BCM5705:
2034                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2035                 break;
2036         }
2037
2038         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2039                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2040
2041         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2042         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2043             (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2044              misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2045                 sc->bge_flags |= BGE_FLAG_5788;
2046
2047         /* BCM5755 or higher and BCM5906 have short DMA bug. */
2048         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2049                 sc->bge_flags |= BGE_FLAG_SHORTDMA;
2050
2051         /*
2052          * Check if this is a PCI-X or PCI Express device.
2053          */
2054         if (BGE_IS_5705_PLUS(sc)) {
2055                 if (pci_is_pcie(dev)) {
2056                         sc->bge_flags |= BGE_FLAG_PCIE;
2057                         sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev);
2058                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2059                 }
2060         } else {
2061                 /*
2062                  * Check if the device is in PCI-X Mode.
2063                  * (This bit is not valid on PCI Express controllers.)
2064                  */
2065                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2066                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
2067                         sc->bge_flags |= BGE_FLAG_PCIX;
2068                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2069                         sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev,
2070                             "mbox_reorder", 0);
2071                 }
2072         }
2073         device_printf(dev, "CHIP ID 0x%08x; "
2074                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2075                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2076                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2077                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2078                         "PCI-E" : "PCI"));
2079
2080         /*
2081          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2082          * not actually a MAC controller bug but an issue with the embedded
2083          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2084          */
2085         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2086                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2087
2088         /* Identify the chips that use an CPMU. */
2089         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2090             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2091             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2092             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2093                 sc->bge_flags |= BGE_FLAG_CPMU;
2094
2095         /*
2096          * When using the BCM5701 in PCI-X mode, data corruption has
2097          * been observed in the first few bytes of some received packets.
2098          * Aligning the packet buffer in memory eliminates the corruption.
2099          * Unfortunately, this misaligns the packet payloads.  On platforms
2100          * which do not support unaligned accesses, we will realign the
2101          * payloads by copying the received packets.
2102          */
2103         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2104             (sc->bge_flags & BGE_FLAG_PCIX))
2105                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2106
2107         if (!BGE_IS_5788(sc) && sc->bge_asicrev != BGE_ASICREV_BCM5700) {
2108                 if (device_getenv_int(dev, "status_tag", 1)) {
2109                         sc->bge_flags |= BGE_FLAG_STATUS_TAG;
2110                         sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS;
2111                         if (bootverbose)
2112                                 device_printf(dev, "enable status tag\n");
2113                 }
2114         }
2115
2116         /*
2117          * Set various PHY quirk flags.
2118          */
2119         product = pci_get_device(dev);
2120         vendor = pci_get_vendor(dev);
2121
2122         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2123              sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2124             pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2125                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2126
2127         capmask = MII_CAPMASK_DEFAULT;
2128         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2129              (misccfg == 0x4000 || misccfg == 0x8000)) ||
2130             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2131              vendor == PCI_VENDOR_BROADCOM &&
2132              (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2133               product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2134               product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2135             (vendor == PCI_VENDOR_BROADCOM &&
2136              (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2137               product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2138               product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2139             product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2140             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2141                 /* 10/100 only */
2142                 capmask &= ~BMSR_EXTSTAT;
2143         }
2144
2145         sc->bge_phy_flags |= BGE_PHY_WIRESPEED;
2146         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2147             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2148              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2149               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2150             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2151                 sc->bge_phy_flags &= ~BGE_PHY_WIRESPEED;
2152
2153         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2154             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2155                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
2156
2157         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2158             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2159                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
2160
2161         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2162                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
2163
2164         if (BGE_IS_5705_PLUS(sc) &&
2165             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2166             /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2167             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2168             /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2169             sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2170                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2171                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2172                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2173                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2174                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2175                             product != PCI_PRODUCT_BROADCOM_BCM5756)
2176                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
2177                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
2178                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
2179                 } else {
2180                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
2181                 }
2182         }
2183
2184         /* Allocate interrupt */
2185         rid = 0;
2186         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2187             RF_SHAREABLE | RF_ACTIVE);
2188         if (sc->bge_irq == NULL) {
2189                 device_printf(dev, "couldn't map interrupt\n");
2190                 error = ENXIO;
2191                 goto fail;
2192         }
2193
2194         /* Initialize if_name earlier, so if_printf could be used */
2195         ifp = &sc->arpcom.ac_if;
2196         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2197
2198         /* Try to reset the chip. */
2199         bge_reset(sc);
2200
2201         if (bge_chipinit(sc)) {
2202                 device_printf(dev, "chip initialization failed\n");
2203                 error = ENXIO;
2204                 goto fail;
2205         }
2206
2207         /*
2208          * Get station address
2209          */
2210         error = bge_get_eaddr(sc, ether_addr);
2211         if (error) {
2212                 device_printf(dev, "failed to read station address\n");
2213                 goto fail;
2214         }
2215
2216         /* 5705/5750 limits RX return ring to 512 entries. */
2217         if (BGE_IS_5705_PLUS(sc))
2218                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2219         else
2220                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2221
2222         error = bge_dma_alloc(sc);
2223         if (error)
2224                 goto fail;
2225
2226         /* Set default tuneable values. */
2227         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2228         sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF;
2229         sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF;
2230         sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF;
2231         sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF;
2232         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2233                 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF;
2234                 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF;
2235                 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF;
2236                 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF;
2237         } else {
2238                 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN;
2239                 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN;
2240                 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN;
2241                 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN;
2242         }
2243
2244         /* Set up ifnet structure */
2245         ifp->if_softc = sc;
2246         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2247         ifp->if_ioctl = bge_ioctl;
2248         ifp->if_start = bge_start;
2249 #ifdef DEVICE_POLLING
2250         ifp->if_poll = bge_poll;
2251 #endif
2252         ifp->if_watchdog = bge_watchdog;
2253         ifp->if_init = bge_init;
2254         ifp->if_mtu = ETHERMTU;
2255         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2256         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2257         ifq_set_ready(&ifp->if_snd);
2258
2259         /*
2260          * 5700 B0 chips do not support checksumming correctly due
2261          * to hardware bugs.
2262          */
2263         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2264                 ifp->if_capabilities |= IFCAP_HWCSUM;
2265                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2266         }
2267         ifp->if_capenable = ifp->if_capabilities;
2268
2269         /*
2270          * Figure out what sort of media we have by checking the
2271          * hardware config word in the first 32k of NIC internal memory,
2272          * or fall back to examining the EEPROM if necessary.
2273          * Note: on some BCM5700 cards, this value appears to be unset.
2274          * If that's the case, we have to rely on identifying the NIC
2275          * by its PCI subsystem ID, as we do below for the SysKonnect
2276          * SK-9D41.
2277          */
2278         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2279                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2280         } else {
2281                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2282                                     sizeof(hwcfg))) {
2283                         device_printf(dev, "failed to read EEPROM\n");
2284                         error = ENXIO;
2285                         goto fail;
2286                 }
2287                 hwcfg = ntohl(hwcfg);
2288         }
2289
2290         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2291         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2292             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2293                 if (BGE_IS_5714_FAMILY(sc))
2294                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2295                 else
2296                         sc->bge_flags |= BGE_FLAG_TBI;
2297         }
2298
2299         /* Setup MI MODE */
2300         if (sc->bge_flags & BGE_FLAG_CPMU)
2301                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2302         else
2303                 sc->bge_mi_mode = BGE_MIMODE_BASE;
2304         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) {
2305                 /* Enable auto polling for BCM570[0-5]. */
2306                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2307         }
2308
2309         /* Setup link status update stuffs */
2310         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2311             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2312                 sc->bge_link_upd = bge_bcm5700_link_upd;
2313                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2314         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2315                 sc->bge_link_upd = bge_tbi_link_upd;
2316                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2317         } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2318                 sc->bge_link_upd = bge_autopoll_link_upd;
2319                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2320         } else {
2321                 sc->bge_link_upd = bge_copper_link_upd;
2322                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2323         }
2324
2325         /*
2326          * Broadcom's own driver always assumes the internal
2327          * PHY is at GMII address 1.  On some chips, the PHY responds
2328          * to accesses at all addresses, which could cause us to
2329          * bogusly attach the PHY 32 times at probe type.  Always
2330          * restricting the lookup to address 1 is simpler than
2331          * trying to figure out which chips revisions should be
2332          * special-cased.
2333          */
2334         sc->bge_phyno = 1;
2335
2336         if (sc->bge_flags & BGE_FLAG_TBI) {
2337                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2338                     bge_ifmedia_upd, bge_ifmedia_sts);
2339                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2340                 ifmedia_add(&sc->bge_ifmedia,
2341                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2342                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2343                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2344                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2345         } else {
2346                 struct mii_probe_args mii_args;
2347
2348                 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2349                 mii_args.mii_probemask = 1 << sc->bge_phyno;
2350                 mii_args.mii_capmask = capmask;
2351
2352                 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2353                 if (error) {
2354                         device_printf(dev, "MII without any PHY!\n");
2355                         goto fail;
2356                 }
2357         }
2358
2359         /*
2360          * Create sysctl nodes.
2361          */
2362         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2363         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2364                                               SYSCTL_STATIC_CHILDREN(_hw),
2365                                               OID_AUTO,
2366                                               device_get_nameunit(dev),
2367                                               CTLFLAG_RD, 0, "");
2368         if (sc->bge_sysctl_tree == NULL) {
2369                 device_printf(dev, "can't add sysctl node\n");
2370                 error = ENXIO;
2371                 goto fail;
2372         }
2373
2374         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2375                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2376                         OID_AUTO, "rx_coal_ticks",
2377                         CTLTYPE_INT | CTLFLAG_RW,
2378                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2379                         "Receive coalescing ticks (usec).");
2380         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2381                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2382                         OID_AUTO, "tx_coal_ticks",
2383                         CTLTYPE_INT | CTLFLAG_RW,
2384                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2385                         "Transmit coalescing ticks (usec).");
2386         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2387                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2388                         OID_AUTO, "rx_coal_bds",
2389                         CTLTYPE_INT | CTLFLAG_RW,
2390                         sc, 0, bge_sysctl_rx_coal_bds, "I",
2391                         "Receive max coalesced BD count.");
2392         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2393                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2394                         OID_AUTO, "tx_coal_bds",
2395                         CTLTYPE_INT | CTLFLAG_RW,
2396                         sc, 0, bge_sysctl_tx_coal_bds, "I",
2397                         "Transmit max coalesced BD count.");
2398         if (sc->bge_flags & BGE_FLAG_PCIE) {
2399                 /*
2400                  * A common design characteristic for many Broadcom
2401                  * client controllers is that they only support a
2402                  * single outstanding DMA read operation on the PCIe
2403                  * bus. This means that it will take twice as long to
2404                  * fetch a TX frame that is split into header and
2405                  * payload buffers as it does to fetch a single,
2406                  * contiguous TX frame (2 reads vs. 1 read). For these
2407                  * controllers, coalescing buffers to reduce the number
2408                  * of memory reads is effective way to get maximum
2409                  * performance(about 940Mbps).  Without collapsing TX
2410                  * buffers the maximum TCP bulk transfer performance
2411                  * is about 850Mbps. However forcing coalescing mbufs
2412                  * consumes a lot of CPU cycles, so leave it off by
2413                  * default.
2414                  */
2415                 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2416                                SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2417                                OID_AUTO, "force_defrag", CTLFLAG_RW,
2418                                &sc->bge_force_defrag, 0,
2419                                "Force defragment on TX path");
2420         }
2421         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2422                 if (!BGE_IS_5705_PLUS(sc)) {
2423                         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2424                             SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2425                             "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2426                             sc, 0, bge_sysctl_rx_coal_ticks_int, "I",
2427                             "Receive coalescing ticks "
2428                             "during interrupt (usec).");
2429                         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2430                             SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2431                             "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2432                             sc, 0, bge_sysctl_tx_coal_ticks_int, "I",
2433                             "Transmit coalescing ticks "
2434                             "during interrupt (usec).");
2435                 }
2436                 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2437                     SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2438                     "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2439                     sc, 0, bge_sysctl_rx_coal_bds_int, "I",
2440                     "Receive max coalesced BD count during interrupt.");
2441                 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2442                     SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2443                     "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2444                     sc, 0, bge_sysctl_tx_coal_bds_int, "I",
2445                     "Transmit max coalesced BD count during interrupt.");
2446         }
2447
2448         /*
2449          * Call MI attach routine.
2450          */
2451         ether_ifattach(ifp, ether_addr, NULL);
2452
2453         if (sc->bge_flags & BGE_FLAG_STATUS_TAG)
2454                 intr_func = bge_intr_status_tag;
2455         else
2456                 intr_func = bge_intr;
2457
2458         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc,
2459             &sc->bge_intrhand, ifp->if_serializer);
2460         if (error) {
2461                 ether_ifdetach(ifp);
2462                 device_printf(dev, "couldn't set up irq\n");
2463                 goto fail;
2464         }
2465
2466         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2467         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2468
2469         return(0);
2470 fail:
2471         bge_detach(dev);
2472         return(error);
2473 }
2474
2475 static int
2476 bge_detach(device_t dev)
2477 {
2478         struct bge_softc *sc = device_get_softc(dev);
2479
2480         if (device_is_attached(dev)) {
2481                 struct ifnet *ifp = &sc->arpcom.ac_if;
2482
2483                 lwkt_serialize_enter(ifp->if_serializer);
2484                 bge_stop(sc);
2485                 bge_reset(sc);
2486                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2487                 lwkt_serialize_exit(ifp->if_serializer);
2488
2489                 ether_ifdetach(ifp);
2490         }
2491
2492         if (sc->bge_flags & BGE_FLAG_TBI)
2493                 ifmedia_removeall(&sc->bge_ifmedia);
2494         if (sc->bge_miibus)
2495                 device_delete_child(dev, sc->bge_miibus);
2496         bus_generic_detach(dev);
2497
2498         if (sc->bge_irq != NULL)
2499                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2500
2501         if (sc->bge_res != NULL)
2502                 bus_release_resource(dev, SYS_RES_MEMORY,
2503                     BGE_PCI_BAR0, sc->bge_res);
2504
2505         if (sc->bge_sysctl_tree != NULL)
2506                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2507
2508         bge_dma_free(sc);
2509
2510         return 0;
2511 }
2512
2513 static void
2514 bge_reset(struct bge_softc *sc)
2515 {
2516         device_t dev;
2517         uint32_t cachesize, command, pcistate, reset;
2518         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2519         int i, val = 0;
2520
2521         dev = sc->bge_dev;
2522
2523         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2524             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2525                 if (sc->bge_flags & BGE_FLAG_PCIE)
2526                         write_op = bge_writemem_direct;
2527                 else
2528                         write_op = bge_writemem_ind;
2529         } else {
2530                 write_op = bge_writereg_ind;
2531         }
2532
2533         /* Save some important PCI state. */
2534         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2535         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2536         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2537
2538         pci_write_config(dev, BGE_PCI_MISC_CTL,
2539             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2540             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2541             sc->bge_pci_miscctl, 4);
2542
2543         /* Disable fastboot on controllers that support it. */
2544         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2545             BGE_IS_5755_PLUS(sc)) {
2546                 if (bootverbose)
2547                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2548                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2549         }
2550
2551         /*
2552          * Write the magic number to SRAM at offset 0xB50.
2553          * When firmware finishes its initialization it will
2554          * write ~BGE_MAGIC_NUMBER to the same location.
2555          */
2556         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2557
2558         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2559
2560         /* XXX: Broadcom Linux driver. */
2561         if (sc->bge_flags & BGE_FLAG_PCIE) {
2562                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2563                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2564                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2565                         /* Prevent PCIE link training during global reset */
2566                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2567                         reset |= (1<<29);
2568                 }
2569         }
2570
2571         /* 
2572          * Set GPHY Power Down Override to leave GPHY
2573          * powered up in D0 uninitialized.
2574          */
2575         if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0)
2576                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2577
2578         /* Issue global reset */
2579         write_op(sc, BGE_MISC_CFG, reset);
2580
2581         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2582                 uint32_t status, ctrl;
2583
2584                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2585                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2586                     status | BGE_VCPU_STATUS_DRV_RESET);
2587                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2588                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2589                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2590         }
2591
2592         DELAY(1000);
2593
2594         /* XXX: Broadcom Linux driver. */
2595         if (sc->bge_flags & BGE_FLAG_PCIE) {
2596                 uint16_t devctl;
2597
2598                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2599                         uint32_t v;
2600
2601                         DELAY(500000); /* wait for link training to complete */
2602                         v = pci_read_config(dev, 0xc4, 4);
2603                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2604                 }
2605
2606                 /* Clear enable no snoop and disable relaxed ordering. */
2607                 devctl = pci_read_config(dev,
2608                     sc->bge_pciecap + PCIER_DEVCTRL, 2);
2609                 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2610                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL,
2611                     devctl, 2);
2612
2613                 /* Clear error status. */
2614                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS,
2615                     PCIEM_DEVSTS_CORR_ERR |
2616                     PCIEM_DEVSTS_NFATAL_ERR |
2617                     PCIEM_DEVSTS_FATAL_ERR |
2618                     PCIEM_DEVSTS_UNSUPP_REQ, 2);
2619         }
2620
2621         /* Reset some of the PCI state that got zapped by reset */
2622         pci_write_config(dev, BGE_PCI_MISC_CTL,
2623             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2624             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2625             sc->bge_pci_miscctl, 4);
2626         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2627         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2628         write_op(sc, BGE_MISC_CFG, (65 << 1));
2629
2630         /*
2631          * Disable PCI-X relaxed ordering to ensure status block update
2632          * comes first then packet buffer DMA. Otherwise driver may
2633          * read stale status block.
2634          */
2635         if (sc->bge_flags & BGE_FLAG_PCIX) {
2636                 uint16_t devctl;
2637
2638                 devctl = pci_read_config(dev,
2639                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
2640                 devctl &= ~PCIXM_COMMAND_ERO;
2641                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2642                         devctl &= ~PCIXM_COMMAND_MAX_READ;
2643                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2644                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2645                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2646                             PCIXM_COMMAND_MAX_READ);
2647                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2648                 }
2649                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2650                     devctl, 2);
2651         }
2652
2653         /* Enable memory arbiter. */
2654         if (BGE_IS_5714_FAMILY(sc)) {
2655                 uint32_t val;
2656
2657                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2658                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2659         } else {
2660                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2661         }
2662
2663         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2664                 for (i = 0; i < BGE_TIMEOUT; i++) {
2665                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2666                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2667                                 break;
2668                         DELAY(100);
2669                 }
2670                 if (i == BGE_TIMEOUT) {
2671                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2672                         return;
2673                 }
2674         } else {
2675                 /*
2676                  * Poll until we see the 1's complement of the magic number.
2677                  * This indicates that the firmware initialization
2678                  * is complete.
2679                  */
2680                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2681                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2682                         if (val == ~BGE_MAGIC_NUMBER)
2683                                 break;
2684                         DELAY(10);
2685                 }
2686                 if (i == BGE_FIRMWARE_TIMEOUT) {
2687                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2688                                   "timed out, found 0x%08x\n", val);
2689                         return;
2690                 }
2691         }
2692
2693         /*
2694          * XXX Wait for the value of the PCISTATE register to
2695          * return to its original pre-reset state. This is a
2696          * fairly good indicator of reset completion. If we don't
2697          * wait for the reset to fully complete, trying to read
2698          * from the device's non-PCI registers may yield garbage
2699          * results.
2700          */
2701         for (i = 0; i < BGE_TIMEOUT; i++) {
2702                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2703                         break;
2704                 DELAY(10);
2705         }
2706
2707         /* Fix up byte swapping */
2708         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2709             BGE_MODECTL_BYTESWAP_DATA);
2710
2711         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2712
2713         /*
2714          * The 5704 in TBI mode apparently needs some special
2715          * adjustment to insure the SERDES drive level is set
2716          * to 1.2V.
2717          */
2718         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2719             (sc->bge_flags & BGE_FLAG_TBI)) {
2720                 uint32_t serdescfg;
2721
2722                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2723                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2724                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2725         }
2726
2727         /* XXX: Broadcom Linux driver. */
2728         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2729             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2730             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
2731                 uint32_t v;
2732
2733                 /* Enable Data FIFO protection. */
2734                 v = CSR_READ_4(sc, 0x7c00);
2735                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2736         }
2737
2738         DELAY(10000);
2739 }
2740
2741 /*
2742  * Frame reception handling. This is called if there's a frame
2743  * on the receive return list.
2744  *
2745  * Note: we have to be able to handle two possibilities here:
2746  * 1) the frame is from the jumbo recieve ring
2747  * 2) the frame is from the standard receive ring
2748  */
2749
2750 static void
2751 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod)
2752 {
2753         struct ifnet *ifp;
2754         int stdcnt = 0, jumbocnt = 0;
2755
2756         ifp = &sc->arpcom.ac_if;
2757
2758         while (sc->bge_rx_saved_considx != rx_prod) {
2759                 struct bge_rx_bd        *cur_rx;
2760                 uint32_t                rxidx;
2761                 struct mbuf             *m = NULL;
2762                 uint16_t                vlan_tag = 0;
2763                 int                     have_tag = 0;
2764
2765                 cur_rx =
2766             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2767
2768                 rxidx = cur_rx->bge_idx;
2769                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2770                 logif(rx_pkt);
2771
2772                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2773                         have_tag = 1;
2774                         vlan_tag = cur_rx->bge_vlan_tag;
2775                 }
2776
2777                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2778                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2779                         jumbocnt++;
2780
2781                         if (rxidx != sc->bge_jumbo) {
2782                                 ifp->if_ierrors++;
2783                                 if_printf(ifp, "sw jumbo index(%d) "
2784                                     "and hw jumbo index(%d) mismatch, drop!\n",
2785                                     sc->bge_jumbo, rxidx);
2786                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2787                                 continue;
2788                         }
2789
2790                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2791                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2792                                 ifp->if_ierrors++;
2793                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2794                                 continue;
2795                         }
2796                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2797                                 ifp->if_ierrors++;
2798                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2799                                 continue;
2800                         }
2801                 } else {
2802                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2803                         stdcnt++;
2804
2805                         if (rxidx != sc->bge_std) {
2806                                 ifp->if_ierrors++;
2807                                 if_printf(ifp, "sw std index(%d) "
2808                                     "and hw std index(%d) mismatch, drop!\n",
2809                                     sc->bge_std, rxidx);
2810                                 bge_setup_rxdesc_std(sc, rxidx);
2811                                 continue;
2812                         }
2813
2814                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2815                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2816                                 ifp->if_ierrors++;
2817                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2818                                 continue;
2819                         }
2820                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2821                                 ifp->if_ierrors++;
2822                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2823                                 continue;
2824                         }
2825                 }
2826
2827                 ifp->if_ipackets++;
2828 #if !defined(__i386__) && !defined(__x86_64__)
2829                 /*
2830                  * The x86 allows unaligned accesses, but for other
2831                  * platforms we must make sure the payload is aligned.
2832                  */
2833                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2834                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2835                             cur_rx->bge_len);
2836                         m->m_data += ETHER_ALIGN;
2837                 }
2838 #endif
2839                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2840                 m->m_pkthdr.rcvif = ifp;
2841
2842                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2843                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2844                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2845                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2846                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2847                         }
2848                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2849                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2850                                 m->m_pkthdr.csum_data =
2851                                         cur_rx->bge_tcp_udp_csum;
2852                                 m->m_pkthdr.csum_flags |=
2853                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2854                         }
2855                 }
2856
2857                 /*
2858                  * If we received a packet with a vlan tag, pass it
2859                  * to vlan_input() instead of ether_input().
2860                  */
2861                 if (have_tag) {
2862                         m->m_flags |= M_VLANTAG;
2863                         m->m_pkthdr.ether_vlantag = vlan_tag;
2864                         have_tag = vlan_tag = 0;
2865                 }
2866                 ifp->if_input(ifp, m);
2867         }
2868
2869         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2870         if (stdcnt)
2871                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2872         if (jumbocnt)
2873                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2874 }
2875
2876 static void
2877 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
2878 {
2879         struct bge_tx_bd *cur_tx = NULL;
2880         struct ifnet *ifp;
2881
2882         ifp = &sc->arpcom.ac_if;
2883
2884         /*
2885          * Go through our tx ring and free mbufs for those
2886          * frames that have been sent.
2887          */
2888         while (sc->bge_tx_saved_considx != tx_cons) {
2889                 uint32_t idx = 0;
2890
2891                 idx = sc->bge_tx_saved_considx;
2892                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2893                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2894                         ifp->if_opackets++;
2895                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2896                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2897                             sc->bge_cdata.bge_tx_dmamap[idx]);
2898                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2899                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2900                 }
2901                 sc->bge_txcnt--;
2902                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2903                 logif(tx_pkt);
2904         }
2905
2906         if (cur_tx != NULL &&
2907             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2908             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2909                 ifp->if_flags &= ~IFF_OACTIVE;
2910
2911         if (sc->bge_txcnt == 0)
2912                 ifp->if_timer = 0;
2913
2914         if (!ifq_is_empty(&ifp->if_snd))
2915                 if_devstart(ifp);
2916 }
2917
2918 #ifdef DEVICE_POLLING
2919
2920 static void
2921 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2922 {
2923         struct bge_softc *sc = ifp->if_softc;
2924         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
2925         uint16_t rx_prod, tx_cons;
2926         uint32_t status;
2927
2928         switch(cmd) {
2929         case POLL_REGISTER:
2930                 bge_disable_intr(sc);
2931                 break;
2932         case POLL_DEREGISTER:
2933                 bge_enable_intr(sc);
2934                 break;
2935         case POLL_AND_CHECK_STATUS:
2936                 /*
2937                  * Process link state changes.
2938                  */
2939                 status = CSR_READ_4(sc, BGE_MAC_STS);
2940                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2941                         sc->bge_link_evt = 0;
2942                         sc->bge_link_upd(sc, status);
2943                 }
2944                 /* fall through */
2945         case POLL_ONLY:
2946                 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2947                         sc->bge_status_tag = sblk->bge_status_tag;
2948                         /*
2949                          * Use a load fence to ensure that status_tag
2950                          * is saved  before rx_prod and tx_cons.
2951                          */
2952                         cpu_lfence();
2953                 }
2954                 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2955                 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2956                 if (ifp->if_flags & IFF_RUNNING) {
2957                         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2958                         if (sc->bge_rx_saved_considx != rx_prod)
2959                                 bge_rxeof(sc, rx_prod);
2960
2961                         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2962                         if (sc->bge_tx_saved_considx != tx_cons)
2963                                 bge_txeof(sc, tx_cons);
2964                 }
2965                 break;
2966         }
2967 }
2968
2969 #endif
2970
2971 static void
2972 bge_intr(void *xsc)
2973 {
2974         struct bge_softc *sc = xsc;
2975         struct ifnet *ifp = &sc->arpcom.ac_if;
2976         uint32_t status;
2977
2978         logif(intr);
2979
2980         /*
2981          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2982          * disable interrupts by writing nonzero like we used to, since with
2983          * our current organization this just gives complications and
2984          * pessimizations for re-enabling interrupts.  We used to have races
2985          * instead of the necessary complications.  Disabling interrupts
2986          * would just reduce the chance of a status update while we are
2987          * running (by switching to the interrupt-mode coalescence
2988          * parameters), but this chance is already very low so it is more
2989          * efficient to get another interrupt than prevent it.
2990          *
2991          * We do the ack first to ensure another interrupt if there is a
2992          * status update after the ack.  We don't check for the status
2993          * changing later because it is more efficient to get another
2994          * interrupt than prevent it, not quite as above (not checking is
2995          * a smaller optimization than not toggling the interrupt enable,
2996          * since checking doesn't involve PCI accesses and toggling require
2997          * the status check).  So toggling would probably be a pessimization
2998          * even with MSI.  It would only be needed for using a task queue.
2999          */
3000         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3001
3002         /*
3003          * Process link state changes.
3004          */
3005         status = CSR_READ_4(sc, BGE_MAC_STS);
3006         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
3007                 sc->bge_link_evt = 0;
3008                 sc->bge_link_upd(sc, status);
3009         }
3010
3011         if (ifp->if_flags & IFF_RUNNING) {
3012                 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3013                 uint16_t rx_prod, tx_cons;
3014
3015                 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3016                 if (sc->bge_rx_saved_considx != rx_prod)
3017                         bge_rxeof(sc, rx_prod);
3018
3019                 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3020                 if (sc->bge_tx_saved_considx != tx_cons)
3021                         bge_txeof(sc, tx_cons);
3022         }
3023
3024         if (sc->bge_coal_chg)
3025                 bge_coal_change(sc);
3026 }
3027
3028 static void
3029 bge_intr_status_tag(void *xsc)
3030 {
3031         struct bge_softc *sc = xsc;
3032         struct ifnet *ifp = &sc->arpcom.ac_if;
3033         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3034         uint16_t rx_prod, tx_cons;
3035         uint32_t val, status;
3036
3037         if (sc->bge_status_tag == sblk->bge_status_tag) {
3038                 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3039                 if (val & BGE_PCISTAT_INTR_NOTACT)
3040                         return;
3041         }
3042
3043         /*
3044          * NOTE:
3045          * Interrupt will have to be disabled if tagged status
3046          * is used, else interrupt will always be asserted on
3047          * certain chips (at least on BCM5750 AX/BX).
3048          */
3049         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3050
3051         sc->bge_status_tag = sblk->bge_status_tag;
3052         /*
3053          * Use a load fence to ensure that status_tag is saved 
3054          * before rx_prod and tx_cons.
3055          */
3056         cpu_lfence();
3057
3058         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3059         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3060         status = sblk->bge_status;
3061
3062         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt) {
3063                 val = CSR_READ_4(sc, BGE_MAC_STS);
3064                 if ((val & sc->bge_link_chg) || sc->bge_link_evt) {
3065                         sc->bge_link_evt = 0;
3066                         sc->bge_link_upd(sc, val);
3067                 }
3068         }
3069
3070         if (ifp->if_flags & IFF_RUNNING) {
3071                 if (sc->bge_rx_saved_considx != rx_prod)
3072                         bge_rxeof(sc, rx_prod);
3073
3074                 if (sc->bge_tx_saved_considx != tx_cons)
3075                         bge_txeof(sc, tx_cons);
3076         }
3077
3078         bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
3079
3080         if (sc->bge_coal_chg)
3081                 bge_coal_change(sc);
3082 }
3083
3084 static void
3085 bge_tick(void *xsc)
3086 {
3087         struct bge_softc *sc = xsc;
3088         struct ifnet *ifp = &sc->arpcom.ac_if;
3089
3090         lwkt_serialize_enter(ifp->if_serializer);
3091
3092         if (BGE_IS_5705_PLUS(sc))
3093                 bge_stats_update_regs(sc);
3094         else
3095                 bge_stats_update(sc);
3096
3097         if (sc->bge_flags & BGE_FLAG_TBI) {
3098                 /*
3099                  * Since in TBI mode auto-polling can't be used we should poll
3100                  * link status manually. Here we register pending link event
3101                  * and trigger interrupt.
3102                  */
3103                 sc->bge_link_evt++;
3104                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3105                     BGE_IS_5788(sc))
3106                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3107                 else
3108                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3109         } else if (!sc->bge_link) {
3110                 mii_tick(device_get_softc(sc->bge_miibus));
3111         }
3112
3113         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3114
3115         lwkt_serialize_exit(ifp->if_serializer);
3116 }
3117
3118 static void
3119 bge_stats_update_regs(struct bge_softc *sc)
3120 {
3121         struct ifnet *ifp = &sc->arpcom.ac_if;
3122         struct bge_mac_stats_regs stats;
3123         uint32_t *s;
3124         int i;
3125
3126         s = (uint32_t *)&stats;
3127         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3128                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3129                 s++;
3130         }
3131
3132         ifp->if_collisions +=
3133            (stats.dot3StatsSingleCollisionFrames +
3134            stats.dot3StatsMultipleCollisionFrames +
3135            stats.dot3StatsExcessiveCollisions +
3136            stats.dot3StatsLateCollisions) -
3137            ifp->if_collisions;
3138 }
3139
3140 static void
3141 bge_stats_update(struct bge_softc *sc)
3142 {
3143         struct ifnet *ifp = &sc->arpcom.ac_if;
3144         bus_size_t stats;
3145
3146         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3147
3148 #define READ_STAT(sc, stats, stat)      \
3149         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3150
3151         ifp->if_collisions +=
3152            (READ_STAT(sc, stats,
3153                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3154             READ_STAT(sc, stats,
3155                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3156             READ_STAT(sc, stats,
3157                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3158             READ_STAT(sc, stats,
3159                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
3160            ifp->if_collisions;
3161
3162 #undef READ_STAT
3163
3164 #ifdef notdef
3165         ifp->if_collisions +=
3166            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3167            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3168            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3169            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
3170            ifp->if_collisions;
3171 #endif
3172 }
3173
3174 /*
3175  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3176  * pointers to descriptors.
3177  */
3178 static int
3179 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
3180 {
3181         struct bge_tx_bd *d = NULL;
3182         uint16_t csum_flags = 0;
3183         bus_dma_segment_t segs[BGE_NSEG_NEW];
3184         bus_dmamap_t map;
3185         int error, maxsegs, nsegs, idx, i;
3186         struct mbuf *m_head = *m_head0, *m_new;
3187
3188         if (m_head->m_pkthdr.csum_flags) {
3189                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3190                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3191                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3192                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3193                 if (m_head->m_flags & M_LASTFRAG)
3194                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3195                 else if (m_head->m_flags & M_FRAG)
3196                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3197         }
3198
3199         idx = *txidx;
3200         map = sc->bge_cdata.bge_tx_dmamap[idx];
3201
3202         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
3203         KASSERT(maxsegs >= BGE_NSEG_SPARE,
3204                 ("not enough segments %d", maxsegs));
3205
3206         if (maxsegs > BGE_NSEG_NEW)
3207                 maxsegs = BGE_NSEG_NEW;
3208
3209         /*
3210          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
3211          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
3212          * but when such padded frames employ the bge IP/TCP checksum
3213          * offload, the hardware checksum assist gives incorrect results
3214          * (possibly from incorporating its own padding into the UDP/TCP
3215          * checksum; who knows).  If we pad such runts with zeros, the
3216          * onboard checksum comes out correct.
3217          */
3218         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3219             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
3220                 error = m_devpad(m_head, BGE_MIN_FRAME);
3221                 if (error)
3222                         goto back;
3223         }
3224
3225         if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
3226                 m_new = bge_defrag_shortdma(m_head);
3227                 if (m_new == NULL) {
3228                         error = ENOBUFS;
3229                         goto back;
3230                 }
3231                 *m_head0 = m_head = m_new;
3232         }
3233         if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3234             m_head->m_next != NULL) {
3235                 /*
3236                  * Forcefully defragment mbuf chain to overcome hardware
3237                  * limitation which only support a single outstanding
3238                  * DMA read operation.  If it fails, keep moving on using
3239                  * the original mbuf chain.
3240                  */
3241                 m_new = m_defrag(m_head, MB_DONTWAIT);
3242                 if (m_new != NULL)
3243                         *m_head0 = m_head = m_new;
3244         }
3245
3246         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3247                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3248         if (error)
3249                 goto back;
3250
3251         m_head = *m_head0;
3252         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3253
3254         for (i = 0; ; i++) {
3255                 d = &sc->bge_ldata.bge_tx_ring[idx];
3256
3257                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3258                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3259                 d->bge_len = segs[i].ds_len;
3260                 d->bge_flags = csum_flags;
3261
3262                 if (i == nsegs - 1)
3263                         break;
3264                 BGE_INC(idx, BGE_TX_RING_CNT);
3265         }
3266         /* Mark the last segment as end of packet... */
3267         d->bge_flags |= BGE_TXBDFLAG_END;
3268
3269         /* Set vlan tag to the first segment of the packet. */
3270         d = &sc->bge_ldata.bge_tx_ring[*txidx];
3271         if (m_head->m_flags & M_VLANTAG) {
3272                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3273                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
3274         } else {
3275                 d->bge_vlan_tag = 0;
3276         }
3277
3278         /*
3279          * Insure that the map for this transmission is placed at
3280          * the array index of the last descriptor in this chain.
3281          */
3282         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3283         sc->bge_cdata.bge_tx_dmamap[idx] = map;
3284         sc->bge_cdata.bge_tx_chain[idx] = m_head;
3285         sc->bge_txcnt += nsegs;
3286
3287         BGE_INC(idx, BGE_TX_RING_CNT);
3288         *txidx = idx;
3289 back:
3290         if (error) {
3291                 m_freem(*m_head0);
3292                 *m_head0 = NULL;
3293         }
3294         return error;
3295 }
3296
3297 /*
3298  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3299  * to the mbuf data regions directly in the transmit descriptors.
3300  */
3301 static void
3302 bge_start(struct ifnet *ifp)
3303 {
3304         struct bge_softc *sc = ifp->if_softc;
3305         struct mbuf *m_head = NULL;
3306         uint32_t prodidx;
3307         int need_trans;
3308
3309         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3310                 return;
3311
3312         prodidx = sc->bge_tx_prodidx;
3313
3314         need_trans = 0;
3315         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3316                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3317                 if (m_head == NULL)
3318                         break;
3319
3320                 /*
3321                  * XXX
3322                  * The code inside the if() block is never reached since we
3323                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3324                  * requests to checksum TCP/UDP in a fragmented packet.
3325                  * 
3326                  * XXX
3327                  * safety overkill.  If this is a fragmented packet chain
3328                  * with delayed TCP/UDP checksums, then only encapsulate
3329                  * it if we have enough descriptors to handle the entire
3330                  * chain at once.
3331                  * (paranoia -- may not actually be needed)
3332                  */
3333                 if ((m_head->m_flags & M_FIRSTFRAG) &&
3334                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3335                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3336                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
3337                                 ifp->if_flags |= IFF_OACTIVE;
3338                                 ifq_prepend(&ifp->if_snd, m_head);
3339                                 break;
3340                         }
3341                 }
3342
3343                 /*
3344                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3345                  * descriptors of the end of the ring.  Also make
3346                  * sure there are BGE_NSEG_SPARE descriptors for
3347                  * jumbo buffers' defragmentation.
3348                  */
3349                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3350                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
3351                         ifp->if_flags |= IFF_OACTIVE;
3352                         ifq_prepend(&ifp->if_snd, m_head);
3353                         break;
3354                 }
3355
3356                 /*
3357                  * Pack the data into the transmit ring. If we
3358                  * don't have room, set the OACTIVE flag and wait
3359                  * for the NIC to drain the ring.
3360                  */
3361                 if (bge_encap(sc, &m_head, &prodidx)) {
3362                         ifp->if_flags |= IFF_OACTIVE;
3363                         ifp->if_oerrors++;
3364                         break;
3365                 }
3366                 need_trans = 1;
3367
3368                 ETHER_BPF_MTAP(ifp, m_head);
3369         }
3370
3371         if (!need_trans)
3372                 return;
3373
3374         /* Transmit */
3375         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3376         /* 5700 b2 errata */
3377         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3378                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3379
3380         sc->bge_tx_prodidx = prodidx;
3381
3382         /*
3383          * Set a timeout in case the chip goes out to lunch.
3384          */
3385         ifp->if_timer = 5;
3386 }
3387
3388 static void
3389 bge_init(void *xsc)
3390 {
3391         struct bge_softc *sc = xsc;
3392         struct ifnet *ifp = &sc->arpcom.ac_if;
3393         uint16_t *m;
3394         uint32_t mode;
3395
3396         ASSERT_SERIALIZED(ifp->if_serializer);
3397
3398         /* Cancel pending I/O and flush buffers. */
3399         bge_stop(sc);
3400         bge_reset(sc);
3401         bge_chipinit(sc);
3402
3403         /*
3404          * Init the various state machines, ring
3405          * control blocks and firmware.
3406          */
3407         if (bge_blockinit(sc)) {
3408                 if_printf(ifp, "initialization failure\n");
3409                 bge_stop(sc);
3410                 return;
3411         }
3412
3413         /* Specify MTU. */
3414         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3415             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3416
3417         /* Load our MAC address. */
3418         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3419         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3420         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3421
3422         /* Enable or disable promiscuous mode as needed. */
3423         bge_setpromisc(sc);
3424
3425         /* Program multicast filter. */
3426         bge_setmulti(sc);
3427
3428         /* Init RX ring. */
3429         if (bge_init_rx_ring_std(sc)) {
3430                 if_printf(ifp, "RX ring initialization failed\n");
3431                 bge_stop(sc);
3432                 return;
3433         }
3434
3435         /*
3436          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3437          * memory to insure that the chip has in fact read the first
3438          * entry of the ring.
3439          */
3440         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3441                 uint32_t                v, i;
3442                 for (i = 0; i < 10; i++) {
3443                         DELAY(20);
3444                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3445                         if (v == (MCLBYTES - ETHER_ALIGN))
3446                                 break;
3447                 }
3448                 if (i == 10)
3449                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3450         }
3451
3452         /* Init jumbo RX ring. */
3453         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3454                 if (bge_init_rx_ring_jumbo(sc)) {
3455                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3456                         bge_stop(sc);
3457                         return;
3458                 }
3459         }
3460
3461         /* Init our RX return ring index */
3462         sc->bge_rx_saved_considx = 0;
3463
3464         /* Init TX ring. */
3465         bge_init_tx_ring(sc);
3466
3467         /* Enable TX MAC state machine lockup fix. */
3468         mode = CSR_READ_4(sc, BGE_TX_MODE);
3469         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3470                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3471         /* Turn on transmitter */
3472         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3473
3474         /* Turn on receiver */
3475         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3476
3477         /*
3478          * Set the number of good frames to receive after RX MBUF
3479          * Low Watermark has been reached.  After the RX MAC receives
3480          * this number of frames, it will drop subsequent incoming
3481          * frames until the MBUF High Watermark is reached.
3482          */
3483         CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3484
3485         /* Tell firmware we're alive. */
3486         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3487
3488         /* Enable host interrupts if polling(4) is not enabled. */
3489         PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3490 #ifdef DEVICE_POLLING
3491         if (ifp->if_flags & IFF_POLLING)
3492                 bge_disable_intr(sc);
3493         else
3494 #endif
3495         bge_enable_intr(sc);
3496
3497         bge_ifmedia_upd(ifp);
3498
3499         ifp->if_flags |= IFF_RUNNING;
3500         ifp->if_flags &= ~IFF_OACTIVE;
3501
3502         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3503 }
3504
3505 /*
3506  * Set media options.
3507  */
3508 static int
3509 bge_ifmedia_upd(struct ifnet *ifp)
3510 {
3511         struct bge_softc *sc = ifp->if_softc;
3512
3513         /* If this is a 1000baseX NIC, enable the TBI port. */
3514         if (sc->bge_flags & BGE_FLAG_TBI) {
3515                 struct ifmedia *ifm = &sc->bge_ifmedia;
3516
3517                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3518                         return(EINVAL);
3519
3520                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3521                 case IFM_AUTO:
3522                         /*
3523                          * The BCM5704 ASIC appears to have a special
3524                          * mechanism for programming the autoneg
3525                          * advertisement registers in TBI mode.
3526                          */
3527                         if (!bge_fake_autoneg &&
3528                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3529                                 uint32_t sgdig;
3530
3531                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3532                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3533                                 sgdig |= BGE_SGDIGCFG_AUTO |
3534                                          BGE_SGDIGCFG_PAUSE_CAP |
3535                                          BGE_SGDIGCFG_ASYM_PAUSE;
3536                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3537                                             sgdig | BGE_SGDIGCFG_SEND);
3538                                 DELAY(5);
3539                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3540                         }
3541                         break;
3542                 case IFM_1000_SX:
3543                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3544                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3545                                     BGE_MACMODE_HALF_DUPLEX);
3546                         } else {
3547                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3548                                     BGE_MACMODE_HALF_DUPLEX);
3549                         }
3550                         break;
3551                 default:
3552                         return(EINVAL);
3553                 }
3554         } else {
3555                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3556
3557                 sc->bge_link_evt++;
3558                 sc->bge_link = 0;
3559                 if (mii->mii_instance) {
3560                         struct mii_softc *miisc;
3561
3562                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3563                                 mii_phy_reset(miisc);
3564                 }
3565                 mii_mediachg(mii);
3566
3567                 /*
3568                  * Force an interrupt so that we will call bge_link_upd
3569                  * if needed and clear any pending link state attention.
3570                  * Without this we are not getting any further interrupts
3571                  * for link state changes and thus will not UP the link and
3572                  * not be able to send in bge_start.  The only way to get
3573                  * things working was to receive a packet and get an RX
3574                  * intr.
3575                  *
3576                  * bge_tick should help for fiber cards and we might not
3577                  * need to do this here if BGE_FLAG_TBI is set but as
3578                  * we poll for fiber anyway it should not harm.
3579                  */
3580                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3581                     BGE_IS_5788(sc))
3582                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3583                 else
3584                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3585         }
3586         return(0);
3587 }
3588
3589 /*
3590  * Report current media status.
3591  */
3592 static void
3593 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3594 {
3595         struct bge_softc *sc = ifp->if_softc;
3596
3597         if (sc->bge_flags & BGE_FLAG_TBI) {
3598                 ifmr->ifm_status = IFM_AVALID;
3599                 ifmr->ifm_active = IFM_ETHER;
3600                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3601                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3602                         ifmr->ifm_status |= IFM_ACTIVE;
3603                 } else {
3604                         ifmr->ifm_active |= IFM_NONE;
3605                         return;
3606                 }
3607
3608                 ifmr->ifm_active |= IFM_1000_SX;
3609                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3610                         ifmr->ifm_active |= IFM_HDX;    
3611                 else
3612                         ifmr->ifm_active |= IFM_FDX;
3613         } else {
3614                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3615
3616                 mii_pollstat(mii);
3617                 ifmr->ifm_active = mii->mii_media_active;
3618                 ifmr->ifm_status = mii->mii_media_status;
3619         }
3620 }
3621
3622 static int
3623 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3624 {
3625         struct bge_softc *sc = ifp->if_softc;
3626         struct ifreq *ifr = (struct ifreq *)data;
3627         int mask, error = 0;
3628
3629         ASSERT_SERIALIZED(ifp->if_serializer);
3630
3631         switch (command) {
3632         case SIOCSIFMTU:
3633                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3634                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3635                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3636                         error = EINVAL;
3637                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3638                         ifp->if_mtu = ifr->ifr_mtu;
3639                         if (ifp->if_flags & IFF_RUNNING)
3640                                 bge_init(sc);
3641                 }
3642                 break;
3643         case SIOCSIFFLAGS:
3644                 if (ifp->if_flags & IFF_UP) {
3645                         if (ifp->if_flags & IFF_RUNNING) {
3646                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3647
3648                                 /*
3649                                  * If only the state of the PROMISC flag
3650                                  * changed, then just use the 'set promisc
3651                                  * mode' command instead of reinitializing
3652                                  * the entire NIC. Doing a full re-init
3653                                  * means reloading the firmware and waiting
3654                                  * for it to start up, which may take a
3655                                  * second or two.  Similarly for ALLMULTI.
3656                                  */
3657                                 if (mask & IFF_PROMISC)
3658                                         bge_setpromisc(sc);
3659                                 if (mask & IFF_ALLMULTI)
3660                                         bge_setmulti(sc);
3661                         } else {
3662                                 bge_init(sc);
3663                         }
3664                 } else if (ifp->if_flags & IFF_RUNNING) {
3665                         bge_stop(sc);
3666                 }
3667                 sc->bge_if_flags = ifp->if_flags;
3668                 break;
3669         case SIOCADDMULTI:
3670         case SIOCDELMULTI:
3671                 if (ifp->if_flags & IFF_RUNNING)
3672                         bge_setmulti(sc);
3673                 break;
3674         case SIOCSIFMEDIA:
3675         case SIOCGIFMEDIA:
3676                 if (sc->bge_flags & BGE_FLAG_TBI) {
3677                         error = ifmedia_ioctl(ifp, ifr,
3678                             &sc->bge_ifmedia, command);
3679                 } else {
3680                         struct mii_data *mii;
3681
3682                         mii = device_get_softc(sc->bge_miibus);
3683                         error = ifmedia_ioctl(ifp, ifr,
3684                                               &mii->mii_media, command);
3685                 }
3686                 break;
3687         case SIOCSIFCAP:
3688                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3689                 if (mask & IFCAP_HWCSUM) {
3690                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3691                         if (IFCAP_HWCSUM & ifp->if_capenable)
3692                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3693                         else
3694                                 ifp->if_hwassist = 0;
3695                 }
3696                 break;
3697         default:
3698                 error = ether_ioctl(ifp, command, data);
3699                 break;
3700         }
3701         return error;
3702 }
3703
3704 static void
3705 bge_watchdog(struct ifnet *ifp)
3706 {
3707         struct bge_softc *sc = ifp->if_softc;
3708
3709         if_printf(ifp, "watchdog timeout -- resetting\n");
3710
3711         bge_init(sc);
3712
3713         ifp->if_oerrors++;
3714
3715         if (!ifq_is_empty(&ifp->if_snd))
3716                 if_devstart(ifp);
3717 }
3718
3719 /*
3720  * Stop the adapter and free any mbufs allocated to the
3721  * RX and TX lists.
3722  */
3723 static void
3724 bge_stop(struct bge_softc *sc)
3725 {
3726         struct ifnet *ifp = &sc->arpcom.ac_if;
3727
3728         ASSERT_SERIALIZED(ifp->if_serializer);
3729
3730         callout_stop(&sc->bge_stat_timer);
3731
3732         /*
3733          * Disable all of the receiver blocks
3734          */
3735         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3736         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3737         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3738         if (BGE_IS_5700_FAMILY(sc))
3739                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3740         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3741         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3742         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3743
3744         /*
3745          * Disable all of the transmit blocks
3746          */
3747         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3748         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3749         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3750         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3751         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3752         if (BGE_IS_5700_FAMILY(sc))
3753                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3754         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3755
3756         /*
3757          * Shut down all of the memory managers and related
3758          * state machines.
3759          */
3760         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3761         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3762         if (BGE_IS_5700_FAMILY(sc))
3763                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3764         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3765         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3766         if (!BGE_IS_5705_PLUS(sc)) {
3767                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3768                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3769         }
3770
3771         /* Disable host interrupts. */
3772         bge_disable_intr(sc);
3773
3774         /*
3775          * Tell firmware we're shutting down.
3776          */
3777         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3778
3779         /* Free the RX lists. */
3780         bge_free_rx_ring_std(sc);
3781
3782         /* Free jumbo RX list. */
3783         if (BGE_IS_JUMBO_CAPABLE(sc))
3784                 bge_free_rx_ring_jumbo(sc);
3785
3786         /* Free TX buffers. */
3787         bge_free_tx_ring(sc);
3788
3789         sc->bge_status_tag = 0;
3790         sc->bge_link = 0;
3791         sc->bge_coal_chg = 0;
3792
3793         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3794
3795         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3796         ifp->if_timer = 0;
3797 }
3798
3799 /*
3800  * Stop all chip I/O so that the kernel's probe routines don't
3801  * get confused by errant DMAs when rebooting.
3802  */
3803 static void
3804 bge_shutdown(device_t dev)
3805 {
3806         struct bge_softc *sc = device_get_softc(dev);
3807         struct ifnet *ifp = &sc->arpcom.ac_if;
3808
3809         lwkt_serialize_enter(ifp->if_serializer);
3810         bge_stop(sc);
3811         bge_reset(sc);
3812         lwkt_serialize_exit(ifp->if_serializer);
3813 }
3814
3815 static int
3816 bge_suspend(device_t dev)
3817 {
3818         struct bge_softc *sc = device_get_softc(dev);
3819         struct ifnet *ifp = &sc->arpcom.ac_if;
3820
3821         lwkt_serialize_enter(ifp->if_serializer);
3822         bge_stop(sc);
3823         lwkt_serialize_exit(ifp->if_serializer);
3824
3825         return 0;
3826 }
3827
3828 static int
3829 bge_resume(device_t dev)
3830 {
3831         struct bge_softc *sc = device_get_softc(dev);
3832         struct ifnet *ifp = &sc->arpcom.ac_if;
3833
3834         lwkt_serialize_enter(ifp->if_serializer);
3835
3836         if (ifp->if_flags & IFF_UP) {
3837                 bge_init(sc);
3838
3839                 if (!ifq_is_empty(&ifp->if_snd))
3840                         if_devstart(ifp);
3841         }
3842
3843         lwkt_serialize_exit(ifp->if_serializer);
3844
3845         return 0;
3846 }
3847
3848 static void
3849 bge_setpromisc(struct bge_softc *sc)
3850 {
3851         struct ifnet *ifp = &sc->arpcom.ac_if;
3852
3853         if (ifp->if_flags & IFF_PROMISC)
3854                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3855         else
3856                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3857 }
3858
3859 static void
3860 bge_dma_free(struct bge_softc *sc)
3861 {
3862         int i;
3863
3864         /* Destroy RX mbuf DMA stuffs. */
3865         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3866                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3867                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3868                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3869                 }
3870                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3871                                    sc->bge_cdata.bge_rx_tmpmap);
3872                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3873         }
3874
3875         /* Destroy TX mbuf DMA stuffs. */
3876         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3877                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3878                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3879                             sc->bge_cdata.bge_tx_dmamap[i]);
3880                 }
3881                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3882         }
3883
3884         /* Destroy standard RX ring */
3885         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3886                            sc->bge_cdata.bge_rx_std_ring_map,
3887                            sc->bge_ldata.bge_rx_std_ring);
3888
3889         if (BGE_IS_JUMBO_CAPABLE(sc))
3890                 bge_free_jumbo_mem(sc);
3891
3892         /* Destroy RX return ring */
3893         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3894                            sc->bge_cdata.bge_rx_return_ring_map,
3895                            sc->bge_ldata.bge_rx_return_ring);
3896
3897         /* Destroy TX ring */
3898         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3899                            sc->bge_cdata.bge_tx_ring_map,
3900                            sc->bge_ldata.bge_tx_ring);
3901
3902         /* Destroy status block */
3903         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3904                            sc->bge_cdata.bge_status_map,
3905                            sc->bge_ldata.bge_status_block);
3906
3907         /* Destroy statistics block */
3908         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3909                            sc->bge_cdata.bge_stats_map,
3910                            sc->bge_ldata.bge_stats);
3911
3912         /* Destroy the parent tag */
3913         if (sc->bge_cdata.bge_parent_tag != NULL)
3914                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3915 }
3916
3917 static int
3918 bge_dma_alloc(struct bge_softc *sc)
3919 {
3920         struct ifnet *ifp = &sc->arpcom.ac_if;
3921         int i, error;
3922         bus_addr_t lowaddr;
3923
3924         lowaddr = BUS_SPACE_MAXADDR;
3925         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3926                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3927
3928         /*
3929