2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
34 #include <machine/globaldata.h>
35 #include <machine/smp.h>
36 #include <machine/cputypes.h>
37 #include <machine/md_var.h>
38 #include <machine/pmap.h>
39 #include <machine_base/apic/lapic.h>
40 #include <machine_base/apic/ioapic.h>
41 #include <machine_base/apic/ioapic_abi.h>
42 #include <machine/segments.h>
43 #include <sys/thread2.h>
45 #include <machine/intr_machdep.h>
47 #define IOAPIC_COUNT_MAX 16
48 #define IOAPIC_ID_MASK (IOAPIC_COUNT_MAX - 1)
51 extern pt_entry_t *SMPpt;
60 TAILQ_ENTRY(ioapic_info) io_link;
62 TAILQ_HEAD(ioapic_info_list, ioapic_info);
64 struct ioapic_intsrc {
66 enum intr_trigger int_trig;
67 enum intr_polarity int_pola;
71 struct ioapic_info_list ioc_list;
72 struct ioapic_intsrc ioc_intsrc[16]; /* XXX magic number */
75 static void ioapic_setup(const struct ioapic_info *);
76 static int ioapic_alloc_apic_id(int);
77 static void ioapic_set_apic_id(const struct ioapic_info *);
78 static void ioapic_gsi_setup(int);
79 static const struct ioapic_info *
80 ioapic_gsi_search(int);
81 static void ioapic_pin_prog(void *, int, int,
82 enum intr_trigger, enum intr_polarity, uint32_t);
84 static struct ioapic_conf ioapic_conf;
86 static TAILQ_HEAD(, ioapic_enumerator) ioapic_enumerators =
87 TAILQ_HEAD_INITIALIZER(ioapic_enumerators);
92 struct ioapic_info *info;
93 int start_apic_id = 0;
94 struct ioapic_enumerator *e;
98 TAILQ_INIT(&ioapic_conf.ioc_list);
99 /* XXX magic number */
100 for (i = 0; i < 16; ++i)
101 ioapic_conf.ioc_intsrc[i].int_gsi = -1;
103 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
104 error = e->ioapic_probe(e);
110 panic("can't config I/O APIC\n");
112 kprintf("no I/O APIC\n");
123 * Switch to I/O APIC MachIntrABI and reconfigure
124 * the default IDT entries.
126 MachIntrABI = MachIntrABI_IOAPIC;
127 MachIntrABI.setdefault();
129 e->ioapic_enumerate(e);
135 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
138 if (i > IOAPIC_COUNT_MAX) /* XXX magic number */
139 panic("ioapic_config: more than 16 I/O APIC\n");
144 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
147 apic_id = ioapic_alloc_apic_id(start_apic_id);
148 if (apic_id == NAPICID) {
149 kprintf("IOAPIC: can't alloc APIC ID for "
150 "%dth I/O APIC\n", info->io_idx);
153 info->io_apic_id = apic_id;
155 start_apic_id = apic_id + 1;
159 * xAPIC allows I/O APIC's APIC ID to be same
160 * as the LAPIC's APIC ID
162 kprintf("IOAPIC: use xAPIC model to alloc APIC ID "
165 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
166 info->io_apic_id = info->io_idx;
170 * Warning about any GSI holes
172 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
173 const struct ioapic_info *prev_info;
175 prev_info = TAILQ_PREV(info, ioapic_info_list, io_link);
176 if (prev_info != NULL) {
177 if (info->io_gsi_base !=
178 prev_info->io_gsi_base + prev_info->io_npin) {
179 kprintf("IOAPIC: warning gsi hole "
181 prev_info->io_gsi_base +
183 info->io_gsi_base - 1);
189 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
190 kprintf("IOAPIC: idx %d, apic id %d, "
191 "gsi base %d, npin %d\n",
202 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
204 ioapic_abi_fixup_irqmap();
208 MachIntrABI.cleanup();
214 ioapic_enumerator_register(struct ioapic_enumerator *ne)
216 struct ioapic_enumerator *e;
218 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
219 if (e->ioapic_prio < ne->ioapic_prio) {
220 TAILQ_INSERT_BEFORE(e, ne, ioapic_link);
224 TAILQ_INSERT_TAIL(&ioapic_enumerators, ne, ioapic_link);
228 ioapic_add(void *addr, int gsi_base, int npin)
230 struct ioapic_info *info, *ninfo;
233 gsi_end = gsi_base + npin - 1;
234 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
235 if ((gsi_base >= info->io_gsi_base &&
236 gsi_base < info->io_gsi_base + info->io_npin) ||
237 (gsi_end >= info->io_gsi_base &&
238 gsi_end < info->io_gsi_base + info->io_npin)) {
239 panic("ioapic_add: overlapped gsi, base %d npin %d, "
240 "hit base %d, npin %d\n", gsi_base, npin,
241 info->io_gsi_base, info->io_npin);
243 if (info->io_addr == addr)
244 panic("ioapic_add: duplicated addr %p\n", addr);
247 ninfo = kmalloc(sizeof(*ninfo), M_DEVBUF, M_WAITOK | M_ZERO);
248 ninfo->io_addr = addr;
249 ninfo->io_npin = npin;
250 ninfo->io_gsi_base = gsi_base;
251 ninfo->io_apic_id = -1;
254 * Create IOAPIC list in ascending order of GSI base
256 TAILQ_FOREACH_REVERSE(info, &ioapic_conf.ioc_list,
257 ioapic_info_list, io_link) {
258 if (ninfo->io_gsi_base > info->io_gsi_base) {
259 TAILQ_INSERT_AFTER(&ioapic_conf.ioc_list,
260 info, ninfo, io_link);
265 TAILQ_INSERT_HEAD(&ioapic_conf.ioc_list, ninfo, io_link);
269 ioapic_intsrc(int irq, int gsi, enum intr_trigger trig, enum intr_polarity pola)
271 struct ioapic_intsrc *int_src;
274 int_src = &ioapic_conf.ioc_intsrc[irq];
277 /* Don't allow mixed mode */
278 kprintf("IOAPIC: warning intsrc irq %d -> gsi 0\n", irq);
282 if (int_src->int_gsi != -1) {
283 if (int_src->int_gsi != gsi) {
284 kprintf("IOAPIC: warning intsrc irq %d, gsi "
285 "%d -> %d\n", irq, int_src->int_gsi, gsi);
287 if (int_src->int_trig != trig) {
288 kprintf("IOAPIC: warning intsrc irq %d, trig "
290 intr_str_trigger(int_src->int_trig),
291 intr_str_trigger(trig));
293 if (int_src->int_pola != pola) {
294 kprintf("IOAPIC: warning intsrc irq %d, pola "
296 intr_str_polarity(int_src->int_pola),
297 intr_str_polarity(pola));
300 int_src->int_gsi = gsi;
301 int_src->int_trig = trig;
302 int_src->int_pola = pola;
306 ioapic_set_apic_id(const struct ioapic_info *info)
311 id = ioapic_read(info->io_addr, IOAPIC_ID);
314 id |= (info->io_apic_id << 24);
316 ioapic_write(info->io_addr, IOAPIC_ID, id);
321 id = ioapic_read(info->io_addr, IOAPIC_ID);
322 apic_id = (id & APIC_ID_MASK) >> 24;
325 * I/O APIC ID is a 4bits field
327 if ((apic_id & IOAPIC_ID_MASK) !=
328 (info->io_apic_id & IOAPIC_ID_MASK)) {
329 panic("ioapic_set_apic_id: can't set apic id to %d, "
330 "currently set to %d\n", info->io_apic_id, apic_id);
335 ioapic_gsi_setup(int gsi)
337 enum intr_trigger trig;
338 enum intr_polarity pola;
344 ioapic_extpin_setup(ioapic_gsi_ioaddr(gsi),
345 ioapic_gsi_pin(gsi), 0);
350 trig = 0; /* silence older gcc's */
351 pola = 0; /* silence older gcc's */
353 for (irq = 0; irq < 16; ++irq) {
354 const struct ioapic_intsrc *int_src =
355 &ioapic_conf.ioc_intsrc[irq];
357 if (gsi == int_src->int_gsi) {
358 trig = int_src->int_trig;
359 pola = int_src->int_pola;
366 trig = INTR_TRIGGER_EDGE;
367 pola = INTR_POLARITY_HIGH;
369 trig = INTR_TRIGGER_LEVEL;
370 pola = INTR_POLARITY_LOW;
375 ioapic_abi_set_irqmap(irq, gsi, trig, pola);
379 ioapic_gsi_ioaddr(int gsi)
381 const struct ioapic_info *info;
383 info = ioapic_gsi_search(gsi);
384 return info->io_addr;
388 ioapic_gsi_pin(int gsi)
390 const struct ioapic_info *info;
392 info = ioapic_gsi_search(gsi);
393 return gsi - info->io_gsi_base;
396 static const struct ioapic_info *
397 ioapic_gsi_search(int gsi)
399 const struct ioapic_info *info;
401 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
402 if (gsi >= info->io_gsi_base &&
403 gsi < info->io_gsi_base + info->io_npin)
406 panic("ioapic_gsi_search: no I/O APIC\n");
410 ioapic_gsi(int idx, int pin)
412 const struct ioapic_info *info;
414 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
415 if (info->io_idx == idx)
420 if (pin >= info->io_npin)
422 return info->io_gsi_base + pin;
426 ioapic_extpin_setup(void *addr, int pin, int vec)
428 ioapic_pin_prog(addr, pin, vec,
429 INTR_TRIGGER_CONFORM, INTR_POLARITY_CONFORM, IOART_DELEXINT);
433 ioapic_extpin_gsi(void)
439 ioapic_pin_setup(void *addr, int pin, int vec,
440 enum intr_trigger trig, enum intr_polarity pola)
443 * Always clear an I/O APIC pin before [re]programming it. This is
444 * particularly important if the pin is set up for a level interrupt
445 * as the IOART_REM_IRR bit might be set. When we reprogram the
446 * vector any EOI from pending ints on this pin could be lost and
447 * IRR might never get reset.
449 * To fix this problem, clear the vector and make sure it is
450 * programmed as an edge interrupt. This should theoretically
451 * clear IRR so we can later, safely program it as a level
454 ioapic_pin_prog(addr, pin, vec, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH,
456 ioapic_pin_prog(addr, pin, vec, trig, pola, IOART_DELFIXED);
460 ioapic_pin_prog(void *addr, int pin, int vec,
461 enum intr_trigger trig, enum intr_polarity pola, uint32_t del_mode)
463 uint32_t flags, target;
466 KKASSERT(del_mode == IOART_DELEXINT || del_mode == IOART_DELFIXED);
468 select = IOAPIC_REDTBL0 + (2 * pin);
470 flags = ioapic_read(addr, select) & IOART_RESV;
471 flags |= IOART_INTMSET | IOART_DESTPHY;
476 * We only support limited I/O APIC mixed mode,
477 * so even for ExtINT, we still use "fixed"
480 flags |= IOART_DELFIXED;
483 if (del_mode == IOART_DELEXINT) {
484 KKASSERT(trig == INTR_TRIGGER_CONFORM &&
485 pola == INTR_POLARITY_CONFORM);
486 flags |= IOART_TRGREDG | IOART_INTAHI;
489 case INTR_TRIGGER_EDGE:
490 flags |= IOART_TRGREDG;
493 case INTR_TRIGGER_LEVEL:
494 flags |= IOART_TRGRLVL;
497 case INTR_TRIGGER_CONFORM:
498 panic("ioapic_pin_prog: trig conform is not "
502 case INTR_POLARITY_HIGH:
503 flags |= IOART_INTAHI;
506 case INTR_POLARITY_LOW:
507 flags |= IOART_INTALO;
510 case INTR_POLARITY_CONFORM:
511 panic("ioapic_pin_prog: pola conform is not "
516 target = ioapic_read(addr, select + 1) & IOART_HI_DEST_RESV;
517 target |= (CPUID_TO_APICID(0) << IOART_HI_DEST_SHIFT) &
520 ioapic_write(addr, select, flags | vec);
521 ioapic_write(addr, select + 1, target);
525 ioapic_setup(const struct ioapic_info *info)
529 ioapic_set_apic_id(info);
531 for (i = 0; i < info->io_npin; ++i)
532 ioapic_gsi_setup(info->io_gsi_base + i);
536 ioapic_alloc_apic_id(int start)
539 const struct ioapic_info *info;
540 int apic_id, apic_id16;
542 apic_id = lapic_unused_apic_id(start);
543 if (apic_id == NAPICID) {
544 kprintf("IOAPIC: can't find unused APIC ID\n");
547 apic_id16 = apic_id & IOAPIC_ID_MASK;
550 * Check against other I/O APIC's APIC ID's lower 4bits.
552 * The new APIC ID will have to be different from others
553 * in the lower 4bits, no matter whether xAPIC is used
556 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
557 if (info->io_apic_id == -1) {
561 if ((info->io_apic_id & IOAPIC_ID_MASK) == apic_id16)
567 kprintf("IOAPIC: APIC ID %d has same lower 4bits as "
568 "%dth I/O APIC, keep searching...\n",
569 apic_id, info->io_idx);
573 panic("ioapic_unused_apic_id: never reached\n");
577 ioapic_map(vm_paddr_t pa)
579 KKASSERT(pa < 0x100000000LL);
580 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);