2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <machine_base/icu/icu.h> /* IPIs */
67 #include <machine_base/isa/intr_machdep.h> /* IPIs */
69 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
71 #define WARMBOOT_TARGET 0
72 #define WARMBOOT_OFF (KERNBASE + 0x0467)
73 #define WARMBOOT_SEG (KERNBASE + 0x0469)
75 #define BIOS_BASE (0xf0000)
76 #define BIOS_SIZE (0x10000)
77 #define BIOS_COUNT (BIOS_SIZE/4)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
84 #define PROCENTRY_FLAG_EN 0x01
85 #define PROCENTRY_FLAG_BP 0x02
86 #define IOAPICENTRY_FLAG_EN 0x01
89 /* MP Floating Pointer Structure */
90 typedef struct MPFPS {
103 /* MP Configuration Table Header */
104 typedef struct MPCTH {
106 u_short base_table_length;
110 u_char product_id[12];
111 u_int32_t oem_table_pointer;
112 u_short oem_table_size;
114 u_int32_t apic_address;
115 u_short extended_table_length;
116 u_char extended_table_checksum;
121 typedef struct PROCENTRY {
126 u_int32_t cpu_signature;
127 u_int32_t feature_flags;
132 typedef struct BUSENTRY {
138 typedef struct IOAPICENTRY {
143 u_int32_t apic_address;
144 } *io_apic_entry_ptr;
146 typedef struct INTENTRY {
156 /* descriptions of MP basetable entries */
157 typedef struct BASETABLE_ENTRY {
164 * this code MUST be enabled here and in mpboot.s.
165 * it follows the very early stages of AP boot by placing values in CMOS ram.
166 * it NORMALLY will never be needed and thus the primitive method for enabling.
169 #if defined(CHECK_POINTS)
170 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
171 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
173 #define CHECK_INIT(D); \
174 CHECK_WRITE(0x34, (D)); \
175 CHECK_WRITE(0x35, (D)); \
176 CHECK_WRITE(0x36, (D)); \
177 CHECK_WRITE(0x37, (D)); \
178 CHECK_WRITE(0x38, (D)); \
179 CHECK_WRITE(0x39, (D));
181 #define CHECK_PRINT(S); \
182 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
191 #else /* CHECK_POINTS */
193 #define CHECK_INIT(D)
194 #define CHECK_PRINT(S)
196 #endif /* CHECK_POINTS */
199 * Values to send to the POST hardware.
201 #define MP_BOOTADDRESS_POST 0x10
202 #define MP_PROBE_POST 0x11
203 #define MPTABLE_PASS1_POST 0x12
205 #define MP_START_POST 0x13
206 #define MP_ENABLE_POST 0x14
207 #define MPTABLE_PASS2_POST 0x15
209 #define START_ALL_APS_POST 0x16
210 #define INSTALL_AP_TRAMP_POST 0x17
211 #define START_AP_POST 0x18
213 #define MP_ANNOUNCE_POST 0x19
215 static int need_hyperthreading_fixup;
216 static u_int logical_cpus;
217 u_int logical_cpus_mask;
219 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
220 int current_postcode;
222 /** XXX FIXME: what system files declare these??? */
223 extern struct region_descriptor r_gdt, r_idt;
225 int bsp_apic_ready = 0; /* flags useability of BSP apic */
226 int mp_naps; /* # of Applications processors */
227 int mp_nbusses; /* # of busses */
229 int mp_napics; /* # of IO APICs */
231 int boot_cpu_id; /* designated BSP */
232 vm_offset_t cpu_apic_address;
234 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
235 u_int32_t *io_apic_versions;
239 u_int32_t cpu_apic_versions[MAXCPU];
241 extern int64_t tsc_offsets[];
244 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
248 * APIC ID logical/physical mapping structures.
249 * We oversize these to simplify boot-time config.
251 int cpu_num_to_apic_id[NAPICID];
253 int io_num_to_apic_id[NAPICID];
255 int apic_id_to_logical[NAPICID];
257 /* AP uses this during bootstrap. Do not staticize. */
262 * SMP page table page. Setup by locore to point to a page table
263 * page from which we allocate per-cpu privatespace areas io_apics,
267 #define IO_MAPPING_START_INDEX \
268 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
270 extern pt_entry_t *SMPpt;
272 struct pcb stoppcbs[MAXCPU];
274 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
277 * Local data and functions.
280 static u_int boot_address;
281 static u_int base_memory;
282 static int mp_finish;
284 static mpfps_t mpfps;
285 static long search_for_sig(u_int32_t target, int count);
286 static void mp_enable(u_int boot_addr);
288 static void mptable_hyperthread_fixup(u_int id_mask);
289 static void mptable_pass1(void);
290 static int mptable_pass2(void);
291 static void default_mp_table(int type);
292 static void fix_mp_table(void);
294 static void setup_apic_irq_mapping(void);
295 static int apic_int_is_bus_type(int intr, int bus_type);
297 static int start_all_aps(u_int boot_addr);
299 static void install_ap_tramp(u_int boot_addr);
301 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
302 static int smitest(void);
304 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
305 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
306 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
307 static u_int bootMP_size;
310 * Calculate usable address in base memory for AP trampoline code.
313 mp_bootaddress(u_int basemem)
315 POSTCODE(MP_BOOTADDRESS_POST);
317 base_memory = basemem;
319 bootMP_size = mptramp_end - mptramp_start;
320 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
321 if (((basemem * 1024) - boot_address) < bootMP_size)
322 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
323 /* 3 levels of page table pages */
324 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
326 return mptramp_pagetables;
331 * Look for an Intel MP spec table (ie, SMP capable hardware).
341 * Make sure our SMPpt[] page table is big enough to hold all the
344 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
346 POSTCODE(MP_PROBE_POST);
348 /* see if EBDA exists */
349 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
350 /* search first 1K of EBDA */
351 target = (u_int32_t) (segment << 4);
352 if ((x = search_for_sig(target, 1024 / 4)) != -1L)
355 /* last 1K of base memory, effective 'top of base' passed in */
356 target = (u_int32_t) (base_memory - 0x400);
357 if ((x = search_for_sig(target, 1024 / 4)) != -1L)
361 /* search the BIOS */
362 target = (u_int32_t) BIOS_BASE;
363 if ((x = search_for_sig(target, BIOS_COUNT)) != -1L)
372 * Calculate needed resources. We can safely map physical
373 * memory into SMPpt after mptable_pass1() completes.
383 * Startup the SMP processors.
388 POSTCODE(MP_START_POST);
389 mp_enable(boot_address);
394 * Print various information about the SMP system hardware and setup.
401 POSTCODE(MP_ANNOUNCE_POST);
403 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
404 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
405 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
406 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
407 for (x = 1; x <= mp_naps; ++x) {
408 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
409 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
410 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
414 for (x = 0; x < mp_napics; ++x) {
415 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
416 kprintf(", version: 0x%08x", io_apic_versions[x]);
417 kprintf(", at 0x%08lx\n", io_apic_address[x]);
420 kprintf(" Warning: APIC I/O disabled\n");
425 * AP cpu's call this to sync up protected mode.
427 * WARNING! %gs is not set up on entry. This routine sets up %gs.
433 int x, myid = bootAP;
435 struct mdglobaldata *md;
436 struct privatespace *ps;
438 ps = &CPU_prvspace[myid];
440 gdt_segs[GPROC0_SEL].ssd_base =
441 (long) &ps->mdglobaldata.gd_common_tss;
442 ps->mdglobaldata.mi.gd_prvspace = ps;
444 /* We fill the 32-bit segment descriptors */
445 for (x = 0; x < NGDT; x++) {
446 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
447 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
449 /* And now a 64-bit one */
450 ssdtosyssd(&gdt_segs[GPROC0_SEL],
451 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
453 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
454 r_gdt.rd_base = (long) &gdt[myid * NGDT];
455 lgdt(&r_gdt); /* does magic intra-segment return */
457 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
458 wrmsr(MSR_FSBASE, 0); /* User value */
459 wrmsr(MSR_GSBASE, (u_int64_t)ps);
460 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
466 mdcpu->gd_currentldt = _default_ldt;
469 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
470 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
472 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
474 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
476 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
478 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
479 md->gd_common_tssd = *md->gd_tss_gdt;
481 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
486 * Set to a known state:
487 * Set by mpboot.s: CR0_PG, CR0_PE
488 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
491 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
494 /* Set up the fast syscall stuff */
495 msr = rdmsr(MSR_EFER) | EFER_SCE;
496 wrmsr(MSR_EFER, msr);
497 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
498 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
499 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
500 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
501 wrmsr(MSR_STAR, msr);
502 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
504 pmap_set_opt(); /* PSE/4MB pages, etc */
506 /* Initialize the PAT MSR. */
510 /* set up CPU registers and state */
513 /* set up SSE/NX registers */
516 /* set up FPU state on the AP */
517 npxinit(__INITIAL_NPXCW__);
519 /* disable the APIC, just to be SURE */
520 lapic->svr &= ~APIC_SVR_ENABLE;
522 /* data returned to BSP */
523 cpu_apic_versions[0] = lapic->version;
526 /*******************************************************************
527 * local functions and data
531 * start the SMP system
534 mp_enable(u_int boot_addr)
542 POSTCODE(MP_ENABLE_POST);
544 if (cpu_apic_address == 0)
545 panic("pmap_bootstrap: no local apic!");
548 /* turn on 4MB of V == P addressing so we can get to MP table */
549 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
553 /* examine the MP table for needed info, uses physical addresses */
561 /* can't process default configs till the CPU APIC is pmapped */
565 /* post scan cleanup */
570 setup_apic_irq_mapping();
572 /* fill the LOGICAL io_apic_versions table */
573 for (apic = 0; apic < mp_napics; ++apic) {
574 ux = io_apic_read(apic, IOAPIC_VER);
575 io_apic_versions[apic] = ux;
576 io_apic_set_id(apic, IO_TO_ID(apic));
579 /* program each IO APIC in the system */
580 for (apic = 0; apic < mp_napics; ++apic)
581 if (io_apic_setup(apic) < 0)
582 panic("IO APIC setup failure");
587 * These are required for SMP operation
590 /* install a 'Spurious INTerrupt' vector */
591 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
592 SDT_SYSIGT, SEL_KPL, 0);
594 /* install an inter-CPU IPI for TLB invalidation */
595 setidt(XINVLTLB_OFFSET, Xinvltlb,
596 SDT_SYSIGT, SEL_KPL, 0);
598 /* install an inter-CPU IPI for IPIQ messaging */
599 setidt(XIPIQ_OFFSET, Xipiq,
600 SDT_SYSIGT, SEL_KPL, 0);
602 /* install a timer vector */
603 setidt(XTIMER_OFFSET, Xtimer,
604 SDT_SYSIGT, SEL_KPL, 0);
606 /* install an inter-CPU IPI for CPU stop/restart */
607 setidt(XCPUSTOP_OFFSET, Xcpustop,
608 SDT_SYSIGT, SEL_KPL, 0);
610 /* start each Application Processor */
611 start_all_aps(boot_addr);
616 * look for the MP spec signature
619 /* string defined by the Intel MP Spec as identifying the MP table */
620 #define MP_SIG 0x5f504d5f /* _MP_ */
621 #define NEXT(X) ((X) += 4)
623 search_for_sig(u_int32_t target, int count)
626 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
628 for (x = 0; x < count; NEXT(x))
629 if (addr[x] == MP_SIG)
630 /* make array index a byte index */
631 return (long)(&addr[x]);
637 static basetable_entry basetable_entry_types[] =
639 {0, 20, "Processor"},
646 typedef struct BUSDATA {
648 enum busTypes bus_type;
651 typedef struct INTDATA {
661 typedef struct BUSTYPENAME {
666 static bus_type_name bus_type_table[] =
672 {UNKNOWN_BUSTYPE, "---"},
675 {UNKNOWN_BUSTYPE, "---"},
676 {UNKNOWN_BUSTYPE, "---"},
677 {UNKNOWN_BUSTYPE, "---"},
678 {UNKNOWN_BUSTYPE, "---"},
679 {UNKNOWN_BUSTYPE, "---"},
681 {UNKNOWN_BUSTYPE, "---"},
682 {UNKNOWN_BUSTYPE, "---"},
683 {UNKNOWN_BUSTYPE, "---"},
684 {UNKNOWN_BUSTYPE, "---"},
686 {UNKNOWN_BUSTYPE, "---"}
688 /* from MP spec v1.4, table 5-1 */
689 static int default_data[7][5] =
691 /* nbus, id0, type0, id1, type1 */
692 {1, 0, ISA, 255, 255},
693 {1, 0, EISA, 255, 255},
694 {1, 0, EISA, 255, 255},
695 {1, 0, MCA, 255, 255},
697 {2, 0, EISA, 1, PCI},
703 static bus_datum *bus_data;
706 /* the IO INT data, one entry per possible APIC INTerrupt */
707 static io_int *io_apic_ints;
711 static int processor_entry (proc_entry_ptr entry, int cpu);
712 static int bus_entry (bus_entry_ptr entry, int bus);
714 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
715 static int int_entry (int_entry_ptr entry, int intr);
717 static int lookup_bus_type (char *name);
721 * 1st pass on motherboard's Intel MP specification table.
727 * cpu_apic_address (common to all CPUs)
747 POSTCODE(MPTABLE_PASS1_POST);
750 /* clear various tables */
751 for (x = 0; x < NAPICID; ++x) {
752 io_apic_address[x] = ~0; /* IO APIC address table */
756 /* init everything to empty */
765 /* check for use of 'default' configuration */
766 if (mpfps->mpfb1 != 0) {
767 /* use default addresses */
768 cpu_apic_address = DEFAULT_APIC_BASE;
770 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
773 /* fill in with defaults */
774 mp_naps = 2; /* includes BSP */
775 mp_nbusses = default_data[mpfps->mpfb1 - 1][0];
783 panic("MP Configuration Table Header MISSING!");
784 cth = (void *)PHYS_TO_DMAP(mpfps->pap);
786 cpu_apic_address = (vm_offset_t) cth->apic_address;
788 /* walk the table, recording info of interest */
789 totalSize = cth->base_table_length - sizeof(struct MPCTH);
790 position = (u_char *) cth + sizeof(struct MPCTH);
791 count = cth->entry_count;
794 switch (type = *(u_char *) position) {
795 case 0: /* processor_entry */
796 if (((proc_entry_ptr)position)->cpu_flags
797 & PROCENTRY_FLAG_EN) {
800 ((proc_entry_ptr)position)->apic_id;
803 case 1: /* bus_entry */
806 case 2: /* io_apic_entry */
808 if (((io_apic_entry_ptr)position)->apic_flags
809 & IOAPICENTRY_FLAG_EN)
810 io_apic_address[mp_napics++] =
811 (vm_offset_t)((io_apic_entry_ptr)
812 position)->apic_address;
815 case 3: /* int_entry */
820 case 4: /* int_entry */
823 panic("mpfps Base Table HOSED!");
827 totalSize -= basetable_entry_types[type].length;
828 position = (uint8_t *)position +
829 basetable_entry_types[type].length;
833 /* qualify the numbers */
834 if (mp_naps > MAXCPU) {
835 kprintf("Warning: only using %d of %d available CPUs!\n",
840 /* See if we need to fixup HT logical CPUs. */
841 mptable_hyperthread_fixup(id_mask);
843 --mp_naps; /* subtract the BSP */
848 * 2nd pass on motherboard's Intel MP specification table.
852 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
853 * CPU_TO_ID(N), logical CPU to APIC ID table
854 * IO_TO_ID(N), logical IO to APIC ID table
861 struct PROCENTRY proc;
868 int apic, bus, cpu, intr;
871 POSTCODE(MPTABLE_PASS2_POST);
873 /* Initialize fake proc entry for use with HT fixup. */
874 bzero(&proc, sizeof(proc));
876 proc.cpu_flags = PROCENTRY_FLAG_EN;
879 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
881 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
882 M_DEVBUF, M_WAITOK | M_ZERO);
883 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
886 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
890 for (i = 0; i < mp_napics; i++) {
891 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
895 /* clear various tables */
896 for (x = 0; x < NAPICID; ++x) {
897 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
899 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
900 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
904 /* clear bus data table */
905 for (x = 0; x < mp_nbusses; ++x)
906 bus_data[x].bus_id = 0xff;
909 /* clear IO APIC INT table */
910 for (x = 0; x < (nintrs + 1); ++x) {
911 io_apic_ints[x].int_type = 0xff;
912 io_apic_ints[x].int_vector = 0xff;
916 /* setup the cpu/apic mapping arrays */
919 /* record whether PIC or virtual-wire mode */
920 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, mpfps->mpfb2 & 0x80);
922 /* check for use of 'default' configuration */
923 if (mpfps->mpfb1 != 0)
924 return mpfps->mpfb1; /* return default configuration type */
927 panic("MP Configuration Table Header MISSING!");
929 cth = (void *)PHYS_TO_DMAP(mpfps->pap);
930 /* walk the table, recording info of interest */
931 totalSize = cth->base_table_length - sizeof(struct MPCTH);
932 position = (u_char *) cth + sizeof(struct MPCTH);
933 count = cth->entry_count;
934 apic = bus = intr = 0;
935 cpu = 1; /* pre-count the BSP */
938 switch (type = *(u_char *) position) {
940 if (processor_entry(position, cpu))
943 if (need_hyperthreading_fixup) {
945 * Create fake mptable processor entries
946 * and feed them to processor_entry() to
947 * enumerate the logical CPUs.
949 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
950 for (i = 1; i < logical_cpus; i++) {
952 processor_entry(&proc, cpu);
953 logical_cpus_mask |= (1 << cpu);
959 if (bus_entry(position, bus))
964 if (io_apic_entry(position, apic))
970 if (int_entry(position, intr))
975 /* int_entry(position); */
978 panic("mpfps Base Table HOSED!");
982 totalSize -= basetable_entry_types[type].length;
983 position = (uint8_t *)position + basetable_entry_types[type].length;
986 if (boot_cpu_id == -1)
987 panic("NO BSP found!");
989 /* report fact that its NOT a default configuration */
994 * Check if we should perform a hyperthreading "fix-up" to
995 * enumerate any logical CPU's that aren't already listed
998 * XXX: We assume that all of the physical CPUs in the
999 * system have the same number of logical CPUs.
1001 * XXX: We assume that APIC ID's are allocated such that
1002 * the APIC ID's for a physical processor are aligned
1003 * with the number of logical CPU's in the processor.
1006 mptable_hyperthread_fixup(u_int id_mask)
1010 /* Nothing to do if there is no HTT support. */
1011 if ((cpu_feature & CPUID_HTT) == 0)
1013 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1014 if (logical_cpus <= 1)
1018 * For each APIC ID of a CPU that is set in the mask,
1019 * scan the other candidate APIC ID's for this
1020 * physical processor. If any of those ID's are
1021 * already in the table, then kill the fixup.
1023 for (id = 0; id <= MAXCPU; id++) {
1024 if ((id_mask & 1 << id) == 0)
1026 /* First, make sure we are on a logical_cpus boundary. */
1027 if (id % logical_cpus != 0)
1029 for (i = id + 1; i < id + logical_cpus; i++)
1030 if ((id_mask & 1 << i) != 0)
1035 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1036 * mp_naps right now.
1038 need_hyperthreading_fixup = 1;
1039 mp_naps *= logical_cpus;
1045 assign_apic_irq(int apic, int intpin, int irq)
1049 if (int_to_apicintpin[irq].ioapic != -1)
1050 panic("assign_apic_irq: inconsistent table");
1052 int_to_apicintpin[irq].ioapic = apic;
1053 int_to_apicintpin[irq].int_pin = intpin;
1054 int_to_apicintpin[irq].apic_address = ioapic[apic];
1055 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1057 for (x = 0; x < nintrs; x++) {
1058 if ((io_apic_ints[x].int_type == 0 ||
1059 io_apic_ints[x].int_type == 3) &&
1060 io_apic_ints[x].int_vector == 0xff &&
1061 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1062 io_apic_ints[x].dst_apic_int == intpin)
1063 io_apic_ints[x].int_vector = irq;
1068 revoke_apic_irq(int irq)
1074 if (int_to_apicintpin[irq].ioapic == -1)
1075 panic("revoke_apic_irq: inconsistent table");
1077 oldapic = int_to_apicintpin[irq].ioapic;
1078 oldintpin = int_to_apicintpin[irq].int_pin;
1080 int_to_apicintpin[irq].ioapic = -1;
1081 int_to_apicintpin[irq].int_pin = 0;
1082 int_to_apicintpin[irq].apic_address = NULL;
1083 int_to_apicintpin[irq].redirindex = 0;
1085 for (x = 0; x < nintrs; x++) {
1086 if ((io_apic_ints[x].int_type == 0 ||
1087 io_apic_ints[x].int_type == 3) &&
1088 io_apic_ints[x].int_vector != 0xff &&
1089 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1090 io_apic_ints[x].dst_apic_int == oldintpin)
1091 io_apic_ints[x].int_vector = 0xff;
1099 allocate_apic_irq(int intr)
1105 if (io_apic_ints[intr].int_vector != 0xff)
1106 return; /* Interrupt handler already assigned */
1108 if (io_apic_ints[intr].int_type != 0 &&
1109 (io_apic_ints[intr].int_type != 3 ||
1110 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1111 io_apic_ints[intr].dst_apic_int == 0)))
1112 return; /* Not INT or ExtInt on != (0, 0) */
1115 while (irq < APIC_INTMAPSIZE &&
1116 int_to_apicintpin[irq].ioapic != -1)
1119 if (irq >= APIC_INTMAPSIZE)
1120 return; /* No free interrupt handlers */
1122 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1123 intpin = io_apic_ints[intr].dst_apic_int;
1125 assign_apic_irq(apic, intpin, irq);
1130 swap_apic_id(int apic, int oldid, int newid)
1137 return; /* Nothing to do */
1139 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1140 apic, oldid, newid);
1142 /* Swap physical APIC IDs in interrupt entries */
1143 for (x = 0; x < nintrs; x++) {
1144 if (io_apic_ints[x].dst_apic_id == oldid)
1145 io_apic_ints[x].dst_apic_id = newid;
1146 else if (io_apic_ints[x].dst_apic_id == newid)
1147 io_apic_ints[x].dst_apic_id = oldid;
1150 /* Swap physical APIC IDs in IO_TO_ID mappings */
1151 for (oapic = 0; oapic < mp_napics; oapic++)
1152 if (IO_TO_ID(oapic) == newid)
1155 if (oapic < mp_napics) {
1156 kprintf("Changing APIC ID for IO APIC #%d from "
1157 "%d to %d in MP table\n",
1158 oapic, newid, oldid);
1159 IO_TO_ID(oapic) = oldid;
1161 IO_TO_ID(apic) = newid;
1166 fix_id_to_io_mapping(void)
1170 for (x = 0; x < NAPICID; x++)
1173 for (x = 0; x <= mp_naps; x++)
1174 if (CPU_TO_ID(x) < NAPICID)
1175 ID_TO_IO(CPU_TO_ID(x)) = x;
1177 for (x = 0; x < mp_napics; x++)
1178 if (IO_TO_ID(x) < NAPICID)
1179 ID_TO_IO(IO_TO_ID(x)) = x;
1184 first_free_apic_id(void)
1188 for (freeid = 0; freeid < NAPICID; freeid++) {
1189 for (x = 0; x <= mp_naps; x++)
1190 if (CPU_TO_ID(x) == freeid)
1194 for (x = 0; x < mp_napics; x++)
1195 if (IO_TO_ID(x) == freeid)
1206 io_apic_id_acceptable(int apic, int id)
1208 int cpu; /* Logical CPU number */
1209 int oapic; /* Logical IO APIC number for other IO APIC */
1212 return 0; /* Out of range */
1214 for (cpu = 0; cpu <= mp_naps; cpu++)
1215 if (CPU_TO_ID(cpu) == id)
1216 return 0; /* Conflict with CPU */
1218 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1219 if (IO_TO_ID(oapic) == id)
1220 return 0; /* Conflict with other APIC */
1222 return 1; /* ID is acceptable for IO APIC */
1227 io_apic_find_int_entry(int apic, int pin)
1231 /* search each of the possible INTerrupt sources */
1232 for (x = 0; x < nintrs; ++x) {
1233 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1234 (pin == io_apic_ints[x].dst_apic_int))
1235 return (&io_apic_ints[x]);
1243 * parse an Intel MP specification table
1251 int apic; /* IO APIC unit number */
1252 int freeid; /* Free physical APIC ID */
1253 int physid; /* Current physical IO APIC ID */
1256 int bus_0 = 0; /* Stop GCC warning */
1257 int bus_pci = 0; /* Stop GCC warning */
1261 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1262 * did it wrong. The MP spec says that when more than 1 PCI bus
1263 * exists the BIOS must begin with bus entries for the PCI bus and use
1264 * actual PCI bus numbering. This implies that when only 1 PCI bus
1265 * exists the BIOS can choose to ignore this ordering, and indeed many
1266 * MP motherboards do ignore it. This causes a problem when the PCI
1267 * sub-system makes requests of the MP sub-system based on PCI bus
1268 * numbers. So here we look for the situation and renumber the
1269 * busses and associated INTs in an effort to "make it right".
1272 /* find bus 0, PCI bus, count the number of PCI busses */
1273 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1274 if (bus_data[x].bus_id == 0) {
1277 if (bus_data[x].bus_type == PCI) {
1283 * bus_0 == slot of bus with ID of 0
1284 * bus_pci == slot of last PCI bus encountered
1287 /* check the 1 PCI bus case for sanity */
1288 /* if it is number 0 all is well */
1289 if (num_pci_bus == 1 &&
1290 bus_data[bus_pci].bus_id != 0) {
1292 /* mis-numbered, swap with whichever bus uses slot 0 */
1294 /* swap the bus entry types */
1295 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1296 bus_data[bus_0].bus_type = PCI;
1299 /* swap each relavant INTerrupt entry */
1300 id = bus_data[bus_pci].bus_id;
1301 for (x = 0; x < nintrs; ++x) {
1302 if (io_apic_ints[x].src_bus_id == id) {
1303 io_apic_ints[x].src_bus_id = 0;
1305 else if (io_apic_ints[x].src_bus_id == 0) {
1306 io_apic_ints[x].src_bus_id = id;
1313 /* Assign IO APIC IDs.
1315 * First try the existing ID. If a conflict is detected, try
1316 * the ID in the MP table. If a conflict is still detected, find
1319 * We cannot use the ID_TO_IO table before all conflicts has been
1320 * resolved and the table has been corrected.
1322 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1324 /* First try to use the value set by the BIOS */
1325 physid = io_apic_get_id(apic);
1326 if (io_apic_id_acceptable(apic, physid)) {
1327 if (IO_TO_ID(apic) != physid)
1328 swap_apic_id(apic, IO_TO_ID(apic), physid);
1332 /* Then check if the value in the MP table is acceptable */
1333 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1336 /* Last resort, find a free APIC ID and use it */
1337 freeid = first_free_apic_id();
1338 if (freeid >= NAPICID)
1339 panic("No free physical APIC IDs found");
1341 if (io_apic_id_acceptable(apic, freeid)) {
1342 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1345 panic("Free physical APIC ID not usable");
1347 fix_id_to_io_mapping();
1351 /* detect and fix broken Compaq MP table */
1352 if (apic_int_type(0, 0) == -1) {
1353 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1354 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1355 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1356 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1357 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1358 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1360 } else if (apic_int_type(0, 0) == 0) {
1361 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1362 for (x = 0; x < nintrs; ++x)
1363 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1364 (0 == io_apic_ints[x].dst_apic_int)) {
1365 io_apic_ints[x].int_type = 3;
1366 io_apic_ints[x].int_vector = 0xff;
1372 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1373 * controllers universally come in pairs. If IRQ 14 is specified
1374 * as an ISA interrupt, then IRQ 15 had better be too.
1376 * [ Shuttle XPC / AMD Athlon X2 ]
1377 * The MPTable is missing an entry for IRQ 15. Note that the
1378 * ACPI table has an entry for both 14 and 15.
1380 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1381 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1382 io14 = io_apic_find_int_entry(0, 14);
1383 io_apic_ints[nintrs] = *io14;
1384 io_apic_ints[nintrs].src_bus_irq = 15;
1385 io_apic_ints[nintrs].dst_apic_int = 15;
1393 /* Assign low level interrupt handlers */
1395 setup_apic_irq_mapping(void)
1401 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1402 int_to_apicintpin[x].ioapic = -1;
1403 int_to_apicintpin[x].int_pin = 0;
1404 int_to_apicintpin[x].apic_address = NULL;
1405 int_to_apicintpin[x].redirindex = 0;
1408 /* First assign ISA/EISA interrupts */
1409 for (x = 0; x < nintrs; x++) {
1410 int_vector = io_apic_ints[x].src_bus_irq;
1411 if (int_vector < APIC_INTMAPSIZE &&
1412 io_apic_ints[x].int_vector == 0xff &&
1413 int_to_apicintpin[int_vector].ioapic == -1 &&
1414 (apic_int_is_bus_type(x, ISA) ||
1415 apic_int_is_bus_type(x, EISA)) &&
1416 io_apic_ints[x].int_type == 0) {
1417 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1418 io_apic_ints[x].dst_apic_int,
1423 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1424 for (x = 0; x < nintrs; x++) {
1425 if (io_apic_ints[x].dst_apic_int == 0 &&
1426 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1427 io_apic_ints[x].int_vector == 0xff &&
1428 int_to_apicintpin[0].ioapic == -1 &&
1429 io_apic_ints[x].int_type == 3) {
1430 assign_apic_irq(0, 0, 0);
1435 /* Assign PCI interrupts */
1436 for (x = 0; x < nintrs; ++x) {
1437 if (io_apic_ints[x].int_type == 0 &&
1438 io_apic_ints[x].int_vector == 0xff &&
1439 apic_int_is_bus_type(x, PCI))
1440 allocate_apic_irq(x);
1447 processor_entry(proc_entry_ptr entry, int cpu)
1449 /* check for usability */
1450 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1453 if(entry->apic_id >= NAPICID)
1454 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1455 /* check for BSP flag */
1456 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1457 boot_cpu_id = entry->apic_id;
1458 CPU_TO_ID(0) = entry->apic_id;
1459 ID_TO_CPU(entry->apic_id) = 0;
1460 return 0; /* its already been counted */
1463 /* add another AP to list, if less than max number of CPUs */
1464 else if (cpu < MAXCPU) {
1465 CPU_TO_ID(cpu) = entry->apic_id;
1466 ID_TO_CPU(entry->apic_id) = cpu;
1475 bus_entry(bus_entry_ptr entry, int bus)
1480 /* encode the name into an index */
1481 for (x = 0; x < 6; ++x) {
1482 if ((c = entry->bus_type[x]) == ' ')
1488 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1489 panic("unknown bus type: '%s'", name);
1491 bus_data[bus].bus_id = entry->bus_id;
1492 bus_data[bus].bus_type = x;
1500 io_apic_entry(io_apic_entry_ptr entry, int apic)
1502 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1505 IO_TO_ID(apic) = entry->apic_id;
1506 if (entry->apic_id < NAPICID)
1507 ID_TO_IO(entry->apic_id) = apic;
1515 lookup_bus_type(char *name)
1519 for (x = 0; x < MAX_BUSTYPE; ++x)
1520 if (strcmp(bus_type_table[x].name, name) == 0)
1521 return bus_type_table[x].type;
1523 return UNKNOWN_BUSTYPE;
1529 int_entry(int_entry_ptr entry, int intr)
1533 io_apic_ints[intr].int_type = entry->int_type;
1534 io_apic_ints[intr].int_flags = entry->int_flags;
1535 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1536 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1537 if (entry->dst_apic_id == 255) {
1538 /* This signal goes to all IO APICS. Select an IO APIC
1539 with sufficient number of interrupt pins */
1540 for (apic = 0; apic < mp_napics; apic++)
1541 if (((io_apic_read(apic, IOAPIC_VER) &
1542 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1543 entry->dst_apic_int)
1545 if (apic < mp_napics)
1546 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1548 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1550 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1551 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1557 apic_int_is_bus_type(int intr, int bus_type)
1561 for (bus = 0; bus < mp_nbusses; ++bus)
1562 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1563 && ((int) bus_data[bus].bus_type == bus_type))
1570 * Given a traditional ISA INT mask, return an APIC mask.
1573 isa_apic_mask(u_int isa_mask)
1578 #if defined(SKIP_IRQ15_REDIRECT)
1579 if (isa_mask == (1 << 15)) {
1580 kprintf("skipping ISA IRQ15 redirect\n");
1583 #endif /* SKIP_IRQ15_REDIRECT */
1585 isa_irq = ffs(isa_mask); /* find its bit position */
1586 if (isa_irq == 0) /* doesn't exist */
1588 --isa_irq; /* make it zero based */
1590 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1594 return (1 << apic_pin); /* convert pin# to a mask */
1598 * Determine which APIC pin an ISA/EISA INT is attached to.
1600 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1601 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1602 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1603 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1605 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1607 isa_apic_irq(int isa_irq)
1611 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1612 if (INTTYPE(intr) == 0) { /* standard INT */
1613 if (SRCBUSIRQ(intr) == isa_irq) {
1614 if (apic_int_is_bus_type(intr, ISA) ||
1615 apic_int_is_bus_type(intr, EISA)) {
1616 if (INTIRQ(intr) == 0xff)
1617 return -1; /* unassigned */
1618 return INTIRQ(intr); /* found */
1623 return -1; /* NOT found */
1628 * Determine which APIC pin a PCI INT is attached to.
1630 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1631 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1632 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1634 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1638 --pciInt; /* zero based */
1640 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1641 if ((INTTYPE(intr) == 0) /* standard INT */
1642 && (SRCBUSID(intr) == pciBus)
1643 && (SRCBUSDEVICE(intr) == pciDevice)
1644 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1645 if (apic_int_is_bus_type(intr, PCI)) {
1646 if (INTIRQ(intr) == 0xff) {
1647 kprintf("IOAPIC: pci_apic_irq() "
1649 return -1; /* unassigned */
1651 return INTIRQ(intr); /* exact match */
1656 return -1; /* NOT found */
1660 next_apic_irq(int irq)
1667 for (intr = 0; intr < nintrs; intr++) {
1668 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1670 bus = SRCBUSID(intr);
1671 bustype = apic_bus_type(bus);
1672 if (bustype != ISA &&
1678 if (intr >= nintrs) {
1681 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1682 if (INTTYPE(ointr) != 0)
1684 if (bus != SRCBUSID(ointr))
1686 if (bustype == PCI) {
1687 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1689 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1692 if (bustype == ISA || bustype == EISA) {
1693 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1696 if (INTPIN(intr) == INTPIN(ointr))
1700 if (ointr >= nintrs) {
1703 return INTIRQ(ointr);
1718 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1721 * Exactly what this means is unclear at this point. It is a solution
1722 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1723 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1724 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1728 undirect_isa_irq(int rirq)
1732 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1733 /** FIXME: tickle the MB redirector chip */
1737 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1744 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1747 undirect_pci_irq(int rirq)
1751 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1753 /** FIXME: tickle the MB redirector chip */
1757 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1765 * given a bus ID, return:
1766 * the bus type if found
1770 apic_bus_type(int id)
1774 for (x = 0; x < mp_nbusses; ++x)
1775 if (bus_data[x].bus_id == id)
1776 return bus_data[x].bus_type;
1784 * given a LOGICAL APIC# and pin#, return:
1785 * the associated src bus ID if found
1789 apic_src_bus_id(int apic, int pin)
1793 /* search each of the possible INTerrupt sources */
1794 for (x = 0; x < nintrs; ++x)
1795 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1796 (pin == io_apic_ints[x].dst_apic_int))
1797 return (io_apic_ints[x].src_bus_id);
1799 return -1; /* NOT found */
1803 * given a LOGICAL APIC# and pin#, return:
1804 * the associated src bus IRQ if found
1808 apic_src_bus_irq(int apic, int pin)
1812 for (x = 0; x < nintrs; x++)
1813 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1814 (pin == io_apic_ints[x].dst_apic_int))
1815 return (io_apic_ints[x].src_bus_irq);
1817 return -1; /* NOT found */
1822 * given a LOGICAL APIC# and pin#, return:
1823 * the associated INTerrupt type if found
1827 apic_int_type(int apic, int pin)
1831 /* search each of the possible INTerrupt sources */
1832 for (x = 0; x < nintrs; ++x) {
1833 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1834 (pin == io_apic_ints[x].dst_apic_int))
1835 return (io_apic_ints[x].int_type);
1837 return -1; /* NOT found */
1841 * Return the IRQ associated with an APIC pin
1844 apic_irq(int apic, int pin)
1849 for (x = 0; x < nintrs; ++x) {
1850 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1851 (pin == io_apic_ints[x].dst_apic_int)) {
1852 res = io_apic_ints[x].int_vector;
1855 if (apic != int_to_apicintpin[res].ioapic)
1856 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1857 if (pin != int_to_apicintpin[res].int_pin)
1858 panic("apic_irq inconsistent table (2)");
1867 * given a LOGICAL APIC# and pin#, return:
1868 * the associated trigger mode if found
1872 apic_trigger(int apic, int pin)
1876 /* search each of the possible INTerrupt sources */
1877 for (x = 0; x < nintrs; ++x)
1878 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1879 (pin == io_apic_ints[x].dst_apic_int))
1880 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1882 return -1; /* NOT found */
1887 * given a LOGICAL APIC# and pin#, return:
1888 * the associated 'active' level if found
1892 apic_polarity(int apic, int pin)
1896 /* search each of the possible INTerrupt sources */
1897 for (x = 0; x < nintrs; ++x)
1898 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1899 (pin == io_apic_ints[x].dst_apic_int))
1900 return (io_apic_ints[x].int_flags & 0x03);
1902 return -1; /* NOT found */
1908 * set data according to MP defaults
1909 * FIXME: probably not complete yet...
1912 default_mp_table(int type)
1915 #if defined(APIC_IO)
1918 #endif /* APIC_IO */
1921 kprintf(" MP default config type: %d\n", type);
1924 kprintf(" bus: ISA, APIC: 82489DX\n");
1927 kprintf(" bus: EISA, APIC: 82489DX\n");
1930 kprintf(" bus: EISA, APIC: 82489DX\n");
1933 kprintf(" bus: MCA, APIC: 82489DX\n");
1936 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
1939 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
1942 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
1945 kprintf(" future type\n");
1951 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
1952 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1955 CPU_TO_ID(0) = boot_cpu_id;
1956 ID_TO_CPU(boot_cpu_id) = 0;
1958 /* one and only AP */
1959 CPU_TO_ID(1) = ap_cpu_id;
1960 ID_TO_CPU(ap_cpu_id) = 1;
1962 #if defined(APIC_IO)
1963 /* one and only IO APIC */
1964 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1967 * sanity check, refer to MP spec section 3.6.6, last paragraph
1968 * necessary as some hardware isn't properly setting up the IO APIC
1970 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1971 if (io_apic_id != 2) {
1973 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1974 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1975 io_apic_set_id(0, 2);
1978 IO_TO_ID(0) = io_apic_id;
1979 ID_TO_IO(io_apic_id) = 0;
1980 #endif /* APIC_IO */
1982 /* fill out bus entries */
1991 bus_data[0].bus_id = default_data[type - 1][1];
1992 bus_data[0].bus_type = default_data[type - 1][2];
1993 bus_data[1].bus_id = default_data[type - 1][3];
1994 bus_data[1].bus_type = default_data[type - 1][4];
1997 /* case 4: case 7: MCA NOT supported */
1998 default: /* illegal/reserved */
1999 panic("BAD default MP config: %d", type);
2003 #if defined(APIC_IO)
2004 /* general cases from MP v1.4, table 5-2 */
2005 for (pin = 0; pin < 16; ++pin) {
2006 io_apic_ints[pin].int_type = 0;
2007 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2008 io_apic_ints[pin].src_bus_id = 0;
2009 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2010 io_apic_ints[pin].dst_apic_id = io_apic_id;
2011 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2014 /* special cases from MP v1.4, table 5-2 */
2016 io_apic_ints[2].int_type = 0xff; /* N/C */
2017 io_apic_ints[13].int_type = 0xff; /* N/C */
2018 #if !defined(APIC_MIXED_MODE)
2020 panic("sorry, can't support type 2 default yet");
2021 #endif /* APIC_MIXED_MODE */
2024 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2027 io_apic_ints[0].int_type = 0xff; /* N/C */
2029 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2030 #endif /* APIC_IO */
2034 * Map a physical memory address representing I/O into KVA. The I/O
2035 * block is assumed not to cross a page boundary.
2038 permanent_io_mapping(vm_paddr_t pa)
2040 KKASSERT(pa < 0x100000000LL);
2042 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2046 * start each AP in our list
2049 start_all_aps(u_int boot_addr)
2051 vm_offset_t va = boot_address + KERNBASE;
2052 u_int64_t *pt4, *pt3, *pt2;
2058 u_char mpbiosreason;
2059 u_long mpbioswarmvec;
2060 struct mdglobaldata *gd;
2061 struct privatespace *ps;
2063 POSTCODE(START_ALL_APS_POST);
2065 /* Initialize BSP's local APIC */
2066 apic_initialize(TRUE);
2069 /* install the AP 1st level boot code */
2070 pmap_kenter(va, boot_address);
2071 cpu_invlpg((void *)va); /* JG XXX */
2072 bcopy(mptramp_start, (void *)va, bootMP_size);
2074 /* Locate the page tables, they'll be below the trampoline */
2075 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2076 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2077 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2079 /* Create the initial 1GB replicated page tables */
2080 for (i = 0; i < 512; i++) {
2081 /* Each slot of the level 4 pages points to the same level 3 page */
2082 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2083 pt4[i] |= PG_V | PG_RW | PG_U;
2085 /* Each slot of the level 3 pages points to the same level 2 page */
2086 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2087 pt3[i] |= PG_V | PG_RW | PG_U;
2089 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2090 pt2[i] = i * (2 * 1024 * 1024);
2091 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2094 /* save the current value of the warm-start vector */
2095 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2096 outb(CMOS_REG, BIOS_RESET);
2097 mpbiosreason = inb(CMOS_DATA);
2099 /* setup a vector to our boot code */
2100 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2101 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2102 outb(CMOS_REG, BIOS_RESET);
2103 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2106 * If we have a TSC we can figure out the SMI interrupt rate.
2107 * The SMI does not necessarily use a constant rate. Spend
2108 * up to 250ms trying to figure it out.
2111 if (cpu_feature & CPUID_TSC) {
2112 set_apic_timer(275000);
2113 smilast = read_apic_timer();
2114 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2115 smicount = smitest();
2116 if (smibest == 0 || smilast - smicount < smibest)
2117 smibest = smilast - smicount;
2120 if (smibest > 250000)
2123 smibest = smibest * (int64_t)1000000 /
2124 get_apic_timer_frequency();
2128 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2129 1000000 / smibest, smibest);
2132 for (x = 1; x <= mp_naps; ++x) {
2134 /* This is a bit verbose, it will go away soon. */
2136 /* first page of AP's private space */
2137 pg = x * x86_64_btop(sizeof(struct privatespace));
2139 /* allocate new private data page(s) */
2140 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2141 MDGLOBALDATA_BASEALLOC_SIZE);
2143 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2144 bzero(gd, sizeof(*gd));
2145 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2147 /* prime data page for it to use */
2148 mi_gdinit(&gd->mi, x);
2150 gd->gd_CMAP1 = &SMPpt[pg + 0];
2151 gd->gd_CMAP2 = &SMPpt[pg + 1];
2152 gd->gd_CMAP3 = &SMPpt[pg + 2];
2153 gd->gd_PMAP1 = &SMPpt[pg + 3];
2154 gd->gd_CADDR1 = ps->CPAGE1;
2155 gd->gd_CADDR2 = ps->CPAGE2;
2156 gd->gd_CADDR3 = ps->CPAGE3;
2157 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2158 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2159 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2161 /* setup a vector to our boot code */
2162 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2163 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2164 outb(CMOS_REG, BIOS_RESET);
2165 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2168 * Setup the AP boot stack
2170 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2173 /* attempt to start the Application Processor */
2174 CHECK_INIT(99); /* setup checkpoints */
2175 if (!start_ap(gd, boot_addr, smibest)) {
2176 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2177 CHECK_PRINT("trace"); /* show checkpoints */
2178 /* better panic as the AP may be running loose */
2179 kprintf("panic y/n? [y] ");
2180 if (cngetc() != 'n')
2183 CHECK_PRINT("trace"); /* show checkpoints */
2185 /* record its version info */
2186 cpu_apic_versions[x] = cpu_apic_versions[0];
2189 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2192 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2193 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2196 ncpus2_shift = shift;
2197 ncpus2 = 1 << shift;
2198 ncpus2_mask = ncpus2 - 1;
2200 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2201 if ((1 << shift) < ncpus)
2203 ncpus_fit = 1 << shift;
2204 ncpus_fit_mask = ncpus_fit - 1;
2206 /* build our map of 'other' CPUs */
2207 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2208 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2209 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2211 /* fill in our (BSP) APIC version */
2212 cpu_apic_versions[0] = lapic->version;
2214 /* restore the warmstart vector */
2215 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2216 outb(CMOS_REG, BIOS_RESET);
2217 outb(CMOS_DATA, mpbiosreason);
2220 * NOTE! The idlestack for the BSP was setup by locore. Finish
2221 * up, clean out the P==V mapping we did earlier.
2225 /* number of APs actually started */
2231 * load the 1st level AP boot code into base memory.
2234 /* targets for relocation */
2235 extern void bigJump(void);
2236 extern void bootCodeSeg(void);
2237 extern void bootDataSeg(void);
2238 extern void MPentry(void);
2239 extern u_int MP_GDT;
2240 extern u_int mp_gdtbase;
2245 install_ap_tramp(u_int boot_addr)
2248 int size = *(int *) ((u_long) & bootMP_size);
2249 u_char *src = (u_char *) ((u_long) bootMP);
2250 u_char *dst = (u_char *) boot_addr + KERNBASE;
2251 u_int boot_base = (u_int) bootMP;
2256 POSTCODE(INSTALL_AP_TRAMP_POST);
2258 for (x = 0; x < size; ++x)
2262 * modify addresses in code we just moved to basemem. unfortunately we
2263 * need fairly detailed info about mpboot.s for this to work. changes
2264 * to mpboot.s might require changes here.
2267 /* boot code is located in KERNEL space */
2268 dst = (u_char *) boot_addr + KERNBASE;
2270 /* modify the lgdt arg */
2271 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2272 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2274 /* modify the ljmp target for MPentry() */
2275 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2276 *dst32 = ((u_int) MPentry - KERNBASE);
2278 /* modify the target for boot code segment */
2279 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2280 dst8 = (u_int8_t *) (dst16 + 1);
2281 *dst16 = (u_int) boot_addr & 0xffff;
2282 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2284 /* modify the target for boot data segment */
2285 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2286 dst8 = (u_int8_t *) (dst16 + 1);
2287 *dst16 = (u_int) boot_addr & 0xffff;
2288 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2294 * This function starts the AP (application processor) identified
2295 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2296 * to accomplish this. This is necessary because of the nuances
2297 * of the different hardware we might encounter. It ain't pretty,
2298 * but it seems to work.
2300 * NOTE: eventually an AP gets to ap_init(), which is called just
2301 * before the AP goes into the LWKT scheduler's idle loop.
2304 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2308 u_long icr_lo, icr_hi;
2310 POSTCODE(START_AP_POST);
2312 /* get the PHYSICAL APIC ID# */
2313 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2315 /* calculate the vector */
2316 vector = (boot_addr >> 12) & 0xff;
2318 /* We don't want anything interfering */
2321 /* Make sure the target cpu sees everything */
2325 * Try to detect when a SMI has occurred, wait up to 200ms.
2327 * If a SMI occurs during an AP reset but before we issue
2328 * the STARTUP command, the AP may brick. To work around
2329 * this problem we hold off doing the AP startup until
2330 * after we have detected the SMI. Hopefully another SMI
2331 * will not occur before we finish the AP startup.
2333 * Retries don't seem to help. SMIs have a window of opportunity
2334 * and if USB->legacy keyboard emulation is enabled in the BIOS
2335 * the interrupt rate can be quite high.
2337 * NOTE: Don't worry about the L1 cache load, it might bloat
2338 * ldelta a little but ndelta will be so huge when the SMI
2339 * occurs the detection logic will still work fine.
2342 set_apic_timer(200000);
2347 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2348 * and running the target CPU. OR this INIT IPI might be latched (P5
2349 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2352 * see apic/apicreg.h for icr bit definitions.
2354 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2358 * Setup the address for the target AP. We can setup
2359 * icr_hi once and then just trigger operations with
2362 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2363 icr_hi |= (physical_cpu << 24);
2364 icr_lo = lapic->icr_lo & 0xfff00000;
2365 lapic->icr_hi = icr_hi;
2368 * Do an INIT IPI: assert RESET
2370 * Use edge triggered mode to assert INIT
2372 lapic->icr_lo = icr_lo | 0x00004500;
2373 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2377 * The spec calls for a 10ms delay but we may have to use a
2378 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2379 * interrupt. We have other loops here too and dividing by 2
2380 * doesn't seem to be enough even after subtracting 350us,
2381 * so we divide by 4.
2383 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2384 * interrupt was detected we use the full 10ms.
2388 else if (smibest < 150 * 4 + 350)
2390 else if ((smibest - 350) / 4 < 10000)
2391 u_sleep((smibest - 350) / 4);
2396 * Do an INIT IPI: deassert RESET
2398 * Use level triggered mode to deassert. It is unclear
2399 * why we need to do this.
2401 lapic->icr_lo = icr_lo | 0x00008500;
2402 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2404 u_sleep(150); /* wait 150us */
2407 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2408 * latched, (P5 bug) this 1st STARTUP would then terminate
2409 * immediately, and the previously started INIT IPI would continue. OR
2410 * the previous INIT IPI has already run. and this STARTUP IPI will
2411 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2414 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2415 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2417 u_sleep(200); /* wait ~200uS */
2420 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2421 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2422 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2423 * recognized after hardware RESET or INIT IPI.
2425 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2426 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2429 /* Resume normal operation */
2432 /* wait for it to start, see ap_init() */
2433 set_apic_timer(5000000);/* == 5 seconds */
2434 while (read_apic_timer()) {
2435 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2436 return 1; /* return SUCCESS */
2439 return 0; /* return FAILURE */
2454 while (read_apic_timer()) {
2456 for (count = 0; count < 100; ++count)
2457 ntsc = rdtsc(); /* force loop to occur */
2459 ndelta = ntsc - ltsc;
2460 if (ldelta > ndelta)
2462 if (ndelta > ldelta * 2)
2465 ldelta = ntsc - ltsc;
2468 return(read_apic_timer());
2472 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2474 * If for some reason we were unable to start all cpus we cannot safely
2475 * use broadcast IPIs.
2481 if (smp_startup_mask == smp_active_mask) {
2482 all_but_self_ipi(XINVLTLB_OFFSET);
2484 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2485 APIC_DELMODE_FIXED);
2491 * When called the executing CPU will send an IPI to all other CPUs
2492 * requesting that they halt execution.
2494 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2496 * - Signals all CPUs in map to stop.
2497 * - Waits for each to stop.
2504 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2505 * from executing at same time.
2508 stop_cpus(u_int map)
2510 map &= smp_active_mask;
2512 /* send the Xcpustop IPI to all CPUs in map */
2513 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2515 while ((stopped_cpus & map) != map)
2523 * Called by a CPU to restart stopped CPUs.
2525 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2527 * - Signals all CPUs in map to restart.
2528 * - Waits for each to restart.
2536 restart_cpus(u_int map)
2538 /* signal other cpus to restart */
2539 started_cpus = map & smp_active_mask;
2541 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2548 * This is called once the mpboot code has gotten us properly relocated
2549 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2550 * and when it returns the scheduler will call the real cpu_idle() main
2551 * loop for the idlethread. Interrupts are disabled on entry and should
2552 * remain disabled at return.
2560 * Adjust smp_startup_mask to signal the BSP that we have started
2561 * up successfully. Note that we do not yet hold the BGL. The BSP
2562 * is waiting for our signal.
2564 * We can't set our bit in smp_active_mask yet because we are holding
2565 * interrupts physically disabled and remote cpus could deadlock
2566 * trying to send us an IPI.
2568 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2572 * Interlock for finalization. Wait until mp_finish is non-zero,
2573 * then get the MP lock.
2575 * Note: We are in a critical section.
2577 * Note: We have to synchronize td_mpcount to our desired MP state
2578 * before calling cpu_try_mplock().
2580 * Note: we are the idle thread, we can only spin.
2582 * Note: The load fence is memory volatile and prevents the compiler
2583 * from improperly caching mp_finish, and the cpu from improperly
2586 while (mp_finish == 0)
2588 ++curthread->td_mpcount;
2589 while (cpu_try_mplock() == 0)
2592 if (cpu_feature & CPUID_TSC) {
2594 * The BSP is constantly updating tsc0_offset, figure out the
2595 * relative difference to synchronize ktrdump.
2597 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2600 /* BSP may have changed PTD while we're waiting for the lock */
2603 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2607 /* Build our map of 'other' CPUs. */
2608 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2610 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2612 /* A quick check from sanity claus */
2613 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2614 if (mycpu->gd_cpuid != apic_id) {
2615 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2616 kprintf("SMP: apic_id = %d\n", apic_id);
2618 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2620 panic("cpuid mismatch! boom!!");
2623 /* Initialize AP's local APIC for irq's */
2624 apic_initialize(FALSE);
2626 /* Set memory range attributes for this CPU to match the BSP */
2627 mem_range_AP_init();
2630 * Once we go active we must process any IPIQ messages that may
2631 * have been queued, because no actual IPI will occur until we
2632 * set our bit in the smp_active_mask. If we don't the IPI
2633 * message interlock could be left set which would also prevent
2636 * The idle loop doesn't expect the BGL to be held and while
2637 * lwkt_switch() normally cleans things up this is a special case
2638 * because we returning almost directly into the idle loop.
2640 * The idle thread is never placed on the runq, make sure
2641 * nothing we've done put it there.
2643 KKASSERT(curthread->td_mpcount == 1);
2644 smp_active_mask |= 1 << mycpu->gd_cpuid;
2647 * Enable interrupts here. idle_restore will also do it, but
2648 * doing it here lets us clean up any strays that got posted to
2649 * the CPU during the AP boot while we are still in a critical
2652 __asm __volatile("sti; pause; pause"::);
2653 mdcpu->gd_fpending = 0;
2655 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2656 lwkt_process_ipiq();
2659 * Releasing the mp lock lets the BSP finish up the SMP init
2662 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2666 * Get SMP fully working before we start initializing devices.
2674 kprintf("Finish MP startup\n");
2675 if (cpu_feature & CPUID_TSC)
2676 tsc0_offset = rdtsc();
2679 while (smp_active_mask != smp_startup_mask) {
2681 if (cpu_feature & CPUID_TSC)
2682 tsc0_offset = rdtsc();
2684 while (try_mplock() == 0)
2687 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2690 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2693 cpu_send_ipiq(int dcpu)
2695 if ((1 << dcpu) & smp_active_mask)
2696 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2699 #if 0 /* single_apic_ipi_passive() not working yet */
2701 * Returns 0 on failure, 1 on success
2704 cpu_send_ipiq_passive(int dcpu)
2707 if ((1 << dcpu) & smp_active_mask) {
2708 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2709 APIC_DELMODE_FIXED);