2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <machine/globaldata.h>
34 #include <machine/smp.h>
35 #include <machine/md_var.h>
36 #include <machine/pmap.h>
37 #include <machine_base/apic/lapic.h>
38 #include <machine_base/apic/ioapic.h>
39 #include <machine_base/apic/ioapic_abi.h>
40 #include <machine/segments.h>
41 #include <sys/thread2.h>
43 #include <machine/intr_machdep.h>
49 volatile lapic_t *lapic;
51 static void lapic_timer_calibrate(void);
52 static void lapic_timer_set_divisor(int);
53 static void lapic_timer_fixup_handler(void *);
54 static void lapic_timer_restart_handler(void *);
56 void lapic_timer_process(void);
57 void lapic_timer_process_frame(struct intrframe *);
58 void lapic_timer_always(struct intrframe *);
60 static int lapic_timer_enable = 1;
61 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
63 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
64 static void lapic_timer_intr_enable(struct cputimer_intr *);
65 static void lapic_timer_intr_restart(struct cputimer_intr *);
66 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
68 static struct cputimer_intr lapic_cputimer_intr = {
70 .reload = lapic_timer_intr_reload,
71 .enable = lapic_timer_intr_enable,
72 .config = cputimer_intr_default_config,
73 .restart = lapic_timer_intr_restart,
74 .pmfixup = lapic_timer_intr_pmfixup,
75 .initclock = cputimer_intr_default_initclock,
76 .next = SLIST_ENTRY_INITIALIZER,
78 .type = CPUTIMER_INTR_LAPIC,
79 .prio = CPUTIMER_INTR_PRIO_LAPIC,
80 .caps = CPUTIMER_INTR_CAP_NONE
83 static int lapic_timer_divisor_idx = -1;
84 static const uint32_t lapic_timer_divisors[] = {
85 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
86 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
88 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
91 * APIC ID <-> CPU ID mapping structures.
93 int cpu_id_to_apic_id[NAPICID];
94 int apic_id_to_cpu_id[NAPICID];
105 * Enable LAPIC, configure interrupts.
108 lapic_init(boolean_t bsp)
116 * Since IDT is shared between BSP and APs, these vectors
117 * only need to be installed once; we do it on BSP.
120 /* Install a 'Spurious INTerrupt' vector */
121 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
122 SDT_SYSIGT, SEL_KPL, 0);
124 /* Install an inter-CPU IPI for TLB invalidation */
125 setidt(XINVLTLB_OFFSET, Xinvltlb,
126 SDT_SYSIGT, SEL_KPL, 0);
128 /* Install an inter-CPU IPI for IPIQ messaging */
129 setidt(XIPIQ_OFFSET, Xipiq,
130 SDT_SYSIGT, SEL_KPL, 0);
132 /* Install a timer vector */
133 setidt(XTIMER_OFFSET, Xtimer,
134 SDT_SYSIGT, SEL_KPL, 0);
136 /* Install an inter-CPU IPI for CPU stop/restart */
137 setidt(XCPUSTOP_OFFSET, Xcpustop,
138 SDT_SYSIGT, SEL_KPL, 0);
142 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
143 * aggregate interrupt input from the 8259. The INTA cycle
144 * will be routed to the external controller (the 8259) which
145 * is expected to supply the vector.
147 * Must be setup edge triggered, active high.
149 * Disable LINT0 on BSP, if I/O APIC is enabled.
151 * Disable LINT0 on the APs. It doesn't matter what delivery
152 * mode we use because we leave it masked.
154 temp = lapic->lvt_lint0;
155 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
156 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
158 temp |= APIC_LVT_DM_EXTINT;
160 temp |= APIC_LVT_MASKED;
162 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
164 lapic->lvt_lint0 = temp;
167 * Setup LINT1 as NMI.
169 * Must be setup edge trigger, active high.
171 * Enable LINT1 on BSP, if I/O APIC is enabled.
173 * Disable LINT1 on the APs.
175 temp = lapic->lvt_lint1;
176 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
177 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
178 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
179 if (bsp && ioapic_enable)
180 temp &= ~APIC_LVT_MASKED;
181 lapic->lvt_lint1 = temp;
184 * Mask the LAPIC error interrupt, LAPIC performance counter
187 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
188 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
191 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
193 timer = lapic->lvt_timer;
194 timer &= ~APIC_LVTT_VECTOR;
195 timer |= XTIMER_OFFSET;
196 timer |= APIC_LVTT_MASKED;
197 lapic->lvt_timer = timer;
200 * Set the Task Priority Register as needed. At the moment allow
201 * interrupts on all cpus (the APs will remain CLId until they are
205 temp &= ~APIC_TPR_PRIO; /* clear priority field */
212 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
213 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
216 * Set the spurious interrupt vector. The low 4 bits of the vector
219 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
220 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
221 temp &= ~APIC_SVR_VECTOR;
222 temp |= XSPURIOUSINT_OFFSET;
227 * Pump out a few EOIs to clean out interrupts that got through
228 * before we were able to set the TPR.
235 lapic_timer_calibrate();
236 if (lapic_timer_enable) {
237 cputimer_intr_register(&lapic_cputimer_intr);
238 cputimer_intr_select(&lapic_cputimer_intr, 0);
241 lapic_timer_set_divisor(lapic_timer_divisor_idx);
245 apic_dump("apic_initialize()");
249 lapic_timer_set_divisor(int divisor_idx)
251 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
252 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
256 lapic_timer_oneshot(u_int count)
260 value = lapic->lvt_timer;
261 value &= ~APIC_LVTT_PERIODIC;
262 lapic->lvt_timer = value;
263 lapic->icr_timer = count;
267 lapic_timer_oneshot_quick(u_int count)
269 lapic->icr_timer = count;
273 lapic_timer_calibrate(void)
277 /* Try to calibrate the local APIC timer. */
278 for (lapic_timer_divisor_idx = 0;
279 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
280 lapic_timer_divisor_idx++) {
281 lapic_timer_set_divisor(lapic_timer_divisor_idx);
282 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
284 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
285 if (value != APIC_TIMER_MAX_COUNT)
288 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
289 panic("lapic: no proper timer divisor?!\n");
290 lapic_cputimer_intr.freq = value / 2;
292 kprintf("lapic: divisor index %d, frequency %u Hz\n",
293 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
297 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
301 gd->gd_timer_running = 0;
303 count = sys_cputimer->count();
304 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
305 systimer_intr(&count, 0, frame);
309 lapic_timer_process(void)
311 lapic_timer_process_oncpu(mycpu, NULL);
315 lapic_timer_process_frame(struct intrframe *frame)
317 lapic_timer_process_oncpu(mycpu, frame);
321 * This manual debugging code is called unconditionally from Xtimer
322 * (the lapic timer interrupt) whether the current thread is in a
323 * critical section or not) and can be useful in tracking down lockups.
325 * NOTE: MANUAL DEBUG CODE
328 static int saveticks[SMP_MAXCPU];
329 static int savecounts[SMP_MAXCPU];
333 lapic_timer_always(struct intrframe *frame)
336 globaldata_t gd = mycpu;
337 int cpu = gd->gd_cpuid;
343 gptr = (short *)0xFFFFFFFF800b8000 + 80 * cpu;
344 *gptr = ((*gptr + 1) & 0x00FF) | 0x0700;
347 ksnprintf(buf, sizeof(buf), " %p %16s %d %16s ",
348 (void *)frame->if_rip, gd->gd_curthread->td_comm, ticks,
350 for (i = 0; buf[i]; ++i) {
351 gptr[i] = 0x0700 | (unsigned char)buf[i];
355 if (saveticks[gd->gd_cpuid] != ticks) {
356 saveticks[gd->gd_cpuid] = ticks;
357 savecounts[gd->gd_cpuid] = 0;
359 ++savecounts[gd->gd_cpuid];
360 if (savecounts[gd->gd_cpuid] > 2000 && panicstr == NULL) {
361 panic("cpud %d panicing on ticks failure",
364 for (i = 0; i < ncpus; ++i) {
366 if (saveticks[i] && panicstr == NULL) {
367 delta = saveticks[i] - ticks;
368 if (delta < -10 || delta > 10) {
369 panic("cpu %d panicing on cpu %d watchdog",
379 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
381 struct globaldata *gd = mycpu;
383 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
387 if (gd->gd_timer_running) {
388 if (reload < lapic->ccr_timer)
389 lapic_timer_oneshot_quick(reload);
391 gd->gd_timer_running = 1;
392 lapic_timer_oneshot_quick(reload);
397 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
401 timer = lapic->lvt_timer;
402 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
403 lapic->lvt_timer = timer;
405 lapic_timer_fixup_handler(NULL);
409 lapic_timer_fixup_handler(void *arg)
416 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
418 * Detect the presence of C1E capability mostly on latest
419 * dual-cores (or future) k8 family. This feature renders
420 * the local APIC timer dead, so we disable it by reading
421 * the Interrupt Pending Message register and clearing both
422 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
425 * "BIOS and Kernel Developer's Guide for AMD NPT
426 * Family 0Fh Processors"
427 * #32559 revision 3.00
429 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
430 (cpu_id & 0x0fff0000) >= 0x00040000) {
433 msr = rdmsr(0xc0010055);
434 if (msr & 0x18000000) {
435 struct globaldata *gd = mycpu;
437 kprintf("cpu%d: AMD C1E detected\n",
439 wrmsr(0xc0010055, msr & ~0x18000000ULL);
442 * We are kinda stalled;
445 gd->gd_timer_running = 1;
446 lapic_timer_oneshot_quick(2);
456 lapic_timer_restart_handler(void *dummy __unused)
460 lapic_timer_fixup_handler(&started);
462 struct globaldata *gd = mycpu;
464 gd->gd_timer_running = 1;
465 lapic_timer_oneshot_quick(2);
470 * This function is called only by ACPI-CA code currently:
471 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
472 * module controls PM. So once ACPI-CA is attached, we try
473 * to apply the fixup to prevent LAPIC timer from hanging.
476 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
478 lwkt_send_ipiq_mask(smp_active_mask,
479 lapic_timer_fixup_handler, NULL);
483 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
485 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
490 * dump contents of local APIC registers
495 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
496 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
497 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
501 * Inter Processor Interrupt functions.
505 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
507 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
508 * vector is any valid SYSTEM INT vector
509 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
511 * A backlog of requests can create a deadlock between cpus. To avoid this
512 * we have to be able to accept IPIs at the same time we are trying to send
513 * them. The critical section prevents us from attempting to send additional
514 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
515 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
516 * to occur but fortunately it does not happen too often.
519 apic_ipi(int dest_type, int vector, int delivery_mode)
524 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
525 unsigned long rflags = read_rflags();
527 DEBUG_PUSH_INFO("apic_ipi");
528 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
532 write_rflags(rflags);
535 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
536 delivery_mode | vector;
537 lapic->icr_lo = icr_lo;
543 single_apic_ipi(int cpu, int vector, int delivery_mode)
549 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
550 unsigned long rflags = read_rflags();
552 DEBUG_PUSH_INFO("single_apic_ipi");
553 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
557 write_rflags(rflags);
559 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
560 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
561 lapic->icr_hi = icr_hi;
564 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
565 | APIC_DEST_DESTFLD | delivery_mode | vector;
568 lapic->icr_lo = icr_lo;
575 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
577 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
578 * to the target, and the scheduler does not 'poll' for IPI messages.
581 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
587 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
591 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
592 icr_hi |= (CPUID_TO_APICID(cpu) << 24);
593 lapic->icr_hi = icr_hi;
596 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
597 | APIC_DEST_DESTFLD | delivery_mode | vector;
600 lapic->icr_lo = icr_lo;
608 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
610 * target is a bitmask of destination cpus. Vector is any
611 * valid system INT vector. Delivery mode may be either
612 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
615 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
619 int n = BSFCPUMASK(target);
620 target &= ~CPUMASK(n);
621 single_apic_ipi(n, vector, delivery_mode);
627 * Timer code, in development...
628 * - suggested by rgrimes@gndrsh.aac.dev.com
631 get_apic_timer_frequency(void)
633 return(lapic_cputimer_intr.freq);
637 * Load a 'downcount time' in uSeconds.
640 set_apic_timer(int us)
645 * When we reach here, lapic timer's frequency
646 * must have been calculated as well as the
647 * divisor (lapic->dcr_timer is setup during the
648 * divisor calculation).
650 KKASSERT(lapic_cputimer_intr.freq != 0 &&
651 lapic_timer_divisor_idx >= 0);
653 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
654 lapic_timer_oneshot(count);
659 * Read remaining time in timer.
662 read_apic_timer(void)
665 /** XXX FIXME: we need to return the actual remaining time,
666 * for now we just return the remaining count.
669 return lapic->ccr_timer;
675 * Spin-style delay, set delay time in uS, spin till it drains.
680 set_apic_timer(count);
681 while (read_apic_timer())
686 lapic_unused_apic_id(int start)
690 for (i = start; i < NAPICID; ++i) {
691 if (APICID_TO_CPUID(i) == -1)
698 lapic_map(vm_offset_t lapic_addr)
700 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
702 kprintf("lapic: at 0x%08lx\n", lapic_addr);
705 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
706 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
711 struct lapic_enumerator *e;
712 int error, i, ap_max;
714 KKASSERT(lapic_enable);
716 for (i = 0; i < NAPICID; ++i)
717 APICID_TO_CPUID(i) = -1;
719 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
720 error = e->lapic_probe(e);
725 kprintf("LAPIC: Can't find LAPIC\n");
729 e->lapic_enumerate(e);
732 TUNABLE_INT_FETCH("hw.ap_max", &ap_max);
733 if (ap_max > MAXCPU - 1)
737 kprintf("LAPIC: Warning use only %d out of %d "
747 lapic_enumerator_register(struct lapic_enumerator *ne)
749 struct lapic_enumerator *e;
751 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
752 if (e->lapic_prio < ne->lapic_prio) {
753 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
757 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
761 lapic_set_cpuid(int cpu_id, int apic_id)
763 CPUID_TO_APICID(cpu_id) = apic_id;
764 APICID_TO_CPUID(apic_id) = cpu_id;
768 lapic_fixup_noioapic(void)
772 /* Only allowed on BSP */
773 KKASSERT(mycpuid == 0);
774 KKASSERT(!ioapic_enable);
776 temp = lapic->lvt_lint0;
777 temp &= ~APIC_LVT_MASKED;
778 lapic->lvt_lint0 = temp;
780 temp = lapic->lvt_lint1;
781 temp |= APIC_LVT_MASKED;
782 lapic->lvt_lint1 = temp;