2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $
33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.14 2004/07/23 07:16:30 joerg Exp $
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
79 * The 3c90x series chips use a bus-master DMA interface for transfering
80 * packets to and from the controller chip. Some of the "vortex" cards
81 * (3c59x) also supported a bus master mode, however for those chips
82 * you could only DMA packets to/from a contiguous memory buffer. For
83 * transmission this would mean copying the contents of the queued mbuf
84 * chain into an mbuf cluster and then DMAing the cluster. This extra
85 * copy would sort of defeat the purpose of the bus master support for
86 * any packet that doesn't fit into a single mbuf.
88 * By contrast, the 3c90x cards support a fragment-based bus master
89 * mode where mbuf chains can be encapsulated using TX descriptors.
90 * This is similar to other PCI chips such as the Texas Instruments
91 * ThunderLAN and the Intel 82557/82558.
93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
94 * bus master chips because they maintain the old PIO interface for
95 * backwards compatibility, but starting with the 3c905B and the
96 * "cyclone" chips, the compatibility interface has been dropped.
97 * Since using bus master DMA is a big win, we use this driver to
98 * support the PCI "boomerang" chips even though they work with the
99 * "vortex" driver in order to obtain better performance.
101 * This driver is in the /sys/pci directory because it only supports
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/sockio.h>
108 #include <sys/endian.h>
109 #include <sys/mbuf.h>
110 #include <sys/kernel.h>
111 #include <sys/socket.h>
114 #include <net/if_arp.h>
115 #include <net/ethernet.h>
116 #include <net/if_dl.h>
117 #include <net/if_media.h>
118 #include <net/vlan/if_vlan_var.h>
122 #include <machine/bus_memio.h>
123 #include <machine/bus_pio.h>
124 #include <machine/bus.h>
125 #include <machine/clock.h> /* for DELAY */
126 #include <machine/resource.h>
128 #include <sys/rman.h>
130 #include "../mii_layer/mii.h"
131 #include "../mii_layer/miivar.h"
133 #include <bus/pci/pcireg.h>
134 #include <bus/pci/pcivar.h>
136 /* "controller miibus0" required. See GENERIC if you get errors here. */
137 #include "miibus_if.h"
139 #include "if_xlreg.h"
141 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
144 * Various supported device vendors/types and their names.
146 static struct xl_type xl_devs[] = {
147 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
148 "3Com 3c900-TPO Etherlink XL" },
149 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
150 "3Com 3c900-COMBO Etherlink XL" },
151 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
152 "3Com 3c905-TX Fast Etherlink XL" },
153 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
154 "3Com 3c905-T4 Fast Etherlink XL" },
155 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
156 "3Com 3c900B-TPO Etherlink XL" },
157 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
158 "3Com 3c900B-COMBO Etherlink XL" },
159 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
160 "3Com 3c900B-TPC Etherlink XL" },
161 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
162 "3Com 3c900B-FL Etherlink XL" },
163 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
164 "3Com 3c905B-TX Fast Etherlink XL" },
165 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
166 "3Com 3c905B-T4 Fast Etherlink XL" },
167 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
168 "3Com 3c905B-FX/SC Fast Etherlink XL" },
169 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
170 "3Com 3c905B-COMBO Fast Etherlink XL" },
171 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
172 "3Com 3c905C-TX Fast Etherlink XL" },
173 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
174 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
175 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
176 "3Com 3c980 Fast Etherlink XL" },
177 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
178 "3Com 3c980C Fast Etherlink XL" },
179 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
180 "3Com 3cSOHO100-TX OfficeConnect" },
181 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
182 "3Com 3c450-TX HomeConnect" },
183 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
184 "3Com 3c555 Fast Etherlink XL" },
185 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
186 "3Com 3c556 Fast Etherlink XL" },
187 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
188 "3Com 3c556B Fast Etherlink XL" },
189 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
190 "3Com 3c575TX Fast Etherlink XL" },
191 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
192 "3Com 3c575B Fast Etherlink XL" },
193 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
194 "3Com 3c575C Fast Etherlink XL" },
195 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
196 "3Com 3c656 Fast Etherlink XL" },
197 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
198 "3Com 3c656B Fast Etherlink XL" },
199 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
200 "3Com 3c656C Fast Etherlink XL" },
204 static int xl_probe (device_t);
205 static int xl_attach (device_t);
206 static int xl_detach (device_t);
208 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *);
209 static void xl_stats_update (void *);
210 static int xl_encap (struct xl_softc *, struct xl_chain *,
212 static void xl_rxeof (struct xl_softc *);
213 static int xl_rx_resync (struct xl_softc *);
214 static void xl_txeof (struct xl_softc *);
215 static void xl_txeof_90xB (struct xl_softc *);
216 static void xl_txeoc (struct xl_softc *);
217 static void xl_intr (void *);
218 static void xl_start (struct ifnet *);
219 static void xl_start_90xB (struct ifnet *);
220 static int xl_ioctl (struct ifnet *, u_long, caddr_t,
222 static void xl_init (void *);
223 static void xl_stop (struct xl_softc *);
224 static void xl_watchdog (struct ifnet *);
225 static void xl_shutdown (device_t);
226 static int xl_suspend (device_t);
227 static int xl_resume (device_t);
229 static int xl_ifmedia_upd (struct ifnet *);
230 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
232 static int xl_eeprom_wait (struct xl_softc *);
233 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
234 static void xl_mii_sync (struct xl_softc *);
235 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
236 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
237 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
239 static void xl_setcfg (struct xl_softc *);
240 static void xl_setmode (struct xl_softc *, int);
241 static u_int8_t xl_calchash (caddr_t);
242 static void xl_setmulti (struct xl_softc *);
243 static void xl_setmulti_hash (struct xl_softc *);
244 static void xl_reset (struct xl_softc *);
245 static int xl_list_rx_init (struct xl_softc *);
246 static int xl_list_tx_init (struct xl_softc *);
247 static int xl_list_tx_init_90xB (struct xl_softc *);
248 static void xl_wait (struct xl_softc *);
249 static void xl_mediacheck (struct xl_softc *);
250 static void xl_choose_xcvr (struct xl_softc *, int);
251 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int);
252 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t,
254 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t,
257 static void xl_testpacket (struct xl_softc *);
260 static int xl_miibus_readreg (device_t, int, int);
261 static int xl_miibus_writereg (device_t, int, int, int);
262 static void xl_miibus_statchg (device_t);
263 static void xl_miibus_mediainit (device_t);
265 static device_method_t xl_methods[] = {
266 /* Device interface */
267 DEVMETHOD(device_probe, xl_probe),
268 DEVMETHOD(device_attach, xl_attach),
269 DEVMETHOD(device_detach, xl_detach),
270 DEVMETHOD(device_shutdown, xl_shutdown),
271 DEVMETHOD(device_suspend, xl_suspend),
272 DEVMETHOD(device_resume, xl_resume),
275 DEVMETHOD(bus_print_child, bus_generic_print_child),
276 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
279 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
280 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
281 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
282 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
287 static driver_t xl_driver = {
290 sizeof(struct xl_softc)
293 static devclass_t xl_devclass;
295 DECLARE_DUMMY_MODULE(if_xl);
296 MODULE_DEPEND(if_xl, miibus, 1, 1, 1);
297 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
298 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
301 xl_dma_map_addr(arg, segs, nseg, error)
303 bus_dma_segment_t *segs;
309 *paddr = segs->ds_addr;
313 xl_dma_map_rxbuf(arg, segs, nseg, mapsize, error)
315 bus_dma_segment_t *segs;
324 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
326 *paddr = segs->ds_addr;
330 xl_dma_map_txbuf(arg, segs, nseg, mapsize, error)
332 bus_dma_segment_t *segs;
343 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
347 for (i = 0; i < nseg; i++) {
348 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
349 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
350 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
351 total_len += segs[i].ds_len;
353 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
355 l->xl_status = htole32(total_len);
360 * Murphy's law says that it's possible the chip can wedge and
361 * the 'command in progress' bit may never clear. Hence, we wait
362 * only a finite amount of time to avoid getting caught in an
363 * infinite loop. Normally this delay routine would be a macro,
364 * but it isn't called during normal operation so we can afford
365 * to make it a function.
373 for (i = 0; i < XL_TIMEOUT; i++) {
374 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
379 printf("xl%d: command never completed!\n", sc->xl_unit);
385 * MII access routines are provided for adapters with external
386 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
387 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
388 * Note: if you don't perform the MDIO operations just right,
389 * it's possible to end up with code that works correctly with
390 * some chips/CPUs/processor speeds/bus speeds/etc but not
394 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
395 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
398 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
399 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
402 * Sync the PHYs by setting data bit and strobing the clock 32 times.
411 MII_SET(XL_MII_DIR|XL_MII_DATA);
413 for (i = 0; i < 32; i++) {
415 MII_SET(XL_MII_DATA);
416 MII_SET(XL_MII_DATA);
418 MII_SET(XL_MII_DATA);
419 MII_SET(XL_MII_DATA);
426 * Clock a series of bits through the MII.
429 xl_mii_send(sc, bits, cnt)
439 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
441 MII_SET(XL_MII_DATA);
443 MII_CLR(XL_MII_DATA);
451 * Read an PHY register through the MII.
454 xl_mii_readreg(sc, frame)
456 struct xl_mii_frame *frame;
464 * Set up frame for RX.
466 frame->mii_stdelim = XL_MII_STARTDELIM;
467 frame->mii_opcode = XL_MII_READOP;
468 frame->mii_turnaround = 0;
472 * Select register window 4.
477 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
486 * Send command/address info.
488 xl_mii_send(sc, frame->mii_stdelim, 2);
489 xl_mii_send(sc, frame->mii_opcode, 2);
490 xl_mii_send(sc, frame->mii_phyaddr, 5);
491 xl_mii_send(sc, frame->mii_regaddr, 5);
494 MII_CLR((XL_MII_CLK|XL_MII_DATA));
502 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
506 * Now try reading data bits. If the ack failed, we still
507 * need to clock through 16 cycles to keep the PHY(s) in sync.
510 for(i = 0; i < 16; i++) {
517 for (i = 0x8000; i; i >>= 1) {
520 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
521 frame->mii_data |= i;
539 * Write to a PHY register through the MII.
542 xl_mii_writereg(sc, frame)
544 struct xl_mii_frame *frame;
552 * Set up frame for TX.
555 frame->mii_stdelim = XL_MII_STARTDELIM;
556 frame->mii_opcode = XL_MII_WRITEOP;
557 frame->mii_turnaround = XL_MII_TURNAROUND;
560 * Select the window 4.
565 * Turn on data output.
571 xl_mii_send(sc, frame->mii_stdelim, 2);
572 xl_mii_send(sc, frame->mii_opcode, 2);
573 xl_mii_send(sc, frame->mii_phyaddr, 5);
574 xl_mii_send(sc, frame->mii_regaddr, 5);
575 xl_mii_send(sc, frame->mii_turnaround, 2);
576 xl_mii_send(sc, frame->mii_data, 16);
593 xl_miibus_readreg(dev, phy, reg)
598 struct xl_mii_frame frame;
600 sc = device_get_softc(dev);
603 * Pretend that PHYs are only available at MII address 24.
604 * This is to guard against problems with certain 3Com ASIC
605 * revisions that incorrectly map the internal transceiver
606 * control registers at all MII addresses. This can cause
607 * the miibus code to attach the same PHY several times over.
609 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
612 bzero((char *)&frame, sizeof(frame));
614 frame.mii_phyaddr = phy;
615 frame.mii_regaddr = reg;
616 xl_mii_readreg(sc, &frame);
618 return(frame.mii_data);
622 xl_miibus_writereg(dev, phy, reg, data)
627 struct xl_mii_frame frame;
629 sc = device_get_softc(dev);
631 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
634 bzero((char *)&frame, sizeof(frame));
636 frame.mii_phyaddr = phy;
637 frame.mii_regaddr = reg;
638 frame.mii_data = data;
640 xl_mii_writereg(sc, &frame);
646 xl_miibus_statchg(dev)
650 struct mii_data *mii;
653 sc = device_get_softc(dev);
654 mii = device_get_softc(sc->xl_miibus);
658 /* Set ASIC's duplex mode to match the PHY. */
660 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
661 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
663 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
664 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
670 * Special support for the 3c905B-COMBO. This card has 10/100 support
671 * plus BNC and AUI ports. This means we will have both an miibus attached
672 * plus some non-MII media settings. In order to allow this, we have to
673 * add the extra media to the miibus's ifmedia struct, but we can't do
674 * that during xl_attach() because the miibus hasn't been attached yet.
675 * So instead, we wait until the miibus probe/attach is done, at which
676 * point we will get a callback telling is that it's safe to add our
680 xl_miibus_mediainit(dev)
684 struct mii_data *mii;
687 sc = device_get_softc(dev);
688 mii = device_get_softc(sc->xl_miibus);
689 ifm = &mii->mii_media;
691 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
693 * Check for a 10baseFL board in disguise.
695 if (sc->xl_type == XL_TYPE_905B &&
696 sc->xl_media == XL_MEDIAOPT_10FL) {
698 printf("xl%d: found 10baseFL\n", sc->xl_unit);
699 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
700 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
701 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
703 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
706 printf("xl%d: found AUI\n", sc->xl_unit);
707 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
711 if (sc->xl_media & XL_MEDIAOPT_BNC) {
713 printf("xl%d: found BNC\n", sc->xl_unit);
714 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
721 * The EEPROM is slow: give it time to come ready after issuing
730 for (i = 0; i < 100; i++) {
731 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
738 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit);
746 * Read a sequence of words from the EEPROM. Note that ethernet address
747 * data is stored in the EEPROM in network byte order.
750 xl_read_eeprom(sc, dest, off, cnt, swap)
758 u_int16_t word = 0, *ptr;
759 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
760 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
762 * It's easy to accidentally overwrite the rom content!
763 * Note: the 3c575 uses 8bit EEPROM offsets.
767 if (xl_eeprom_wait(sc))
770 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
773 for (i = 0; i < cnt; i++) {
774 if (sc->xl_flags & XL_FLAG_8BITROM)
775 CSR_WRITE_2(sc, XL_W0_EE_CMD,
776 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
778 CSR_WRITE_2(sc, XL_W0_EE_CMD,
779 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
780 err = xl_eeprom_wait(sc);
783 word = CSR_READ_2(sc, XL_W0_EE_DATA);
784 ptr = (u_int16_t *)(dest + (i * 2));
795 * This routine is taken from the 3Com Etherlink XL manual,
796 * page 10-7. It calculates a CRC of the supplied multicast
797 * group address and returns the lower 8 bits, which are used
798 * as the multicast filter position.
799 * Note: the 3c905B currently only supports a 64-bit hash table,
800 * which means we really only need 6 bits, but the manual indicates
801 * that future chip revisions will have a 256-bit hash table,
802 * hence the routine is set up to calculate 8 bits of position
803 * info in case we need it some day.
804 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a
805 * 256 bit hash table. This means we have to use all 8 bits regardless.
806 * On older cards, the upper 2 bits will be ignored. Grrrr....
808 static u_int8_t xl_calchash(addr)
811 u_int32_t crc, carry;
815 /* Compute CRC for the address value. */
816 crc = 0xFFFFFFFF; /* initial value */
818 for (i = 0; i < 6; i++) {
820 for (j = 0; j < 8; j++) {
821 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
825 crc = (crc ^ 0x04c11db6) | carry;
829 /* return the filter bit position */
830 return(crc & 0x000000FF);
834 * NICs older than the 3c905B have only one multicast option, which
835 * is to enable reception of all multicast frames.
842 struct ifmultiaddr *ifma;
846 ifp = &sc->arpcom.ac_if;
849 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
851 if (ifp->if_flags & IFF_ALLMULTI) {
852 rxfilt |= XL_RXFILTER_ALLMULTI;
853 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
857 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
858 ifma = ifma->ifma_link.le_next)
862 rxfilt |= XL_RXFILTER_ALLMULTI;
864 rxfilt &= ~XL_RXFILTER_ALLMULTI;
866 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
872 * 3c905B adapters have a hash filter that we can program.
880 struct ifmultiaddr *ifma;
884 ifp = &sc->arpcom.ac_if;
887 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
889 if (ifp->if_flags & IFF_ALLMULTI) {
890 rxfilt |= XL_RXFILTER_ALLMULTI;
891 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
894 rxfilt &= ~XL_RXFILTER_ALLMULTI;
897 /* first, zot all the existing hash bits */
898 for (i = 0; i < XL_HASHFILT_SIZE; i++)
899 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
901 /* now program new ones */
902 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
903 ifma = ifma->ifma_link.le_next) {
904 if (ifma->ifma_addr->sa_family != AF_LINK)
906 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
907 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
912 rxfilt |= XL_RXFILTER_MULTIHASH;
914 rxfilt &= ~XL_RXFILTER_MULTIHASH;
916 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
929 ifp = &sc->arpcom.ac_if;
931 MGETHDR(m, MB_DONTWAIT, MT_DATA);
936 bcopy(&sc->arpcom.ac_enaddr,
937 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
938 bcopy(&sc->arpcom.ac_enaddr,
939 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
940 mtod(m, struct ether_header *)->ether_type = htons(3);
941 mtod(m, unsigned char *)[14] = 0;
942 mtod(m, unsigned char *)[15] = 0;
943 mtod(m, unsigned char *)[16] = 0xE3;
944 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
945 IF_ENQUEUE(&ifp->if_snd, m);
959 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
960 icfg &= ~XL_ICFG_CONNECTOR_MASK;
961 if (sc->xl_media & XL_MEDIAOPT_MII ||
962 sc->xl_media & XL_MEDIAOPT_BT4)
963 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
964 if (sc->xl_media & XL_MEDIAOPT_BTX)
965 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
967 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
968 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
974 xl_setmode(sc, media)
981 printf("xl%d: selecting ", sc->xl_unit);
984 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
986 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
988 if (sc->xl_media & XL_MEDIAOPT_BT) {
989 if (IFM_SUBTYPE(media) == IFM_10_T) {
990 printf("10baseT transceiver, ");
991 sc->xl_xcvr = XL_XCVR_10BT;
992 icfg &= ~XL_ICFG_CONNECTOR_MASK;
993 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
994 mediastat |= XL_MEDIASTAT_LINKBEAT|
995 XL_MEDIASTAT_JABGUARD;
996 mediastat &= ~XL_MEDIASTAT_SQEENB;
1000 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1001 if (IFM_SUBTYPE(media) == IFM_100_FX) {
1002 printf("100baseFX port, ");
1003 sc->xl_xcvr = XL_XCVR_100BFX;
1004 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1005 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
1006 mediastat |= XL_MEDIASTAT_LINKBEAT;
1007 mediastat &= ~XL_MEDIASTAT_SQEENB;
1011 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1012 if (IFM_SUBTYPE(media) == IFM_10_5) {
1013 printf("AUI port, ");
1014 sc->xl_xcvr = XL_XCVR_AUI;
1015 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1016 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
1017 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1018 XL_MEDIASTAT_JABGUARD);
1019 mediastat |= ~XL_MEDIASTAT_SQEENB;
1021 if (IFM_SUBTYPE(media) == IFM_10_FL) {
1022 printf("10baseFL transceiver, ");
1023 sc->xl_xcvr = XL_XCVR_AUI;
1024 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1025 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
1026 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1027 XL_MEDIASTAT_JABGUARD);
1028 mediastat |= ~XL_MEDIASTAT_SQEENB;
1032 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1033 if (IFM_SUBTYPE(media) == IFM_10_2) {
1034 printf("BNC port, ");
1035 sc->xl_xcvr = XL_XCVR_COAX;
1036 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1037 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
1038 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1039 XL_MEDIASTAT_JABGUARD|
1040 XL_MEDIASTAT_SQEENB);
1044 if ((media & IFM_GMASK) == IFM_FDX ||
1045 IFM_SUBTYPE(media) == IFM_100_FX) {
1046 printf("full duplex\n");
1048 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
1050 printf("half duplex\n");
1052 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
1053 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
1056 if (IFM_SUBTYPE(media) == IFM_10_2)
1057 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1059 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1060 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1062 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1071 struct xl_softc *sc;
1076 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1077 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1078 XL_RESETOPT_DISADVFD:0));
1081 * If we're using memory mapped register mode, pause briefly
1082 * after issuing the reset command before trying to access any
1083 * other registers. With my 3c575C cardbus card, failing to do
1084 * this results in the system locking up while trying to poll
1085 * the command busy bit in the status register.
1087 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1090 for (i = 0; i < XL_TIMEOUT; i++) {
1092 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1096 if (i == XL_TIMEOUT)
1097 printf("xl%d: reset didn't complete\n", sc->xl_unit);
1099 /* Reset TX and RX. */
1100 /* Note: the RX reset takes an absurd amount of time
1101 * on newer versions of the Tornado chips such as those
1102 * on the 3c905CX and newer 3c908C cards. We wait an
1103 * extra amount of time so that xl_wait() doesn't complain
1104 * and annoy the users.
1106 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1109 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1112 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1113 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1115 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1116 XL_W2_RESET_OPTIONS)
1117 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1118 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1122 /* Wait a little while for the chip to get its brains in order. */
1128 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1129 * IDs against our list and return a device name if we find a match.
1139 while(t->xl_name != NULL) {
1140 if ((pci_get_vendor(dev) == t->xl_vid) &&
1141 (pci_get_device(dev) == t->xl_did)) {
1142 device_set_desc(dev, t->xl_name);
1152 * This routine is a kludge to work around possible hardware faults
1153 * or manufacturing defects that can cause the media options register
1154 * (or reset options register, as it's called for the first generation
1155 * 3c90x adapters) to return an incorrect result. I have encountered
1156 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1157 * which doesn't have any of the 'mediaopt' bits set. This screws up
1158 * the attach routine pretty badly because it doesn't know what media
1159 * to look for. If we find ourselves in this predicament, this routine
1160 * will try to guess the media options values and warn the user of a
1161 * possible manufacturing defect with his adapter/system/whatever.
1165 struct xl_softc *sc;
1169 * If some of the media options bits are set, assume they are
1170 * correct. If not, try to figure it out down below.
1171 * XXX I should check for 10baseFL, but I don't have an adapter
1174 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1176 * Check the XCVR value. If it's not in the normal range
1177 * of values, we need to fake it up here.
1179 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1182 printf("xl%d: bogus xcvr value "
1183 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr);
1184 printf("xl%d: choosing new default based "
1185 "on card type\n", sc->xl_unit);
1188 if (sc->xl_type == XL_TYPE_905B &&
1189 sc->xl_media & XL_MEDIAOPT_10FL)
1191 printf("xl%d: WARNING: no media options bits set in "
1192 "the media options register!!\n", sc->xl_unit);
1193 printf("xl%d: this could be a manufacturing defect in "
1194 "your adapter or system\n", sc->xl_unit);
1195 printf("xl%d: attempting to guess media type; you "
1196 "should probably consult your vendor\n", sc->xl_unit);
1199 xl_choose_xcvr(sc, 1);
1205 xl_choose_xcvr(sc, verbose)
1206 struct xl_softc *sc;
1212 * Read the device ID from the EEPROM.
1213 * This is what's loaded into the PCI device ID register, so it has
1214 * to be correct otherwise we wouldn't have gotten this far.
1216 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1219 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1220 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1221 sc->xl_media = XL_MEDIAOPT_BT;
1222 sc->xl_xcvr = XL_XCVR_10BT;
1224 printf("xl%d: guessing 10BaseT "
1225 "transceiver\n", sc->xl_unit);
1227 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1228 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1229 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1230 sc->xl_xcvr = XL_XCVR_10BT;
1232 printf("xl%d: guessing COMBO "
1233 "(AUI/BNC/TP)\n", sc->xl_unit);
1235 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1236 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1237 sc->xl_xcvr = XL_XCVR_10BT;
1239 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit);
1241 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1242 sc->xl_media = XL_MEDIAOPT_10FL;
1243 sc->xl_xcvr = XL_XCVR_AUI;
1245 printf("xl%d: guessing 10baseFL\n", sc->xl_unit);
1247 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1248 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1249 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1250 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1251 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1252 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1253 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1254 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1255 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1256 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1257 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1258 sc->xl_media = XL_MEDIAOPT_MII;
1259 sc->xl_xcvr = XL_XCVR_MII;
1261 printf("xl%d: guessing MII\n", sc->xl_unit);
1263 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1264 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1265 sc->xl_media = XL_MEDIAOPT_BT4;
1266 sc->xl_xcvr = XL_XCVR_MII;
1268 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit);
1270 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1271 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1272 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1273 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1274 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1275 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1276 sc->xl_media = XL_MEDIAOPT_BTX;
1277 sc->xl_xcvr = XL_XCVR_AUTO;
1279 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit);
1281 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1282 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1283 sc->xl_xcvr = XL_XCVR_AUTO;
1285 printf("xl%d: guessing 10/100 "
1286 "plus BNC/AUI\n", sc->xl_unit);
1289 printf("xl%d: unknown device ID: %x -- "
1290 "defaulting to 10baseT\n", sc->xl_unit, devid);
1291 sc->xl_media = XL_MEDIAOPT_BT;
1299 * Attach the interface. Allocate softc structures, do ifmedia
1300 * setup and ethernet/BPF attach.
1307 u_char eaddr[ETHER_ADDR_LEN];
1310 struct xl_softc *sc;
1312 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1313 int unit, error = 0, rid, res;
1317 sc = device_get_softc(dev);
1318 unit = device_get_unit(dev);
1320 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1323 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555)
1324 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1325 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 ||
1326 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1327 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1328 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1329 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1330 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 ||
1331 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556)
1332 sc->xl_flags |= XL_FLAG_8BITROM;
1333 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1334 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1336 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A ||
1337 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1338 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1339 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B ||
1340 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1341 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1342 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM;
1343 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656)
1344 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1345 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B)
1346 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1347 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C)
1348 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1349 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1350 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1351 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 ||
1352 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B)
1353 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1354 XL_FLAG_INVERT_LED_PWR;
1355 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B)
1356 sc->xl_flags |= XL_FLAG_PHYOK;
1357 #ifndef BURN_BRIDGES
1359 * If this is a 3c905B, we have to check one extra thing.
1360 * The 905B supports power management and may be placed in
1361 * a low-power mode (D3 mode), typically by certain operating
1362 * systems which shall not be named. The PCI BIOS is supposed
1363 * to reset the NIC and bring it out of low-power mode, but
1364 * some do not. Consequently, we have to see if this chip
1365 * supports power management, and if so, make sure it's not
1366 * in low-power mode. If power management is available, the
1367 * capid byte will be 0x01.
1369 * I _think_ that what actually happens is that the chip
1370 * loses its PCI configuration during the transition from
1371 * D3 back to D0; this means that it should be possible for
1372 * us to save the PCI iobase, membase and IRQ, put the chip
1373 * back in the D0 state, then restore the PCI config ourselves.
1376 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1377 u_int32_t iobase, membase, irq;
1379 /* Save important PCI config data. */
1380 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1381 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1382 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1384 /* Reset the power state. */
1385 printf("xl%d: chip is in D%d power mode "
1386 "-- setting to D0\n", unit,
1387 pci_get_powerstate(dev));
1389 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1391 /* Restore PCI config data. */
1392 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1393 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1394 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1398 * Map control/status registers.
1400 pci_enable_busmaster(dev);
1401 pci_enable_io(dev, SYS_RES_IOPORT);
1402 pci_enable_io(dev, SYS_RES_MEMORY);
1403 command = pci_read_config(dev, PCIR_COMMAND, 4);
1405 if (!(command & PCIM_CMD_PORTEN) && !(command & PCIM_CMD_MEMEN)) {
1406 printf("xl%d: failed to enable I/O ports and memory mappings!\n", unit);
1412 res = SYS_RES_MEMORY;
1415 sc->xl_res = bus_alloc_resource(dev, res, &rid,
1416 0, ~0, 1, RF_ACTIVE);
1419 if (sc->xl_res != NULL) {
1420 sc->xl_flags |= XL_FLAG_USE_MMIO;
1422 printf("xl%d: using memory mapped I/O\n", unit);
1425 res = SYS_RES_IOPORT;
1426 sc->xl_res = bus_alloc_resource(dev, res, &rid,
1427 0, ~0, 1, RF_ACTIVE);
1428 if (sc->xl_res == NULL) {
1429 printf ("xl%d: couldn't map ports/memory\n", unit);
1434 printf("xl%d: using port I/O\n", unit);
1437 sc->xl_btag = rman_get_bustag(sc->xl_res);
1438 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1440 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1441 rid = XL_PCI_FUNCMEM;
1442 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1443 0, ~0, 1, RF_ACTIVE);
1445 if (sc->xl_fres == NULL) {
1446 printf ("xl%d: couldn't map ports/memory\n", unit);
1451 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1452 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1455 /* Allocate interrupt */
1457 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1458 RF_SHAREABLE | RF_ACTIVE);
1459 if (sc->xl_irq == NULL) {
1460 printf("xl%d: couldn't map interrupt\n", unit);
1465 sc->xl_flags |= XL_FLAG_ATTACH_MAPPED;
1467 /* Reset the adapter. */
1471 * Get station address from the EEPROM.
1473 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1474 printf("xl%d: failed to read station address\n", sc->xl_unit);
1480 callout_handle_init(&sc->xl_stat_ch);
1483 * Now allocate a tag for the DMA descriptor lists and a chunk
1484 * of DMA-able memory based on the tag. Also obtain the DMA
1485 * addresses of the RX and TX ring, which we'll need later.
1486 * All of our lists are allocated as a contiguous block
1489 error = bus_dma_tag_create(NULL, 8, 0,
1490 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1491 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0,
1492 &sc->xl_ldata.xl_rx_tag);
1494 printf("xl%d: failed to allocate rx dma tag\n", unit);
1498 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1499 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT,
1500 &sc->xl_ldata.xl_rx_dmamap);
1502 printf("xl%d: no memory for rx list buffers!\n", unit);
1503 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1504 sc->xl_ldata.xl_rx_tag = NULL;
1508 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1509 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1510 XL_RX_LIST_SZ, xl_dma_map_addr,
1511 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1513 printf("xl%d: cannot get dma address of the rx ring!\n", unit);
1514 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1515 sc->xl_ldata.xl_rx_dmamap);
1516 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1517 sc->xl_ldata.xl_rx_tag = NULL;
1521 error = bus_dma_tag_create(NULL, 8, 0,
1522 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1523 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0,
1524 &sc->xl_ldata.xl_tx_tag);
1526 printf("xl%d: failed to allocate tx dma tag\n", unit);
1530 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1531 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT,
1532 &sc->xl_ldata.xl_tx_dmamap);
1534 printf("xl%d: no memory for list buffers!\n", unit);
1535 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1536 sc->xl_ldata.xl_tx_tag = NULL;
1540 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1541 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1542 XL_TX_LIST_SZ, xl_dma_map_addr,
1543 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1545 printf("xl%d: cannot get dma address of the tx ring!\n", unit);
1546 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1547 sc->xl_ldata.xl_tx_dmamap);
1548 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1549 sc->xl_ldata.xl_tx_tag = NULL;
1554 * Allocate a DMA tag for the mapping of mbufs.
1556 error = bus_dma_tag_create(NULL, 1, 0,
1557 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1558 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0,
1561 printf("xl%d: failed to allocate mbuf dma tag\n", unit);
1565 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
1566 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
1568 /* We need a spare DMA map for the RX ring. */
1569 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1574 * Figure out the card type. 3c905B adapters have the
1575 * 'supportsNoTxLength' bit set in the capabilities
1576 * word in the EEPROM.
1577 * Note: my 3c575C cardbus card lies. It returns a value
1578 * of 0x1578 for its capabilities word, which is somewhat
1579 * nonsensical. Another way to distinguish a 3c90x chip
1580 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1581 * bit. This will only be set for 3c90x boomerage chips.
1583 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1584 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1585 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1586 sc->xl_type = XL_TYPE_905B;
1588 sc->xl_type = XL_TYPE_90X;
1590 ifp = &sc->arpcom.ac_if;
1592 if_initname(ifp, "xl", unit);
1593 ifp->if_mtu = ETHERMTU;
1594 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1595 ifp->if_ioctl = xl_ioctl;
1596 ifp->if_capabilities = 0;
1597 if (sc->xl_type == XL_TYPE_905B) {
1598 ifp->if_start = xl_start_90xB;
1599 ifp->if_capabilities |= IFCAP_HWCSUM;
1601 ifp->if_start = xl_start;
1603 ifp->if_watchdog = xl_watchdog;
1604 ifp->if_init = xl_init;
1605 ifp->if_baudrate = 10000000;
1606 ifp->if_snd.ifq_maxlen = XL_TX_LIST_CNT - 1;
1608 * NOTE: features disabled by default. This seems to corrupt
1609 * tx packet data one out of a million packets or so and then
1610 * generates a good checksum so the receiver doesn't
1611 * know the packet is bad
1613 ifp->if_capenable = 0; /*ifp->if_capabilities;*/
1614 if (ifp->if_capenable & IFCAP_TXCSUM)
1615 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1618 * Now we have to see what sort of media we have.
1619 * This includes probing for an MII interace and a
1623 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1625 printf("xl%d: media options word: %x\n", sc->xl_unit,
1628 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1629 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1630 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1631 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1635 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1636 || sc->xl_media & XL_MEDIAOPT_BT4) {
1638 printf("xl%d: found MII/AUTO\n", sc->xl_unit);
1640 if (mii_phy_probe(dev, &sc->xl_miibus,
1641 xl_ifmedia_upd, xl_ifmedia_sts)) {
1642 printf("xl%d: no PHY found!\n", sc->xl_unit);
1651 * Sanity check. If the user has selected "auto" and this isn't
1652 * a 10/100 card of some kind, we need to force the transceiver
1653 * type to something sane.
1655 if (sc->xl_xcvr == XL_XCVR_AUTO)
1656 xl_choose_xcvr(sc, bootverbose);
1661 if (sc->xl_media & XL_MEDIAOPT_BT) {
1663 printf("xl%d: found 10baseT\n", sc->xl_unit);
1664 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1665 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1666 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1667 ifmedia_add(&sc->ifmedia,
1668 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1671 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1673 * Check for a 10baseFL board in disguise.
1675 if (sc->xl_type == XL_TYPE_905B &&
1676 sc->xl_media == XL_MEDIAOPT_10FL) {
1678 printf("xl%d: found 10baseFL\n", sc->xl_unit);
1679 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1680 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1682 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1683 ifmedia_add(&sc->ifmedia,
1684 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1687 printf("xl%d: found AUI\n", sc->xl_unit);
1688 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1692 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1694 printf("xl%d: found BNC\n", sc->xl_unit);
1695 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1698 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1700 printf("xl%d: found 100baseFX\n", sc->xl_unit);
1701 ifp->if_baudrate = 100000000;
1702 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1705 /* Choose a default media. */
1706 switch(sc->xl_xcvr) {
1708 media = IFM_ETHER|IFM_10_T;
1709 xl_setmode(sc, media);
1712 if (sc->xl_type == XL_TYPE_905B &&
1713 sc->xl_media == XL_MEDIAOPT_10FL) {
1714 media = IFM_ETHER|IFM_10_FL;
1715 xl_setmode(sc, media);
1717 media = IFM_ETHER|IFM_10_5;
1718 xl_setmode(sc, media);
1722 media = IFM_ETHER|IFM_10_2;
1723 xl_setmode(sc, media);
1726 case XL_XCVR_100BTX:
1728 /* Chosen by miibus */
1730 case XL_XCVR_100BFX:
1731 media = IFM_ETHER|IFM_100_FX;
1734 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit,
1737 * This will probably be wrong, but it prevents
1738 * the ifmedia code from panicking.
1740 media = IFM_ETHER|IFM_10_T;
1744 if (sc->xl_miibus == NULL)
1745 ifmedia_set(&sc->ifmedia, media);
1749 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1751 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1755 * Call MI attach routine.
1757 ether_ifattach(ifp, eaddr);
1760 * Tell the upper layer(s) we support long frames.
1762 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1764 /* Hook interrupt last to avoid having to lock softc */
1765 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET,
1766 xl_intr, sc, &sc->xl_intrhand);
1768 printf("xl%d: couldn't set up irq\n", unit);
1769 ether_ifdetach(ifp);
1783 * Shutdown hardware and free up resources. This can be called any
1784 * time after the mutex has been initialized. It is called in both
1785 * the error case in attach and the normal detach case so it needs
1786 * to be careful about only freeing resources that have actually been
1793 struct xl_softc *sc;
1800 sc = device_get_softc(dev);
1801 ifp = &sc->arpcom.ac_if;
1803 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1805 res = SYS_RES_MEMORY;
1808 res = SYS_RES_IOPORT;
1812 * Only try to communicate with the device if we were able to map
1813 * the ports. This flag is set before ether_ifattach() so it also
1814 * governs our call to ether_ifdetach().
1816 if (sc->xl_flags & XL_FLAG_ATTACH_MAPPED) {
1819 ether_ifdetach(ifp);
1823 device_delete_child(dev, sc->xl_miibus);
1824 bus_generic_detach(dev);
1825 ifmedia_removeall(&sc->ifmedia);
1827 if (sc->xl_intrhand)
1828 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1830 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1831 if (sc->xl_fres != NULL)
1832 bus_release_resource(dev, SYS_RES_MEMORY,
1833 XL_PCI_FUNCMEM, sc->xl_fres);
1835 bus_release_resource(dev, res, rid, sc->xl_res);
1838 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1839 bus_dma_tag_destroy(sc->xl_mtag);
1841 if (sc->xl_ldata.xl_rx_tag) {
1842 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1843 sc->xl_ldata.xl_rx_dmamap);
1844 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1845 sc->xl_ldata.xl_rx_dmamap);
1846 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1848 if (sc->xl_ldata.xl_tx_tag) {
1849 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1850 sc->xl_ldata.xl_tx_dmamap);
1851 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1852 sc->xl_ldata.xl_tx_dmamap);
1853 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1862 * Initialize the transmit descriptors.
1866 struct xl_softc *sc;
1868 struct xl_chain_data *cd;
1869 struct xl_list_data *ld;
1874 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1875 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1876 error = bus_dmamap_create(sc->xl_mtag, 0,
1877 &cd->xl_tx_chain[i].xl_map);
1880 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1881 i * sizeof(struct xl_list);
1882 if (i == (XL_TX_LIST_CNT - 1))
1883 cd->xl_tx_chain[i].xl_next = NULL;
1885 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1888 cd->xl_tx_free = &cd->xl_tx_chain[0];
1889 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1891 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1896 * Initialize the transmit descriptors.
1899 xl_list_tx_init_90xB(sc)
1900 struct xl_softc *sc;
1902 struct xl_chain_data *cd;
1903 struct xl_list_data *ld;
1908 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1909 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1910 error = bus_dmamap_create(sc->xl_mtag, 0,
1911 &cd->xl_tx_chain[i].xl_map);
1914 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1915 i * sizeof(struct xl_list);
1916 if (i == (XL_TX_LIST_CNT - 1))
1917 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1919 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1921 cd->xl_tx_chain[i].xl_prev =
1922 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1924 cd->xl_tx_chain[i].xl_prev =
1925 &cd->xl_tx_chain[i - 1];
1928 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1929 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1935 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1940 * Initialize the RX descriptors and allocate mbufs for them. Note that
1941 * we arrange the descriptors in a closed ring, so that the last descriptor
1942 * points back to the first.
1946 struct xl_softc *sc;
1948 struct xl_chain_data *cd;
1949 struct xl_list_data *ld;
1956 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1957 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1958 error = bus_dmamap_create(sc->xl_mtag, 0,
1959 &cd->xl_rx_chain[i].xl_map);
1962 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1965 if (i == (XL_RX_LIST_CNT - 1))
1969 nextptr = ld->xl_rx_dmaaddr +
1970 next * sizeof(struct xl_list_onefrag);
1971 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1972 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1975 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1976 cd->xl_rx_head = &cd->xl_rx_chain[0];
1982 * Initialize an RX descriptor and attach an MBUF cluster.
1983 * If we fail to do so, we need to leave the old mbuf and
1984 * the old DMA map untouched so that it can be reused.
1988 struct xl_softc *sc;
1989 struct xl_chain_onefrag *c;
1991 struct mbuf *m_new = NULL;
1996 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2000 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2002 /* Force longword alignment for packet payload. */
2003 m_adj(m_new, ETHER_ALIGN);
2005 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
2006 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
2009 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error);
2013 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
2015 c->xl_map = sc->xl_tmpmap;
2016 sc->xl_tmpmap = map;
2018 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
2019 c->xl_ptr->xl_status = 0;
2020 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
2021 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
2027 struct xl_softc *sc;
2029 struct xl_chain_onefrag *pos;
2032 pos = sc->xl_cdata.xl_rx_head;
2034 for (i = 0; i < XL_RX_LIST_CNT; i++) {
2035 if (pos->xl_ptr->xl_status)
2040 if (i == XL_RX_LIST_CNT)
2043 sc->xl_cdata.xl_rx_head = pos;
2049 * A frame has been uploaded: pass the resulting mbuf chain up to
2050 * the higher level protocols.
2054 struct xl_softc *sc;
2058 struct xl_chain_onefrag *cur_rx;
2062 ifp = &sc->arpcom.ac_if;
2066 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
2067 BUS_DMASYNC_POSTREAD);
2068 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
2069 cur_rx = sc->xl_cdata.xl_rx_head;
2070 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
2071 total_len = rxstat & XL_RXSTAT_LENMASK;
2074 * Since we have told the chip to allow large frames,
2075 * we need to trap giant frame errors in software. We allow
2076 * a little more than the normal frame size to account for
2077 * frames with VLAN tags.
2079 if (total_len > XL_MAX_FRAMELEN)
2080 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
2083 * If an error occurs, update stats, clear the
2084 * status word and leave the mbuf cluster in place:
2085 * it should simply get re-used next time this descriptor
2086 * comes up in the ring.
2088 if (rxstat & XL_RXSTAT_UP_ERROR) {
2090 cur_rx->xl_ptr->xl_status = 0;
2091 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2092 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2097 * If the error bit was not set, the upload complete
2098 * bit should be set which means we have a valid packet.
2099 * If not, something truly strange has happened.
2101 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2102 printf("xl%d: bad receive status -- "
2103 "packet dropped\n", sc->xl_unit);
2105 cur_rx->xl_ptr->xl_status = 0;
2106 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2107 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2111 /* No errors; receive the packet. */
2112 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2113 BUS_DMASYNC_POSTREAD);
2114 m = cur_rx->xl_mbuf;
2117 * Try to conjure up a new mbuf cluster. If that
2118 * fails, it means we have an out of memory condition and
2119 * should leave the buffer in place and continue. This will
2120 * result in a lost packet, but there's little else we
2121 * can do in this situation.
2123 if (xl_newbuf(sc, cur_rx)) {
2125 cur_rx->xl_ptr->xl_status = 0;
2126 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2127 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2130 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2131 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2134 m->m_pkthdr.rcvif = ifp;
2135 m->m_pkthdr.len = m->m_len = total_len;
2137 if (ifp->if_capenable & IFCAP_RXCSUM) {
2138 /* Do IP checksum checking. */
2139 if (rxstat & XL_RXSTAT_IPCKOK)
2140 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2141 if (!(rxstat & XL_RXSTAT_IPCKERR))
2142 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2143 if ((rxstat & XL_RXSTAT_TCPCOK &&
2144 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2145 (rxstat & XL_RXSTAT_UDPCKOK &&
2146 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2147 m->m_pkthdr.csum_flags |=
2148 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2149 m->m_pkthdr.csum_data = 0xffff;
2153 (*ifp->if_input)(ifp, m);
2157 * Handle the 'end of channel' condition. When the upload
2158 * engine hits the end of the RX ring, it will stall. This
2159 * is our cue to flush the RX ring, reload the uplist pointer
2160 * register and unstall the engine.
2161 * XXX This is actually a little goofy. With the ThunderLAN
2162 * chip, you get an interrupt when the receiver hits the end
2163 * of the receive ring, which tells you exactly when you
2164 * you need to reload the ring pointer. Here we have to
2165 * fake it. I'm mad at myself for not being clever enough
2166 * to avoid the use of a goto here.
2168 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2169 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2170 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2172 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2173 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2174 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2182 * A frame was downloaded to the chip. It's safe for us to clean up
2187 struct xl_softc *sc;
2189 struct xl_chain *cur_tx;
2192 ifp = &sc->arpcom.ac_if;
2194 /* Clear the timeout timer. */
2198 * Go through our tx list and free mbufs for those
2199 * frames that have been uploaded. Note: the 3c905B
2200 * sets a special bit in the status word to let us
2201 * know that a frame has been downloaded, but the
2202 * original 3c900/3c905 adapters don't do that.
2203 * Consequently, we have to use a different test if
2204 * xl_type != XL_TYPE_905B.
2206 while(sc->xl_cdata.xl_tx_head != NULL) {
2207 cur_tx = sc->xl_cdata.xl_tx_head;
2209 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2212 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2213 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2214 BUS_DMASYNC_POSTWRITE);
2215 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2216 m_freem(cur_tx->xl_mbuf);
2217 cur_tx->xl_mbuf = NULL;
2220 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2221 sc->xl_cdata.xl_tx_free = cur_tx;
2224 if (sc->xl_cdata.xl_tx_head == NULL) {
2225 ifp->if_flags &= ~IFF_OACTIVE;
2226 sc->xl_cdata.xl_tx_tail = NULL;
2228 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2229 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2230 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2231 sc->xl_cdata.xl_tx_head->xl_phys);
2232 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2241 struct xl_softc *sc;
2243 struct xl_chain *cur_tx = NULL;
2247 ifp = &sc->arpcom.ac_if;
2249 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2250 BUS_DMASYNC_POSTREAD);
2251 idx = sc->xl_cdata.xl_tx_cons;
2252 while(idx != sc->xl_cdata.xl_tx_prod) {
2254 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2256 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2257 XL_TXSTAT_DL_COMPLETE))
2260 if (cur_tx->xl_mbuf != NULL) {
2261 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2262 BUS_DMASYNC_POSTWRITE);
2263 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2264 m_freem(cur_tx->xl_mbuf);
2265 cur_tx->xl_mbuf = NULL;
2270 sc->xl_cdata.xl_tx_cnt--;
2271 XL_INC(idx, XL_TX_LIST_CNT);
2275 sc->xl_cdata.xl_tx_cons = idx;
2278 ifp->if_flags &= ~IFF_OACTIVE;
2284 * TX 'end of channel' interrupt handler. Actually, we should
2285 * only get a 'TX complete' interrupt if there's a transmit error,
2286 * so this is really TX error handler.
2290 struct xl_softc *sc;
2294 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2295 if (txstat & XL_TXSTATUS_UNDERRUN ||
2296 txstat & XL_TXSTATUS_JABBER ||
2297 txstat & XL_TXSTATUS_RECLAIM) {
2298 printf("xl%d: transmission error: %x\n",
2299 sc->xl_unit, txstat);
2300 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2302 if (sc->xl_type == XL_TYPE_905B) {
2303 if (sc->xl_cdata.xl_tx_cnt) {
2306 i = sc->xl_cdata.xl_tx_cons;
2307 c = &sc->xl_cdata.xl_tx_chain[i];
2308 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2310 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2313 if (sc->xl_cdata.xl_tx_head != NULL)
2314 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2315 sc->xl_cdata.xl_tx_head->xl_phys);
2318 * Remember to set this for the
2319 * first generation 3c90X chips.
2321 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2322 if (txstat & XL_TXSTATUS_UNDERRUN &&
2323 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2324 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2325 printf("xl%d: tx underrun, increasing tx start"
2326 " threshold to %d bytes\n", sc->xl_unit,
2329 CSR_WRITE_2(sc, XL_COMMAND,
2330 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2331 if (sc->xl_type == XL_TYPE_905B) {
2332 CSR_WRITE_2(sc, XL_COMMAND,
2333 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2335 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2336 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2338 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2339 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2342 * Write an arbitrary byte to the TX_STATUS register
2343 * to clear this interrupt/error and advance to the next.
2345 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2355 struct xl_softc *sc;
2360 ifp = &sc->arpcom.ac_if;
2362 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) {
2364 CSR_WRITE_2(sc, XL_COMMAND,
2365 XL_CMD_INTR_ACK|(status & XL_INTRS));
2367 if (status & XL_STAT_UP_COMPLETE) {
2370 curpkts = ifp->if_ipackets;
2372 if (curpkts == ifp->if_ipackets) {
2373 while (xl_rx_resync(sc))
2378 if (status & XL_STAT_DOWN_COMPLETE) {
2379 if (sc->xl_type == XL_TYPE_905B)
2385 if (status & XL_STAT_TX_COMPLETE) {
2390 if (status & XL_STAT_ADFAIL) {
2395 if (status & XL_STAT_STATSOFLOW) {
2396 sc->xl_stats_no_timeout = 1;
2397 xl_stats_update(sc);
2398 sc->xl_stats_no_timeout = 0;
2402 if (ifp->if_snd.ifq_head != NULL)
2403 (*ifp->if_start)(ifp);
2409 xl_stats_update(xsc)
2412 struct xl_softc *sc;
2414 struct xl_stats xl_stats;
2417 struct mii_data *mii = NULL;
2419 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2422 ifp = &sc->arpcom.ac_if;
2423 if (sc->xl_miibus != NULL)
2424 mii = device_get_softc(sc->xl_miibus);
2426 p = (u_int8_t *)&xl_stats;
2428 /* Read all the stats registers. */
2431 for (i = 0; i < 16; i++)
2432 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2434 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2436 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2437 xl_stats.xl_tx_single_collision +
2438 xl_stats.xl_tx_late_collision;
2441 * Boomerang and cyclone chips have an extra stats counter
2442 * in window 4 (BadSSD). We have to read this too in order
2443 * to clear out all the stats registers and avoid a statsoflow
2447 CSR_READ_1(sc, XL_W4_BADSSD);
2449 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2454 if (!sc->xl_stats_no_timeout)
2455 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2461 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2462 * pointers to the fragment pointers.
2465 xl_encap(sc, c, m_head)
2466 struct xl_softc *sc;
2468 struct mbuf *m_head;
2474 ifp = &sc->arpcom.ac_if;
2477 * Start packing the mbufs in this chain into
2478 * the fragment pointers. Stop when we run out
2479 * of fragments or hit the end of the mbuf chain.
2481 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2482 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2484 if (error && error != EFBIG) {
2486 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error);
2491 * Handle special case: we used up all 63 fragments,
2492 * but we have more mbufs left in the chain. Copy the
2493 * data into an mbuf cluster. Note that we don't
2494 * bother clearing the values in the other fragment
2495 * pointers/counters; it wouldn't gain us anything,
2496 * and would waste cycles.
2501 m_new = m_defrag(m_head, MB_DONTWAIT);
2502 if (m_new == NULL) {
2509 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2510 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2513 printf("xl%d: can't map mbuf (error %d)\n",
2514 sc->xl_unit, error);
2519 if (sc->xl_type == XL_TYPE_905B) {
2520 status = XL_TXSTAT_RND_DEFEAT;
2522 if (m_head->m_pkthdr.csum_flags) {
2523 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2524 status |= XL_TXSTAT_IPCKSUM;
2525 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2526 status |= XL_TXSTAT_TCPCKSUM;
2527 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2528 status |= XL_TXSTAT_UDPCKSUM;
2530 c->xl_ptr->xl_status = htole32(status);
2533 c->xl_mbuf = m_head;
2534 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2539 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2540 * to the mbuf data regions directly in the transmit lists. We also save a
2541 * copy of the pointers since the transmit list fragment pointers are
2542 * physical addresses.
2548 struct xl_softc *sc;
2549 struct mbuf *m_head = NULL;
2550 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2551 struct xl_chain *prev_tx;
2557 * Check for an available queue slot. If there are none,
2560 if (sc->xl_cdata.xl_tx_free == NULL) {
2563 if (sc->xl_cdata.xl_tx_free == NULL) {
2564 ifp->if_flags |= IFF_OACTIVE;
2569 start_tx = sc->xl_cdata.xl_tx_free;
2571 while(sc->xl_cdata.xl_tx_free != NULL) {
2572 IF_DEQUEUE(&ifp->if_snd, m_head);
2576 /* Pick a descriptor off the free list. */
2578 cur_tx = sc->xl_cdata.xl_tx_free;
2580 /* Pack the data into the descriptor. */
2581 error = xl_encap(sc, cur_tx, m_head);
2587 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2588 cur_tx->xl_next = NULL;
2590 /* Chain it together. */
2592 prev->xl_next = cur_tx;
2593 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2598 * If there's a BPF listener, bounce a copy of this frame
2602 bpf_mtap(ifp, cur_tx->xl_mbuf);
2606 * If there are no packets queued, bail.
2608 if (cur_tx == NULL) {
2613 * Place the request for the upload interrupt
2614 * in the last descriptor in the chain. This way, if
2615 * we're chaining several packets at once, we'll only
2616 * get an interupt once for the whole chain rather than
2617 * once for each packet.
2619 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2621 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2622 BUS_DMASYNC_PREWRITE);
2625 * Queue the packets. If the TX channel is clear, update
2626 * the downlist pointer register.
2628 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2631 if (sc->xl_cdata.xl_tx_head != NULL) {
2632 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2633 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2634 htole32(start_tx->xl_phys);
2635 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2636 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2637 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2638 sc->xl_cdata.xl_tx_tail = cur_tx;
2640 sc->xl_cdata.xl_tx_head = start_tx;
2641 sc->xl_cdata.xl_tx_tail = cur_tx;
2643 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2644 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2646 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2651 * Set a timeout in case the chip goes out to lunch.
2656 * XXX Under certain conditions, usually on slower machines
2657 * where interrupts may be dropped, it's possible for the
2658 * adapter to chew up all the buffers in the receive ring
2659 * and stall, without us being able to do anything about it.
2660 * To guard against this, we need to make a pass over the
2661 * RX queue to make sure there aren't any packets pending.
2662 * Doing it here means we can flush the receive ring at the
2663 * same time the chip is DMAing the transmit descriptors we
2666 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2667 * nature of their chips in all their marketing literature;
2668 * we may as well take advantage of it. :)
2679 struct xl_softc *sc;
2680 struct mbuf *m_head = NULL;
2681 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2682 struct xl_chain *prev_tx;
2687 if (ifp->if_flags & IFF_OACTIVE) {
2691 idx = sc->xl_cdata.xl_tx_prod;
2692 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2694 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2696 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2697 ifp->if_flags |= IFF_OACTIVE;
2701 IF_DEQUEUE(&ifp->if_snd, m_head);
2706 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2708 /* Pack the data into the descriptor. */
2709 error = xl_encap(sc, cur_tx, m_head);
2715 /* Chain it together. */
2717 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2721 * If there's a BPF listener, bounce a copy of this frame
2725 bpf_mtap(ifp, cur_tx->xl_mbuf);
2727 XL_INC(idx, XL_TX_LIST_CNT);
2728 sc->xl_cdata.xl_tx_cnt++;
2732 * If there are no packets queued, bail.
2734 if (cur_tx == NULL) {
2739 * Place the request for the upload interrupt
2740 * in the last descriptor in the chain. This way, if
2741 * we're chaining several packets at once, we'll only
2742 * get an interupt once for the whole chain rather than
2743 * once for each packet.
2745 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2747 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2748 BUS_DMASYNC_PREWRITE);
2750 /* Start transmission */
2751 sc->xl_cdata.xl_tx_prod = idx;
2752 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2755 * Set a timeout in case the chip goes out to lunch.
2766 struct xl_softc *sc = xsc;
2767 struct ifnet *ifp = &sc->arpcom.ac_if;
2769 u_int16_t rxfilt = 0;
2770 struct mii_data *mii = NULL;
2776 * Cancel pending I/O and free all RX/TX buffers.
2780 if (sc->xl_miibus == NULL) {
2781 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2784 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2788 if (sc->xl_miibus != NULL)
2789 mii = device_get_softc(sc->xl_miibus);
2791 /* Init our MAC address */
2793 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2794 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2795 sc->arpcom.ac_enaddr[i]);
2798 /* Clear the station mask. */
2799 for (i = 0; i < 3; i++)
2800 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2802 /* Reset TX and RX. */
2803 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2805 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2808 /* Init circular RX list. */
2809 error = xl_list_rx_init(sc);
2811 printf("xl%d: initialization of the rx ring failed (%d)\n",
2812 sc->xl_unit, error);
2818 /* Init TX descriptors. */
2819 if (sc->xl_type == XL_TYPE_905B)
2820 error = xl_list_tx_init_90xB(sc);
2822 error = xl_list_tx_init(sc);
2824 printf("xl%d: initialization of the tx ring failed (%d)\n",
2825 sc->xl_unit, error);
2831 * Set the TX freethresh value.
2832 * Note that this has no effect on 3c905B "cyclone"
2833 * cards but is required for 3c900/3c905 "boomerang"
2834 * cards in order to enable the download engine.
2836 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2838 /* Set the TX start threshold for best performance. */
2839 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2840 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2843 * If this is a 3c905B, also set the tx reclaim threshold.
2844 * This helps cut down on the number of tx reclaim errors
2845 * that could happen on a busy network. The chip multiplies
2846 * the register value by 16 to obtain the actual threshold
2847 * in bytes, so we divide by 16 when setting the value here.
2848 * The existing threshold value can be examined by reading
2849 * the register at offset 9 in window 5.
2851 if (sc->xl_type == XL_TYPE_905B) {
2852 CSR_WRITE_2(sc, XL_COMMAND,
2853 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2856 /* Set RX filter bits. */
2858 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2860 /* Set the individual bit to receive frames for this host only. */
2861 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2863 /* If we want promiscuous mode, set the allframes bit. */
2864 if (ifp->if_flags & IFF_PROMISC) {
2865 rxfilt |= XL_RXFILTER_ALLFRAMES;
2866 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2868 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2873 * Set capture broadcast bit to capture broadcast frames.
2875 if (ifp->if_flags & IFF_BROADCAST) {
2876 rxfilt |= XL_RXFILTER_BROADCAST;
2877 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2879 rxfilt &= ~XL_RXFILTER_BROADCAST;
2880 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2884 * Program the multicast filter, if necessary.
2886 if (sc->xl_type == XL_TYPE_905B)
2887 xl_setmulti_hash(sc);
2892 * Load the address of the RX list. We have to
2893 * stall the upload engine before we can manipulate
2894 * the uplist pointer register, then unstall it when
2895 * we're finished. We also have to wait for the
2896 * stall command to complete before proceeding.
2897 * Note that we have to do this after any RX resets
2898 * have completed since the uplist register is cleared
2901 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2903 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2904 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2908 if (sc->xl_type == XL_TYPE_905B) {
2909 /* Set polling interval */
2910 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2911 /* Load the address of the TX list */
2912 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2914 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2915 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2916 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2921 * If the coax transceiver is on, make sure to enable
2922 * the DC-DC converter.
2925 if (sc->xl_xcvr == XL_XCVR_COAX)
2926 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2928 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2931 * increase packet size to allow reception of 802.1q or ISL packets.
2932 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2933 * control register. For 3c90xB/C chips, use the RX packet size
2937 if (sc->xl_type == XL_TYPE_905B)
2938 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2941 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2942 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2943 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2946 /* Clear out the stats counters. */
2947 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2948 sc->xl_stats_no_timeout = 1;
2949 xl_stats_update(sc);
2950 sc->xl_stats_no_timeout = 0;
2952 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2953 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2956 * Enable interrupts.
2958 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2959 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2960 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2961 if (sc->xl_flags & XL_FLAG_FUNCREG)
2962 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2964 /* Set the RX early threshold */
2965 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2966 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2968 /* Enable receiver and transmitter. */
2969 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2971 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2977 /* Select window 7 for normal operations. */
2980 ifp->if_flags |= IFF_RUNNING;
2981 ifp->if_flags &= ~IFF_OACTIVE;
2983 sc->xl_stat_ch = timeout(xl_stats_update, sc, hz);
2991 * Set media options.
2997 struct xl_softc *sc;
2998 struct ifmedia *ifm = NULL;
2999 struct mii_data *mii = NULL;
3002 if (sc->xl_miibus != NULL)
3003 mii = device_get_softc(sc->xl_miibus);
3007 ifm = &mii->mii_media;
3009 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3014 xl_setmode(sc, ifm->ifm_media);
3021 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
3022 || sc->xl_media & XL_MEDIAOPT_BT4) {
3025 xl_setmode(sc, ifm->ifm_media);
3032 * Report current media status.
3035 xl_ifmedia_sts(ifp, ifmr)
3037 struct ifmediareq *ifmr;
3039 struct xl_softc *sc;
3041 struct mii_data *mii = NULL;
3044 if (sc->xl_miibus != NULL)
3045 mii = device_get_softc(sc->xl_miibus);
3048 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3049 icfg >>= XL_ICFG_CONNECTOR_BITS;
3051 ifmr->ifm_active = IFM_ETHER;
3055 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3056 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3057 ifmr->ifm_active |= IFM_FDX;
3059 ifmr->ifm_active |= IFM_HDX;
3062 if (sc->xl_type == XL_TYPE_905B &&
3063 sc->xl_media == XL_MEDIAOPT_10FL) {
3064 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3065 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3066 ifmr->ifm_active |= IFM_FDX;
3068 ifmr->ifm_active |= IFM_HDX;
3070 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3073 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3076 * XXX MII and BTX/AUTO should be separate cases.
3079 case XL_XCVR_100BTX:
3084 ifmr->ifm_active = mii->mii_media_active;
3085 ifmr->ifm_status = mii->mii_media_status;
3088 case XL_XCVR_100BFX:
3089 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3092 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg);
3100 xl_ioctl(ifp, command, data, cr)
3106 struct xl_softc *sc = ifp->if_softc;
3107 struct ifreq *ifr = (struct ifreq *) data;
3109 struct mii_data *mii = NULL;
3119 error = ether_ioctl(ifp, command, data);
3123 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3124 if (ifp->if_flags & IFF_UP) {
3125 if (ifp->if_flags & IFF_RUNNING &&
3126 ifp->if_flags & IFF_PROMISC &&
3127 !(sc->xl_if_flags & IFF_PROMISC)) {
3128 rxfilt |= XL_RXFILTER_ALLFRAMES;
3129 CSR_WRITE_2(sc, XL_COMMAND,
3130 XL_CMD_RX_SET_FILT|rxfilt);
3132 } else if (ifp->if_flags & IFF_RUNNING &&
3133 !(ifp->if_flags & IFF_PROMISC) &&
3134 sc->xl_if_flags & IFF_PROMISC) {
3135 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3136 CSR_WRITE_2(sc, XL_COMMAND,
3137 XL_CMD_RX_SET_FILT|rxfilt);
3142 if (ifp->if_flags & IFF_RUNNING)
3145 sc->xl_if_flags = ifp->if_flags;
3150 if (sc->xl_type == XL_TYPE_905B)
3151 xl_setmulti_hash(sc);
3158 if (sc->xl_miibus != NULL)
3159 mii = device_get_softc(sc->xl_miibus);
3161 error = ifmedia_ioctl(ifp, ifr,
3162 &sc->ifmedia, command);
3164 error = ifmedia_ioctl(ifp, ifr,
3165 &mii->mii_media, command);
3168 ifp->if_capenable = ifr->ifr_reqcap;
3169 if (ifp->if_capenable & IFCAP_TXCSUM)
3170 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3172 ifp->if_hwassist = 0;
3187 struct xl_softc *sc;
3188 u_int16_t status = 0;
3194 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3195 printf("xl%d: watchdog timeout\n", sc->xl_unit);
3197 if (status & XL_MEDIASTAT_CARRIER)
3198 printf("xl%d: no carrier - transceiver cable problem?\n",
3206 if (ifp->if_snd.ifq_head != NULL)
3207 (*ifp->if_start)(ifp);
3213 * Stop the adapter and free any mbufs allocated to the
3218 struct xl_softc *sc;
3223 ifp = &sc->arpcom.ac_if;
3226 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3227 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3228 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3229 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3231 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3232 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3236 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3238 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3242 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3243 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3244 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3245 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3247 /* Stop the stats updater. */
3248 untimeout(xl_stats_update, sc, sc->xl_stat_ch);
3251 * Free data in the RX lists.
3253 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3254 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3255 bus_dmamap_unload(sc->xl_mtag,
3256 sc->xl_cdata.xl_rx_chain[i].xl_map);
3257 bus_dmamap_destroy(sc->xl_mtag,
3258 sc->xl_cdata.xl_rx_chain[i].xl_map);
3259 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3260 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3263 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3265 * Free the TX list buffers.
3267 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3268 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3269 bus_dmamap_unload(sc->xl_mtag,
3270 sc->xl_cdata.xl_tx_chain[i].xl_map);
3271 bus_dmamap_destroy(sc->xl_mtag,
3272 sc->xl_cdata.xl_tx_chain[i].xl_map);
3273 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3274 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3277 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3279 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3285 * Stop all chip I/O so that the kernel's probe routines don't
3286 * get confused by errant DMAs when rebooting.
3292 struct xl_softc *sc;
3294 sc = device_get_softc(dev);
3306 struct xl_softc *sc;
3311 sc = device_get_softc(dev);
3324 struct xl_softc *sc;
3330 sc = device_get_softc(dev);
3331 ifp = &sc->arpcom.ac_if;
3334 if (ifp->if_flags & IFF_UP)