2 * Copyright (c) 2016 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Imre Vadász <imre@vdsz.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * Cherryview GPIO support.
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/errno.h>
44 #include <sys/mutex.h>
51 #include <dev/acpica/acpivar.h>
53 #include "gpio_intel_var.h"
57 #define CHV_GPIO_REG_IS 0x300
58 #define CHV_GPIO_REG_MASK 0x380
59 #define CHV_GPIO_REG_PINS 0x4400 /* start of pin control registers */
61 #define CHV_GPIO_REGOFF_CTL0 0x0
62 #define CHV_GPIO_REGOFF_CTL1 0x4
64 #define CHV_GPIO_CTL0_RXSTATE 0x00000001u
65 #define CHV_GPIO_CTL0_TXSTATE 0x00000002u
66 #define CHV_GPIO_CTL0_GPIOCFG_MASK 0x00000700u
67 #define CHV_GPIO_CTL0_GPIOEN 0x00008000u
68 #define CHV_GPIO_CTL0_PULLUP 0x00800000u
69 #define CHV_GPIO_CTL1_INTCFG_MASK 0x00000007u
70 #define CHV_GPIO_CTL1_INVRXDATA 0x00000040u
72 #define CHV_GPIO_PINSIZE 0x8 /* 8 bytes for each pin */
73 #define CHV_GPIO_PINCHUNK 15 /* 15 pins at a time */
74 #define CHV_GPIO_PININC 0x400 /* every 0x400 bytes */
76 #define PIN_ADDRESS(x) \
77 (CHV_GPIO_REG_PINS + \
78 ((x) / CHV_GPIO_PINCHUNK) * CHV_GPIO_PININC + \
79 ((x) % CHV_GPIO_PINCHUNK) * CHV_GPIO_PINSIZE)
81 #define PIN_CTL0(x) (PIN_ADDRESS(x) + CHV_GPIO_REGOFF_CTL0)
82 #define PIN_CTL1(x) (PIN_ADDRESS(x) + CHV_GPIO_REGOFF_CTL1)
84 static void gpio_cherryview_init(struct gpio_intel_softc *sc);
85 static void gpio_cherryview_intr(void *arg);
86 static int gpio_cherryview_map_intr(struct gpio_intel_softc *sc,
87 uint16_t pin, int trigger, int polarity, int termination,
88 void *arg, driver_intr_t *handler);
89 static void gpio_cherryview_unmap_intr(struct gpio_intel_softc *sc,
91 static int gpio_cherryview_read_pin(struct gpio_intel_softc *sc,
93 static void gpio_cherryview_write_pin(struct gpio_intel_softc *sc,
94 uint16_t pin, int value);
96 static struct gpio_intel_fns gpio_cherryview_fns = {
97 .init = gpio_cherryview_init,
98 .intr = gpio_cherryview_intr,
99 .map_intr = gpio_cherryview_map_intr,
100 .unmap_intr = gpio_cherryview_unmap_intr,
101 .read_pin = gpio_cherryview_read_pin,
102 .write_pin = gpio_cherryview_write_pin,
106 static struct pinrange chv_sw_ranges[] = {
118 static struct pinrange chv_n_ranges[] = {
128 static struct pinrange chv_e_ranges[] = {
135 static struct pinrange chv_se_ranges[] = {
146 gpio_cherryview_matchuid(struct gpio_intel_softc *sc)
150 handle = acpi_get_handle(sc->dev);
151 if (acpi_MatchUid(handle, "1")) {
152 sc->ranges = chv_sw_ranges;
153 } else if (acpi_MatchUid(handle, "2")) {
154 sc->ranges = chv_n_ranges;
155 } else if (acpi_MatchUid(handle, "3")) {
156 sc->ranges = chv_e_ranges;
157 } else if (acpi_MatchUid(handle, "4")) {
158 sc->ranges = chv_se_ranges;
163 sc->fns = &gpio_cherryview_fns;
169 gpio_cherryview_init(struct gpio_intel_softc *sc)
171 /* mask and clear all interrupt lines */
172 bus_write_4(sc->mem_res, CHV_GPIO_REG_MASK, 0);
173 bus_write_4(sc->mem_res, CHV_GPIO_REG_IS, 0xffff);
177 gpio_cherryview_intr(void *arg)
179 struct gpio_intel_softc *sc = (struct gpio_intel_softc *)arg;
180 struct pin_intr_map *mapping;
184 status = bus_read_4(sc->mem_res, CHV_GPIO_REG_IS);
185 for (i = 0; i < 16; i++) {
186 if (status & (1U << i)) {
187 mapping = &sc->intrmaps[i];
188 if (!mapping->is_level) {
189 bus_write_4(sc->mem_res, CHV_GPIO_REG_IS,
192 if (mapping->pin != -1 && mapping->handler != NULL)
193 mapping->handler(mapping->arg);
194 if (mapping->is_level) {
195 bus_write_4(sc->mem_res, CHV_GPIO_REG_IS,
202 /* XXX Add shared/exclusive argument. */
204 gpio_cherryview_map_intr(struct gpio_intel_softc *sc, uint16_t pin, int trigger,
205 int polarity, int termination, void *arg, driver_intr_t *handler)
207 uint32_t reg, reg1, reg2;
208 uint32_t intcfg, new_intcfg, gpiocfg, new_gpiocfg;
211 reg1 = bus_read_4(sc->mem_res, PIN_CTL0(pin));
212 reg2 = bus_read_4(sc->mem_res, PIN_CTL1(pin));
213 device_printf(sc->dev,
214 "pin=%d trigger=%d polarity=%d ctrl0=0x%08x ctrl1=0x%08x\n",
215 pin, trigger, polarity, reg1, reg2);
217 new_intcfg = intcfg = reg2 & CHV_GPIO_CTL1_INTCFG_MASK;
218 new_gpiocfg = gpiocfg = reg1 & CHV_GPIO_CTL0_GPIOCFG_MASK;
221 * Sanity Checks, for now we just abort if the configuration doesn't
222 * match our expectations.
224 if (!(reg1 & CHV_GPIO_CTL0_GPIOEN)) {
225 device_printf(sc->dev, "GPIO mode is disabled\n");
228 if (gpiocfg != 0x0 && gpiocfg != 0x200) {
229 device_printf(sc->dev, "RX is disabled\n");
230 if (gpiocfg == 0x100)
232 else if (gpiocfg == 0x300)
237 if (trigger == ACPI_LEVEL_SENSITIVE) {
239 device_printf(sc->dev,
240 "trigger is %x, should be 4 (Level)\n", intcfg);
243 if (polarity == ACPI_ACTIVE_BOTH) {
244 device_printf(sc->dev,
245 "ACTIVE_BOTH incompatible with level trigger\n");
247 } else if (polarity == ACPI_ACTIVE_LOW) {
248 if (!(reg2 & CHV_GPIO_CTL1_INVRXDATA)) {
249 device_printf(sc->dev,
250 "Invert RX not enabled (needed for "
251 "level/low trigger/polarity)\n");
255 if (reg2 & CHV_GPIO_CTL1_INVRXDATA) {
256 device_printf(sc->dev,
257 "Invert RX should not be enabled for "
258 "level/high trigger/polarity\n");
264 * For edge-triggered interrupts it's definitely harmless to
265 * change between rising-edge, falling-edge and both-edges
268 if (polarity == ACPI_ACTIVE_HIGH && intcfg != 2) {
269 device_printf(sc->dev,
270 "Wrong interrupt configuration, is 0x%x should "
271 "be 0x%x\n", intcfg, 2);
272 if (intcfg == 1 || intcfg == 3)
276 } else if (polarity == ACPI_ACTIVE_LOW && intcfg != 1) {
277 device_printf(sc->dev,
278 "Wrong interrupt configuration, is 0x%x should "
279 "be 0x%x\n", intcfg, 1);
280 if (intcfg == 2 || intcfg == 3)
284 } else if (polarity == ACPI_ACTIVE_BOTH && intcfg != 3) {
285 device_printf(sc->dev,
286 "Wrong interrupt configuration, is 0x%x should "
287 "be 0x%x\n", intcfg, 3);
288 if (intcfg == 1 || intcfg == 2)
294 if (termination == ACPI_PIN_CONFIG_PULLUP &&
295 !(reg1 & CHV_GPIO_CTL0_PULLUP)) {
296 device_printf(sc->dev,
297 "Wrong termination, is pull-down, should be pull-up\n");
299 } else if (termination == ACPI_PIN_CONFIG_PULLDOWN &&
300 (reg1 & CHV_GPIO_CTL0_PULLUP)) {
301 device_printf(sc->dev,
302 "Wrong termination, is pull-up, should be pull-down\n");
306 /* Check if the interrupt/line configured by BIOS/UEFI is unused */
307 i = (reg1 >> 28) & 0xf;
308 if (sc->intrmaps[i].pin != -1) {
309 device_printf(sc->dev, "Interrupt line %d already used\n", i);
313 if (new_intcfg != intcfg) {
314 device_printf(sc->dev,
315 "Switching interrupt configuration from 0x%x to 0x%x\n",
317 reg = reg2 & ~CHV_GPIO_CTL1_INTCFG_MASK;
318 reg |= (new_intcfg & CHV_GPIO_CTL1_INTCFG_MASK) << 0;
319 bus_write_4(sc->mem_res, PIN_CTL1(pin), reg);
322 if (new_gpiocfg != gpiocfg) {
323 device_printf(sc->dev,
324 "Switching gpio configuration from 0x%x to 0x%x\n",
325 gpiocfg, new_gpiocfg);
326 reg = reg1 & ~CHV_GPIO_CTL0_GPIOCFG_MASK;
327 reg |= (new_gpiocfg & CHV_GPIO_CTL0_GPIOCFG_MASK) << 0;
328 bus_write_4(sc->mem_res, PIN_CTL0(pin), reg);
331 sc->intrmaps[i].pin = pin;
332 sc->intrmaps[i].arg = arg;
333 sc->intrmaps[i].handler = handler;
334 sc->intrmaps[i].orig_intcfg = intcfg;
335 sc->intrmaps[i].orig_gpiocfg = gpiocfg;
337 if (trigger == ACPI_LEVEL_SENSITIVE)
338 sc->intrmaps[i].is_level = 1;
340 sc->intrmaps[i].is_level = 0;
342 /* unmask interrupt */
343 reg = bus_read_4(sc->mem_res, CHV_GPIO_REG_MASK);
345 bus_write_4(sc->mem_res, CHV_GPIO_REG_MASK, reg);
351 gpio_cherryview_unmap_intr(struct gpio_intel_softc *sc, uint16_t pin)
353 uint32_t reg, intcfg, gpiocfg;
356 for (i = 0; i < 16; i++) {
357 if (sc->intrmaps[i].pin == pin) {
358 intcfg = sc->intrmaps[i].orig_intcfg;
359 intcfg &= CHV_GPIO_CTL1_INTCFG_MASK;
361 gpiocfg = sc->intrmaps[i].orig_gpiocfg;
362 gpiocfg &= CHV_GPIO_CTL0_GPIOCFG_MASK;
364 sc->intrmaps[i].pin = -1;
365 sc->intrmaps[i].arg = NULL;
366 sc->intrmaps[i].handler = NULL;
367 sc->intrmaps[i].is_level = 0;
368 sc->intrmaps[i].orig_intcfg = 0;
369 sc->intrmaps[i].orig_gpiocfg = 0;
371 /* mask interrupt line */
372 reg = bus_read_4(sc->mem_res, CHV_GPIO_REG_MASK);
374 bus_write_4(sc->mem_res, CHV_GPIO_REG_MASK, reg);
376 /* Restore interrupt configuration if needed */
377 reg = bus_read_4(sc->mem_res, PIN_CTL1(pin));
378 if ((reg & CHV_GPIO_CTL1_INTCFG_MASK) != intcfg) {
379 reg &= ~CHV_GPIO_CTL1_INTCFG_MASK;
381 bus_write_4(sc->mem_res, PIN_CTL1(pin), reg);
384 /* Restore gpio configuration if needed */
385 reg = bus_read_4(sc->mem_res, PIN_CTL0(pin));
386 if ((reg & CHV_GPIO_CTL0_GPIOCFG_MASK) != gpiocfg) {
387 reg &= ~CHV_GPIO_CTL0_GPIOCFG_MASK;
389 bus_write_4(sc->mem_res, PIN_CTL0(pin), reg);
396 gpio_cherryview_read_pin(struct gpio_intel_softc *sc, uint16_t pin)
401 reg = bus_read_4(sc->mem_res, PIN_CTL0(pin));
402 /* Verify that RX is enabled */
403 KKASSERT((reg & CHV_GPIO_CTL0_GPIOCFG_MASK) == 0x0 ||
404 (reg & CHV_GPIO_CTL0_GPIOCFG_MASK) == 0x200);
406 if (reg & CHV_GPIO_CTL0_RXSTATE)
415 gpio_cherryview_write_pin(struct gpio_intel_softc *sc, uint16_t pin, int value)
419 reg2 = bus_read_4(sc->mem_res, PIN_CTL1(pin));
420 /* Verify that interrupt is disabled */
421 KKASSERT((reg2 & CHV_GPIO_CTL1_INTCFG_MASK) == 0);
423 reg1 = bus_read_4(sc->mem_res, PIN_CTL0(pin));
424 /* Verify that TX is enabled */
425 KKASSERT((reg1 & CHV_GPIO_CTL0_GPIOCFG_MASK) == 0 ||
426 (reg1 & CHV_GPIO_CTL0_GPIOCFG_MASK) == 0x100);
429 reg1 |= CHV_GPIO_CTL0_TXSTATE;
431 reg1 &= ~CHV_GPIO_CTL0_TXSTATE;
432 bus_write_4(sc->mem_res, PIN_CTL0(pin), reg1);