2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/mpapic.h>
60 #include <machine/psl.h>
61 #include <machine/segments.h>
62 #include <machine/tss.h>
63 #include <machine/specialreg.h>
64 #include <machine/globaldata.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine_base/isa/intr_machdep.h> /* IPIs */
70 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define BIOS_BASE (0xf0000)
77 #define BIOS_BASE2 (0xe0000)
78 #define BIOS_SIZE (0x10000)
79 #define BIOS_COUNT (BIOS_SIZE/4)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 #define PROCENTRY_FLAG_EN 0x01
87 #define PROCENTRY_FLAG_BP 0x02
88 #define IOAPICENTRY_FLAG_EN 0x01
91 /* MP Floating Pointer Structure */
92 typedef struct MPFPS {
105 /* MP Configuration Table Header */
106 typedef struct MPCTH {
108 u_short base_table_length;
112 u_char product_id[12];
113 void *oem_table_pointer;
114 u_short oem_table_size;
117 u_short extended_table_length;
118 u_char extended_table_checksum;
123 typedef struct PROCENTRY {
128 u_long cpu_signature;
129 u_long feature_flags;
134 typedef struct BUSENTRY {
140 typedef struct IOAPICENTRY {
146 } *io_apic_entry_ptr;
148 typedef struct INTENTRY {
158 /* descriptions of MP basetable entries */
159 typedef struct BASETABLE_ENTRY {
168 vm_size_t mp_cth_mapsz;
171 typedef int (*mptable_iter_func)(void *, const void *, int);
174 * this code MUST be enabled here and in mpboot.s.
175 * it follows the very early stages of AP boot by placing values in CMOS ram.
176 * it NORMALLY will never be needed and thus the primitive method for enabling.
179 #if defined(CHECK_POINTS)
180 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
181 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
183 #define CHECK_INIT(D); \
184 CHECK_WRITE(0x34, (D)); \
185 CHECK_WRITE(0x35, (D)); \
186 CHECK_WRITE(0x36, (D)); \
187 CHECK_WRITE(0x37, (D)); \
188 CHECK_WRITE(0x38, (D)); \
189 CHECK_WRITE(0x39, (D));
191 #define CHECK_PRINT(S); \
192 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
201 #else /* CHECK_POINTS */
203 #define CHECK_INIT(D)
204 #define CHECK_PRINT(S)
206 #endif /* CHECK_POINTS */
209 * Values to send to the POST hardware.
211 #define MP_BOOTADDRESS_POST 0x10
212 #define MP_PROBE_POST 0x11
213 #define MPTABLE_PASS1_POST 0x12
215 #define MP_START_POST 0x13
216 #define MP_ENABLE_POST 0x14
217 #define MPTABLE_PASS2_POST 0x15
219 #define START_ALL_APS_POST 0x16
220 #define INSTALL_AP_TRAMP_POST 0x17
221 #define START_AP_POST 0x18
223 #define MP_ANNOUNCE_POST 0x19
225 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
226 int current_postcode;
228 /** XXX FIXME: what system files declare these??? */
229 extern struct region_descriptor r_gdt, r_idt;
231 int mp_naps; /* # of Applications processors */
232 #ifdef SMP /* APIC-IO */
233 static int mp_nbusses; /* # of busses */
234 int mp_napics; /* # of IO APICs */
235 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
236 u_int32_t *io_apic_versions;
240 u_int32_t cpu_apic_versions[MAXCPU];
242 extern int64_t tsc_offsets[];
244 extern u_long ebda_addr;
246 #ifdef SMP /* APIC-IO */
247 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
251 * APIC ID logical/physical mapping structures.
252 * We oversize these to simplify boot-time config.
254 int cpu_num_to_apic_id[NAPICID];
255 #ifdef SMP /* APIC-IO */
256 int io_num_to_apic_id[NAPICID];
258 int apic_id_to_logical[NAPICID];
260 /* AP uses this during bootstrap. Do not staticize. */
264 /* Hotwire a 0->4MB V==P mapping */
265 extern pt_entry_t *KPTphys;
268 * SMP page table page. Setup by locore to point to a page table
269 * page from which we allocate per-cpu privatespace areas io_apics,
273 #define IO_MAPPING_START_INDEX \
274 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
276 extern pt_entry_t *SMPpt;
277 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
279 struct pcb stoppcbs[MAXCPU];
281 static basetable_entry basetable_entry_types[] =
283 {0, 20, "Processor"},
291 * Local data and functions.
294 static u_int boot_address;
295 static u_int base_memory;
296 static int mp_finish;
298 static void mp_enable(u_int boot_addr);
300 static int mptable_iterate_entries(const mpcth_t,
301 mptable_iter_func, void *);
302 static int mptable_probe(void);
303 static int mptable_search(void);
304 static int mptable_check(vm_paddr_t);
305 static int mptable_search_sig(u_int32_t target, int count);
306 static int mptable_hyperthread_fixup(u_int, int);
307 #ifdef SMP /* APIC-IO */
308 static void mptable_pass1(struct mptable_pos *);
309 static void mptable_pass2(struct mptable_pos *);
310 static void mptable_default(int type);
311 static void mptable_fix(void);
313 static int mptable_map(struct mptable_pos *, vm_paddr_t);
314 static void mptable_unmap(struct mptable_pos *);
315 static void mptable_imcr(struct mptable_pos *);
317 static int mptable_lapic_probe(struct lapic_enumerator *);
318 static void mptable_lapic_enumerate(struct lapic_enumerator *);
319 static void mptable_lapic_default(void);
321 #ifdef SMP /* APIC-IO */
322 static void setup_apic_irq_mapping(void);
323 static int apic_int_is_bus_type(int intr, int bus_type);
325 static int start_all_aps(u_int boot_addr);
326 static void install_ap_tramp(u_int boot_addr);
327 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
328 static int smitest(void);
330 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
331 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
332 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
335 * Calculate usable address in base memory for AP trampoline code.
338 mp_bootaddress(u_int basemem)
340 POSTCODE(MP_BOOTADDRESS_POST);
342 base_memory = basemem;
344 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
345 if ((base_memory - boot_address) < bootMP_size)
346 boot_address -= 4096; /* not enough, lower by 4k */
357 mpfps_paddr = mptable_search();
358 if (mptable_check(mpfps_paddr))
365 * Look for an Intel MP spec table (ie, SMP capable hardware).
374 * Make sure our SMPpt[] page table is big enough to hold all the
377 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
379 POSTCODE(MP_PROBE_POST);
381 /* see if EBDA exists */
382 if (ebda_addr != 0) {
383 /* search first 1K of EBDA */
384 target = (u_int32_t)ebda_addr;
385 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
388 /* last 1K of base memory, effective 'top of base' passed in */
389 target = (u_int32_t)(base_memory - 0x400);
390 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
394 /* search the BIOS */
395 target = (u_int32_t)BIOS_BASE;
396 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
399 /* search the extended BIOS */
400 target = (u_int32_t)BIOS_BASE2;
401 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
408 struct mptable_check_cbarg {
414 mptable_check_callback(void *xarg, const void *pos, int type)
416 const struct PROCENTRY *ent;
417 struct mptable_check_cbarg *arg = xarg;
423 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
427 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
428 if (arg->found_bsp) {
429 kprintf("more than one BSP in base MP table\n");
438 mptable_check(vm_paddr_t mpfps_paddr)
440 struct mptable_pos mpt;
441 struct mptable_check_cbarg arg;
445 if (mpfps_paddr == 0)
448 error = mptable_map(&mpt, mpfps_paddr);
452 if (mpt.mp_fps->mpfb1 != 0)
460 if (cth->apic_address == 0)
463 bzero(&arg, sizeof(arg));
464 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
466 if (arg.cpu_count == 0) {
467 kprintf("MP table contains no processor entries\n");
469 } else if (!arg.found_bsp) {
470 kprintf("MP table does not contains BSP entry\n");
480 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
482 int count, total_size;
483 const void *position;
485 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
486 total_size = cth->base_table_length - sizeof(struct MPCTH);
487 position = (const uint8_t *)cth + sizeof(struct MPCTH);
488 count = cth->entry_count;
493 KKASSERT(total_size >= 0);
494 if (total_size == 0) {
495 kprintf("invalid base MP table, "
496 "entry count and length mismatch\n");
500 type = *(const uint8_t *)position;
502 case 0: /* processor_entry */
503 case 1: /* bus_entry */
504 case 2: /* io_apic_entry */
505 case 3: /* int_entry */
506 case 4: /* int_entry */
509 kprintf("unknown base MP table entry type %d\n", type);
513 if (total_size < basetable_entry_types[type].length) {
514 kprintf("invalid base MP table length, "
515 "does not contain all entries\n");
518 total_size -= basetable_entry_types[type].length;
520 error = func(arg, position, type);
524 position = (const uint8_t *)position +
525 basetable_entry_types[type].length;
532 * Startup the SMP processors.
537 POSTCODE(MP_START_POST);
538 mp_enable(boot_address);
543 * Print various information about the SMP system hardware and setup.
550 POSTCODE(MP_ANNOUNCE_POST);
552 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
553 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
554 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
555 for (x = 1; x <= mp_naps; ++x) {
556 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
557 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
560 if (apic_io_enable) {
561 for (x = 0; x < mp_napics; ++x) {
562 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
563 kprintf(", version: 0x%08x", io_apic_versions[x]);
564 kprintf(", at 0x%08lx\n", io_apic_address[x]);
567 kprintf(" Warning: APIC I/O disabled\n");
572 * AP cpu's call this to sync up protected mode.
574 * WARNING! We must ensure that the cpu is sufficiently initialized to
575 * be able to use to the FP for our optimized bzero/bcopy code before
576 * we enter more mainstream C code.
578 * WARNING! %fs is not set up on entry. This routine sets up %fs.
584 int x, myid = bootAP;
586 struct mdglobaldata *md;
587 struct privatespace *ps;
589 ps = &CPU_prvspace[myid];
591 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
592 gdt_segs[GPROC0_SEL].ssd_base =
593 (int) &ps->mdglobaldata.gd_common_tss;
594 ps->mdglobaldata.mi.gd_prvspace = ps;
596 for (x = 0; x < NGDT; x++) {
597 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
600 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
601 r_gdt.rd_base = (int) &gdt[myid * NGDT];
602 lgdt(&r_gdt); /* does magic intra-segment return */
607 mdcpu->gd_currentldt = _default_ldt;
609 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
610 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
612 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
614 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
615 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
616 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
617 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
618 md->gd_common_tssd = *md->gd_tss_gdt;
622 * Set to a known state:
623 * Set by mpboot.s: CR0_PG, CR0_PE
624 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
627 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
629 pmap_set_opt(); /* PSE/4MB pages, etc */
631 /* set up CPU registers and state */
634 /* set up FPU state on the AP */
635 npxinit(__INITIAL_NPXCW__);
637 /* set up SSE registers */
641 /*******************************************************************
642 * local functions and data
646 * start the SMP system
649 mp_enable(u_int boot_addr)
653 vm_paddr_t mpfps_paddr;
654 struct mptable_pos mpt;
656 POSTCODE(MP_ENABLE_POST);
660 mpfps_paddr = mptable_probe();
662 mptable_map(&mpt, mpfps_paddr);
666 if (apic_io_enable) {
669 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
671 mptable_map(&mpt, mpfps_paddr);
674 * Examine the MP table for needed info
681 /* Post scan cleanup */
684 setup_apic_irq_mapping();
686 /* fill the LOGICAL io_apic_versions table */
687 for (apic = 0; apic < mp_napics; ++apic) {
688 ux = io_apic_read(apic, IOAPIC_VER);
689 io_apic_versions[apic] = ux;
690 io_apic_set_id(apic, IO_TO_ID(apic));
693 /* program each IO APIC in the system */
694 for (apic = 0; apic < mp_napics; ++apic)
695 if (io_apic_setup(apic) < 0)
696 panic("IO APIC setup failure");
701 * These are required for SMP operation
704 /* install a 'Spurious INTerrupt' vector */
705 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
706 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
708 /* install an inter-CPU IPI for TLB invalidation */
709 setidt(XINVLTLB_OFFSET, Xinvltlb,
710 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
712 /* install an inter-CPU IPI for IPIQ messaging */
713 setidt(XIPIQ_OFFSET, Xipiq,
714 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
716 /* install a timer vector */
717 setidt(XTIMER_OFFSET, Xtimer,
718 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
720 /* install an inter-CPU IPI for CPU stop/restart */
721 setidt(XCPUSTOP_OFFSET, Xcpustop,
722 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
724 /* start each Application Processor */
725 start_all_aps(boot_addr);
730 * look for the MP spec signature
733 /* string defined by the Intel MP Spec as identifying the MP table */
734 #define MP_SIG 0x5f504d5f /* _MP_ */
735 #define NEXT(X) ((X) += 4)
737 mptable_search_sig(u_int32_t target, int count)
743 KKASSERT(target != 0);
745 map_size = count * sizeof(u_int32_t);
746 addr = pmap_mapdev((vm_paddr_t)target, map_size);
749 for (x = 0; x < count; NEXT(x)) {
750 if (addr[x] == MP_SIG) {
751 /* make array index a byte index */
752 ret = target + (x * sizeof(u_int32_t));
757 pmap_unmapdev((vm_offset_t)addr, map_size);
762 typedef struct BUSDATA {
764 enum busTypes bus_type;
767 typedef struct INTDATA {
777 typedef struct BUSTYPENAME {
782 static bus_type_name bus_type_table[] =
788 {UNKNOWN_BUSTYPE, "---"},
791 {UNKNOWN_BUSTYPE, "---"},
792 {UNKNOWN_BUSTYPE, "---"},
793 {UNKNOWN_BUSTYPE, "---"},
794 {UNKNOWN_BUSTYPE, "---"},
795 {UNKNOWN_BUSTYPE, "---"},
797 {UNKNOWN_BUSTYPE, "---"},
798 {UNKNOWN_BUSTYPE, "---"},
799 {UNKNOWN_BUSTYPE, "---"},
800 {UNKNOWN_BUSTYPE, "---"},
802 {UNKNOWN_BUSTYPE, "---"}
804 /* from MP spec v1.4, table 5-1 */
805 static int default_data[7][5] =
807 /* nbus, id0, type0, id1, type1 */
808 {1, 0, ISA, 255, 255},
809 {1, 0, EISA, 255, 255},
810 {1, 0, EISA, 255, 255},
811 {1, 0, MCA, 255, 255},
813 {2, 0, EISA, 1, PCI},
819 static bus_datum *bus_data;
821 /* the IO INT data, one entry per possible APIC INTerrupt */
822 static io_int *io_apic_ints;
825 static int processor_entry (const struct PROCENTRY *entry, int cpu);
826 static int bus_entry (const struct BUSENTRY *entry, int bus);
827 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
828 static int int_entry (const struct INTENTRY *entry, int intr);
829 static int lookup_bus_type (char *name);
832 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
834 const struct IOAPICENTRY *ioapic_ent;
837 case 1: /* bus_entry */
841 case 2: /* io_apic_entry */
843 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
844 io_apic_address[mp_napics++] =
845 (vm_offset_t)ioapic_ent->apic_address;
849 case 3: /* int_entry */
857 * 1st pass on motherboard's Intel MP specification table.
866 mptable_pass1(struct mptable_pos *mpt)
871 POSTCODE(MPTABLE_PASS1_POST);
874 KKASSERT(fps != NULL);
876 /* clear various tables */
877 for (x = 0; x < NAPICID; ++x)
878 io_apic_address[x] = ~0; /* IO APIC address table */
884 /* check for use of 'default' configuration */
885 if (fps->mpfb1 != 0) {
886 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
887 mp_nbusses = default_data[fps->mpfb1 - 1][0];
893 error = mptable_iterate_entries(mpt->mp_cth,
894 mptable_ioapic_pass1_callback, NULL);
896 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
900 struct mptable_ioapic2_cbarg {
907 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
909 struct mptable_ioapic2_cbarg *arg = xarg;
913 if (bus_entry(pos, arg->bus))
918 if (io_apic_entry(pos, arg->apic))
923 if (int_entry(pos, arg->intr))
931 * 2nd pass on motherboard's Intel MP specification table.
934 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
935 * IO_TO_ID(N), logical IO to APIC ID table
940 mptable_pass2(struct mptable_pos *mpt)
942 struct mptable_ioapic2_cbarg arg;
946 POSTCODE(MPTABLE_PASS2_POST);
949 KKASSERT(fps != NULL);
951 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
953 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
954 M_DEVBUF, M_WAITOK | M_ZERO);
955 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
957 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
960 for (x = 0; x < mp_napics; x++)
961 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
963 /* clear various tables */
964 for (x = 0; x < NAPICID; ++x) {
965 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
966 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
969 /* clear bus data table */
970 for (x = 0; x < mp_nbusses; ++x)
971 bus_data[x].bus_id = 0xff;
973 /* clear IO APIC INT table */
974 for (x = 0; x < (nintrs + 1); ++x) {
975 io_apic_ints[x].int_type = 0xff;
976 io_apic_ints[x].int_vector = 0xff;
979 /* check for use of 'default' configuration */
980 if (fps->mpfb1 != 0) {
981 mptable_default(fps->mpfb1);
985 bzero(&arg, sizeof(arg));
986 error = mptable_iterate_entries(mpt->mp_cth,
987 mptable_ioapic_pass2_callback, &arg);
989 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
993 * Check if we should perform a hyperthreading "fix-up" to
994 * enumerate any logical CPU's that aren't already listed
997 * XXX: We assume that all of the physical CPUs in the
998 * system have the same number of logical CPUs.
1000 * XXX: We assume that APIC ID's are allocated such that
1001 * the APIC ID's for a physical processor are aligned
1002 * with the number of logical CPU's in the processor.
1005 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1007 int i, id, lcpus_max, logical_cpus;
1009 if ((cpu_feature & CPUID_HTT) == 0)
1012 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1016 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
1018 * INSTRUCTION SET REFERENCE, A-M (#253666)
1019 * Page 3-181, Table 3-20
1020 * "The nearest power-of-2 integer that is not smaller
1021 * than EBX[23:16] is the number of unique initial APIC
1022 * IDs reserved for addressing different logical
1023 * processors in a physical package."
1025 for (i = 0; ; ++i) {
1026 if ((1 << i) >= lcpus_max) {
1033 KKASSERT(cpu_count != 0);
1034 if (cpu_count == lcpus_max) {
1035 /* We have nothing to fix */
1037 } else if (cpu_count == 1) {
1038 /* XXX this may be incorrect */
1039 logical_cpus = lcpus_max;
1041 int cur, prev, dist;
1044 * Calculate the distances between two nearest
1045 * APIC IDs. If all such distances are same,
1046 * then it is the number of missing cpus that
1047 * we are going to fill later.
1049 dist = cur = prev = -1;
1050 for (id = 0; id < MAXCPU; ++id) {
1051 if ((id_mask & 1 << id) == 0)
1056 int new_dist = cur - prev;
1062 * Make sure that all distances
1063 * between two nearest APIC IDs
1066 if (dist != new_dist)
1074 /* Must be power of 2 */
1075 if (dist & (dist - 1))
1078 /* Can't exceed CPU package capacity */
1079 if (dist > lcpus_max)
1080 logical_cpus = lcpus_max;
1082 logical_cpus = dist;
1086 * For each APIC ID of a CPU that is set in the mask,
1087 * scan the other candidate APIC ID's for this
1088 * physical processor. If any of those ID's are
1089 * already in the table, then kill the fixup.
1091 for (id = 0; id < MAXCPU; id++) {
1092 if ((id_mask & 1 << id) == 0)
1094 /* First, make sure we are on a logical_cpus boundary. */
1095 if (id % logical_cpus != 0)
1097 for (i = id + 1; i < id + logical_cpus; i++)
1098 if ((id_mask & 1 << i) != 0)
1101 return logical_cpus;
1105 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1109 vm_size_t cth_mapsz = 0;
1111 bzero(mpt, sizeof(*mpt));
1113 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1114 if (fps->pap != 0) {
1116 * Map configuration table header to get
1117 * the base table size
1119 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1120 cth_mapsz = cth->base_table_length;
1121 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1123 if (cth_mapsz < sizeof(*cth)) {
1124 kprintf("invalid base MP table length %d\n",
1126 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1131 * Map the base table
1133 cth = pmap_mapdev(fps->pap, cth_mapsz);
1138 mpt->mp_cth_mapsz = cth_mapsz;
1144 mptable_unmap(struct mptable_pos *mpt)
1146 if (mpt->mp_cth != NULL) {
1147 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1149 mpt->mp_cth_mapsz = 0;
1151 if (mpt->mp_fps != NULL) {
1152 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1158 assign_apic_irq(int apic, int intpin, int irq)
1162 if (int_to_apicintpin[irq].ioapic != -1)
1163 panic("assign_apic_irq: inconsistent table");
1165 int_to_apicintpin[irq].ioapic = apic;
1166 int_to_apicintpin[irq].int_pin = intpin;
1167 int_to_apicintpin[irq].apic_address = ioapic[apic];
1168 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1170 for (x = 0; x < nintrs; x++) {
1171 if ((io_apic_ints[x].int_type == 0 ||
1172 io_apic_ints[x].int_type == 3) &&
1173 io_apic_ints[x].int_vector == 0xff &&
1174 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1175 io_apic_ints[x].dst_apic_int == intpin)
1176 io_apic_ints[x].int_vector = irq;
1181 revoke_apic_irq(int irq)
1187 if (int_to_apicintpin[irq].ioapic == -1)
1188 panic("revoke_apic_irq: inconsistent table");
1190 oldapic = int_to_apicintpin[irq].ioapic;
1191 oldintpin = int_to_apicintpin[irq].int_pin;
1193 int_to_apicintpin[irq].ioapic = -1;
1194 int_to_apicintpin[irq].int_pin = 0;
1195 int_to_apicintpin[irq].apic_address = NULL;
1196 int_to_apicintpin[irq].redirindex = 0;
1198 for (x = 0; x < nintrs; x++) {
1199 if ((io_apic_ints[x].int_type == 0 ||
1200 io_apic_ints[x].int_type == 3) &&
1201 io_apic_ints[x].int_vector != 0xff &&
1202 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1203 io_apic_ints[x].dst_apic_int == oldintpin)
1204 io_apic_ints[x].int_vector = 0xff;
1212 allocate_apic_irq(int intr)
1218 if (io_apic_ints[intr].int_vector != 0xff)
1219 return; /* Interrupt handler already assigned */
1221 if (io_apic_ints[intr].int_type != 0 &&
1222 (io_apic_ints[intr].int_type != 3 ||
1223 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1224 io_apic_ints[intr].dst_apic_int == 0)))
1225 return; /* Not INT or ExtInt on != (0, 0) */
1228 while (irq < APIC_INTMAPSIZE &&
1229 int_to_apicintpin[irq].ioapic != -1)
1232 if (irq >= APIC_INTMAPSIZE)
1233 return; /* No free interrupt handlers */
1235 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1236 intpin = io_apic_ints[intr].dst_apic_int;
1238 assign_apic_irq(apic, intpin, irq);
1239 io_apic_setup_intpin(apic, intpin);
1244 swap_apic_id(int apic, int oldid, int newid)
1251 return; /* Nothing to do */
1253 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1254 apic, oldid, newid);
1256 /* Swap physical APIC IDs in interrupt entries */
1257 for (x = 0; x < nintrs; x++) {
1258 if (io_apic_ints[x].dst_apic_id == oldid)
1259 io_apic_ints[x].dst_apic_id = newid;
1260 else if (io_apic_ints[x].dst_apic_id == newid)
1261 io_apic_ints[x].dst_apic_id = oldid;
1264 /* Swap physical APIC IDs in IO_TO_ID mappings */
1265 for (oapic = 0; oapic < mp_napics; oapic++)
1266 if (IO_TO_ID(oapic) == newid)
1269 if (oapic < mp_napics) {
1270 kprintf("Changing APIC ID for IO APIC #%d from "
1271 "%d to %d in MP table\n",
1272 oapic, newid, oldid);
1273 IO_TO_ID(oapic) = oldid;
1275 IO_TO_ID(apic) = newid;
1280 fix_id_to_io_mapping(void)
1284 for (x = 0; x < NAPICID; x++)
1287 for (x = 0; x <= mp_naps; x++)
1288 if (CPU_TO_ID(x) < NAPICID)
1289 ID_TO_IO(CPU_TO_ID(x)) = x;
1291 for (x = 0; x < mp_napics; x++)
1292 if (IO_TO_ID(x) < NAPICID)
1293 ID_TO_IO(IO_TO_ID(x)) = x;
1298 first_free_apic_id(void)
1302 for (freeid = 0; freeid < NAPICID; freeid++) {
1303 for (x = 0; x <= mp_naps; x++)
1304 if (CPU_TO_ID(x) == freeid)
1308 for (x = 0; x < mp_napics; x++)
1309 if (IO_TO_ID(x) == freeid)
1320 io_apic_id_acceptable(int apic, int id)
1322 int cpu; /* Logical CPU number */
1323 int oapic; /* Logical IO APIC number for other IO APIC */
1326 return 0; /* Out of range */
1328 for (cpu = 0; cpu <= mp_naps; cpu++)
1329 if (CPU_TO_ID(cpu) == id)
1330 return 0; /* Conflict with CPU */
1332 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1333 if (IO_TO_ID(oapic) == id)
1334 return 0; /* Conflict with other APIC */
1336 return 1; /* ID is acceptable for IO APIC */
1341 io_apic_find_int_entry(int apic, int pin)
1345 /* search each of the possible INTerrupt sources */
1346 for (x = 0; x < nintrs; ++x) {
1347 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1348 (pin == io_apic_ints[x].dst_apic_int))
1349 return (&io_apic_ints[x]);
1355 * parse an Intel MP specification table
1362 int apic; /* IO APIC unit number */
1363 int freeid; /* Free physical APIC ID */
1364 int physid; /* Current physical IO APIC ID */
1366 int bus_0 = 0; /* Stop GCC warning */
1367 int bus_pci = 0; /* Stop GCC warning */
1371 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1372 * did it wrong. The MP spec says that when more than 1 PCI bus
1373 * exists the BIOS must begin with bus entries for the PCI bus and use
1374 * actual PCI bus numbering. This implies that when only 1 PCI bus
1375 * exists the BIOS can choose to ignore this ordering, and indeed many
1376 * MP motherboards do ignore it. This causes a problem when the PCI
1377 * sub-system makes requests of the MP sub-system based on PCI bus
1378 * numbers. So here we look for the situation and renumber the
1379 * busses and associated INTs in an effort to "make it right".
1382 /* find bus 0, PCI bus, count the number of PCI busses */
1383 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1384 if (bus_data[x].bus_id == 0) {
1387 if (bus_data[x].bus_type == PCI) {
1393 * bus_0 == slot of bus with ID of 0
1394 * bus_pci == slot of last PCI bus encountered
1397 /* check the 1 PCI bus case for sanity */
1398 /* if it is number 0 all is well */
1399 if (num_pci_bus == 1 &&
1400 bus_data[bus_pci].bus_id != 0) {
1402 /* mis-numbered, swap with whichever bus uses slot 0 */
1404 /* swap the bus entry types */
1405 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1406 bus_data[bus_0].bus_type = PCI;
1408 /* swap each relavant INTerrupt entry */
1409 id = bus_data[bus_pci].bus_id;
1410 for (x = 0; x < nintrs; ++x) {
1411 if (io_apic_ints[x].src_bus_id == id) {
1412 io_apic_ints[x].src_bus_id = 0;
1414 else if (io_apic_ints[x].src_bus_id == 0) {
1415 io_apic_ints[x].src_bus_id = id;
1420 /* Assign IO APIC IDs.
1422 * First try the existing ID. If a conflict is detected, try
1423 * the ID in the MP table. If a conflict is still detected, find
1426 * We cannot use the ID_TO_IO table before all conflicts has been
1427 * resolved and the table has been corrected.
1429 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1431 /* First try to use the value set by the BIOS */
1432 physid = io_apic_get_id(apic);
1433 if (io_apic_id_acceptable(apic, physid)) {
1434 if (IO_TO_ID(apic) != physid)
1435 swap_apic_id(apic, IO_TO_ID(apic), physid);
1439 /* Then check if the value in the MP table is acceptable */
1440 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1443 /* Last resort, find a free APIC ID and use it */
1444 freeid = first_free_apic_id();
1445 if (freeid >= NAPICID)
1446 panic("No free physical APIC IDs found");
1448 if (io_apic_id_acceptable(apic, freeid)) {
1449 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1452 panic("Free physical APIC ID not usable");
1454 fix_id_to_io_mapping();
1456 /* detect and fix broken Compaq MP table */
1457 if (apic_int_type(0, 0) == -1) {
1458 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1459 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1460 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1461 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1462 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1463 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1465 } else if (apic_int_type(0, 0) == 0) {
1466 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1467 for (x = 0; x < nintrs; ++x)
1468 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1469 (0 == io_apic_ints[x].dst_apic_int)) {
1470 io_apic_ints[x].int_type = 3;
1471 io_apic_ints[x].int_vector = 0xff;
1477 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1478 * controllers universally come in pairs. If IRQ 14 is specified
1479 * as an ISA interrupt, then IRQ 15 had better be too.
1481 * [ Shuttle XPC / AMD Athlon X2 ]
1482 * The MPTable is missing an entry for IRQ 15. Note that the
1483 * ACPI table has an entry for both 14 and 15.
1485 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1486 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1487 io14 = io_apic_find_int_entry(0, 14);
1488 io_apic_ints[nintrs] = *io14;
1489 io_apic_ints[nintrs].src_bus_irq = 15;
1490 io_apic_ints[nintrs].dst_apic_int = 15;
1495 /* Assign low level interrupt handlers */
1497 setup_apic_irq_mapping(void)
1503 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1504 int_to_apicintpin[x].ioapic = -1;
1505 int_to_apicintpin[x].int_pin = 0;
1506 int_to_apicintpin[x].apic_address = NULL;
1507 int_to_apicintpin[x].redirindex = 0;
1509 /* Default to masked */
1510 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1513 /* First assign ISA/EISA interrupts */
1514 for (x = 0; x < nintrs; x++) {
1515 int_vector = io_apic_ints[x].src_bus_irq;
1516 if (int_vector < APIC_INTMAPSIZE &&
1517 io_apic_ints[x].int_vector == 0xff &&
1518 int_to_apicintpin[int_vector].ioapic == -1 &&
1519 (apic_int_is_bus_type(x, ISA) ||
1520 apic_int_is_bus_type(x, EISA)) &&
1521 io_apic_ints[x].int_type == 0) {
1522 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1523 io_apic_ints[x].dst_apic_int,
1528 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1529 for (x = 0; x < nintrs; x++) {
1530 if (io_apic_ints[x].dst_apic_int == 0 &&
1531 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1532 io_apic_ints[x].int_vector == 0xff &&
1533 int_to_apicintpin[0].ioapic == -1 &&
1534 io_apic_ints[x].int_type == 3) {
1535 assign_apic_irq(0, 0, 0);
1539 /* PCI interrupt assignment is deferred */
1543 mp_set_cpuids(int cpu_id, int apic_id)
1545 CPU_TO_ID(cpu_id) = apic_id;
1546 ID_TO_CPU(apic_id) = cpu_id;
1550 processor_entry(const struct PROCENTRY *entry, int cpu)
1554 /* check for usability */
1555 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1558 /* check for BSP flag */
1559 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1560 mp_set_cpuids(0, entry->apic_id);
1561 return 0; /* its already been counted */
1564 /* add another AP to list, if less than max number of CPUs */
1565 else if (cpu < MAXCPU) {
1566 mp_set_cpuids(cpu, entry->apic_id);
1574 bus_entry(const struct BUSENTRY *entry, int bus)
1579 /* encode the name into an index */
1580 for (x = 0; x < 6; ++x) {
1581 if ((c = entry->bus_type[x]) == ' ')
1587 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1588 panic("unknown bus type: '%s'", name);
1590 bus_data[bus].bus_id = entry->bus_id;
1591 bus_data[bus].bus_type = x;
1597 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1599 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1602 IO_TO_ID(apic) = entry->apic_id;
1603 ID_TO_IO(entry->apic_id) = apic;
1609 lookup_bus_type(char *name)
1613 for (x = 0; x < MAX_BUSTYPE; ++x)
1614 if (strcmp(bus_type_table[x].name, name) == 0)
1615 return bus_type_table[x].type;
1617 return UNKNOWN_BUSTYPE;
1621 int_entry(const struct INTENTRY *entry, int intr)
1625 io_apic_ints[intr].int_type = entry->int_type;
1626 io_apic_ints[intr].int_flags = entry->int_flags;
1627 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1628 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1629 if (entry->dst_apic_id == 255) {
1630 /* This signal goes to all IO APICS. Select an IO APIC
1631 with sufficient number of interrupt pins */
1632 for (apic = 0; apic < mp_napics; apic++)
1633 if (((io_apic_read(apic, IOAPIC_VER) &
1634 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1635 entry->dst_apic_int)
1637 if (apic < mp_napics)
1638 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1640 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1642 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1643 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1649 apic_int_is_bus_type(int intr, int bus_type)
1653 for (bus = 0; bus < mp_nbusses; ++bus)
1654 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1655 && ((int) bus_data[bus].bus_type == bus_type))
1662 * Given a traditional ISA INT mask, return an APIC mask.
1665 isa_apic_mask(u_int isa_mask)
1670 #if defined(SKIP_IRQ15_REDIRECT)
1671 if (isa_mask == (1 << 15)) {
1672 kprintf("skipping ISA IRQ15 redirect\n");
1675 #endif /* SKIP_IRQ15_REDIRECT */
1677 isa_irq = ffs(isa_mask); /* find its bit position */
1678 if (isa_irq == 0) /* doesn't exist */
1680 --isa_irq; /* make it zero based */
1682 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1686 return (1 << apic_pin); /* convert pin# to a mask */
1690 * Determine which APIC pin an ISA/EISA INT is attached to.
1692 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1693 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1694 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1695 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1697 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1699 isa_apic_irq(int isa_irq)
1703 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1704 if (INTTYPE(intr) == 0) { /* standard INT */
1705 if (SRCBUSIRQ(intr) == isa_irq) {
1706 if (apic_int_is_bus_type(intr, ISA) ||
1707 apic_int_is_bus_type(intr, EISA)) {
1708 if (INTIRQ(intr) == 0xff)
1709 return -1; /* unassigned */
1710 return INTIRQ(intr); /* found */
1715 return -1; /* NOT found */
1720 * Determine which APIC pin a PCI INT is attached to.
1722 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1723 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1724 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1726 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1730 --pciInt; /* zero based */
1732 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1733 if ((INTTYPE(intr) == 0) /* standard INT */
1734 && (SRCBUSID(intr) == pciBus)
1735 && (SRCBUSDEVICE(intr) == pciDevice)
1736 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1737 if (apic_int_is_bus_type(intr, PCI)) {
1738 if (INTIRQ(intr) == 0xff)
1739 allocate_apic_irq(intr);
1740 if (INTIRQ(intr) == 0xff)
1741 return -1; /* unassigned */
1742 return INTIRQ(intr); /* exact match */
1747 return -1; /* NOT found */
1751 next_apic_irq(int irq)
1758 for (intr = 0; intr < nintrs; intr++) {
1759 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1761 bus = SRCBUSID(intr);
1762 bustype = apic_bus_type(bus);
1763 if (bustype != ISA &&
1769 if (intr >= nintrs) {
1772 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1773 if (INTTYPE(ointr) != 0)
1775 if (bus != SRCBUSID(ointr))
1777 if (bustype == PCI) {
1778 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1780 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1783 if (bustype == ISA || bustype == EISA) {
1784 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1787 if (INTPIN(intr) == INTPIN(ointr))
1791 if (ointr >= nintrs) {
1794 return INTIRQ(ointr);
1807 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1810 * Exactly what this means is unclear at this point. It is a solution
1811 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1812 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1813 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1817 undirect_isa_irq(int rirq)
1821 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1822 /** FIXME: tickle the MB redirector chip */
1826 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1833 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1836 undirect_pci_irq(int rirq)
1840 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1842 /** FIXME: tickle the MB redirector chip */
1846 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1854 * given a bus ID, return:
1855 * the bus type if found
1859 apic_bus_type(int id)
1863 for (x = 0; x < mp_nbusses; ++x)
1864 if (bus_data[x].bus_id == id)
1865 return bus_data[x].bus_type;
1871 * given a LOGICAL APIC# and pin#, return:
1872 * the associated src bus ID if found
1876 apic_src_bus_id(int apic, int pin)
1880 /* search each of the possible INTerrupt sources */
1881 for (x = 0; x < nintrs; ++x)
1882 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1883 (pin == io_apic_ints[x].dst_apic_int))
1884 return (io_apic_ints[x].src_bus_id);
1886 return -1; /* NOT found */
1890 * given a LOGICAL APIC# and pin#, return:
1891 * the associated src bus IRQ if found
1895 apic_src_bus_irq(int apic, int pin)
1899 for (x = 0; x < nintrs; x++)
1900 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1901 (pin == io_apic_ints[x].dst_apic_int))
1902 return (io_apic_ints[x].src_bus_irq);
1904 return -1; /* NOT found */
1909 * given a LOGICAL APIC# and pin#, return:
1910 * the associated INTerrupt type if found
1914 apic_int_type(int apic, int pin)
1918 /* search each of the possible INTerrupt sources */
1919 for (x = 0; x < nintrs; ++x) {
1920 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1921 (pin == io_apic_ints[x].dst_apic_int))
1922 return (io_apic_ints[x].int_type);
1924 return -1; /* NOT found */
1928 * Return the IRQ associated with an APIC pin
1931 apic_irq(int apic, int pin)
1936 for (x = 0; x < nintrs; ++x) {
1937 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1938 (pin == io_apic_ints[x].dst_apic_int)) {
1939 res = io_apic_ints[x].int_vector;
1942 if (apic != int_to_apicintpin[res].ioapic)
1943 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1944 if (pin != int_to_apicintpin[res].int_pin)
1945 panic("apic_irq inconsistent table (2)");
1954 * given a LOGICAL APIC# and pin#, return:
1955 * the associated trigger mode if found
1959 apic_trigger(int apic, int pin)
1963 /* search each of the possible INTerrupt sources */
1964 for (x = 0; x < nintrs; ++x)
1965 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1966 (pin == io_apic_ints[x].dst_apic_int))
1967 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1969 return -1; /* NOT found */
1974 * given a LOGICAL APIC# and pin#, return:
1975 * the associated 'active' level if found
1979 apic_polarity(int apic, int pin)
1983 /* search each of the possible INTerrupt sources */
1984 for (x = 0; x < nintrs; ++x)
1985 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1986 (pin == io_apic_ints[x].dst_apic_int))
1987 return (io_apic_ints[x].int_flags & 0x03);
1989 return -1; /* NOT found */
1993 * set data according to MP defaults
1994 * FIXME: probably not complete yet...
1997 mptable_default(int type)
2003 kprintf(" MP default config type: %d\n", type);
2006 kprintf(" bus: ISA, APIC: 82489DX\n");
2009 kprintf(" bus: EISA, APIC: 82489DX\n");
2012 kprintf(" bus: EISA, APIC: 82489DX\n");
2015 kprintf(" bus: MCA, APIC: 82489DX\n");
2018 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2021 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2024 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2027 kprintf(" future type\n");
2033 /* one and only IO APIC */
2034 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2037 * sanity check, refer to MP spec section 3.6.6, last paragraph
2038 * necessary as some hardware isn't properly setting up the IO APIC
2040 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2041 if (io_apic_id != 2) {
2043 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2044 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2045 io_apic_set_id(0, 2);
2048 IO_TO_ID(0) = io_apic_id;
2049 ID_TO_IO(io_apic_id) = 0;
2051 /* fill out bus entries */
2060 bus_data[0].bus_id = default_data[type - 1][1];
2061 bus_data[0].bus_type = default_data[type - 1][2];
2062 bus_data[1].bus_id = default_data[type - 1][3];
2063 bus_data[1].bus_type = default_data[type - 1][4];
2066 /* case 4: case 7: MCA NOT supported */
2067 default: /* illegal/reserved */
2068 panic("BAD default MP config: %d", type);
2072 /* general cases from MP v1.4, table 5-2 */
2073 for (pin = 0; pin < 16; ++pin) {
2074 io_apic_ints[pin].int_type = 0;
2075 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2076 io_apic_ints[pin].src_bus_id = 0;
2077 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2078 io_apic_ints[pin].dst_apic_id = io_apic_id;
2079 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2082 /* special cases from MP v1.4, table 5-2 */
2084 io_apic_ints[2].int_type = 0xff; /* N/C */
2085 io_apic_ints[13].int_type = 0xff; /* N/C */
2086 #if !defined(APIC_MIXED_MODE)
2088 panic("sorry, can't support type 2 default yet");
2089 #endif /* APIC_MIXED_MODE */
2092 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2095 io_apic_ints[0].int_type = 0xff; /* N/C */
2097 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2101 * Map a physical memory address representing I/O into KVA. The I/O
2102 * block is assumed not to cross a page boundary.
2105 permanent_io_mapping(vm_paddr_t pa)
2111 KKASSERT(pa < 0x100000000LL);
2113 pgeflag = 0; /* not used for SMP yet */
2116 * If the requested physical address has already been incidently
2117 * mapped, just use the existing mapping. Otherwise create a new
2120 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2121 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2122 ((vm_offset_t)pa & PG_FRAME)) {
2126 if (i == SMPpt_alloc_index) {
2127 if (i == NPTEPG - 2) {
2128 panic("permanent_io_mapping: We ran out of space"
2131 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
2132 ((vm_offset_t)pa & PG_FRAME));
2133 ++SMPpt_alloc_index;
2135 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2136 ((vm_offset_t)pa & PAGE_MASK);
2137 return ((void *)vaddr);
2141 * start each AP in our list
2144 start_all_aps(u_int boot_addr)
2151 u_char mpbiosreason;
2152 u_long mpbioswarmvec;
2153 struct mdglobaldata *gd;
2154 struct privatespace *ps;
2158 POSTCODE(START_ALL_APS_POST);
2160 /* Initialize BSP's local APIC */
2161 apic_initialize(TRUE);
2163 /* install the AP 1st level boot code */
2164 install_ap_tramp(boot_addr);
2167 /* save the current value of the warm-start vector */
2168 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2169 outb(CMOS_REG, BIOS_RESET);
2170 mpbiosreason = inb(CMOS_DATA);
2172 /* setup a vector to our boot code */
2173 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2174 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2175 outb(CMOS_REG, BIOS_RESET);
2176 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2179 * If we have a TSC we can figure out the SMI interrupt rate.
2180 * The SMI does not necessarily use a constant rate. Spend
2181 * up to 250ms trying to figure it out.
2184 if (cpu_feature & CPUID_TSC) {
2185 set_apic_timer(275000);
2186 smilast = read_apic_timer();
2187 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2188 smicount = smitest();
2189 if (smibest == 0 || smilast - smicount < smibest)
2190 smibest = smilast - smicount;
2193 if (smibest > 250000)
2196 smibest = smibest * (int64_t)1000000 /
2197 get_apic_timer_frequency();
2201 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2202 1000000 / smibest, smibest);
2205 /* set up temporary P==V mapping for AP boot */
2206 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2207 kptbase = (uintptr_t)(void *)KPTphys;
2208 for (x = 0; x < NKPT; x++) {
2209 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2210 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2215 for (x = 1; x <= mp_naps; ++x) {
2217 /* This is a bit verbose, it will go away soon. */
2219 /* first page of AP's private space */
2220 pg = x * i386_btop(sizeof(struct privatespace));
2222 /* allocate new private data page(s) */
2223 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2224 MDGLOBALDATA_BASEALLOC_SIZE);
2225 /* wire it into the private page table page */
2226 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2227 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2228 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2230 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2232 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2233 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2234 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2235 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2237 /* allocate and set up an idle stack data page */
2238 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2239 for (i = 0; i < UPAGES; i++) {
2240 SMPpt[pg + 4 + i] = (pt_entry_t)
2241 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2244 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2245 bzero(gd, sizeof(*gd));
2246 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2248 /* prime data page for it to use */
2249 mi_gdinit(&gd->mi, x);
2251 gd->gd_CMAP1 = &SMPpt[pg + 0];
2252 gd->gd_CMAP2 = &SMPpt[pg + 1];
2253 gd->gd_CMAP3 = &SMPpt[pg + 2];
2254 gd->gd_PMAP1 = &SMPpt[pg + 3];
2255 gd->gd_CADDR1 = ps->CPAGE1;
2256 gd->gd_CADDR2 = ps->CPAGE2;
2257 gd->gd_CADDR3 = ps->CPAGE3;
2258 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2261 * Per-cpu pmap for get_ptbase().
2263 gd->gd_GDADDR1= (unsigned *)
2264 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
2265 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
2267 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2268 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2271 * Setup the AP boot stack
2273 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2276 /* attempt to start the Application Processor */
2277 CHECK_INIT(99); /* setup checkpoints */
2278 if (!start_ap(gd, boot_addr, smibest)) {
2279 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2280 CHECK_PRINT("trace"); /* show checkpoints */
2281 /* better panic as the AP may be running loose */
2282 kprintf("panic y/n? [y] ");
2283 if (cngetc() != 'n')
2286 CHECK_PRINT("trace"); /* show checkpoints */
2288 /* record its version info */
2289 cpu_apic_versions[x] = cpu_apic_versions[0];
2292 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2295 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2296 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2299 ncpus2_shift = shift;
2300 ncpus2 = 1 << shift;
2301 ncpus2_mask = ncpus2 - 1;
2303 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2304 if ((1 << shift) < ncpus)
2306 ncpus_fit = 1 << shift;
2307 ncpus_fit_mask = ncpus_fit - 1;
2309 /* build our map of 'other' CPUs */
2310 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2311 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2312 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2314 /* fill in our (BSP) APIC version */
2315 cpu_apic_versions[0] = lapic.version;
2317 /* restore the warmstart vector */
2318 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2319 outb(CMOS_REG, BIOS_RESET);
2320 outb(CMOS_DATA, mpbiosreason);
2323 * NOTE! The idlestack for the BSP was setup by locore. Finish
2324 * up, clean out the P==V mapping we did earlier.
2326 for (x = 0; x < NKPT; x++)
2330 /* number of APs actually started */
2335 * load the 1st level AP boot code into base memory.
2338 /* targets for relocation */
2339 extern void bigJump(void);
2340 extern void bootCodeSeg(void);
2341 extern void bootDataSeg(void);
2342 extern void MPentry(void);
2343 extern u_int MP_GDT;
2344 extern u_int mp_gdtbase;
2347 install_ap_tramp(u_int boot_addr)
2350 int size = *(int *) ((u_long) & bootMP_size);
2351 u_char *src = (u_char *) ((u_long) bootMP);
2352 u_char *dst = (u_char *) boot_addr + KERNBASE;
2353 u_int boot_base = (u_int) bootMP;
2358 POSTCODE(INSTALL_AP_TRAMP_POST);
2360 for (x = 0; x < size; ++x)
2364 * modify addresses in code we just moved to basemem. unfortunately we
2365 * need fairly detailed info about mpboot.s for this to work. changes
2366 * to mpboot.s might require changes here.
2369 /* boot code is located in KERNEL space */
2370 dst = (u_char *) boot_addr + KERNBASE;
2372 /* modify the lgdt arg */
2373 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2374 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2376 /* modify the ljmp target for MPentry() */
2377 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2378 *dst32 = ((u_int) MPentry - KERNBASE);
2380 /* modify the target for boot code segment */
2381 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2382 dst8 = (u_int8_t *) (dst16 + 1);
2383 *dst16 = (u_int) boot_addr & 0xffff;
2384 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2386 /* modify the target for boot data segment */
2387 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2388 dst8 = (u_int8_t *) (dst16 + 1);
2389 *dst16 = (u_int) boot_addr & 0xffff;
2390 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2395 * This function starts the AP (application processor) identified
2396 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2397 * to accomplish this. This is necessary because of the nuances
2398 * of the different hardware we might encounter. It ain't pretty,
2399 * but it seems to work.
2401 * NOTE: eventually an AP gets to ap_init(), which is called just
2402 * before the AP goes into the LWKT scheduler's idle loop.
2405 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2409 u_long icr_lo, icr_hi;
2411 POSTCODE(START_AP_POST);
2413 /* get the PHYSICAL APIC ID# */
2414 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2416 /* calculate the vector */
2417 vector = (boot_addr >> 12) & 0xff;
2419 /* We don't want anything interfering */
2422 /* Make sure the target cpu sees everything */
2426 * Try to detect when a SMI has occurred, wait up to 200ms.
2428 * If a SMI occurs during an AP reset but before we issue
2429 * the STARTUP command, the AP may brick. To work around
2430 * this problem we hold off doing the AP startup until
2431 * after we have detected the SMI. Hopefully another SMI
2432 * will not occur before we finish the AP startup.
2434 * Retries don't seem to help. SMIs have a window of opportunity
2435 * and if USB->legacy keyboard emulation is enabled in the BIOS
2436 * the interrupt rate can be quite high.
2438 * NOTE: Don't worry about the L1 cache load, it might bloat
2439 * ldelta a little but ndelta will be so huge when the SMI
2440 * occurs the detection logic will still work fine.
2443 set_apic_timer(200000);
2448 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2449 * and running the target CPU. OR this INIT IPI might be latched (P5
2450 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2453 * see apic/apicreg.h for icr bit definitions.
2455 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2459 * Setup the address for the target AP. We can setup
2460 * icr_hi once and then just trigger operations with
2463 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2464 icr_hi |= (physical_cpu << 24);
2465 icr_lo = lapic.icr_lo & 0xfff00000;
2466 lapic.icr_hi = icr_hi;
2469 * Do an INIT IPI: assert RESET
2471 * Use edge triggered mode to assert INIT
2473 lapic.icr_lo = icr_lo | 0x0000c500;
2474 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2478 * The spec calls for a 10ms delay but we may have to use a
2479 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2480 * interrupt. We have other loops here too and dividing by 2
2481 * doesn't seem to be enough even after subtracting 350us,
2482 * so we divide by 4.
2484 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2485 * interrupt was detected we use the full 10ms.
2489 else if (smibest < 150 * 4 + 350)
2491 else if ((smibest - 350) / 4 < 10000)
2492 u_sleep((smibest - 350) / 4);
2497 * Do an INIT IPI: deassert RESET
2499 * Use level triggered mode to deassert. It is unclear
2500 * why we need to do this.
2502 lapic.icr_lo = icr_lo | 0x00008500;
2503 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2505 u_sleep(150); /* wait 150us */
2508 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2509 * latched, (P5 bug) this 1st STARTUP would then terminate
2510 * immediately, and the previously started INIT IPI would continue. OR
2511 * the previous INIT IPI has already run. and this STARTUP IPI will
2512 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2515 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2516 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2518 u_sleep(200); /* wait ~200uS */
2521 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2522 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2523 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2524 * recognized after hardware RESET or INIT IPI.
2526 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2527 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2530 /* Resume normal operation */
2533 /* wait for it to start, see ap_init() */
2534 set_apic_timer(5000000);/* == 5 seconds */
2535 while (read_apic_timer()) {
2536 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2537 return 1; /* return SUCCESS */
2540 return 0; /* return FAILURE */
2555 while (read_apic_timer()) {
2557 for (count = 0; count < 100; ++count)
2558 ntsc = rdtsc(); /* force loop to occur */
2560 ndelta = ntsc - ltsc;
2561 if (ldelta > ndelta)
2563 if (ndelta > ldelta * 2)
2566 ldelta = ntsc - ltsc;
2569 return(read_apic_timer());
2573 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2575 * If for some reason we were unable to start all cpus we cannot safely
2576 * use broadcast IPIs.
2582 if (smp_startup_mask == smp_active_mask) {
2583 all_but_self_ipi(XINVLTLB_OFFSET);
2585 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2586 APIC_DELMODE_FIXED);
2592 * When called the executing CPU will send an IPI to all other CPUs
2593 * requesting that they halt execution.
2595 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2597 * - Signals all CPUs in map to stop.
2598 * - Waits for each to stop.
2605 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2606 * from executing at same time.
2609 stop_cpus(u_int map)
2611 map &= smp_active_mask;
2613 /* send the Xcpustop IPI to all CPUs in map */
2614 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2616 while ((stopped_cpus & map) != map)
2624 * Called by a CPU to restart stopped CPUs.
2626 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2628 * - Signals all CPUs in map to restart.
2629 * - Waits for each to restart.
2637 restart_cpus(u_int map)
2639 /* signal other cpus to restart */
2640 started_cpus = map & smp_active_mask;
2642 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2649 * This is called once the mpboot code has gotten us properly relocated
2650 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2651 * and when it returns the scheduler will call the real cpu_idle() main
2652 * loop for the idlethread. Interrupts are disabled on entry and should
2653 * remain disabled at return.
2661 * Adjust smp_startup_mask to signal the BSP that we have started
2662 * up successfully. Note that we do not yet hold the BGL. The BSP
2663 * is waiting for our signal.
2665 * We can't set our bit in smp_active_mask yet because we are holding
2666 * interrupts physically disabled and remote cpus could deadlock
2667 * trying to send us an IPI.
2669 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2673 * Interlock for finalization. Wait until mp_finish is non-zero,
2674 * then get the MP lock.
2676 * Note: We are in a critical section.
2678 * Note: We have to synchronize td_mpcount to our desired MP state
2679 * before calling cpu_try_mplock().
2681 * Note: we are the idle thread, we can only spin.
2683 * Note: The load fence is memory volatile and prevents the compiler
2684 * from improperly caching mp_finish, and the cpu from improperly
2687 while (mp_finish == 0)
2689 ++curthread->td_mpcount;
2690 while (cpu_try_mplock() == 0)
2693 if (cpu_feature & CPUID_TSC) {
2695 * The BSP is constantly updating tsc0_offset, figure out the
2696 * relative difference to synchronize ktrdump.
2698 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2701 /* BSP may have changed PTD while we're waiting for the lock */
2704 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2708 /* Build our map of 'other' CPUs. */
2709 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2711 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2713 /* A quick check from sanity claus */
2714 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2715 if (mycpu->gd_cpuid != apic_id) {
2716 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2717 kprintf("SMP: apic_id = %d\n", apic_id);
2718 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2719 panic("cpuid mismatch! boom!!");
2722 /* Initialize AP's local APIC for irq's */
2723 apic_initialize(FALSE);
2725 /* Set memory range attributes for this CPU to match the BSP */
2726 mem_range_AP_init();
2729 * Once we go active we must process any IPIQ messages that may
2730 * have been queued, because no actual IPI will occur until we
2731 * set our bit in the smp_active_mask. If we don't the IPI
2732 * message interlock could be left set which would also prevent
2735 * The idle loop doesn't expect the BGL to be held and while
2736 * lwkt_switch() normally cleans things up this is a special case
2737 * because we returning almost directly into the idle loop.
2739 * The idle thread is never placed on the runq, make sure
2740 * nothing we've done put it there.
2742 KKASSERT(curthread->td_mpcount == 1);
2743 smp_active_mask |= 1 << mycpu->gd_cpuid;
2746 * Enable interrupts here. idle_restore will also do it, but
2747 * doing it here lets us clean up any strays that got posted to
2748 * the CPU during the AP boot while we are still in a critical
2751 __asm __volatile("sti; pause; pause"::);
2752 mdcpu->gd_fpending = 0;
2754 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2755 lwkt_process_ipiq();
2758 * Releasing the mp lock lets the BSP finish up the SMP init
2761 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2765 * Get SMP fully working before we start initializing devices.
2773 kprintf("Finish MP startup\n");
2774 if (cpu_feature & CPUID_TSC)
2775 tsc0_offset = rdtsc();
2778 while (smp_active_mask != smp_startup_mask) {
2780 if (cpu_feature & CPUID_TSC)
2781 tsc0_offset = rdtsc();
2783 while (try_mplock() == 0)
2786 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2789 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2792 cpu_send_ipiq(int dcpu)
2794 if ((1 << dcpu) & smp_active_mask)
2795 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2798 #if 0 /* single_apic_ipi_passive() not working yet */
2800 * Returns 0 on failure, 1 on success
2803 cpu_send_ipiq_passive(int dcpu)
2806 if ((1 << dcpu) & smp_active_mask) {
2807 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2808 APIC_DELMODE_FIXED);
2814 struct mptable_lapic_cbarg1 {
2817 u_int ht_apicid_mask;
2821 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2823 const struct PROCENTRY *ent;
2824 struct mptable_lapic_cbarg1 *arg = xarg;
2830 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2834 if (ent->apic_id < 32) {
2835 arg->ht_apicid_mask |= 1 << ent->apic_id;
2836 } else if (arg->ht_fixup) {
2837 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2843 struct mptable_lapic_cbarg2 {
2850 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2852 const struct PROCENTRY *ent;
2853 struct mptable_lapic_cbarg2 *arg = xarg;
2859 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2860 KKASSERT(!arg->found_bsp);
2864 if (processor_entry(ent, arg->cpu))
2867 if (arg->logical_cpus) {
2868 struct PROCENTRY proc;
2872 * Create fake mptable processor entries
2873 * and feed them to processor_entry() to
2874 * enumerate the logical CPUs.
2876 bzero(&proc, sizeof(proc));
2878 proc.cpu_flags = PROCENTRY_FLAG_EN;
2879 proc.apic_id = ent->apic_id;
2881 for (i = 1; i < arg->logical_cpus; i++) {
2883 processor_entry(&proc, arg->cpu);
2891 mptable_imcr(struct mptable_pos *mpt)
2893 /* record whether PIC or virtual-wire mode */
2894 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2895 mpt->mp_fps->mpfb2 & 0x80);
2898 struct mptable_lapic_enumerator {
2899 struct lapic_enumerator enumerator;
2900 vm_paddr_t mpfps_paddr;
2904 mptable_lapic_default(void)
2906 int ap_apicid, bsp_apicid;
2908 mp_naps = 1; /* exclude BSP */
2910 /* Map local apic before the id field is accessed */
2911 lapic_map(DEFAULT_APIC_BASE);
2913 bsp_apicid = APIC_ID(lapic.id);
2914 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2917 mp_set_cpuids(0, bsp_apicid);
2918 /* one and only AP */
2919 mp_set_cpuids(1, ap_apicid);
2925 * ID_TO_CPU(N), APIC ID to logical CPU table
2926 * CPU_TO_ID(N), logical CPU to APIC ID table
2929 mptable_lapic_enumerate(struct lapic_enumerator *e)
2931 struct mptable_pos mpt;
2932 struct mptable_lapic_cbarg1 arg1;
2933 struct mptable_lapic_cbarg2 arg2;
2935 int error, logical_cpus = 0;
2936 vm_offset_t lapic_addr;
2937 vm_paddr_t mpfps_paddr;
2939 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
2940 KKASSERT(mpfps_paddr != 0);
2942 error = mptable_map(&mpt, mpfps_paddr);
2944 panic("mptable_lapic_enumerate mptable_map failed\n");
2946 KKASSERT(mpt.mp_fps != NULL);
2949 * Check for use of 'default' configuration
2951 if (mpt.mp_fps->mpfb1 != 0) {
2952 mptable_lapic_default();
2953 mptable_unmap(&mpt);
2958 KKASSERT(cth != NULL);
2960 /* Save local apic address */
2961 lapic_addr = (vm_offset_t)cth->apic_address;
2962 KKASSERT(lapic_addr != 0);
2965 * Find out how many CPUs do we have
2967 bzero(&arg1, sizeof(arg1));
2968 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2970 error = mptable_iterate_entries(cth,
2971 mptable_lapic_pass1_callback, &arg1);
2973 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2974 KKASSERT(arg1.cpu_count != 0);
2976 /* See if we need to fixup HT logical CPUs. */
2977 if (arg1.ht_fixup) {
2978 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2980 if (logical_cpus != 0)
2981 arg1.cpu_count *= logical_cpus;
2983 mp_naps = arg1.cpu_count;
2985 /* Qualify the numbers again, after possible HT fixup */
2986 if (mp_naps > MAXCPU) {
2987 kprintf("Warning: only using %d of %d available CPUs!\n",
2992 --mp_naps; /* subtract the BSP */
2995 * Link logical CPU id to local apic id
2997 bzero(&arg2, sizeof(arg2));
2999 arg2.logical_cpus = logical_cpus;
3001 error = mptable_iterate_entries(cth,
3002 mptable_lapic_pass2_callback, &arg2);
3004 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3005 KKASSERT(arg2.found_bsp);
3007 /* Map local apic */
3008 lapic_map(lapic_addr);
3010 mptable_unmap(&mpt);
3014 mptable_lapic_probe(struct lapic_enumerator *e)
3016 vm_paddr_t mpfps_paddr;
3018 mpfps_paddr = mptable_probe();
3019 if (mpfps_paddr == 0)
3022 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
3026 static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
3028 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3029 .lapic_probe = mptable_lapic_probe,
3030 .lapic_enumerate = mptable_lapic_enumerate
3035 mptable_apic_register(void)
3037 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
3039 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);