2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/sysctl.h>
34 #include <sys/malloc.h>
35 #include <sys/memrange.h>
36 #include <sys/cons.h> /* cngetc() */
37 #include <sys/machintr.h>
40 #include <vm/vm_param.h>
42 #include <vm/vm_kern.h>
43 #include <vm/vm_extern.h>
45 #include <vm/vm_map.h>
51 #include <sys/mplock2.h>
53 #include <machine/smp.h>
54 #include <machine_base/apic/apicreg.h>
55 #include <machine/atomic.h>
56 #include <machine/cpufunc.h>
57 #include <machine/cputypes.h>
58 #include <machine_base/icu/icu_var.h>
59 #include <machine_base/apic/ioapic_abi.h>
60 #include <machine_base/apic/lapic.h>
61 #include <machine_base/apic/ioapic.h>
62 #include <machine/psl.h>
63 #include <machine/segments.h>
64 #include <machine/tss.h>
65 #include <machine/specialreg.h>
66 #include <machine/globaldata.h>
67 #include <machine/pmap_inval.h>
69 #include <machine/md_var.h> /* setidt() */
70 #include <machine_base/icu/icu.h> /* IPIs */
71 #include <machine/intr_machdep.h> /* IPIs */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
83 * this code MUST be enabled here and in mpboot.s.
84 * it follows the very early stages of AP boot by placing values in CMOS ram.
85 * it NORMALLY will never be needed and thus the primitive method for enabling.
88 #if defined(CHECK_POINTS)
89 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
90 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
92 #define CHECK_INIT(D); \
93 CHECK_WRITE(0x34, (D)); \
94 CHECK_WRITE(0x35, (D)); \
95 CHECK_WRITE(0x36, (D)); \
96 CHECK_WRITE(0x37, (D)); \
97 CHECK_WRITE(0x38, (D)); \
98 CHECK_WRITE(0x39, (D));
100 #define CHECK_PRINT(S); \
101 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
110 #else /* CHECK_POINTS */
112 #define CHECK_INIT(D)
113 #define CHECK_PRINT(S)
115 #endif /* CHECK_POINTS */
118 * Values to send to the POST hardware.
120 #define MP_BOOTADDRESS_POST 0x10
121 #define MP_PROBE_POST 0x11
122 #define MPTABLE_PASS1_POST 0x12
124 #define MP_START_POST 0x13
125 #define MP_ENABLE_POST 0x14
126 #define MPTABLE_PASS2_POST 0x15
128 #define START_ALL_APS_POST 0x16
129 #define INSTALL_AP_TRAMP_POST 0x17
130 #define START_AP_POST 0x18
132 #define MP_ANNOUNCE_POST 0x19
134 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
135 int current_postcode;
137 /** XXX FIXME: what system files declare these??? */
138 extern struct region_descriptor r_gdt, r_idt;
144 extern int64_t tsc_offsets[];
146 /* AP uses this during bootstrap. Do not staticize. */
150 /* Hotwire a 0->4MB V==P mapping */
151 extern pt_entry_t *KPTphys;
154 * SMP page table page. Setup by locore to point to a page table
155 * page from which we allocate per-cpu privatespace areas io_apics,
158 extern pt_entry_t *SMPpt;
160 struct pcb stoppcbs[MAXCPU];
163 * Local data and functions.
166 static u_int boot_address;
167 static int mp_finish;
168 static int mp_finish_lapic;
170 static int start_all_aps(u_int boot_addr);
171 static void install_ap_tramp(u_int boot_addr);
172 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
173 static int smitest(void);
174 static void mp_bsp_simple_setup(void);
176 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
177 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
178 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
179 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
182 * Calculate usable address in base memory for AP trampoline code.
185 mp_bootaddress(u_int basemem)
187 POSTCODE(MP_BOOTADDRESS_POST);
189 boot_address = basemem & ~0xfff; /* round down to 4k boundary */
190 if ((basemem - boot_address) < bootMP_size)
191 boot_address -= 4096; /* not enough, lower by 4k */
197 * Print various information about the SMP system hardware and setup.
204 POSTCODE(MP_ANNOUNCE_POST);
206 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
207 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0));
208 for (x = 1; x <= naps; ++x)
209 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x));
212 kprintf(" Warning: APIC I/O disabled\n");
216 * AP cpu's call this to sync up protected mode.
218 * WARNING! We must ensure that the cpu is sufficiently initialized to
219 * be able to use to the FP for our optimized bzero/bcopy code before
220 * we enter more mainstream C code.
222 * WARNING! %fs is not set up on entry. This routine sets up %fs.
228 int x, myid = bootAP;
230 struct mdglobaldata *md;
231 struct privatespace *ps;
233 ps = &CPU_prvspace[myid];
235 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
236 gdt_segs[GPROC0_SEL].ssd_base =
237 (int) &ps->mdglobaldata.gd_common_tss;
238 ps->mdglobaldata.mi.gd_prvspace = ps;
240 for (x = 0; x < NGDT; x++) {
241 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
244 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
245 r_gdt.rd_base = (int) &gdt[myid * NGDT];
246 lgdt(&r_gdt); /* does magic intra-segment return */
251 mdcpu->gd_currentldt = _default_ldt;
253 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
254 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
256 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
258 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
259 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
260 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
261 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
262 md->gd_common_tssd = *md->gd_tss_gdt;
266 * Set to a known state:
267 * Set by mpboot.s: CR0_PG, CR0_PE
268 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
271 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
273 pmap_set_opt(); /* PSE/4MB pages, etc */
275 /* set up CPU registers and state */
278 /* set up FPU state on the AP */
279 npxinit(__INITIAL_NPXCW__);
281 /* set up SSE registers */
285 /*******************************************************************
286 * local functions and data
290 * Start the SMP system
293 mp_start_aps(void *dummy __unused)
296 /* start each Application Processor */
297 start_all_aps(boot_address);
299 mp_bsp_simple_setup();
302 SYSINIT(startaps, SI_BOOT2_START_APS, SI_ORDER_FIRST, mp_start_aps, NULL)
305 * start each AP in our list
308 start_all_aps(u_int boot_addr)
316 u_long mpbioswarmvec;
317 struct mdglobaldata *gd;
318 struct privatespace *ps;
322 POSTCODE(START_ALL_APS_POST);
324 /* install the AP 1st level boot code */
325 install_ap_tramp(boot_addr);
328 /* save the current value of the warm-start vector */
329 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
330 outb(CMOS_REG, BIOS_RESET);
331 mpbiosreason = inb(CMOS_DATA);
333 /* setup a vector to our boot code */
334 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
335 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
336 outb(CMOS_REG, BIOS_RESET);
337 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
340 * If we have a TSC we can figure out the SMI interrupt rate.
341 * The SMI does not necessarily use a constant rate. Spend
342 * up to 250ms trying to figure it out.
345 if (cpu_feature & CPUID_TSC) {
346 set_apic_timer(275000);
347 smilast = read_apic_timer();
348 for (x = 0; x < 20 && read_apic_timer(); ++x) {
349 smicount = smitest();
350 if (smibest == 0 || smilast - smicount < smibest)
351 smibest = smilast - smicount;
354 if (smibest > 250000)
357 smibest = smibest * (int64_t)1000000 /
358 get_apic_timer_frequency();
362 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
363 1000000 / smibest, smibest);
366 /* set up temporary P==V mapping for AP boot */
367 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
368 kptbase = (uintptr_t)(void *)KPTphys;
369 for (x = 0; x < NKPT; x++) {
370 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
371 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
376 for (x = 1; x <= naps; ++x) {
378 /* This is a bit verbose, it will go away soon. */
380 /* first page of AP's private space */
381 pg = x * i386_btop(sizeof(struct privatespace));
383 /* allocate new private data page(s) */
384 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
385 MDGLOBALDATA_BASEALLOC_SIZE);
386 /* wire it into the private page table page */
387 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
388 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
389 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
391 pg += MDGLOBALDATA_BASEALLOC_PAGES;
393 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
394 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
395 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
396 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
398 /* allocate and set up an idle stack data page */
399 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
400 for (i = 0; i < UPAGES; i++) {
401 SMPpt[pg + 4 + i] = (pt_entry_t)
402 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
405 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
406 bzero(gd, sizeof(*gd));
407 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
409 /* prime data page for it to use */
410 mi_gdinit(&gd->mi, x);
412 gd->gd_CMAP1 = &SMPpt[pg + 0];
413 gd->gd_CMAP2 = &SMPpt[pg + 1];
414 gd->gd_CMAP3 = &SMPpt[pg + 2];
415 gd->gd_PMAP1 = &SMPpt[pg + 3];
416 gd->gd_CADDR1 = ps->CPAGE1;
417 gd->gd_CADDR2 = ps->CPAGE2;
418 gd->gd_CADDR3 = ps->CPAGE3;
419 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
422 * Per-cpu pmap for get_ptbase().
424 gd->gd_GDADDR1= (unsigned *)
425 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
426 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
428 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (naps + 1));
429 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (naps + 1));
432 * Setup the AP boot stack
434 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
437 /* attempt to start the Application Processor */
438 CHECK_INIT(99); /* setup checkpoints */
439 if (!start_ap(gd, boot_addr, smibest)) {
440 kprintf("AP #%d (PHY# %d) failed!\n", x,
442 CHECK_PRINT("trace"); /* show checkpoints */
443 /* better panic as the AP may be running loose */
444 kprintf("panic y/n? [y] ");
448 CHECK_PRINT("trace"); /* show checkpoints */
451 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
454 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
455 for (shift = 0; (1 << shift) <= ncpus; ++shift)
458 ncpus2_shift = shift;
460 ncpus2_mask = ncpus2 - 1;
462 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
463 if ((1 << shift) < ncpus)
465 ncpus_fit = 1 << shift;
466 ncpus_fit_mask = ncpus_fit - 1;
468 /* build our map of 'other' CPUs */
469 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
470 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
471 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
473 /* restore the warmstart vector */
474 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
475 outb(CMOS_REG, BIOS_RESET);
476 outb(CMOS_DATA, mpbiosreason);
479 * NOTE! The idlestack for the BSP was setup by locore. Finish
480 * up, clean out the P==V mapping we did earlier.
482 for (x = 0; x < NKPT; x++)
487 * Wait all APs to finish initializing LAPIC
491 kprintf("SMP: Waiting APs LAPIC initialization\n");
492 if (cpu_feature & CPUID_TSC)
493 tsc0_offset = rdtsc();
496 while (smp_lapic_mask != smp_startup_mask) {
498 if (cpu_feature & CPUID_TSC)
499 tsc0_offset = rdtsc();
501 while (try_mplock() == 0)
504 /* number of APs actually started */
509 * load the 1st level AP boot code into base memory.
512 /* targets for relocation */
513 extern void bigJump(void);
514 extern void bootCodeSeg(void);
515 extern void bootDataSeg(void);
516 extern void MPentry(void);
518 extern u_int mp_gdtbase;
521 install_ap_tramp(u_int boot_addr)
524 int size = *(int *) ((u_long) & bootMP_size);
525 u_char *src = (u_char *) ((u_long) bootMP);
526 u_char *dst = (u_char *) boot_addr + KERNBASE;
527 u_int boot_base = (u_int) bootMP;
532 POSTCODE(INSTALL_AP_TRAMP_POST);
534 for (x = 0; x < size; ++x)
538 * modify addresses in code we just moved to basemem. unfortunately we
539 * need fairly detailed info about mpboot.s for this to work. changes
540 * to mpboot.s might require changes here.
543 /* boot code is located in KERNEL space */
544 dst = (u_char *) boot_addr + KERNBASE;
546 /* modify the lgdt arg */
547 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
548 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
550 /* modify the ljmp target for MPentry() */
551 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
552 *dst32 = ((u_int) MPentry - KERNBASE);
554 /* modify the target for boot code segment */
555 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
556 dst8 = (u_int8_t *) (dst16 + 1);
557 *dst16 = boot_addr & 0xffff;
558 *dst8 = (boot_addr >> 16) & 0xff;
560 /* modify the target for boot data segment */
561 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
562 dst8 = (u_int8_t *) (dst16 + 1);
563 *dst16 = boot_addr & 0xffff;
564 *dst8 = (boot_addr >> 16) & 0xff;
569 * This function starts the AP (application processor) identified
570 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
571 * to accomplish this. This is necessary because of the nuances
572 * of the different hardware we might encounter. It ain't pretty,
573 * but it seems to work.
575 * NOTE: eventually an AP gets to ap_init(), which is called just
576 * before the AP goes into the LWKT scheduler's idle loop.
579 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
583 u_long icr_lo, icr_hi;
585 POSTCODE(START_AP_POST);
587 /* get the PHYSICAL APIC ID# */
588 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid);
590 /* calculate the vector */
591 vector = (boot_addr >> 12) & 0xff;
593 /* We don't want anything interfering */
596 /* Make sure the target cpu sees everything */
600 * Try to detect when a SMI has occurred, wait up to 200ms.
602 * If a SMI occurs during an AP reset but before we issue
603 * the STARTUP command, the AP may brick. To work around
604 * this problem we hold off doing the AP startup until
605 * after we have detected the SMI. Hopefully another SMI
606 * will not occur before we finish the AP startup.
608 * Retries don't seem to help. SMIs have a window of opportunity
609 * and if USB->legacy keyboard emulation is enabled in the BIOS
610 * the interrupt rate can be quite high.
612 * NOTE: Don't worry about the L1 cache load, it might bloat
613 * ldelta a little but ndelta will be so huge when the SMI
614 * occurs the detection logic will still work fine.
617 set_apic_timer(200000);
622 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
623 * and running the target CPU. OR this INIT IPI might be latched (P5
624 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
627 * see apic/apicreg.h for icr bit definitions.
629 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
633 * Setup the address for the target AP. We can setup
634 * icr_hi once and then just trigger operations with
637 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
638 icr_hi |= (physical_cpu << 24);
639 icr_lo = lapic->icr_lo & 0xfff00000;
640 lapic->icr_hi = icr_hi;
643 * Do an INIT IPI: assert RESET
645 * Use edge triggered mode to assert INIT
647 lapic->icr_lo = icr_lo | 0x0000c500;
648 while (lapic->icr_lo & APIC_DELSTAT_MASK)
652 * The spec calls for a 10ms delay but we may have to use a
653 * MUCH lower delay to avoid bricking an AP due to a fast SMI
654 * interrupt. We have other loops here too and dividing by 2
655 * doesn't seem to be enough even after subtracting 350us,
658 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
659 * interrupt was detected we use the full 10ms.
663 else if (smibest < 150 * 4 + 350)
665 else if ((smibest - 350) / 4 < 10000)
666 u_sleep((smibest - 350) / 4);
671 * Do an INIT IPI: deassert RESET
673 * Use level triggered mode to deassert. It is unclear
674 * why we need to do this.
676 lapic->icr_lo = icr_lo | 0x00008500;
677 while (lapic->icr_lo & APIC_DELSTAT_MASK)
679 u_sleep(150); /* wait 150us */
682 * Next we do a STARTUP IPI: the previous INIT IPI might still be
683 * latched, (P5 bug) this 1st STARTUP would then terminate
684 * immediately, and the previously started INIT IPI would continue. OR
685 * the previous INIT IPI has already run. and this STARTUP IPI will
686 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
689 lapic->icr_lo = icr_lo | 0x00000600 | vector;
690 while (lapic->icr_lo & APIC_DELSTAT_MASK)
692 u_sleep(200); /* wait ~200uS */
695 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
696 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
697 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
698 * recognized after hardware RESET or INIT IPI.
700 lapic->icr_lo = icr_lo | 0x00000600 | vector;
701 while (lapic->icr_lo & APIC_DELSTAT_MASK)
704 /* Resume normal operation */
707 /* wait for it to start, see ap_init() */
708 set_apic_timer(5000000);/* == 5 seconds */
709 while (read_apic_timer()) {
710 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
711 return 1; /* return SUCCESS */
714 return 0; /* return FAILURE */
729 while (read_apic_timer()) {
731 for (count = 0; count < 100; ++count)
732 ntsc = rdtsc(); /* force loop to occur */
734 ndelta = ntsc - ltsc;
737 if (ndelta > ldelta * 2)
740 ldelta = ntsc - ltsc;
743 return(read_apic_timer());
747 * Lazy flush the TLB on all other CPU's. DEPRECATED.
749 * If for some reason we were unable to start all cpus we cannot safely
750 * use broadcast IPIs.
753 static cpumask_t smp_invltlb_req;
754 #define SMP_INVLTLB_DEBUG
759 struct mdglobaldata *md = mdcpu;
760 #ifdef SMP_INVLTLB_DEBUG
765 crit_enter_gd(&md->mi);
766 md->gd_invltlb_ret = 0;
767 ++md->mi.gd_cnt.v_smpinvltlb;
768 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
769 #ifdef SMP_INVLTLB_DEBUG
772 if (smp_startup_mask == smp_active_mask) {
773 all_but_self_ipi(XINVLTLB_OFFSET);
775 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
776 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
779 #ifdef SMP_INVLTLB_DEBUG
781 kprintf("smp_invltlb: ipi sent\n");
783 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
784 (smp_active_mask & ~md->mi.gd_cpumask)) {
787 #ifdef SMP_INVLTLB_DEBUG
789 if (++count == 400000000) {
791 kprintf("smp_invltlb: endless loop %08lx %08lx, "
792 "rflags %016lx retry",
793 (long)md->gd_invltlb_ret,
794 (long)smp_invltlb_req,
795 (long)read_eflags());
796 __asm __volatile ("sti");
801 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
805 kprintf("bcpu %d\n", bcpu);
806 xgd = globaldata_find(bcpu);
807 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
816 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
817 crit_exit_gd(&md->mi);
821 * Called from Xinvltlb assembly with interrupts disabled. We didn't
822 * bother to bump the critical section count or nested interrupt count
823 * so only do very low level operations here.
826 smp_invltlb_intr(void)
828 struct mdglobaldata *md = mdcpu;
829 struct mdglobaldata *omd;
833 mask = smp_invltlb_req;
837 cpu = BSFCPUMASK(mask);
838 mask &= ~CPUMASK(cpu);
839 omd = (struct mdglobaldata *)globaldata_find(cpu);
840 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
845 * When called the executing CPU will send an IPI to all other CPUs
846 * requesting that they halt execution.
848 * Usually (but not necessarily) called with 'other_cpus' as its arg.
850 * - Signals all CPUs in map to stop.
851 * - Waits for each to stop.
858 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
859 * from executing at same time.
862 stop_cpus(cpumask_t map)
864 map &= smp_active_mask;
866 /* send the Xcpustop IPI to all CPUs in map */
867 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
869 while ((stopped_cpus & map) != map)
877 * Called by a CPU to restart stopped CPUs.
879 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
881 * - Signals all CPUs in map to restart.
882 * - Waits for each to restart.
890 restart_cpus(cpumask_t map)
892 /* signal other cpus to restart */
893 started_cpus = map & smp_active_mask;
895 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
902 * This is called once the mpboot code has gotten us properly relocated
903 * and the MMU turned on, etc. ap_init() is actually the idle thread,
904 * and when it returns the scheduler will call the real cpu_idle() main
905 * loop for the idlethread. Interrupts are disabled on entry and should
906 * remain disabled at return.
914 * Adjust smp_startup_mask to signal the BSP that we have started
915 * up successfully. Note that we do not yet hold the BGL. The BSP
916 * is waiting for our signal.
918 * We can't set our bit in smp_active_mask yet because we are holding
919 * interrupts physically disabled and remote cpus could deadlock
920 * trying to send us an IPI.
922 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
926 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
927 * non-zero, then get the MP lock.
929 * Note: We are in a critical section.
931 * Note: we are the idle thread, we can only spin.
933 * Note: The load fence is memory volatile and prevents the compiler
934 * from improperly caching mp_finish_lapic, and the cpu from improperly
937 while (mp_finish_lapic == 0)
939 while (try_mplock() == 0)
942 if (cpu_feature & CPUID_TSC) {
944 * The BSP is constantly updating tsc0_offset, figure out
945 * the relative difference to synchronize ktrdump.
947 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
950 /* BSP may have changed PTD while we're waiting for the lock */
953 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
957 /* Build our map of 'other' CPUs. */
958 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
960 /* A quick check from sanity claus */
961 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24);
962 if (mycpu->gd_cpuid != cpu_id) {
963 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid);
964 kprintf("SMP: actual cpuid = %d\n", cpu_id);
965 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
966 panic("cpuid mismatch! boom!!");
969 /* Initialize AP's local APIC for irq's */
972 /* LAPIC initialization is done */
973 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
976 /* Let BSP move onto the next initialization stage */
980 * Interlock for finalization. Wait until mp_finish is non-zero,
981 * then get the MP lock.
983 * Note: We are in a critical section.
985 * Note: we are the idle thread, we can only spin.
987 * Note: The load fence is memory volatile and prevents the compiler
988 * from improperly caching mp_finish, and the cpu from improperly
991 while (mp_finish == 0)
993 while (try_mplock() == 0)
996 /* BSP may have changed PTD while we're waiting for the lock */
999 /* Set memory range attributes for this CPU to match the BSP */
1000 mem_range_AP_init();
1003 * Once we go active we must process any IPIQ messages that may
1004 * have been queued, because no actual IPI will occur until we
1005 * set our bit in the smp_active_mask. If we don't the IPI
1006 * message interlock could be left set which would also prevent
1009 * The idle loop doesn't expect the BGL to be held and while
1010 * lwkt_switch() normally cleans things up this is a special case
1011 * because we returning almost directly into the idle loop.
1013 * The idle thread is never placed on the runq, make sure
1014 * nothing we've done put it there.
1016 KKASSERT(get_mplock_count(curthread) == 1);
1017 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
1020 * Enable interrupts here. idle_restore will also do it, but
1021 * doing it here lets us clean up any strays that got posted to
1022 * the CPU during the AP boot while we are still in a critical
1025 __asm __volatile("sti; pause; pause"::);
1026 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1028 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1029 lwkt_process_ipiq();
1032 * Releasing the mp lock lets the BSP finish up the SMP init
1035 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1039 * Get SMP fully working before we start initializing devices.
1047 kprintf("Finish MP startup\n");
1049 while (smp_active_mask != smp_startup_mask)
1051 while (try_mplock() == 0)
1054 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
1057 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1060 cpu_send_ipiq(int dcpu)
1062 if (CPUMASK(dcpu) & smp_active_mask)
1063 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1066 #if 0 /* single_apic_ipi_passive() not working yet */
1068 * Returns 0 on failure, 1 on success
1071 cpu_send_ipiq_passive(int dcpu)
1074 if (CPUMASK(dcpu) & smp_active_mask) {
1075 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1076 APIC_DELMODE_FIXED);
1083 mp_bsp_simple_setup(void)
1085 /* build our map of 'other' CPUs */
1086 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1087 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
1088 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
1092 if (cpu_feature & CPUID_TSC)
1093 tsc0_offset = rdtsc();