2 * Copyright (c) 1999 Seigo Tanimura
5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in
6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor.
7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * $FreeBSD: src/sys/dev/sound/pci/csa.c,v 1.33.2.1 2005/12/30 19:55:53 netchild Exp $
31 * $DragonFly: src/sys/dev/sound/pci/csa.c,v 1.8 2007/01/04 21:47:02 corecode Exp $
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
41 #include <sys/soundcard.h>
43 #include <dev/sound/pcm/sound.h>
44 #include <dev/sound/chip.h>
45 #include <dev/sound/pci/csareg.h>
46 #include <dev/sound/pci/csavar.h>
48 #include <bus/pci/pcireg.h>
49 #include <bus/pci/pcivar.h>
51 #include <dev/sound/pci/gnu/csaimg.h>
53 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/csa.c,v 1.8 2007/01/04 21:47:02 corecode Exp $");
55 /* This is the pci device id. */
56 #define CS4610_PCI_ID 0x60011013
57 #define CS4614_PCI_ID 0x60031013
58 #define CS4615_PCI_ID 0x60041013
60 /* Here is the parameter structure per a device. */
62 device_t dev; /* device */
63 csa_res res; /* resources */
65 device_t pcm; /* pcm device */
66 driver_intr_t* pcmintr; /* pcm intr */
67 void *pcmintr_arg; /* pcm intr arg */
68 device_t midi; /* midi device */
69 driver_intr_t* midiintr; /* midi intr */
70 void *midiintr_arg; /* midi intr arg */
71 void *ih; /* cookie */
73 struct csa_card *card;
74 struct csa_bridgeinfo binfo; /* The state of this bridge. */
77 typedef struct csa_softc *sc_p;
79 static int csa_probe(device_t dev);
80 static int csa_attach(device_t dev);
81 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
82 u_long start, u_long end, u_long count, u_int flags);
83 static int csa_release_resource(device_t bus, device_t child, int type, int rid,
85 static int csa_setup_intr(device_t bus, device_t child,
86 struct resource *irq, int flags,
87 driver_intr_t *intr, void *arg, void **cookiep);
88 static int csa_teardown_intr(device_t bus, device_t child,
89 struct resource *irq, void *cookie);
90 static driver_intr_t csa_intr;
91 static int csa_initialize(sc_p scp);
92 static int csa_downloadimage(csa_res *resp);
94 static devclass_t csa_devclass;
110 devclass_t pci_devclass;
111 device_t *pci_devices, *pci_children, *busp, *childp;
112 int pci_count = 0, pci_childcount = 0;
115 bus_space_tag_t btag;
117 if ((pci_devclass = devclass_find("pci")) == NULL) {
121 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
123 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
125 device_get_children(*busp, &pci_children, &pci_childcount);
126 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
127 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) {
128 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10;
130 btag = I386_BUS_SPACE_IO;
132 control = bus_space_read_2(btag, 0x0, port);
134 control |= run? 0 : 0x2000;
135 bus_space_write_2(btag, 0x0, port, control);
136 kfree(pci_devices, M_TEMP);
137 kfree(pci_children, M_TEMP);
141 kfree(pci_children, M_TEMP);
144 kfree(pci_devices, M_TEMP);
151 static struct csa_card cards_4610[] = {
152 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0},
155 static struct csa_card cards_4614[] = {
156 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0},
157 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1},
158 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0},
159 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
160 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
161 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0},
162 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0},
163 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0},
164 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0},
167 static struct csa_card cards_4615[] = {
168 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0},
171 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0};
176 struct csa_card *cards;
179 static struct card_type cards[] = {
180 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610},
181 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614},
182 {CS4615_PCI_ID, "CS4615", cards_4615},
186 static struct card_type *
187 csa_findcard(device_t dev)
192 while (cards[i].devid != 0) {
193 if (pci_get_devid(dev) == cards[i].devid)
201 csa_findsubcard(device_t dev)
204 struct card_type *card;
205 struct csa_card *subcard;
207 card = csa_findcard(dev);
210 subcard = card->cards;
212 while (subcard[i].subvendor != 0) {
213 if (pci_get_subvendor(dev) == subcard[i].subvendor
214 && pci_get_subdevice(dev) == subcard[i].subdevice) {
223 csa_probe(device_t dev)
225 struct card_type *card;
227 card = csa_findcard(dev);
229 device_set_desc(dev, card->name);
230 return BUS_PROBE_DEFAULT;
236 csa_attach(device_t dev)
241 struct sndcard_func *func;
244 scp = device_get_softc(dev);
246 /* Fill in the softc. */
247 bzero(scp, sizeof(*scp));
250 /* Wake up the device. */
251 stcmd = pci_read_config(dev, PCIR_COMMAND, 2);
252 if ((stcmd & PCIM_CMD_MEMEN) == 0 || (stcmd & PCIM_CMD_BUSMASTEREN) == 0) {
253 stcmd |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
254 pci_write_config(dev, PCIR_COMMAND, stcmd, 2);
257 /* Allocate the resources. */
259 scp->card = csa_findsubcard(dev);
260 scp->binfo.card = scp->card;
261 kprintf("csa: card is %s\n", scp->card->name);
262 resp->io_rid = PCIR_BAR(0);
263 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
264 &resp->io_rid, RF_ACTIVE);
265 if (resp->io == NULL)
267 resp->mem_rid = PCIR_BAR(1);
268 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
269 &resp->mem_rid, RF_ACTIVE);
270 if (resp->mem == NULL)
273 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
274 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE);
275 if (resp->irq == NULL)
278 /* Enable interrupt. */
279 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih))
282 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
283 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
286 /* Initialize the chip. */
287 if (csa_initialize(scp))
290 /* Reset the Processor. */
293 /* Download the Processor Image to the processor. */
294 if (csa_downloadimage(resp))
297 /* Attach the children. */
300 func = kmalloc(sizeof(struct sndcard_func), M_DEVBUF,
302 func->varinfo = &scp->binfo;
303 func->func = SCF_PCM;
304 scp->pcm = device_add_child(dev, "pcm", -1);
305 device_set_ivars(scp->pcm, func);
308 func = kmalloc(sizeof(struct sndcard_func), M_DEVBUF,
310 func->varinfo = &scp->binfo;
311 func->func = SCF_MIDI;
312 scp->midi = device_add_child(dev, "midi", -1);
313 device_set_ivars(scp->midi, func);
315 bus_generic_attach(dev);
320 bus_teardown_intr(dev, resp->irq, scp->ih);
322 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
324 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
326 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
331 csa_detach(device_t dev)
337 scp = device_get_softc(dev);
341 if (scp->midi != NULL)
342 err = device_delete_child(dev, scp->midi);
347 if (scp->pcm != NULL)
348 err = device_delete_child(dev, scp->pcm);
353 bus_teardown_intr(dev, resp->irq, scp->ih);
354 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
355 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
356 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
358 return bus_generic_detach(dev);
362 csa_resume(device_t dev)
367 scp = device_get_softc(dev);
370 /* Initialize the chip. */
371 if (csa_initialize(scp))
374 /* Reset the Processor. */
377 /* Download the Processor Image to the processor. */
378 if (csa_downloadimage(resp))
381 return (bus_generic_resume(dev));
384 static struct resource *
385 csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
386 u_long start, u_long end, u_long count, u_int flags)
390 struct resource *res;
392 scp = device_get_softc(bus);
420 csa_release_resource(device_t bus, device_t child, int type, int rid,
427 * The following three functions deal with interrupt handling.
428 * An interrupt is primarily handled by the bridge driver.
429 * The bridge driver then determines the child devices to pass
430 * the interrupt. Certain information of the device can be read
431 * only once(eg the value of HISR). The bridge driver is responsible
432 * to pass such the information to the children.
436 csa_setup_intr(device_t bus, device_t child,
437 struct resource *irq, int flags,
438 driver_intr_t *intr, void *arg, void **cookiep)
442 struct sndcard_func *func;
444 scp = device_get_softc(bus);
448 * Look at the function code of the child to determine
449 * the appropriate hander for it.
451 func = device_get_ivars(child);
452 if (func == NULL || irq != resp->irq)
455 switch (func->func) {
458 scp->pcmintr_arg = arg;
462 scp->midiintr = intr;
463 scp->midiintr_arg = arg;
470 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
471 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
477 csa_teardown_intr(device_t bus, device_t child,
478 struct resource *irq, void *cookie)
482 struct sndcard_func *func;
484 scp = device_get_softc(bus);
488 * Look at the function code of the child to determine
489 * the appropriate hander for it.
491 func = device_get_ivars(child);
492 if (func == NULL || irq != resp->irq || cookie != scp)
495 switch (func->func) {
498 scp->pcmintr_arg = NULL;
502 scp->midiintr = NULL;
503 scp->midiintr_arg = NULL;
513 /* The interrupt handler */
523 /* Is this interrupt for us? */
524 hisr = csa_readio(resp, BA0_HISR);
525 if ((hisr & 0x7fffffff) == 0) {
527 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
532 * Pass the value of HISR via struct csa_bridgeinfo.
533 * The children get access through their ivars.
535 scp->binfo.hisr = hisr;
537 /* Invoke the handlers of the children. */
538 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
539 scp->pcmintr(scp->pcmintr_arg);
540 hisr &= ~(HISR_VC0 | HISR_VC1);
542 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
543 scp->midiintr(scp->midiintr_arg);
548 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
552 csa_initialize(sc_p scp)
555 u_int32_t acsts, acisv;
561 * First, blast the clock control register to zero so that the PLL starts
562 * out in a known state, and blast the master serial port control register
563 * to zero so that the serial ports also start out in a known state.
565 csa_writeio(resp, BA0_CLKCR1, 0);
566 csa_writeio(resp, BA0_SERMC1, 0);
569 * If we are in AC97 mode, then we must set the part to a host controlled
570 * AC-link. Otherwise, we won't be able to bring up the link.
573 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
575 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
579 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
580 * spec) and then drive it high. This is done for non AC97 modes since
581 * there might be logic external to the CS461x that uses the ARST# line
584 csa_writeio(resp, BA0_ACCTL, 1);
586 csa_writeio(resp, BA0_ACCTL, 0);
588 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
591 * The first thing we do here is to enable sync generation. As soon
592 * as we start receiving bit clock, we'll start producing the SYNC
595 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
598 * Now wait for a short while to allow the AC97 part to start
599 * generating bit clock (so we don't try to start the PLL without an
605 * Set the serial port timing configuration, so that
606 * the clock control circuit gets its clock from the correct place.
608 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
612 * Write the selected clock control setup to the hardware. Do not turn on
613 * SWCE yet (if requested), so that the devices clocked by the output of
614 * PLL are not clocked until the PLL is stable.
616 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
617 csa_writeio(resp, BA0_PLLM, 0x3a);
618 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
623 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
626 * Wait until the PLL has stabilized.
631 * Turn on clocking of the core so that we can setup the serial ports.
633 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
636 * Fill the serial port FIFOs with silence.
638 csa_clearserialfifos(resp);
641 * Set the serial port FIFO pointer to the first sample in the FIFO.
644 csa_writeio(resp, BA0_SERBSP, 0);
648 * Write the serial port configuration to the part. The master
649 * enable bit is not set until all other values have been written.
651 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
652 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
653 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
656 * Wait for the codec ready signal from the AC97 codec.
659 for (i = 0 ; i < 1000 ; i++) {
661 * First, lets wait a short while to let things settle out a bit,
662 * and to prevent retrying the read too quickly.
667 * Read the AC97 status register to see if we've seen a CODEC READY
668 * signal from the AC97 codec.
670 acsts = csa_readio(resp, BA0_ACSTS);
671 if ((acsts & ACSTS_CRDY) != 0)
676 * Make sure we sampled CODEC READY.
678 if ((acsts & ACSTS_CRDY) == 0)
682 * Assert the vaid frame signal so that we can start sending commands
685 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
688 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
689 * the codec is pumping ADC data across the AC-link.
692 for (i = 0 ; i < 1000 ; i++) {
694 * First, lets wait a short while to let things settle out a bit,
695 * and to prevent retrying the read too quickly.
698 DELAY(10000000L); /* clw */
703 * Read the input slot valid register and see if input slots 3 and
706 acisv = csa_readio(resp, BA0_ACISV);
707 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
711 * Make sure we sampled valid input slots 3 and 4. If not, then return
714 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
718 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
719 * commense the transfer of digital audio data to the AC97 codec.
721 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
724 * Power down the DAC and ADC. We will power them up (if) when we need
728 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
732 * Turn off the Processor by turning off the software clock enable flag in
733 * the clock control register.
736 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
737 csa_writeio(resp, BA0_CLKCR1, clkcr1);
741 * Enable interrupts on the part.
744 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
751 csa_clearserialfifos(csa_res *resp)
754 u_int8_t clkcr1, serbst;
757 * See if the devices are powered down. If so, we must power them up first
758 * or they will not respond.
761 clkcr1 = csa_readio(resp, BA0_CLKCR1);
762 if ((clkcr1 & CLKCR1_SWCE) == 0) {
763 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
768 * We want to clear out the serial port FIFOs so we don't end up playing
769 * whatever random garbage happens to be in them. We fill the sample FIFOs
770 * with zero (silence).
772 csa_writeio(resp, BA0_SERBWP, 0);
774 /* Fill all 256 sample FIFO locations. */
776 for (i = 0 ; i < 256 ; i++) {
777 /* Make sure the previous FIFO write operation has completed. */
778 for (j = 0 ; j < 5 ; j++) {
780 serbst = csa_readio(resp, BA0_SERBST);
781 if ((serbst & SERBST_WBSY) == 0)
784 if ((serbst & SERBST_WBSY) != 0) {
786 csa_writeio(resp, BA0_CLKCR1, clkcr1);
788 /* Write the serial port FIFO index. */
789 csa_writeio(resp, BA0_SERBAD, i);
790 /* Tell the serial port to load the new value into the FIFO location. */
791 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
794 * Now, if we powered up the devices, then power them back down again.
795 * This is kinda ugly, but should never happen.
798 csa_writeio(resp, BA0_CLKCR1, clkcr1);
802 csa_resetdsp(csa_res *resp)
807 * Write the reset bit of the SP control register.
809 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
812 * Write the control register.
814 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
817 * Clear the trap registers.
819 for (i = 0 ; i < 8 ; i++) {
820 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
821 csa_writemem(resp, BA1_TWPR, 0xffff);
823 csa_writemem(resp, BA1_DREG, 0);
826 * Set the frame timer to reflect the number of cycles per frame.
828 csa_writemem(resp, BA1_FRMT, 0xadf);
832 csa_downloadimage(csa_res *resp)
835 u_int32_t tmp, src, dst, count, data;
837 for (i = 0; i < CLEAR__COUNT; i++) {
838 dst = ClrStat[i].BA1__DestByteOffset;
839 count = ClrStat[i].BA1__SourceSize;
840 for (tmp = 0; tmp < count; tmp += 4)
841 csa_writemem(resp, dst + tmp, 0x00000000);
844 for (i = 0; i < FILL__COUNT; i++) {
846 dst = FillStat[i].Offset;
847 count = FillStat[i].Size;
848 for (tmp = 0; tmp < count; tmp += 4) {
849 data = FillStat[i].pFill[src];
850 csa_writemem(resp, dst + tmp, data);
859 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
862 u_int32_t acsda, acctl, acsts;
865 * Make sure that there is not data sitting around from a previous
866 * uncompleted access. ACSDA = Status Data Register = 47Ch
868 acsda = csa_readio(resp, BA0_ACSDA);
871 * Setup the AC97 control registers on the CS461x to send the
872 * appropriate command to the AC97 to perform the read.
873 * ACCAD = Command Address Register = 46Ch
874 * ACCDA = Command Data Register = 470h
875 * ACCTL = Control Register = 460h
876 * set DCV - will clear when process completed
877 * set CRW - Read command
878 * set VFRM - valid frame enabled
879 * set ESYN - ASYNC generation enabled
880 * set RSTN - ARST# inactive, AC97 codec not reset
884 * Get the actual AC97 register from the offset
886 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
887 csa_writeio(resp, BA0_ACCDA, 0);
888 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
891 * Wait for the read to occur.
894 for (i = 0 ; i < 10 ; i++) {
896 * First, we want to wait for a short time.
901 * Now, check to see if the read has completed.
902 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
904 acctl = csa_readio(resp, BA0_ACCTL);
905 if ((acctl & ACCTL_DCV) == 0)
910 * Make sure the read completed.
912 if ((acctl & ACCTL_DCV) != 0)
916 * Wait for the valid status bit to go active.
919 for (i = 0 ; i < 10 ; i++) {
921 * Read the AC97 status register.
922 * ACSTS = Status Register = 464h
924 acsts = csa_readio(resp, BA0_ACSTS);
926 * See if we have valid status.
927 * VSTS - Valid Status
929 if ((acsts & ACSTS_VSTS) != 0)
932 * Wait for a short while.
938 * Make sure we got valid status.
940 if ((acsts & ACSTS_VSTS) == 0)
944 * Read the data returned from the AC97 register.
945 * ACSDA = Status Data Register = 474h
947 *data = csa_readio(resp, BA0_ACSDA);
953 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
959 * Setup the AC97 control registers on the CS461x to send the
960 * appropriate command to the AC97 to perform the write.
961 * ACCAD = Command Address Register = 46Ch
962 * ACCDA = Command Data Register = 470h
963 * ACCTL = Control Register = 460h
964 * set DCV - will clear when process completed
965 * set VFRM - valid frame enabled
966 * set ESYN - ASYNC generation enabled
967 * set RSTN - ARST# inactive, AC97 codec not reset
971 * Get the actual AC97 register from the offset
973 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
974 csa_writeio(resp, BA0_ACCDA, data);
975 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
978 * Wait for the write to occur.
981 for (i = 0 ; i < 10 ; i++) {
983 * First, we want to wait for a short time.
988 * Now, check to see if the read has completed.
989 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
991 acctl = csa_readio(resp, BA0_ACCTL);
992 if ((acctl & ACCTL_DCV) == 0)
997 * Make sure the write completed.
999 if ((acctl & ACCTL_DCV) != 0)
1006 csa_readio(csa_res *resp, u_long offset)
1010 if (offset < BA0_AC97_RESET)
1011 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
1013 if (csa_readcodec(resp, offset, &ul))
1020 csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
1022 if (offset < BA0_AC97_RESET)
1023 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
1025 csa_writecodec(resp, offset, data);
1029 csa_readmem(csa_res *resp, u_long offset)
1031 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset);
1035 csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
1037 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
1040 static device_method_t csa_methods[] = {
1041 /* Device interface */
1042 DEVMETHOD(device_probe, csa_probe),
1043 DEVMETHOD(device_attach, csa_attach),
1044 DEVMETHOD(device_detach, csa_detach),
1045 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1046 DEVMETHOD(device_suspend, bus_generic_suspend),
1047 DEVMETHOD(device_resume, csa_resume),
1050 DEVMETHOD(bus_print_child, bus_generic_print_child),
1051 DEVMETHOD(bus_alloc_resource, csa_alloc_resource),
1052 DEVMETHOD(bus_release_resource, csa_release_resource),
1053 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1054 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1055 DEVMETHOD(bus_setup_intr, csa_setup_intr),
1056 DEVMETHOD(bus_teardown_intr, csa_teardown_intr),
1061 static driver_t csa_driver = {
1064 sizeof(struct csa_softc),
1068 * csa can be attached to a pci bus.
1070 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0);
1071 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1072 MODULE_VERSION(snd_csa, 1);