2 * Copyright (c) 1993 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * $FreeBSD: src/sys/i386/include/cpufunc.h,v 1.96.2.3 2002/04/28 22:50:54 dwmalone Exp $
37 * Functions to provide access to special i386 instructions.
40 #ifndef _CPU_CPUFUNC_H_
41 #define _CPU_CPUFUNC_H_
44 #include <sys/types.h>
47 #include <sys/cdefs.h>
51 #define readb(va) (*(volatile u_int8_t *) (va))
52 #define readw(va) (*(volatile u_int16_t *) (va))
53 #define readl(va) (*(volatile u_int32_t *) (va))
55 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
56 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
57 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
62 #include <machine/lock.h> /* XXX */
65 #ifdef SWTCH_OPTIM_STATS
66 extern int tlb_flush_count; /* XXX */
72 __asm __volatile("int $3");
78 __asm __volatile("pause");
82 * Find the first 1 in mask, starting with bit 0 and return the
83 * bit number. If mask is 0 the result is undefined.
90 __asm __volatile("bsfl %0,%0" : "=r" (result) : "0" (mask));
99 __asm __volatile("bsfl %0,%0" : "=r" (result) : "0" (mask));
104 * Find the last 1 in mask, starting with bit 31 and return the
105 * bit number. If mask is 0 the result is undefined.
107 static __inline u_int
112 __asm __volatile("bsrl %0,%0" : "=r" (result) : "0" (mask));
117 * Test and set the specified bit (1 << bit) in the integer. The
118 * previous value of the bit is returned (0 or 1).
121 btsl(u_int *mask, int bit)
125 __asm __volatile("btsl %2,%1; movl $0,%0; adcl $0,%0" :
126 "=r"(result), "=m"(*mask) : "r" (bit));
131 * Test and clear the specified bit (1 << bit) in the integer. The
132 * previous value of the bit is returned (0 or 1).
135 btrl(u_int *mask, int bit)
139 __asm __volatile("btrl %2,%1; movl $0,%0; adcl $0,%0" :
140 "=r"(result), "=m"(*mask) : "r" (bit));
145 do_cpuid(u_int ax, u_int *p)
147 __asm __volatile("cpuid"
148 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
153 cpuid_count(u_int ax, u_int cx, u_int *p)
155 __asm __volatile("cpuid"
156 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
157 : "0" (ax), "c" (cx));
160 #ifndef _CPU_DISABLE_INTR_DEFINED
163 cpu_disable_intr(void)
165 __asm __volatile("cli" : : : "memory");
170 #ifndef _CPU_ENABLE_INTR_DEFINED
173 cpu_enable_intr(void)
175 __asm __volatile("sti");
181 * Cpu and compiler memory ordering fence. mfence ensures strong read and
184 * A serializing or fence instruction is required here. A locked bus
185 * cycle on data for which we already own cache mastership is the most
193 __asm __volatile("mfence" : : : "memory");
195 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
198 __asm __volatile("" : : : "memory");
203 * cpu_lfence() ensures strong read ordering for reads issued prior
204 * to the instruction verses reads issued afterwords.
206 * A serializing or fence instruction is required here. A locked bus
207 * cycle on data for which we already own cache mastership is the most
215 __asm __volatile("lfence" : : : "memory");
217 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
220 __asm __volatile("" : : : "memory");
225 * cpu_sfence() ensures strong write ordering for writes issued prior
226 * to the instruction verses writes issued afterwords. Writes are
227 * ordered on intel cpus so we do not actually have to do anything.
234 * Don't use 'sfence' here, as it will create a lot of
235 * unnecessary stalls.
237 __asm __volatile("" : : : "memory");
241 * cpu_ccfence() prevents the compiler from reordering instructions, in
242 * particular stores, relative to the current cpu. Use cpu_sfence() if
243 * you need to guarentee ordering by both the compiler and by the cpu.
245 * This also prevents the compiler from caching memory loads into local
246 * variables across the routine.
251 __asm __volatile("" : : : "memory");
256 #define HAVE_INLINE_FFS
262 * Note that gcc-2's builtin ffs would be used if we didn't declare
263 * this inline or turn off the builtin. The builtin is faster but
264 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
267 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
270 #define HAVE_INLINE_FLS
275 return (mask == 0 ? mask : (int) bsrl((u_int)mask) + 1);
281 * The following complications are to get around gcc not having a
282 * constraint letter for the range 0..255. We still put "d" in the
283 * constraint because "i" isn't a valid constraint when the port
284 * isn't constant. This only matters for -O0 because otherwise
285 * the non-working version gets optimized away.
287 * Use an expression-statement instead of a conditional expression
288 * because gcc-2.6.0 would promote the operands of the conditional
289 * and produce poor code for "if ((inb(var) & const1) == const2)".
291 * The unnecessary test `(port) < 0x10000' is to generate a warning if
292 * the `port' has type u_short or smaller. Such types are pessimal.
293 * This actually only works for signed types. The range check is
294 * careful to avoid generating warnings.
296 #define inb(port) __extension__ ({ \
298 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
299 && (port) < 0x10000) \
300 _data = inbc(port); \
302 _data = inbv(port); \
305 #define outb(port, data) ( \
306 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
307 && (port) < 0x10000 \
308 ? outbc(port, data) : outbv(port, data))
310 static __inline u_char
315 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
320 outbc(u_int port, u_char data)
322 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
325 static __inline u_char
330 * We use %%dx and not %1 here because i/o is done at %dx and not at
331 * %edx, while gcc generates inferior code (movw instead of movl)
332 * if we tell it to load (u_short) port.
334 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
338 static __inline u_int
343 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
348 insb(u_int port, void *addr, size_t cnt)
350 __asm __volatile("cld; rep; insb"
351 : "=D" (addr), "=c" (cnt)
352 : "0" (addr), "1" (cnt), "d" (port)
357 insw(u_int port, void *addr, size_t cnt)
359 __asm __volatile("cld; rep; insw"
360 : "=D" (addr), "=c" (cnt)
361 : "0" (addr), "1" (cnt), "d" (port)
366 insl(u_int port, void *addr, size_t cnt)
368 __asm __volatile("cld; rep; insl"
369 : "=D" (addr), "=c" (cnt)
370 : "0" (addr), "1" (cnt), "d" (port)
377 __asm __volatile("invd");
383 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
384 * will cause the invl*() functions to be equivalent to the cpu_invl*()
388 void smp_invltlb(void);
389 void smp_invltlb_intr(void);
391 #define smp_invltlb()
394 #ifndef _CPU_INVLPG_DEFINED
397 * Invalidate a patricular VA on this cpu only
400 cpu_invlpg(void *addr)
402 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
407 #ifndef _CPU_INVLTLB_DEFINED
410 * Invalidate the TLB on this cpu only
417 * This should be implemented as load_cr3(rcr3()) when load_cr3()
420 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
422 #if defined(SWTCH_OPTIM_STATS)
432 __asm __volatile("rep; nop");
437 static __inline u_short
442 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
446 static __inline u_int
447 loadandclear(volatile u_int *addr)
451 __asm __volatile("xorl %0,%0; xchgl %1,%0"
452 : "=&r" (result) : "m" (*addr));
457 outbv(u_int port, u_char data)
461 * Use an unnecessary assignment to help gcc's register allocator.
462 * This make a large difference for gcc-1.40 and a tiny difference
463 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
464 * best results. gcc-2.6.0 can't handle this.
467 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
471 outl(u_int port, u_int data)
474 * outl() and outw() aren't used much so we haven't looked at
475 * possible micro-optimizations such as the unnecessary
476 * assignment for them.
478 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
482 outsb(u_int port, const void *addr, size_t cnt)
484 __asm __volatile("cld; rep; outsb"
485 : "=S" (addr), "=c" (cnt)
486 : "0" (addr), "1" (cnt), "d" (port));
490 outsw(u_int port, const void *addr, size_t cnt)
492 __asm __volatile("cld; rep; outsw"
493 : "=S" (addr), "=c" (cnt)
494 : "0" (addr), "1" (cnt), "d" (port));
498 outsl(u_int port, const void *addr, size_t cnt)
500 __asm __volatile("cld; rep; outsl"
501 : "=S" (addr), "=c" (cnt)
502 : "0" (addr), "1" (cnt), "d" (port));
506 outw(u_int port, u_short data)
508 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
511 static __inline u_int
516 __asm __volatile("movl %%cr2,%0" : "=r" (data));
520 static __inline u_int
525 __asm __volatile("pushfl; popl %0" : "=r" (ef));
529 static __inline u_int64_t
534 __asm __volatile("rdmsr" : "=A" (rv) : "c" (msr));
538 static __inline u_int64_t
543 __asm __volatile("rdpmc" : "=A" (rv) : "c" (pmc));
547 #define _RDTSC_SUPPORTED_
549 static __inline u_int64_t
554 __asm __volatile("rdtsc" : "=A" (rv));
561 __asm __volatile("wbinvd");
565 write_eflags(u_int ef)
567 __asm __volatile("pushl %0; popfl" : : "r" (ef));
571 wrmsr(u_int msr, u_int64_t newval)
573 __asm __volatile("wrmsr" : : "A" (newval), "c" (msr));
576 static __inline u_short
580 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
584 static __inline u_short
588 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
595 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
601 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
604 static __inline u_int
608 __asm __volatile("movl %%dr0,%0" : "=r" (data));
615 __asm __volatile("movl %0,%%dr0" : : "r" (sel));
618 static __inline u_int
622 __asm __volatile("movl %%dr1,%0" : "=r" (data));
629 __asm __volatile("movl %0,%%dr1" : : "r" (sel));
632 static __inline u_int
636 __asm __volatile("movl %%dr2,%0" : "=r" (data));
643 __asm __volatile("movl %0,%%dr2" : : "r" (sel));
646 static __inline u_int
650 __asm __volatile("movl %%dr3,%0" : "=r" (data));
657 __asm __volatile("movl %0,%%dr3" : : "r" (sel));
660 static __inline u_int
664 __asm __volatile("movl %%dr4,%0" : "=r" (data));
671 __asm __volatile("movl %0,%%dr4" : : "r" (sel));
674 static __inline u_int
678 __asm __volatile("movl %%dr5,%0" : "=r" (data));
685 __asm __volatile("movl %0,%%dr5" : : "r" (sel));
688 static __inline u_int
692 __asm __volatile("movl %%dr6,%0" : "=r" (data));
699 __asm __volatile("movl %0,%%dr6" : : "r" (sel));
702 static __inline u_int
706 __asm __volatile("movl %%dr7,%0" : "=r" (data));
713 __asm __volatile("movl %0,%%dr7" : : "r" (sel));
716 #else /* !__GNUC__ */
718 int breakpoint (void);
719 void cpu_pause (void);
720 u_int bsfl (u_int mask);
721 u_int bsrl (u_int mask);
722 void cpu_disable_intr (void);
723 void do_cpuid (u_int ax, u_int *p);
724 void cpu_enable_intr (void);
725 u_char inb (u_int port);
726 u_int inl (u_int port);
727 void insb (u_int port, void *addr, size_t cnt);
728 void insl (u_int port, void *addr, size_t cnt);
729 void insw (u_int port, void *addr, size_t cnt);
731 u_short inw (u_int port);
732 u_int loadandclear (u_int *addr);
733 void outb (u_int port, u_char data);
734 void outl (u_int port, u_int data);
735 void outsb (u_int port, void *addr, size_t cnt);
736 void outsl (u_int port, void *addr, size_t cnt);
737 void outsw (u_int port, void *addr, size_t cnt);
738 void outw (u_int port, u_short data);
740 u_int64_t rdmsr (u_int msr);
741 u_int64_t rdpmc (u_int pmc);
742 u_int64_t rdtsc (void);
743 u_int read_eflags (void);
745 void write_eflags (u_int ef);
746 void wrmsr (u_int msr, u_int64_t newval);
749 void load_fs (u_short sel);
750 void load_gs (u_short sel);
752 #endif /* __GNUC__ */
754 void load_cr0 (u_int cr0);
755 void load_cr3 (u_int cr3);
756 void load_cr4 (u_int cr4);
757 void ltr (u_short sel);
761 int rdmsr_safe (u_int msr, uint64_t *val);
762 void reset_dbregs (void);
765 #endif /* !_CPU_CPUFUNC_H_ */