2 * Copyright (c) 1995 - 2001 John Hay. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Neither the name of the author nor the names of any co-contributors
13 * may be used to endorse or promote products derived from this software
14 * without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY John Hay ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL John Hay BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/ar/if_ar.c,v 1.52.2.1 2002/06/17 15:10:57 jhay Exp $
29 * $DragonFly: src/sys/dev/netif/ar/if_ar.c,v 1.5 2003/11/20 22:07:26 dillon Exp $
33 * Programming assumptions and other issues.
35 * The descriptors of a DMA channel will fit in a 16K memory window.
37 * The buffers of a transmit DMA channel will fit in a 16K memory window.
39 * Only the ISA bus cards with X.21 and V.35 is tested.
41 * When interface is going up, handshaking is set and it is only cleared
42 * when the interface is down'ed.
44 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
45 * internal/external clock, etc.....
49 #include "opt_netgraph.h"
51 #include <sys/param.h>
52 #include <sys/systm.h>
53 #include <sys/kernel.h>
54 #include <sys/malloc.h>
56 #include <sys/socket.h>
57 #include <sys/sockio.h>
58 #include <sys/module.h>
60 #include <machine/bus.h>
61 #include <machine/resource.h>
62 #include <machine/bus_pio.h>
63 #include <machine/bus_memio.h>
68 #include <netgraph/ng_message.h>
69 #include <netgraph/netgraph.h>
70 #include <sys/syslog.h>
73 #include <net/sppp/if_sppp.h>
77 #include <machine/clock.h>
78 #include <machine/md_var.h>
80 #include "../ic_layer/hd64570.h"
81 #include "if_arregs.h"
91 #define PPP_HEADER_LEN 4
97 int unit; /* With regards to all ar devices */
98 int subunit; /* With regards to this card */
102 u_int txdesc; /* On card address */
103 u_int txstart; /* On card address */
104 u_int txend; /* On card address */
105 u_int txtail; /* Index of first unused buffer */
106 u_int txmax; /* number of usable buffers/descriptors */
107 u_int txeda; /* Error descriptor addresses */
108 }block[AR_TX_BLOCKS];
110 char xmit_busy; /* Transmitter is busy */
111 char txb_inuse; /* Number of tx blocks currently in use */
112 u_char txb_new; /* Index to where new buffer will be added */
113 u_char txb_next_tx; /* Index to next block ready to tx */
115 u_int rxdesc; /* On card address */
116 u_int rxstart; /* On card address */
117 u_int rxend; /* On card address */
118 u_int rxhind; /* Index to the head of the rx buffers. */
119 u_int rxmax; /* number of usable buffers/descriptors */
125 int running; /* something is attached so we are running */
126 int dcd; /* do we have dcd? */
127 /* ---netgraph bits --- */
128 char nodename[NG_NODELEN + 1]; /* store our node name */
129 int datahooks; /* number of data hooks attached */
130 node_p node; /* netgraph node */
131 hook_p hook; /* data hook */
133 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */
134 struct ifqueue xmitq; /* transmit queue */
135 int flags; /* state */
136 #define SCF_RUNNING 0x01 /* board is active */
137 #define SCF_OACTIVE 0x02 /* output is active */
138 int out_dog; /* watchdog cycles output count-down */
139 struct callout_handle handle; /* timeout(9) handle */
140 u_long inbytes, outbytes; /* stats */
141 u_long lastinbytes, lastoutbytes; /* a second ago */
142 u_long inrate, outrate; /* highest rate seen */
143 u_long inlast; /* last input N secs ago */
144 u_long out_deficit; /* output since last input */
145 u_long oerrors, ierrors[6];
146 u_long opackets, ipackets;
147 #endif /* NETGRAPH */
150 static int next_ar_unit = 0;
153 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */
154 #define QUITE_A_WHILE 300 /* 5 MINUTES */
155 #define LOTS_OF_PACKETS 100
156 #endif /* NETGRAPH */
159 * This translate from irq numbers to
160 * the value that the arnet card needs
161 * in the lower part of the AR_INT_SEL
164 static int irqtable[16] = {
184 DECLARE_DUMMY_MODULE(if_ar);
185 MODULE_DEPEND(if_ar, sppp, 1, 1, 1);
187 MODULE_DEPEND(ng_sync_ar, netgraph, 1, 1, 1);
190 static void arintr(void *arg);
191 static void ar_xmit(struct ar_softc *sc);
193 static void arstart(struct ifnet *ifp);
194 static int arioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
195 static void arwatchdog(struct ifnet *ifp);
197 static void arstart(struct ar_softc *sc);
198 static void arwatchdog(struct ar_softc *sc);
199 #endif /* NETGRAPH */
200 static int ar_packet_avail(struct ar_softc *sc, int *len, u_char *rxstat);
201 static void ar_copy_rxbuf(struct mbuf *m, struct ar_softc *sc, int len);
202 static void ar_eat_packet(struct ar_softc *sc, int single);
203 static void ar_get_packets(struct ar_softc *sc);
205 static int ar_read_pim_iface(volatile struct ar_hardc *hc, int channel);
206 static void ar_up(struct ar_softc *sc);
207 static void ar_down(struct ar_softc *sc);
208 static void arc_init(struct ar_hardc *hc);
209 static void ar_init_sca(struct ar_hardc *hc, int scano);
210 static void ar_init_msci(struct ar_softc *sc);
211 static void ar_init_rx_dmac(struct ar_softc *sc);
212 static void ar_init_tx_dmac(struct ar_softc *sc);
213 static void ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr);
214 static void ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr);
215 static void ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr);
218 static void ngar_watchdog_frame(void * arg);
219 static void ngar_init(void* ignored);
221 static ng_constructor_t ngar_constructor;
222 static ng_rcvmsg_t ngar_rcvmsg;
223 static ng_shutdown_t ngar_rmnode;
224 static ng_newhook_t ngar_newhook;
225 /*static ng_findhook_t ngar_findhook; */
226 static ng_connect_t ngar_connect;
227 static ng_rcvdata_t ngar_rcvdata;
228 static ng_disconnect_t ngar_disconnect;
230 static struct ng_type typestruct = {
246 static int ngar_done_init = 0;
247 #endif /* NETGRAPH */
250 ar_attach(device_t device)
257 #endif /* NETGRAPH */
260 hc = (struct ar_hardc *)device_get_softc(device);
262 printf("arc%d: %uK RAM, %u ports, rev %u.\n",
270 if(BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
271 INTR_TYPE_NET, arintr, hc, &hc->intr_cookie) != 0)
276 for(unit=0;unit<hc->numports;unit+=NCHAN)
277 ar_init_sca(hc, unit / NCHAN);
280 * Now configure each port on the card.
282 for(unit=0;unit<hc->numports;sc++,unit++) {
285 sc->unit = next_ar_unit;
287 sc->scano = unit / NCHAN;
288 sc->scachan = unit%NCHAN;
295 ifp = &sc->ifsppp.pp_if;
298 ifp->if_unit = sc->unit;
300 ifp->if_mtu = PP_MTU;
301 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
302 ifp->if_ioctl = arioctl;
303 ifp->if_start = arstart;
304 ifp->if_watchdog = arwatchdog;
306 sc->ifsppp.pp_flags = PP_KEEPALIVE;
308 switch(hc->interface[unit]) {
309 default: iface = "UNKNOWN"; break;
310 case AR_IFACE_EIA_232: iface = "EIA-232"; break;
311 case AR_IFACE_V_35: iface = "EIA-232 or V.35"; break;
312 case AR_IFACE_EIA_530: iface = "EIA-530"; break;
313 case AR_IFACE_X_21: iface = "X.21"; break;
314 case AR_IFACE_COMBO: iface = "COMBO X.21 / EIA-530"; break;
317 printf("ar%d: Adapter %d, port %d, interface %s.\n",
323 sppp_attach((struct ifnet *)&sc->ifsppp);
326 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
329 * we have found a node, make sure our 'type' is availabe.
331 if (ngar_done_init == 0) ngar_init(NULL);
332 if (ng_make_node_common(&typestruct, &sc->node) != 0)
334 sc->node->private = sc;
335 callout_handle_init(&sc->handle);
336 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
337 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
338 sprintf(sc->nodename, "%s%d", NG_AR_NODE_TYPE, sc->unit);
339 if (ng_name_node(sc->node, sc->nodename)) {
345 #endif /* NETGRAPH */
348 if(hc->bustype == AR_BUS_ISA)
349 ARC_SET_OFF(hc->iobase);
355 ar_detach(device_t device)
357 device_t parent = device_get_parent(device);
358 struct ar_hardc *hc = device_get_softc(device);
360 if (hc->intr_cookie != NULL) {
361 if (BUS_TEARDOWN_INTR(parent, device,
362 hc->res_irq, hc->intr_cookie) != 0) {
363 printf("intr teardown failed.. continuing\n");
365 hc->intr_cookie = NULL;
369 * deallocate any system resources we may have
370 * allocated on behalf of this driver.
372 FREE(hc->sc, M_DEVBUF);
374 hc->mem_start = NULL;
375 return (ar_deallocate_resources(device));
379 ar_allocate_ioport(device_t device, int rid, u_long size)
381 struct ar_hardc *hc = device_get_softc(device);
383 hc->rid_ioport = rid;
384 hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
385 &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
386 if (hc->res_ioport == NULL) {
392 ar_deallocate_resources(device);
397 ar_allocate_irq(device_t device, int rid, u_long size)
399 struct ar_hardc *hc = device_get_softc(device);
402 hc->res_irq = bus_alloc_resource(device, SYS_RES_IRQ,
403 &hc->rid_irq, 0ul, ~0ul, 1, RF_SHAREABLE|RF_ACTIVE);
404 if (hc->res_irq == NULL) {
410 ar_deallocate_resources(device);
415 ar_allocate_memory(device_t device, int rid, u_long size)
417 struct ar_hardc *hc = device_get_softc(device);
419 hc->rid_memory = rid;
420 hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
421 &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
422 if (hc->res_memory == NULL) {
428 ar_deallocate_resources(device);
433 ar_allocate_plx_memory(device_t device, int rid, u_long size)
435 struct ar_hardc *hc = device_get_softc(device);
437 hc->rid_plx_memory = rid;
438 hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
439 &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
440 if (hc->res_plx_memory == NULL) {
446 ar_deallocate_resources(device);
451 ar_deallocate_resources(device_t device)
453 struct ar_hardc *hc = device_get_softc(device);
455 if (hc->res_irq != 0) {
456 bus_deactivate_resource(device, SYS_RES_IRQ,
457 hc->rid_irq, hc->res_irq);
458 bus_release_resource(device, SYS_RES_IRQ,
459 hc->rid_irq, hc->res_irq);
462 if (hc->res_ioport != 0) {
463 bus_deactivate_resource(device, SYS_RES_IOPORT,
464 hc->rid_ioport, hc->res_ioport);
465 bus_release_resource(device, SYS_RES_IOPORT,
466 hc->rid_ioport, hc->res_ioport);
469 if (hc->res_memory != 0) {
470 bus_deactivate_resource(device, SYS_RES_MEMORY,
471 hc->rid_memory, hc->res_memory);
472 bus_release_resource(device, SYS_RES_MEMORY,
473 hc->rid_memory, hc->res_memory);
476 if (hc->res_plx_memory != 0) {
477 bus_deactivate_resource(device, SYS_RES_MEMORY,
478 hc->rid_plx_memory, hc->res_plx_memory);
479 bus_release_resource(device, SYS_RES_MEMORY,
480 hc->rid_plx_memory, hc->res_plx_memory);
481 hc->res_plx_memory = 0;
487 * First figure out which SCA gave the interrupt.
489 * See if there is other interrupts pending.
490 * Repeat until there is no more interrupts.
495 struct ar_hardc *hc = (struct ar_hardc *)arg;
497 u_char isr0, isr1, isr2, arisr;
500 /* XXX Use the PCI interrupt score board register later */
501 if(hc->bustype == AR_BUS_PCI)
502 arisr = hc->orbase[AR_ISTAT * 4];
504 arisr = inb(hc->iobase + AR_ISTAT);
506 while(arisr & AR_BD_INT) {
507 TRC(printf("arisr = %x\n", arisr));
510 else if(arisr & AR_INT_1)
513 /* XXX Oops this shouldn't happen. */
514 printf("arc%d: Interrupted with no interrupt.\n",
518 sca = hc->sca[scano];
520 if(hc->bustype == AR_BUS_ISA)
521 ARC_SET_SCA(hc->iobase, scano);
527 TRC(printf("arc%d: ARINTR isr0 %x, isr1 %x, isr2 %x\n",
533 ar_msci_intr(hc, scano, isr0);
536 ar_dmac_intr(hc, scano, isr1);
539 ar_timer_intr(hc, scano, isr2);
542 * Proccess the second sca's interrupt if available.
543 * Else see if there are any new interrupts.
545 if((arisr & AR_INT_0) && (arisr & AR_INT_1))
548 if(hc->bustype == AR_BUS_PCI)
549 arisr = hc->orbase[AR_ISTAT * 4];
551 arisr = inb(hc->iobase + AR_ISTAT);
555 if(hc->bustype == AR_BUS_ISA)
556 ARC_SET_OFF(hc->iobase);
561 * This will only start the transmitter. It is assumed that the data
562 * is already there. It is normally called from arstart() or ar_dmac_intr().
566 ar_xmit(struct ar_softc *sc)
570 #endif /* NETGRAPH */
574 ifp = &sc->ifsppp.pp_if;
575 #endif /* NETGRAPH */
576 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
578 if(sc->hc->bustype == AR_BUS_ISA)
579 ARC_SET_SCA(sc->hc->iobase, sc->scano);
580 dmac->cda = (u_short)(sc->block[sc->txb_next_tx].txdesc & 0xffff);
582 dmac->eda = (u_short)(sc->block[sc->txb_next_tx].txeda & 0xffff);
583 dmac->dsr = SCA_DSR_DE;
588 if(sc->txb_next_tx == AR_TX_BLOCKS)
592 ifp->if_timer = 2; /* Value in seconds. */
594 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/
595 #endif /* NETGRAPH */
596 if(sc->hc->bustype == AR_BUS_ISA)
597 ARC_SET_OFF(sc->hc->iobase);
601 * This function will be called from the upper level when a user add a
602 * packet to be send, and from the interrupt handler after a finished
605 * NOTE: it should run at spl_imp().
607 * This function only place the data in the oncard buffers. It does not
608 * start the transmition. ar_xmit() does that.
610 * Transmitter idle state is indicated by the IFF_OACTIVE flag. The function
611 * that clears that should ensure that the transmitter and its DMA is
612 * in a "good" idle state.
616 arstart(struct ifnet *ifp)
618 struct ar_softc *sc = ifp->if_softc;
621 arstart(struct ar_softc *sc)
623 #endif /* NETGRAPH */
627 sca_descriptor *txdesc;
628 struct buf_block *blkp;
631 if(!(ifp->if_flags & IFF_RUNNING))
635 #endif /* NETGRAPH */
640 * See if we have space for more packets.
642 if(sc->txb_inuse == AR_TX_BLOCKS) {
644 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */
646 /*XXX*/ /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */
647 #endif /* NETGRAPH */
652 mtx = sppp_dequeue(ifp);
654 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
656 IF_DEQUEUE(&sc->xmitq, mtx);
658 #endif /* NETGRAPH */
663 * It is OK to set the memory window outside the loop because
664 * all tx buffers and descriptors are assumed to be in the same
667 if(sc->hc->bustype == AR_BUS_ISA)
668 ARC_SET_MEM(sc->hc->iobase, sc->block[0].txdesc);
671 * We stay in this loop until there is nothing in the
672 * TX queue left or the tx buffer is full.
675 blkp = &sc->block[sc->txb_new];
676 txdesc = (sca_descriptor *)
677 (sc->hc->mem_start + (blkp->txdesc & sc->hc->winmsk));
678 txdata = (u_char *)(sc->hc->mem_start + (blkp->txstart & sc->hc->winmsk));
680 len = mtx->m_pkthdr.len;
682 TRC(printf("ar%d: ARstart len %u\n", sc->unit, len));
685 * We can do this because the tx buffers don't wrap.
687 m_copydata(mtx, 0, len, txdata);
689 while(tlen > AR_BUF_SIZ) {
691 txdesc->len = AR_BUF_SIZ;
694 txdata += AR_BUF_SIZ;
697 /* XXX Move into the loop? */
698 txdesc->stat = SCA_DESC_EOM;
701 txdata += AR_BUF_SIZ;
708 ++sc->ifsppp.pp_if.if_opackets;
713 #endif /* NETGRAPH */
716 * Check if we have space for another mbuf.
717 * XXX This is hardcoded. A packet won't be larger
718 * than 3 buffers (3 x 512).
720 if((i + 3) >= blkp->txmax)
724 mtx = sppp_dequeue(ifp);
726 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
728 IF_DEQUEUE(&sc->xmitq, mtx);
730 #endif /* NETGRAPH */
738 * Mark the last descriptor, so that the SCA know where
742 txdesc->stat |= SCA_DESC_EOT;
744 txdesc = (sca_descriptor *)blkp->txdesc;
745 blkp->txeda = (u_short)((u_int)&txdesc[i]);
748 printf("ARstart: %p desc->cp %x\n", &txdesc->cp, txdesc->cp);
749 printf("ARstart: %p desc->bp %x\n", &txdesc->bp, txdesc->bp);
750 printf("ARstart: %p desc->bpb %x\n", &txdesc->bpb, txdesc->bpb);
751 printf("ARstart: %p desc->len %x\n", &txdesc->len, txdesc->len);
752 printf("ARstart: %p desc->stat %x\n", &txdesc->stat, txdesc->stat);
757 if(sc->txb_new == AR_TX_BLOCKS)
760 if(sc->xmit_busy == 0)
763 if(sc->hc->bustype == AR_BUS_ISA)
764 ARC_SET_OFF(sc->hc->iobase);
771 arioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
774 int was_up, should_be_up;
775 struct ar_softc *sc = ifp->if_softc;
777 TRC(printf("ar%d: arioctl.\n", ifp->if_unit);)
779 was_up = ifp->if_flags & IFF_RUNNING;
781 error = sppp_ioctl(ifp, cmd, data);
782 TRC(printf("ar%d: ioctl: ifsppp.pp_flags = %x, if_flags %x.\n",
783 ifp->if_unit, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);)
787 if((cmd != SIOCSIFFLAGS) && cmd != (SIOCSIFADDR))
790 TRC(printf("ar%d: arioctl %s.\n", ifp->if_unit,
791 (cmd == SIOCSIFFLAGS) ? "SIOCSIFFLAGS" : "SIOCSIFADDR");)
794 should_be_up = ifp->if_flags & IFF_RUNNING;
796 if(!was_up && should_be_up) {
797 /* Interface should be up -- start it. */
800 /* XXX Maybe clear the IFF_UP flag so that the link
801 * will only go up after sppp lcp and ipcp negotiation.
803 } else if(was_up && !should_be_up) {
804 /* Interface should be down -- stop it. */
811 #endif /* NETGRAPH */
814 * This is to catch lost tx interrupts.
818 arwatchdog(struct ifnet *ifp)
820 struct ar_softc *sc = ifp->if_softc;
822 arwatchdog(struct ar_softc *sc)
824 #endif /* NETGRAPH */
825 msci_channel *msci = &sc->sca->msci[sc->scachan];
828 if(!(ifp->if_flags & IFF_RUNNING))
830 #endif /* NETGRAPH */
832 if(sc->hc->bustype == AR_BUS_ISA)
833 ARC_SET_SCA(sc->hc->iobase, sc->scano);
835 /* XXX if(sc->ifsppp.pp_if.if_flags & IFF_DEBUG) */
836 printf("ar%d: transmit failed, "
837 "ST0 %x, ST1 %x, ST3 %x, DSR %x.\n",
842 sc->sca->dmac[DMAC_TXCH(sc->scachan)].dsr);
844 if(msci->st1 & SCA_ST1_UDRN) {
845 msci->cmd = SCA_CMD_TXABORT;
846 msci->cmd = SCA_CMD_TXENABLE;
847 msci->st1 = SCA_ST1_UDRN;
852 ifp->if_flags &= ~IFF_OACTIVE;
854 /* XXX ifp->if_flags &= ~IFF_OACTIVE; */
855 #endif /* NETGRAPH */
857 if(sc->txb_inuse && --sc->txb_inuse)
864 #endif /* NETGRAPH */
868 ar_up(struct ar_softc *sc)
874 msci = &sca->msci[sc->scachan];
876 TRC(printf("ar%d: sca %p, msci %p, ch %d\n",
877 sc->unit, sca, msci, sc->scachan));
880 * Enable transmitter and receiver.
884 if(sc->hc->bustype == AR_BUS_ISA)
885 ARC_SET_SCA(sc->hc->iobase, sc->scano);
888 * What about using AUTO mode in msci->md0 ???
889 * And what about CTS/DCD etc... ?
891 if(sc->hc->handshake & AR_SHSK_RTS)
892 msci->ctl &= ~SCA_CTL_RTS;
893 if(sc->hc->handshake & AR_SHSK_DTR) {
894 sc->hc->txc_dtr[sc->scano] &= sc->scachan ?
895 ~AR_TXC_DTR_DTR1 : ~AR_TXC_DTR_DTR0;
896 if(sc->hc->bustype == AR_BUS_PCI)
897 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
898 sc->hc->txc_dtr[sc->scano];
900 outb(sc->hc->iobase + sc->hc->txc_dtr_off[sc->scano],
901 sc->hc->txc_dtr[sc->scano]);
904 if(sc->scachan == 0) {
912 msci->cmd = SCA_CMD_RXENABLE;
913 if(sc->hc->bustype == AR_BUS_ISA)
914 inb(sc->hc->iobase + AR_ID_5); /* XXX slow it down a bit. */
915 msci->cmd = SCA_CMD_TXENABLE;
917 if(sc->hc->bustype == AR_BUS_ISA)
918 ARC_SET_OFF(sc->hc->iobase);
920 untimeout(ngar_watchdog_frame, sc, sc->handle);
921 sc->handle = timeout(ngar_watchdog_frame, sc, hz);
923 #endif /* NETGRAPH */
927 ar_down(struct ar_softc *sc)
933 msci = &sca->msci[sc->scachan];
936 untimeout(ngar_watchdog_frame, sc, sc->handle);
938 #endif /* NETGRAPH */
940 * Disable transmitter and receiver.
942 * Disable interrupts.
944 if(sc->hc->bustype == AR_BUS_ISA)
945 ARC_SET_SCA(sc->hc->iobase, sc->scano);
946 msci->cmd = SCA_CMD_RXDISABLE;
947 if(sc->hc->bustype == AR_BUS_ISA)
948 inb(sc->hc->iobase + AR_ID_5); /* XXX slow it down a bit. */
949 msci->cmd = SCA_CMD_TXDISABLE;
951 if(sc->hc->handshake & AR_SHSK_RTS)
952 msci->ctl |= SCA_CTL_RTS;
953 if(sc->hc->handshake & AR_SHSK_DTR) {
954 sc->hc->txc_dtr[sc->scano] |= sc->scachan ?
955 AR_TXC_DTR_DTR1 : AR_TXC_DTR_DTR0;
956 if(sc->hc->bustype == AR_BUS_PCI)
957 sc->hc->orbase[sc->hc->txc_dtr_off[sc->scano]] =
958 sc->hc->txc_dtr[sc->scano];
960 outb(sc->hc->iobase + sc->hc->txc_dtr_off[sc->scano],
961 sc->hc->txc_dtr[sc->scano]);
964 if(sc->scachan == 0) {
972 if(sc->hc->bustype == AR_BUS_ISA)
973 ARC_SET_OFF(sc->hc->iobase);
977 ar_read_pim_iface(volatile struct ar_hardc *hc, int channel)
979 int ctype, i, val, x;
980 volatile u_char *pimctrl;
985 pimctrl = hc->orbase + AR_PIMCTRL;
989 *pimctrl = AR_PIM_STROBE;
991 /* Check if there is a PIM */
993 *pimctrl = AR_PIM_READ;
995 TRC(printf("x = %x", x));
996 if(x & AR_PIM_DATA) {
997 printf("No PIM installed\n");
998 return (AR_IFACE_UNKNOWN);
1001 x = (x >> 1) & 0x01;
1004 /* Now read the next 15 bits */
1005 for(i = 1; i < 16; i++) {
1006 *pimctrl = AR_PIM_READ;
1007 *pimctrl = AR_PIM_READ | AR_PIM_STROBE;
1009 TRC(printf(" %x ", x));
1010 x = (x >> 1) & 0x01;
1012 if(i == 8 && (val & 0x000f) == 0x0004) {
1016 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1017 *pimctrl = AR_PIM_A2D_DOUT;
1020 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1021 *pimctrl = AR_PIM_A2D_DOUT;
1024 *pimctrl = AR_PIM_A2D_DOUT | AR_PIM_A2D_STROBE;
1025 *pimctrl = AR_PIM_A2D_DOUT;
1027 /* Select channel */
1028 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 2) << 2);
1029 *pimctrl = ((channel & 2) << 2);
1030 *pimctrl = AR_PIM_A2D_STROBE | ((channel & 1) << 3);
1031 *pimctrl = ((channel & 1) << 3);
1033 *pimctrl = AR_PIM_A2D_STROBE;
1037 printf("\nOops A2D start bit not zero (%X)\n", x);
1039 for(ii = 7; ii >= 0; ii--) {
1041 *pimctrl = AR_PIM_A2D_STROBE;
1048 TRC(printf("\nPIM val %x, ctype %x, %d\n", val, ctype, ctype));
1049 *pimctrl = AR_PIM_MODEG;
1050 *pimctrl = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1052 return (AR_IFACE_UNKNOWN);
1054 return (AR_IFACE_V_35);
1056 return (AR_IFACE_EIA_232);
1058 return (AR_IFACE_X_21);
1060 return (AR_IFACE_EIA_530);
1062 return (AR_IFACE_UNKNOWN);
1064 return (AR_IFACE_LOOPBACK);
1065 return (AR_IFACE_UNKNOWN);
1069 * Initialize the card, allocate memory for the ar_softc structures
1070 * and fill in the pointers.
1073 arc_init(struct ar_hardc *hc)
1075 struct ar_softc *sc;
1083 MALLOC(sc, struct ar_softc *, hc->numports * sizeof(struct ar_softc),
1084 M_DEVBUF, M_WAITOK | M_ZERO);
1089 hc->txc_dtr[0] = AR_TXC_DTR_NOTRESET |
1090 AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1091 hc->txc_dtr[1] = AR_TXC_DTR_DTR0 | AR_TXC_DTR_DTR1;
1092 hc->txc_dtr_off[0] = AR_TXC_DTR0;
1093 hc->txc_dtr_off[1] = AR_TXC_DTR2;
1094 if(hc->bustype == AR_BUS_PCI) {
1095 hc->txc_dtr_off[0] *= 4;
1096 hc->txc_dtr_off[1] *= 4;
1100 * reset the card and wait at least 1uS.
1102 if(hc->bustype == AR_BUS_PCI)
1103 hc->orbase[AR_TXC_DTR0 * 4] = ~AR_TXC_DTR_NOTRESET &
1106 outb(hc->iobase + AR_TXC_DTR0, ~AR_TXC_DTR_NOTRESET &
1109 if(hc->bustype == AR_BUS_PCI)
1110 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1112 outb(hc->iobase + AR_TXC_DTR0, hc->txc_dtr[0]);
1114 if(hc->bustype == AR_BUS_ISA) {
1116 * Configure the card.
1119 mar = kvtop(hc->mem_start) >> 16;
1120 isr = irqtable[hc->isa_irq] << 1;
1122 printf("ar%d: Warning illegal interrupt %d\n",
1123 hc->cunit, hc->isa_irq);
1124 isr = isr | ((kvtop(hc->mem_start) & 0xc000) >> 10);
1126 hc->sca[0] = (sca_regs *)hc->mem_start;
1127 hc->sca[1] = (sca_regs *)hc->mem_start;
1129 outb(hc->iobase + AR_MEM_SEL, mar);
1130 outb(hc->iobase + AR_INT_SEL, isr | AR_INTS_CEN);
1133 if(hc->bustype == AR_BUS_PCI && hc->interface[0] == AR_IFACE_PIM)
1134 for(x = 0; x < hc->numports; x++)
1135 hc->interface[x] = ar_read_pim_iface(hc, x);
1138 * Set the TX clock direction and enable TX.
1140 for(x=0;x<hc->numports;x++) {
1141 switch(hc->interface[x]) {
1143 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1144 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1145 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1146 AR_TXC_DTR_TXCS0 : AR_TXC_DTR_TXCS1;
1148 case AR_IFACE_EIA_530:
1149 case AR_IFACE_COMBO:
1151 hc->txc_dtr[x / NCHAN] |= (x % NCHAN == 0) ?
1152 AR_TXC_DTR_TX0 : AR_TXC_DTR_TX1;
1157 if(hc->bustype == AR_BUS_PCI)
1158 hc->orbase[AR_TXC_DTR0 * 4] = hc->txc_dtr[0];
1160 outb(hc->iobase + AR_TXC_DTR0, hc->txc_dtr[0]);
1161 if(hc->numports > NCHAN) {
1162 if(hc->bustype == AR_BUS_PCI)
1163 hc->orbase[AR_TXC_DTR2 * 4] = hc->txc_dtr[1];
1165 outb(hc->iobase + AR_TXC_DTR2, hc->txc_dtr[1]);
1168 chanmem = hc->memsize / hc->numports;
1171 for(x=0;x<hc->numports;x++, sc++) {
1174 sc->sca = hc->sca[x / NCHAN];
1176 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1177 sc->block[blk].txdesc = next;
1178 bufmem = (16 * 1024) / AR_TX_BLOCKS;
1179 descneeded = bufmem / AR_BUF_SIZ;
1180 sc->block[blk].txstart = sc->block[blk].txdesc +
1181 ((((descneeded * sizeof(sca_descriptor)) /
1182 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1183 sc->block[blk].txend = next + bufmem;
1184 sc->block[blk].txmax =
1185 (sc->block[blk].txend - sc->block[blk].txstart)
1189 TRC(printf("ar%d: blk %d: txdesc %x, txstart %x, "
1190 "txend %x, txmax %d\n",
1193 sc->block[blk].txdesc,
1194 sc->block[blk].txstart,
1195 sc->block[blk].txend,
1196 sc->block[blk].txmax));
1200 bufmem = chanmem - (bufmem * AR_TX_BLOCKS);
1201 descneeded = bufmem / AR_BUF_SIZ;
1202 sc->rxstart = sc->rxdesc +
1203 ((((descneeded * sizeof(sca_descriptor)) /
1204 AR_BUF_SIZ) + 1) * AR_BUF_SIZ);
1205 sc->rxend = next + bufmem;
1206 sc->rxmax = (sc->rxend - sc->rxstart) / AR_BUF_SIZ;
1208 TRC(printf("ar%d: rxdesc %x, rxstart %x, "
1209 "rxend %x, rxmax %d\n",
1210 x, sc->rxdesc, sc->rxstart, sc->rxend, sc->rxmax));
1213 if(hc->bustype == AR_BUS_PCI)
1214 hc->orbase[AR_PIMCTRL] = AR_PIM_MODEG | AR_PIM_AUTO_LED;
1219 * The things done here are channel independent.
1221 * Configure the sca waitstates.
1222 * Configure the global interrupt registers.
1223 * Enable master dma enable.
1226 ar_init_sca(struct ar_hardc *hc, int scano)
1230 sca = hc->sca[scano];
1231 if(hc->bustype == AR_BUS_ISA)
1232 ARC_SET_SCA(hc->iobase, scano);
1235 * Do the wait registers.
1236 * Set everything to 0 wait states.
1245 * Configure the interrupt registers.
1246 * Most are cleared until the interface is configured.
1248 sca->ier0 = 0x00; /* MSCI interrupts... Not used with dma. */
1249 sca->ier1 = 0x00; /* DMAC interrupts */
1250 sca->ier2 = 0x00; /* TIMER interrupts... Not used yet. */
1251 sca->itcr = 0x00; /* Use ivr and no intr ack */
1252 sca->ivr = 0x40; /* Fill in the interrupt vector. */
1256 * Configure the timers.
1262 * Set the DMA channel priority to rotate between
1263 * all four channels.
1265 * Enable all dma channels.
1267 if(hc->bustype == AR_BUS_PCI) {
1271 * Stupid problem with the PCI interface chip that break
1276 t[AR_PCI_SCA_PCR] = SCA_PCR_PR2;
1277 t[AR_PCI_SCA_DMER] = SCA_DMER_EN;
1279 sca->pcr = SCA_PCR_PR2;
1280 sca->dmer = SCA_DMER_EN;
1286 * Configure the msci
1288 * NOTE: The serial port configuration is hardcoded at the moment.
1291 ar_init_msci(struct ar_softc *sc)
1295 msci = &sc->sca->msci[sc->scachan];
1297 if(sc->hc->bustype == AR_BUS_ISA)
1298 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1300 msci->cmd = SCA_CMD_RESET;
1302 msci->md0 = SCA_MD0_CRC_1 |
1304 SCA_MD0_CRC_ENABLE |
1306 msci->md1 = SCA_MD1_NOADDRCHK;
1307 msci->md2 = SCA_MD2_DUPLEX | SCA_MD2_NRZ;
1310 * Acording to the manual I should give a reset after changing the
1313 msci->cmd = SCA_CMD_RXRESET;
1314 msci->ctl = SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS;
1317 * For now all interfaces are programmed to use the RX clock for
1320 switch(sc->hc->interface[sc->subunit]) {
1322 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1323 msci->txs = SCA_TXS_CLK_TXC | SCA_TXS_DIV1;
1326 case AR_IFACE_EIA_530:
1327 case AR_IFACE_COMBO:
1328 msci->rxs = SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1;
1329 msci->txs = SCA_TXS_CLK_RX | SCA_TXS_DIV1;
1332 msci->tmc = 153; /* This give 64k for loopback */
1335 * Disable all interrupts for now. I think if you are using
1336 * the dmac you don't use these interrupts.
1339 msci->ie1 = 0x0C; /* XXX CTS and DCD (DSR on 570I) level change. */
1346 msci->idl = 0x7E; /* XXX This is what cisco does. */
1349 * This is what the ARNET diags use.
1357 * Configure the rx dma controller.
1360 ar_init_rx_dmac(struct ar_softc *sc)
1363 sca_descriptor *rxd;
1369 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1371 if(sc->hc->bustype == AR_BUS_ISA)
1372 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc);
1374 rxd = (sca_descriptor *)(sc->hc->mem_start + (sc->rxdesc&sc->hc->winmsk));
1375 rxda_d = (u_int)sc->hc->mem_start - (sc->rxdesc & ~sc->hc->winmsk);
1377 for(rxbuf=sc->rxstart;rxbuf<sc->rxend;rxbuf += AR_BUF_SIZ, rxd++) {
1378 rxda = (u_int)&rxd[1] - rxda_d;
1379 rxd->cp = (u_short)(rxda & 0xfffful);
1383 TRC(printf("Descrp %p, data pt %x, data %x, ",
1386 rxd->bp = (u_short)(rxbuf & 0xfffful);
1387 rxd->bpb = (u_char)((rxbuf >> 16) & 0xff);
1389 rxd->stat = 0xff; /* The sca write here when it is finished. */
1392 TRC(printf("bpb %x, bp %x.\n", rxd->bpb, rxd->bp));
1395 rxd->cp = (u_short)(sc->rxdesc & 0xfffful);
1399 if(sc->hc->bustype == AR_BUS_ISA)
1400 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1402 dmac->dsr = 0; /* Disable DMA transfer */
1403 dmac->dcr = SCA_DCR_ABRT;
1405 /* XXX maybe also SCA_DMR_CNTE */
1406 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1407 dmac->bfl = AR_BUF_SIZ;
1409 dmac->cda = (u_short)(sc->rxdesc & 0xffff);
1410 dmac->sarb = (u_char)((sc->rxdesc >> 16) & 0xff);
1412 rxd = (sca_descriptor *)sc->rxstart;
1413 dmac->eda = (u_short)((u_int)&rxd[sc->rxmax - 1] & 0xffff);
1417 dmac->dsr = SCA_DSR_DE;
1421 * Configure the TX DMA descriptors.
1422 * Initialize the needed values and chain the descriptors.
1425 ar_init_tx_dmac(struct ar_softc *sc)
1428 struct buf_block *blkp;
1430 sca_descriptor *txd;
1435 dmac = &sc->sca->dmac[DMAC_TXCH(sc->scachan)];
1437 if(sc->hc->bustype == AR_BUS_ISA)
1438 ARC_SET_MEM(sc->hc->iobase, sc->block[0].txdesc);
1440 for(blk = 0; blk < AR_TX_BLOCKS; blk++) {
1441 blkp = &sc->block[blk];
1442 txd = (sca_descriptor *)(sc->hc->mem_start +
1443 (blkp->txdesc&sc->hc->winmsk));
1444 txda_d = (u_int)sc->hc->mem_start -
1445 (blkp->txdesc & ~sc->hc->winmsk);
1447 txbuf=blkp->txstart;
1448 for(;txbuf<blkp->txend;txbuf += AR_BUF_SIZ, txd++) {
1449 txda = (u_int)&txd[1] - txda_d;
1450 txd->cp = (u_short)(txda & 0xfffful);
1452 txd->bp = (u_short)(txbuf & 0xfffful);
1453 txd->bpb = (u_char)((txbuf >> 16) & 0xff);
1454 TRC(printf("ar%d: txbuf %x, bpb %x, bp %x\n",
1455 sc->unit, txbuf, txd->bpb, txd->bp));
1460 txd->cp = (u_short)(blkp->txdesc & 0xfffful);
1462 blkp->txtail = (u_int)txd - (u_int)sc->hc->mem_start;
1463 TRC(printf("TX Descriptors start %x, end %x.\n",
1468 if(sc->hc->bustype == AR_BUS_ISA)
1469 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1471 dmac->dsr = 0; /* Disable DMA */
1472 dmac->dcr = SCA_DCR_ABRT;
1473 dmac->dmr = SCA_DMR_TMOD | SCA_DMR_NF;
1474 dmac->dir = SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF;
1476 dmac->sarb = (u_char)((sc->block[0].txdesc >> 16) & 0xff);
1481 * Look through the descriptors to see if there is a complete packet
1482 * available. Stop if we get to where the sca is busy.
1484 * Return the length and status of the packet.
1485 * Return nonzero if there is a packet available.
1488 * It seems that we get the interrupt a bit early. The updateing of
1489 * descriptor values is not always completed when this is called.
1492 ar_packet_avail(struct ar_softc *sc,
1497 sca_descriptor *rxdesc;
1498 sca_descriptor *endp;
1499 sca_descriptor *cda;
1501 if(sc->hc->bustype == AR_BUS_ISA)
1502 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1503 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1504 cda = (sca_descriptor *)(sc->hc->mem_start +
1505 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1507 if(sc->hc->bustype == AR_BUS_ISA)
1508 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc);
1509 rxdesc = (sca_descriptor *)
1510 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1512 rxdesc = &rxdesc[sc->rxhind];
1513 endp = &endp[sc->rxmax];
1517 while(rxdesc != cda) {
1518 *len += rxdesc->len;
1520 if(rxdesc->stat & SCA_DESC_EOM) {
1521 *rxstat = rxdesc->stat;
1522 TRC(printf("ar%d: PKT AVAIL len %d, %x.\n",
1523 sc->unit, *len, *rxstat));
1529 rxdesc = (sca_descriptor *)
1530 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1540 * Copy a packet from the on card memory into a provided mbuf.
1541 * Take into account that buffers wrap and that a packet may
1542 * be larger than a buffer.
1545 ar_copy_rxbuf(struct mbuf *m,
1546 struct ar_softc *sc,
1549 sca_descriptor *rxdesc;
1555 rxdata = sc->rxstart + (sc->rxhind * AR_BUF_SIZ);
1556 rxmax = sc->rxstart + (sc->rxmax * AR_BUF_SIZ);
1558 rxdesc = (sca_descriptor *)
1559 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1560 rxdesc = &rxdesc[sc->rxhind];
1563 tlen = (len < AR_BUF_SIZ) ? len : AR_BUF_SIZ;
1564 if(sc->hc->bustype == AR_BUS_ISA)
1565 ARC_SET_MEM(sc->hc->iobase, rxdata);
1566 bcopy(sc->hc->mem_start + (rxdata & sc->hc->winmsk),
1567 mtod(m, caddr_t) + off,
1573 if(sc->hc->bustype == AR_BUS_ISA)
1574 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc);
1576 rxdesc->stat = 0xff;
1578 rxdata += AR_BUF_SIZ;
1580 if(rxdata == rxmax) {
1581 rxdata = sc->rxstart;
1582 rxdesc = (sca_descriptor *)
1583 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1589 * If single is set, just eat a packet. Otherwise eat everything up to
1590 * where cda points. Update pointers to point to the next packet.
1593 ar_eat_packet(struct ar_softc *sc, int single)
1596 sca_descriptor *rxdesc;
1597 sca_descriptor *endp;
1598 sca_descriptor *cda;
1602 if(sc->hc->bustype == AR_BUS_ISA)
1603 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1604 dmac = &sc->sca->dmac[DMAC_RXCH(sc->scachan)];
1605 cda = (sca_descriptor *)(sc->hc->mem_start +
1606 ((((u_int)dmac->sarb << 16) + dmac->cda) & sc->hc->winmsk));
1609 * Loop until desc->stat == (0xff || EOM)
1610 * Clear the status and length in the descriptor.
1611 * Increment the descriptor.
1613 if(sc->hc->bustype == AR_BUS_ISA)
1614 ARC_SET_MEM(sc->hc->iobase, sc->rxdesc);
1615 rxdesc = (sca_descriptor *)
1616 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1618 rxdesc = &rxdesc[sc->rxhind];
1619 endp = &endp[sc->rxmax];
1621 while(rxdesc != cda) {
1623 if(loopcnt > sc->rxmax) {
1624 printf("ar%d: eat pkt %d loop, cda %p, "
1625 "rxdesc %p, stat %x.\n",
1634 stat = rxdesc->stat;
1637 rxdesc->stat = 0xff;
1641 if(rxdesc == endp) {
1642 rxdesc = (sca_descriptor *)
1643 (sc->hc->mem_start + (sc->rxdesc & sc->hc->winmsk));
1647 if(single && (stat == SCA_DESC_EOM))
1652 * Update the eda to the previous descriptor.
1654 if(sc->hc->bustype == AR_BUS_ISA)
1655 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1657 rxdesc = (sca_descriptor *)sc->rxdesc;
1658 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1660 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1661 (u_short)((u_int)rxdesc & 0xffff);
1666 * While there is packets available in the rx buffer, read them out
1667 * into mbufs and ship them off.
1670 ar_get_packets(struct ar_softc *sc)
1672 sca_descriptor *rxdesc;
1673 struct mbuf *m = NULL;
1678 while(ar_packet_avail(sc, &len, &rxstat)) {
1679 TRC(printf("apa: len %d, rxstat %x\n", len, rxstat));
1680 if(((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
1681 MGETHDR(m, M_DONTWAIT, MT_DATA);
1683 /* eat packet if get mbuf fail!! */
1684 ar_eat_packet(sc, 1);
1688 m->m_pkthdr.rcvif = &sc->ifsppp.pp_if;
1689 #else /* NETGRAPH */
1690 m->m_pkthdr.rcvif = NULL;
1693 #endif /* NETGRAPH */
1694 m->m_pkthdr.len = m->m_len = len;
1696 MCLGET(m, M_DONTWAIT);
1697 if((m->m_flags & M_EXT) == 0) {
1699 ar_eat_packet(sc, 1);
1703 ar_copy_rxbuf(m, sc, len);
1705 if(sc->ifsppp.pp_if.if_bpf)
1706 bpf_mtap(&sc->ifsppp.pp_if, m);
1707 sppp_input(&sc->ifsppp.pp_if, m);
1708 sc->ifsppp.pp_if.if_ipackets++;
1709 #else /* NETGRAPH */
1710 ng_queue_data(sc->hook, m, NULL);
1712 #endif /* NETGRAPH */
1715 * Update the eda to the previous descriptor.
1717 i = (len + AR_BUF_SIZ - 1) / AR_BUF_SIZ;
1718 sc->rxhind = (sc->rxhind + i) % sc->rxmax;
1720 if(sc->hc->bustype == AR_BUS_ISA)
1721 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1723 rxdesc = (sca_descriptor *)sc->rxdesc;
1725 &rxdesc[(sc->rxhind + sc->rxmax - 2 ) % sc->rxmax];
1727 sc->sca->dmac[DMAC_RXCH(sc->scachan)].eda =
1728 (u_short)((u_int)rxdesc & 0xffff);
1732 while((rxstat == 0xff) && --tries)
1733 ar_packet_avail(sc, &len, &rxstat);
1736 * It look like we get an interrupt early
1737 * sometimes and then the status is not
1740 if(tries && (tries != 5))
1743 ar_eat_packet(sc, 1);
1746 sc->ifsppp.pp_if.if_ierrors++;
1747 #else /* NETGRAPH */
1749 #endif /* NETGRAPH */
1751 if(sc->hc->bustype == AR_BUS_ISA)
1752 ARC_SET_SCA(sc->hc->iobase, sc->scano);
1754 TRCL(printf("ar%d: Receive error chan %d, "
1755 "stat %x, msci st3 %x,"
1756 "rxhind %d, cda %x, eda %x.\n",
1760 sc->sca->msci[sc->scachan].st3,
1763 DMAC_RXCH(sc->scachan)].cda,
1765 DMAC_RXCH(sc->scachan)].eda));
1772 * All DMA interrupts come here.
1774 * Each channel has two interrupts.
1775 * Interrupt A for errors and Interrupt B for normal stuff like end
1776 * of transmit or receive dmas.
1779 ar_dmac_intr(struct ar_hardc *hc, int scano, u_char isr1)
1782 u_char dotxstart = isr1;
1784 struct ar_softc *sc;
1788 sca = hc->sca[scano];
1791 * Shortcut if there is no interrupts for dma channel 0 or 1
1793 if((isr1 & 0x0F) == 0) {
1799 sc = &hc->sc[mch + (NCHAN * scano)];
1805 dmac = &sca->dmac[DMAC_TXCH(mch)];
1807 if(hc->bustype == AR_BUS_ISA)
1808 ARC_SET_SCA(hc->iobase, scano);
1813 /* Counter overflow */
1814 if(dsr & SCA_DSR_COF) {
1815 printf("ar%d: TX DMA Counter overflow, "
1816 "txpacket no %lu.\n",
1819 sc->ifsppp.pp_if.if_opackets);
1820 sc->ifsppp.pp_if.if_oerrors++;
1821 #else /* NETGRAPH */
1824 #endif /* NETGRAPH */
1827 /* Buffer overflow */
1828 if(dsr & SCA_DSR_BOF) {
1829 printf("ar%d: TX DMA Buffer overflow, "
1830 "txpacket no %lu, dsr %02x, "
1831 "cda %04x, eda %04x.\n",
1834 sc->ifsppp.pp_if.if_opackets,
1835 #else /* NETGRAPH */
1837 #endif /* NETGRAPH */
1842 sc->ifsppp.pp_if.if_oerrors++;
1843 #else /* NETGRAPH */
1845 #endif /* NETGRAPH */
1848 /* End of Transfer */
1849 if(dsr & SCA_DSR_EOT) {
1851 * This should be the most common case.
1853 * Clear the IFF_OACTIVE flag.
1855 * Call arstart to start a new transmit if
1856 * there is data to transmit.
1860 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
1861 sc->ifsppp.pp_if.if_timer = 0;
1862 #else /* NETGRAPH */
1863 /* XXX c->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; */
1864 sc->out_dog = 0; /* XXX */
1865 #endif /* NETGRAPH */
1867 if(sc->txb_inuse && --sc->txb_inuse)
1876 dmac = &sca->dmac[DMAC_RXCH(mch)];
1878 if(hc->bustype == AR_BUS_ISA)
1879 ARC_SET_SCA(hc->iobase, scano);
1884 TRC(printf("AR: RX DSR %x\n", dsr));
1887 if(dsr & SCA_DSR_EOM) {
1888 TRC(int tt = sc->ifsppp.pp_if.if_ipackets;)
1889 TRC(int ind = sc->rxhind;)
1894 if(tt == sc->ifsppp.pp_if.if_ipackets) {
1895 #else /* NETGRAPH */
1896 if(tt == sc->ipackets) {
1897 #endif /* NETGRAPH */
1898 sca_descriptor *rxdesc;
1901 if(hc->bustype == AR_BUS_ISA)
1902 ARC_SET_SCA(hc->iobase, scano);
1903 printf("AR: RXINTR isr1 %x, dsr %x, "
1904 "no data %d pkts, orxhind %d.\n",
1909 printf("AR: rxdesc %x, rxstart %x, "
1910 "rxend %x, rxhind %d, "
1917 printf("AR: cda %x, eda %x.\n",
1921 if(sc->hc->bustype == AR_BUS_ISA)
1922 ARC_SET_MEM(sc->hc->iobase,
1924 rxdesc = (sca_descriptor *)
1925 (sc->hc->mem_start +
1926 (sc->rxdesc & sc->hc->winmsk));
1927 rxdesc = &rxdesc[sc->rxhind];
1928 for(i=0;i<3;i++,rxdesc++)
1929 printf("AR: rxdesc->stat %x, "
1936 /* Counter overflow */
1937 if(dsr & SCA_DSR_COF) {
1938 printf("ar%d: RX DMA Counter overflow, "
1942 sc->ifsppp.pp_if.if_ipackets);
1943 sc->ifsppp.pp_if.if_ierrors++;
1944 #else /* NETGRAPH */
1947 #endif /* NETGRAPH */
1950 /* Buffer overflow */
1951 if(dsr & SCA_DSR_BOF) {
1952 if(hc->bustype == AR_BUS_ISA)
1953 ARC_SET_SCA(hc->iobase, scano);
1954 printf("ar%d: RX DMA Buffer overflow, "
1955 "rxpkts %lu, rxind %d, "
1956 "cda %x, eda %x, dsr %x.\n",
1959 sc->ifsppp.pp_if.if_ipackets,
1960 #else /* NETGRAPH */
1962 #endif /* NETGRAPH */
1968 * Make sure we eat as many as possible.
1969 * Then get the system running again.
1971 ar_eat_packet(sc, 0);
1973 sc->ifsppp.pp_if.if_ierrors++;
1974 #else /* NETGRAPH */
1976 #endif /* NETGRAPH */
1977 if(hc->bustype == AR_BUS_ISA)
1978 ARC_SET_SCA(hc->iobase, scano);
1979 sca->msci[mch].cmd = SCA_CMD_RXMSGREJ;
1980 dmac->dsr = SCA_DSR_DE;
1982 TRC(printf("ar%d: RX DMA Buffer overflow, "
1983 "rxpkts %lu, rxind %d, "
1984 "cda %x, eda %x, dsr %x. After\n",
1986 sc->ifsppp.pp_if.if_ipackets,
1993 /* End of Transfer */
1994 if(dsr & SCA_DSR_EOT) {
1996 * If this happen, it means that we are
1997 * receiving faster than what the processor
2000 * XXX We should enable the dma again.
2002 printf("ar%d: RX End of transfer, rxpkts %lu.\n",
2005 sc->ifsppp.pp_if.if_ipackets);
2006 sc->ifsppp.pp_if.if_ierrors++;
2007 #else /* NETGRAPH */
2010 #endif /* NETGRAPH */
2017 }while((mch<NCHAN) && isr1);
2020 * Now that we have done all the urgent things, see if we
2021 * can fill the transmit buffers.
2023 for(mch = 0; mch < NCHAN; mch++) {
2024 if(dotxstart & 0x0C) {
2025 sc = &hc->sc[mch + (NCHAN * scano)];
2027 arstart(&sc->ifsppp.pp_if);
2028 #else /* NETGRAPH */
2030 #endif /* NETGRAPH */
2037 ar_msci_intr(struct ar_hardc *hc, int scano, u_char isr0)
2039 printf("arc%d: ARINTR: MSCI\n", hc->cunit);
2043 ar_timer_intr(struct ar_hardc *hc, int scano, u_char isr2)
2045 printf("arc%d: ARINTR: TIMER\n", hc->cunit);
2050 /*****************************************
2051 * Device timeout/watchdog routine.
2052 * called once per second.
2053 * checks to see that if activity was expected, that it hapenned.
2054 * At present we only look to see if expected output was completed.
2057 ngar_watchdog_frame(void * arg)
2059 struct ar_softc * sc = arg;
2063 if(sc->running == 0)
2064 return; /* if we are not running let timeouts die */
2066 * calculate the apparent throughputs
2070 speed = sc->inbytes - sc->lastinbytes;
2071 sc->lastinbytes = sc->inbytes;
2072 if ( sc->inrate < speed )
2074 speed = sc->outbytes - sc->lastoutbytes;
2075 sc->lastoutbytes = sc->outbytes;
2076 if ( sc->outrate < speed )
2077 sc->outrate = speed;
2081 if ((sc->inlast > QUITE_A_WHILE)
2082 && (sc->out_deficit > LOTS_OF_PACKETS)) {
2083 log(LOG_ERR, "ar%d: No response from remote end\n", sc->unit);
2087 sc->inlast = sc->out_deficit = 0;
2089 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2090 if (sc->out_dog == 0) {
2091 log(LOG_ERR, "ar%d: Transmit failure.. no clock?\n",
2100 sc->inlast = sc->out_deficit = 0;
2105 sc->handle = timeout(ngar_watchdog_frame, sc, hz);
2108 /***********************************************************************
2109 * This section contains the methods for the Netgraph interface
2110 ***********************************************************************/
2112 * It is not possible or allowable to create a node of this type.
2113 * If the hardware exists, it will already have created it.
2116 ngar_constructor(node_p *nodep)
2122 * give our ok for a hook to be added...
2123 * If we are not running this should kick the device into life.
2124 * The hook's private info points to our stash of info about that
2128 ngar_newhook(node_p node, hook_p hook, const char *name)
2130 struct ar_softc * sc = node->private;
2133 * check if it's our friend the debug hook
2135 if (strcmp(name, NG_AR_HOOK_DEBUG) == 0) {
2136 hook->private = NULL; /* paranoid */
2137 sc->debug_hook = hook;
2142 * Check for raw mode hook.
2144 if (strcmp(name, NG_AR_HOOK_RAW) != 0) {
2155 * incoming messages.
2156 * Just respond to the generic TEXT_STATUS message
2159 ngar_rcvmsg(node_p node,
2160 struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
2162 struct ar_softc * sc;
2166 switch (msg->header.typecookie) {
2170 case NGM_GENERIC_COOKIE:
2171 switch(msg->header.cmd) {
2172 case NGM_TEXT_STATUS: {
2175 int resplen = sizeof(struct ng_mesg) + 512;
2176 MALLOC(*resp, struct ng_mesg *, resplen,
2177 M_NETGRAPH, M_NOWAIT | M_ZERO);
2178 if (*resp == NULL) {
2182 arg = (*resp)->data;
2185 * Put in the throughput information.
2187 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2188 "highest rate seen: %ld B/S in, %ld B/S out\n",
2189 sc->inbytes, sc->outbytes,
2190 sc->inrate, sc->outrate);
2191 pos += sprintf(arg + pos,
2192 "%ld output errors\n",
2194 pos += sprintf(arg + pos,
2195 "ierrors = %ld, %ld, %ld, %ld\n",
2201 (*resp)->header.version = NG_VERSION;
2202 (*resp)->header.arglen = strlen(arg) + 1;
2203 (*resp)->header.token = msg->header.token;
2204 (*resp)->header.typecookie = NG_AR_COOKIE;
2205 (*resp)->header.cmd = msg->header.cmd;
2206 strncpy((*resp)->header.cmdstr, "status",
2219 free(msg, M_NETGRAPH);
2224 * get data from another node and transmit it to the correct channel
2227 ngar_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2231 struct ar_softc * sc = hook->node->private;
2232 struct ifqueue *xmitq_p;
2235 * data doesn't come in from just anywhere (e.g control hook)
2237 if ( hook->private == NULL) {
2243 * Now queue the data for when it can be sent
2245 if (meta && meta->priority > 0) {
2246 xmitq_p = (&sc->xmitq_hipri);
2248 xmitq_p = (&sc->xmitq);
2251 if (IF_QFULL(xmitq_p)) {
2257 IF_ENQUEUE(xmitq_p, m);
2264 * It was an error case.
2265 * check if we need to free the mbuf, and then return the error
2267 NG_FREE_DATA(m, meta);
2272 * do local shutdown processing..
2273 * this node will refuse to go away, unless the hardware says to..
2274 * don't unref the node, or remove our name. just clear our links up.
2277 ngar_rmnode(node_p node)
2279 struct ar_softc * sc = node->private;
2283 node->flags &= ~NG_INVALID; /* bounce back to life */
2287 /* already linked */
2289 ngar_connect(hook_p hook)
2291 /* be really amiable and just say "YUP that's OK by me! " */
2296 * notify on hook disconnection (destruction)
2298 * Invalidate the private data associated with this dlci.
2299 * For this type, removal of the last link resets tries to destroy the node.
2300 * As the device still exists, the shutdown method will not actually
2301 * destroy the node, but reset the device and leave it 'fresh' :)
2303 * The node removal code will remove all references except that owned by the
2307 ngar_disconnect(hook_p hook)
2309 struct ar_softc * sc = hook->node->private;
2312 * If it's the data hook, then free resources etc.
2314 if (hook->private) {
2317 if (sc->datahooks == 0)
2321 sc->debug_hook = NULL;
2327 * called during bootup
2328 * or LKM loading to put this type into the list of known modules
2331 ngar_init(void *ignored)
2333 if (ng_newtype(&typestruct))
2334 printf("ngar install failed\n");
2337 #endif /* NETGRAPH */
2340 ********************************* END ************************************