sys/net/i4b/layer1/ifpi2/i4b_ifpi2_pci.c

   1 /*
   2  *   Copyright (c) 2001 Gary Jennejohn. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpi2_pci.c: AVM Fritz!Card PCI hardware driver
  34  *      --------------------------------------------------
  35  *
  36  *      $Id$
  37  *
  38  * $FreeBSD: src/sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c,v 1.6.2.2 2002/05/15 08:12:42 gj Exp $
  39  * $DragonFly: src/sys/net/i4b/layer1/ifpi2/i4b_ifpi2_pci.c,v 1.10 2005/06/14 21:19:18 joerg Exp $
  40  *
  41  *      last edit-date: [Fri Jan 12 17:01:26 2001]
  42  *
  43  *---------------------------------------------------------------------------*/
  44
  45 #include "use_ifpi2.h"
  46 #include "use_pci.h"
  47 #include "opt_i4b.h"
  48
  49 #if (NIFPI2 > 0) && (NPCI > 0)
  50
  51 #include <sys/param.h>
  52 #include <sys/kernel.h>
  53 #include <sys/systm.h>
  54 #include <sys/mbuf.h>
  55
  56 #include <machine/bus.h>
  57 #include <sys/bus.h>
  58 #include <sys/rman.h>
  59 #include <sys/thread2.h>
  60
  61 #include <bus/pci/pcireg.h>
  62 #include <bus/pci/pcivar.h>
  63
  64 #include <sys/socket.h>
  65 #include <net/if.h>
  66
  67 #include <net/i4b/include/machine/i4b_debug.h>
  68 #include <net/i4b/include/machine/i4b_ioctl.h>
  69 #include <net/i4b/include/machine/i4b_trace.h>
  70
  71 #include "../../include/i4b_global.h"
  72 #include "../../include/i4b_mbuf.h"
  73
  74 #include "../i4b_l1.h"
  75 #include "../isic/i4b_isic.h"
  76 /*#include "../isic/i4b_isac.h"*/
  77 #include "../isic/i4b_hscx.h"
  78
  79 #include "i4b_ifpi2_ext.h"
  80 #include "i4b_ifpi2_isacsx.h"
  81
  82 #define PCI_AVMA1_VID 0x1244
  83 #define PCI_AVMA1_V2_DID 0x0e00
  84
  85 /* prototypes */
  86 static void avma1pp2_disable(device_t);
  87
  88 static void avma1pp2_intr(void *);
  89 static void hscx_write_reg(int, u_int, struct l1_softc *);
  90 static u_char hscx_read_reg(int, struct l1_softc *);
  91 static u_int hscx_read_reg_int(int, struct l1_softc *);
  92 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  93 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  94 static void avma1pp2_hscx_int_handler(struct l1_softc *);
  95 static void avma1pp2_hscx_intr(int, u_int, struct l1_softc *);
  96 static void avma1pp2_init_linktab(struct l1_softc *);
  97 static void avma1pp2_bchannel_setup(int, int, int, int);
  98 static void avma1pp2_bchannel_start(int, int);
  99 static void avma1pp2_hscx_init(struct l1_softc *, int, int);
 100 static void avma1pp2_bchannel_stat(int, int, bchan_statistics_t *);
 101 static void avma1pp2_set_linktab(int, int, drvr_link_t *);
 102 static isdn_link_t * avma1pp2_ret_linktab(int, int);
 103 static int avma1pp2_pci_probe(device_t);
 104 static int avma1pp2_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
 105 int avma1pp2_attach_avma1pp(device_t);
 106 static void ifpi2_isacsx_intr(struct l1_softc *sc);
 107
 108 static device_method_t avma1pp2_pci_methods[] = {
 109         /* Device interface */
 110         DEVMETHOD(device_probe,         avma1pp2_pci_probe),
 111         DEVMETHOD(device_attach,        avma1pp2_attach_avma1pp),
 112         DEVMETHOD(device_shutdown,      avma1pp2_disable),
 113
 114         /* bus interface */
 115         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 116         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 117
 118         { 0, 0 }
 119 };
 120
 121 static driver_t avma1pp2_pci_driver = {
 122         "ifpi2-",
 123         avma1pp2_pci_methods,
 124         sizeof(struct l1_softc)
 125 };
 126
 127 static devclass_t avma1pp2_pci_devclass;
 128
 129 DRIVER_MODULE(avma1pp2, pci, avma1pp2_pci_driver, avma1pp2_pci_devclass, 0, 0);
 130
 131 /* jump table for multiplex routines */
 132
 133 struct i4b_l1mux_func avma1pp2_l1mux_func = {
 134         avma1pp2_ret_linktab,
 135         avma1pp2_set_linktab,
 136         ifpi2_mph_command_req,
 137         ifpi2_ph_data_req,
 138         ifpi2_ph_activate_req,
 139 };
 140
 141 struct l1_softc *ifpi2_scp[IFPI2_MAXUNIT];
 142
 143 /*---------------------------------------------------------------------------*
 144  *      AVM PCI Fritz!Card V. 2 special registers
 145  *---------------------------------------------------------------------------*/
 146
 147 /*
 148  *      AVM PCI Status Latch 0 read only bits
 149  */
 150 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active high */
 151 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active high */
 152 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active high */
 153 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 154 /* actually active high */
 155 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 156
 157 /*
 158  *      AVM PCI Status Latch 0 read only bits
 159  */
 160 #define ASL_TIMERRESET          0x04
 161 #define ASL_ENABLE_INT          0x08
 162
 163 /*
 164  * "HSCX" status bits
 165  */
 166 #define  HSCX_STAT_RME          0x01
 167 #define  HSCX_STAT_RDO          0x10
 168 #define  HSCX_STAT_CRCVFRRAB    0x0E
 169 #define  HSCX_STAT_CRCVFR       0x06
 170 #define  HSCX_STAT_RML_MASK     0x3f00
 171
 172 /*
 173  * "HSCX" interrupt bits
 174  */
 175 #define  HSCX_INT_XPR           0x80
 176 #define  HSCX_INT_XDU           0x40
 177 #define  HSCX_INT_RPR           0x20
 178 #define  HSCX_INT_MASK          0xE0
 179
 180 /*
 181  * "HSCX" command bits
 182  */
 183 #define  HSCX_CMD_XRS           0x80
 184 #define  HSCX_CMD_XME           0x01
 185 #define  HSCX_CMD_RRS           0x20
 186 #define  HSCX_CMD_XML_MASK      0x3f00
 187
 188 /* "HSCX" mode bits */
 189 #define HSCX_MODE_ITF_FLG       0x01
 190 #define HSCX_MODE_TRANS         0x02
 191
 192 /* offsets to various registers in the ASIC, evidently */
 193 #define  STAT0_OFFSET           0x02
 194
 195 #define  HSCX_FIFO1             0x10
 196 #define  HSCX_FIFO2             0x18
 197
 198 #define  HSCX_STAT1             0x14
 199 #define  HSCX_STAT2             0x1c
 200
 201 #define  ISACSX_INDEX           0x04
 202 #define  ISACSX_DATA            0x08
 203
 204 /*
 205  * Commands and parameters are sent to the "HSCX" as a long, but the
 206  * fields are handled as bytes.
 207  *
 208  * The long contains:
 209  *      (prot << 16)|(txl << 8)|cmd
 210  *
 211  * where:
 212  *      prot = protocol to use
 213  *      txl = transmit length
 214  *      cmd = the command to be executed
 215  *
 216  * The fields are defined as u_char in struct l1_softc.
 217  *
 218  * Macro to coalesce the byte fields into a u_int
 219  */
 220 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
 221                                         | (sc->avma1pp_prot << 16))
 222
 223 /*
 224  * to prevent deactivating the "HSCX" when both channels are active we
 225  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 226  * flag in avma1pp2_bchannel_setup upon active and cleared upon deactivation.
 227  * It is set high to allow room for new flags.
 228  */
 229 #define HSCX_AVMA1PP_ACTIVE     0x1000
 230
 231 /*---------------------------------------------------------------------------*
 232  *      AVM read fifo routines
 233  *---------------------------------------------------------------------------*/
 234
 235 static void
 236 avma1pp2_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 237 {
 238         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 239         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 240         int i;
 241
 242         switch (what) {
 243                 case ISIC_WHAT_ISAC:
 244                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, 0);
 245                         /* evidently each byte must be read as a long */
 246                         for (i = 0; i < size; i++)
 247                                 ((u_int8_t *)buf)[i] = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 248                         break;
 249                 case ISIC_WHAT_HSCXA:
 250                         hscx_read_fifo(0, buf, size, sc);
 251                         break;
 252                 case ISIC_WHAT_HSCXB:
 253                         hscx_read_fifo(1, buf, size, sc);
 254                         break;
 255         }
 256 }
 257
 258 static void
 259 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 260 {
 261         u_int32_t *ip;
 262         size_t cnt;
 263         int dataoff;
 264         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 265         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 266
 267         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 268
 269         ip = (u_int32_t *)buf;
 270         cnt = 0;
 271         /* what if len isn't a multiple of sizeof(int) and buf is */
 272         /* too small ???? */
 273         while (cnt < len)
 274         {
 275                 *ip++ = bus_space_read_4(btag, bhandle, dataoff);
 276                 cnt += 4;
 277         }
 278 }
 279
 280 /*---------------------------------------------------------------------------*
 281  *      AVM write fifo routines
 282  *---------------------------------------------------------------------------*/
 283 static void
 284 avma1pp2_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 285 {
 286         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 287         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 288         int i;
 289
 290         switch (what) {
 291                 case ISIC_WHAT_ISAC:
 292                         bus_space_write_4(btag, bhandle,  ISACSX_INDEX, 0);
 293                         /* evidently each byte must written as a long */
 294                         for (i = 0; i < size; i++)
 295                                 bus_space_write_4(btag, bhandle,  ISACSX_DATA, ((unsigned char *)buf)[i]);
 296                         break;
 297                 case ISIC_WHAT_HSCXA:
 298                         hscx_write_fifo(0, buf, size, sc);
 299                         break;
 300                 case ISIC_WHAT_HSCXB:
 301                         hscx_write_fifo(1, buf, size, sc);
 302                         break;
 303         }
 304 }
 305
 306 static void
 307 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 308 {
 309         u_int32_t *ip;
 310         size_t cnt;
 311         int dataoff;
 312         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 313         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 314         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 315
 316         dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
 317
 318         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 319         sc->avma1pp_txl = 0;
 320         if (Bchan->out_mbuf_cur == NULL)
 321         {
 322           if (Bchan->bprot != BPROT_NONE)
 323                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 324         }
 325         if (len != sc->sc_bfifolen)
 326                 sc->avma1pp_txl = len;
 327
 328         cnt = 0; /* borrow cnt */
 329         AVMA1PPSETCMDLONG(cnt);
 330         hscx_write_reg(chan, cnt, sc);
 331
 332         ip = (u_int32_t *)buf;
 333         cnt = 0;
 334         while (cnt < len)
 335         {
 336                 bus_space_write_4(btag, bhandle, dataoff, *ip);
 337                 ip++;
 338                 cnt += 4;
 339         }
 340 }
 341
 342 /*---------------------------------------------------------------------------*
 343  *      AVM write register routines
 344  *---------------------------------------------------------------------------*/
 345
 346 static void
 347 avma1pp2_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 348 {
 349         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 350         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 351
 352         switch (what) {
 353                 case ISIC_WHAT_ISAC:
 354                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 355                         bus_space_write_4(btag, bhandle, ISACSX_DATA, data);
 356                         break;
 357                 case ISIC_WHAT_HSCXA:
 358                         hscx_write_reg(0, data, sc);
 359                         break;
 360                 case ISIC_WHAT_HSCXB:
 361                         hscx_write_reg(1, data, sc);
 362                         break;
 363         }
 364 }
 365
 366 static void
 367 hscx_write_reg(int chan, u_int val, struct l1_softc *sc)
 368 {
 369         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 370         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 371         u_int off;
 372
 373         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 374
 375         bus_space_write_4(btag, bhandle, off, val);
 376 }
 377
 378 /*---------------------------------------------------------------------------*
 379  *      AVM read register routines
 380  *---------------------------------------------------------------------------*/
 381 static u_int8_t
 382 avma1pp2_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 383 {
 384         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 385         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 386         u_int8_t val;
 387
 388         switch (what) {
 389                 case ISIC_WHAT_ISAC:
 390                         bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
 391                         val = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
 392                         return(val);
 393                 case ISIC_WHAT_HSCXA:
 394                         return hscx_read_reg(0, sc);
 395                 case ISIC_WHAT_HSCXB:
 396                         return hscx_read_reg(1, sc);
 397         }
 398         return 0;
 399 }
 400
 401 static u_char
 402 hscx_read_reg(int chan, struct l1_softc *sc)
 403 {
 404         return(hscx_read_reg_int(chan, sc) & 0xff);
 405 }
 406
 407 /*
 408  * need to be able to return an int because the RBCH is in the 2nd
 409  * byte.
 410  */
 411 static u_int
 412 hscx_read_reg_int(int chan, struct l1_softc *sc)
 413 {
 414         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 415         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 416         u_int off;
 417
 418         off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
 419         return(bus_space_read_4(btag, bhandle, off));
 420 }
 421
 422 /*---------------------------------------------------------------------------*
 423  *      avma1pp2_probe - probe for a card
 424  *---------------------------------------------------------------------------*/
 425 static int
 426 avma1pp2_pci_probe(dev)
 427         device_t                dev;
 428 {
 429         u_int16_t               did, vid;
 430
 431         vid = pci_get_vendor(dev);
 432         did = pci_get_device(dev);
 433
 434         if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_V2_DID)) {
 435                 device_set_desc(dev, "AVM Fritz!Card PCI Version 2");
 436                 return(0);
 437         }
 438
 439         return(ENXIO);
 440 }
 441
 442 /*---------------------------------------------------------------------------*
 443  *      avma1pp2_attach_avma1pp - attach Fritz!Card PCI
 444  *---------------------------------------------------------------------------*/
 445 int
 446 avma1pp2_attach_avma1pp(device_t dev)
 447 {
 448         struct l1_softc *sc;
 449         u_int v;
 450         int unit, error = 0;
 451         u_int16_t did, vid;
 452         void *ih = 0;
 453         bus_space_handle_t bhandle;
 454         bus_space_tag_t btag;
 455
 456         crit_enter();
 457
 458         vid = pci_get_vendor(dev);
 459         did = pci_get_device(dev);
 460         sc = device_get_softc(dev);
 461         unit = device_get_unit(dev);
 462         bzero(sc, sizeof(struct l1_softc));
 463
 464         /* probably not really required */
 465         if(unit > IFPI2_MAXUNIT) {
 466                 printf("ifpi2-%d: Error, unit > IFPI_MAXUNIT!\n", unit);
 467                 crit_exit();
 468                 return(ENXIO);
 469         }
 470
 471         if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_V2_DID)) {
 472                 printf("ifpi2-%d: unknown device!?\n", unit);
 473                 goto fail;
 474         }
 475
 476         ifpi2_scp[unit] = sc;
 477
 478         sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
 479         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
 480                 &sc->sc_resources.io_rid[0],
 481                 0, ~0, 1, RF_ACTIVE);
 482
 483         if (sc->sc_resources.io_base[0] == NULL) {
 484                 printf("ifpi2-%d: couldn't map IO port\n", unit);
 485                 error = ENXIO;
 486                 goto fail;
 487         }
 488
 489         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 490         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 491
 492         /* Allocate interrupt */
 493         sc->sc_resources.irq_rid = 0;
 494         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 495                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 496
 497         if (sc->sc_resources.irq == NULL) {
 498                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 499                 printf("ifpi2-%d: couldn't map interrupt\n", unit);
 500                 error = ENXIO;
 501                 goto fail;
 502         }
 503
 504         error = bus_setup_intr(dev, sc->sc_resources.irq, INTR_TYPE_NET,
 505                                avma1pp2_intr, sc, &ih, NULL);
 506
 507         if (error) {
 508                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
 509                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 510                 printf("ifpi2-%d: couldn't set up irq\n", unit);
 511                 goto fail;
 512         }
 513
 514         sc->sc_unit = unit;
 515
 516         /* end of new-bus stuff */
 517
 518         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 519
 520         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 521         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 522
 523         /* setup access routines */
 524
 525         sc->clearirq = NULL;
 526         sc->readreg = avma1pp2_read_reg;
 527         sc->writereg = avma1pp2_write_reg;
 528
 529         sc->readfifo = avma1pp2_read_fifo;
 530         sc->writefifo = avma1pp2_write_fifo;
 531
 532         /* setup card type */
 533
 534         sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI_V2;
 535
 536         /* setup IOM bus type */
 537
 538         sc->sc_bustyp = BUS_TYPE_IOM2;
 539
 540         /* set up some other miscellaneous things */
 541         sc->sc_ipac = 0;
 542         sc->sc_bfifolen = HSCX_FIFO_LEN;
 543
 544         /* reset the card */
 545         /* the Linux driver does this to clear any pending ISAC interrupts */
 546         v = 0;
 547         v = ISAC_READ(I_RMODED);
 548 #ifdef AVMA1PCI_V2_DEBUG
 549         printf("avma1pp2_attach: I_MODED %x...", v);
 550 #endif
 551         v = ISAC_READ(I_ISTAD);
 552 #ifdef AVMA1PCI_V2_DEBUG
 553         printf("avma1pp2_attach: I_ISTAD %x...", v);
 554 #endif
 555         v = ISAC_READ(I_ISTA);
 556 #ifdef AVMA1PCI_V2_DEBUG
 557         printf("avma1pp2_attach: I_ISTA %x...", v);
 558 #endif
 559         ISAC_WRITE(I_MASKD, 0xff);
 560         ISAC_WRITE(I_MASK, 0xff);
 561         /* the Linux driver does this to clear any pending HSCX interrupts */
 562         v = hscx_read_reg_int(0, sc);
 563 #ifdef AVMA1PCI_V2_DEBUG
 564         printf("avma1pp2_attach: 0 HSCX_STAT %x...", v);
 565 #endif
 566         v = hscx_read_reg_int(1, sc);
 567 #ifdef AVMA1PCI_V2_DEBUG
 568         printf("avma1pp2_attach: 1 HSCX_STAT %x\n", v);
 569 #endif
 570
 571         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET);
 572         DELAY(SEC_DELAY/100); /* 10 ms */
 573         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_ENABLE_INT);
 574         DELAY(SEC_DELAY/100); /* 10 ms */
 575
 576    /* from here to the end would normally be done in isic_pciattach */
 577
 578          printf("ifpi2-%d: ISACSX %s\n", unit, "PSB3186");
 579
 580         /* init the ISAC */
 581         ifpi2_isacsx_init(sc);
 582
 583         /* init the "HSCX" */
 584         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 585
 586         avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 587
 588         /* can't use the normal B-Channel stuff */
 589         avma1pp2_init_linktab(sc);
 590
 591         /* set trace level */
 592
 593         sc->sc_trace = TRACE_OFF;
 594
 595         sc->sc_state = ISAC_IDLE;
 596
 597         sc->sc_ibuf = NULL;
 598         sc->sc_ib = NULL;
 599         sc->sc_ilen = 0;
 600
 601         sc->sc_obuf = NULL;
 602         sc->sc_op = NULL;
 603         sc->sc_ol = 0;
 604         sc->sc_freeflag = 0;
 605
 606         sc->sc_obuf2 = NULL;
 607         sc->sc_freeflag2 = 0;
 608
 609         callout_init(&sc->sc_T3_timeout);
 610         callout_init(&sc->sc_T4_timeout);
 611
 612         /* init higher protocol layers */
 613
 614         i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp2_l1mux_func);
 615
 616   fail:
 617         crit_exit();
 618         return(error);
 619 }
 620
 621 /*
 622  * this is the real interrupt routine
 623  */
 624 static void
 625 avma1pp2_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
 626 {
 627         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 628         int activity = -1;
 629         u_int param = 0;
 630
 631         NDBGL1(L1_H_IRQ, "%#x", stat);
 632
 633         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 634         {
 635                 chan->stat_XDU++;
 636                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 637                 /* abort the transmission */
 638                 sc->avma1pp_txl = 0;
 639                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 640                 AVMA1PPSETCMDLONG(param);
 641                 hscx_write_reg(h_chan, param, sc);
 642                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 643                 AVMA1PPSETCMDLONG(param);
 644                 hscx_write_reg(h_chan, param, sc);
 645
 646                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 647                 {
 648                         i4b_Bfreembuf(chan->out_mbuf_head);
 649                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 650                 }
 651         }
 652
 653         /*
 654          * The following is based on examination of the Linux driver.
 655          *
 656          * The logic here is different than with a "real" HSCX; all kinds
 657          * of information (interrupt/status bits) are in stat.
 658          *              HSCX_INT_RPR indicates a receive interrupt
 659          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 660          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 661          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 662          *                      CRC/framing errors are only reported in this state.
 663          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 664          *                                      CRC/framing error
 665          */
 666
 667         if(stat & HSCX_INT_RPR)
 668         {
 669                 int fifo_data_len;
 670                 int error = 0;
 671                 /* always have to read the FIFO, so use a scratch buffer */
 672                 u_char scrbuf[HSCX_FIFO_LEN];
 673
 674                 if(stat & HSCX_STAT_RDO)
 675                 {
 676                         chan->stat_RDO++;
 677                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 678                         error++;
 679                 }
 680
 681                 /*
 682                  * check whether we're receiving data for an inactive B-channel
 683                  * and discard it. This appears to happen for telephony when
 684                  * both B-channels are active and one is deactivated. Since
 685                  * it is not really possible to deactivate the channel in that
 686                  * case (the ASIC seems to deactivate _both_ channels), the
 687                  * "deactivated" channel keeps receiving data which can lead
 688                  * to exhaustion of mbufs and a kernel panic.
 689                  *
 690                  * This is a hack, but it's the only solution I can think of
 691                  * without having the documentation for the ASIC.
 692                  * GJ - 28 Nov 1999
 693                  */
 694                  if (chan->state == HSCX_IDLE)
 695                  {
 696                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 697                         error++;
 698                  }
 699
 700                 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
 701
 702                 if(fifo_data_len == 0)
 703                         fifo_data_len = sc->sc_bfifolen;
 704
 705                 /* ALWAYS read data from HSCX fifo */
 706
 707                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 708                 chan->rxcount += fifo_data_len;
 709
 710                 /* all error conditions checked, now decide and take action */
 711
 712                 if(error == 0)
 713                 {
 714                         if(chan->in_mbuf == NULL)
 715                         {
 716                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 717                                         panic("L1 avma1pp2_hscx_intr: RME, cannot allocate mbuf!\n");
 718                                 chan->in_cbptr = chan->in_mbuf->m_data;
 719                                 chan->in_len = 0;
 720                         }
 721
 722                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 723                         {
 724                                 /* OK to copy the data */
 725                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 726                                 chan->in_cbptr += fifo_data_len;
 727                                 chan->in_len += fifo_data_len;
 728
 729                                 /* setup mbuf data length */
 730
 731                                 chan->in_mbuf->m_len = chan->in_len;
 732                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 733
 734                                 if(sc->sc_trace & TRACE_B_RX)
 735                                 {
 736                                         i4b_trace_hdr_t hdr;
 737                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 738                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 739                                         hdr.dir = FROM_NT;
 740                                         hdr.count = ++sc->sc_trace_bcount;
 741                                         MICROTIME(hdr.time);
 742                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 743                                 }
 744
 745                                 if (stat & HSCX_STAT_RME)
 746                                 {
 747                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 748                                   {
 749                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 750                                          activity = ACT_RX;
 751
 752                                          /* mark buffer ptr as unused */
 753
 754                                          chan->in_mbuf = NULL;
 755                                          chan->in_cbptr = NULL;
 756                                          chan->in_len = 0;
 757                                   }
 758                                   else
 759                                   {
 760                                                 chan->stat_CRC++;
 761                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 762                                           if (chan->in_mbuf != NULL)
 763                                           {
 764                                                   i4b_Bfreembuf(chan->in_mbuf);
 765                                                   chan->in_mbuf = NULL;
 766                                                   chan->in_cbptr = NULL;
 767                                                   chan->in_len = 0;
 768                                           }
 769                                   }
 770                                 }
 771                         } /* END enough space in mbuf */
 772                         else
 773                         {
 774                                  if(chan->bprot == BPROT_NONE)
 775                                  {
 776                                           /* setup mbuf data length */
 777
 778                                           chan->in_mbuf->m_len = chan->in_len;
 779                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 780
 781                                           if(sc->sc_trace & TRACE_B_RX)
 782                                           {
 783                                                         i4b_trace_hdr_t hdr;
 784                                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 785                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 786                                                         hdr.dir = FROM_NT;
 787                                                         hdr.count = ++sc->sc_trace_bcount;
 788                                                         MICROTIME(hdr.time);
 789                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 790                                                 }
 791
 792                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 793                                                  activity = ACT_RX;
 794
 795                                           /* move rx'd data to rx queue */
 796
 797                                           if(!(IF_QFULL(&chan->rx_queue)))
 798                                           {
 799                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 800                                           }
 801                                           else
 802                                           {
 803                                                 i4b_Bfreembuf(chan->in_mbuf);
 804                                           }
 805                                           /* signal upper layer that data are available */
 806                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 807
 808                                           /* alloc new buffer */
 809
 810                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 811                                                  panic("L1 avma1pp2_hscx_intr: RPF, cannot allocate new mbuf!\n");
 812
 813                                           /* setup new data ptr */
 814
 815                                           chan->in_cbptr = chan->in_mbuf->m_data;
 816
 817                                           /* OK to copy the data */
 818                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 819
 820                                           chan->in_cbptr += fifo_data_len;
 821                                           chan->in_len = fifo_data_len;
 822
 823                                           chan->rxcount += fifo_data_len;
 824                                         }
 825                                  else
 826                                         {
 827                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 828                                           chan->in_cbptr = chan->in_mbuf->m_data;
 829                                           chan->in_len = 0;
 830                                         }
 831                           }
 832                 } /* if(error == 0) */
 833                 else
 834                 {
 835                         /* land here for RDO */
 836                         if (chan->in_mbuf != NULL)
 837                         {
 838                                 i4b_Bfreembuf(chan->in_mbuf);
 839                                 chan->in_mbuf = NULL;
 840                                 chan->in_cbptr = NULL;
 841                                 chan->in_len = 0;
 842                         }
 843                         sc->avma1pp_txl = 0;
 844                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 845                         AVMA1PPSETCMDLONG(param);
 846                         hscx_write_reg(h_chan, param, sc);
 847                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 848                         AVMA1PPSETCMDLONG(param);
 849                         hscx_write_reg(h_chan, param, sc);
 850                 }
 851         }
 852
 853
 854         /* transmit fifo empty, new data can be written to fifo */
 855
 856         if(stat & HSCX_INT_XPR)
 857         {
 858                 /*
 859                  * for a description what is going on here, please have
 860                  * a look at isic_bchannel_start() in i4b_bchan.c !
 861                  */
 862
 863                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 864
 865                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 866                 {
 867                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 868
 869                         if(chan->out_mbuf_head == NULL)
 870                         {
 871                                 chan->state &= ~HSCX_TX_ACTIVE;
 872                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 873                         }
 874                         else
 875                         {
 876                                 chan->state |= HSCX_TX_ACTIVE;
 877                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 878                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 879                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 880
 881                                 if(sc->sc_trace & TRACE_B_TX)
 882                                 {
 883                                         i4b_trace_hdr_t hdr;
 884                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
 885                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 886                                         hdr.dir = FROM_TE;
 887                                         hdr.count = ++sc->sc_trace_bcount;
 888                                         MICROTIME(hdr.time);
 889                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 890                                 }
 891
 892                                 if(chan->bprot == BPROT_NONE)
 893                                 {
 894                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 895                                                 activity = ACT_TX;
 896                                 }
 897                                 else
 898                                 {
 899                                         activity = ACT_TX;
 900                                 }
 901                         }
 902                 }
 903
 904                 avma1pp2_hscx_fifo(chan, sc);
 905         }
 906
 907         /* call timeout handling routine */
 908
 909         if(activity == ACT_RX || activity == ACT_TX)
 910                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 911 }
 912
 913 /*
 914  * this is the main routine which checks each channel and then calls
 915  * the real interrupt routine as appropriate
 916  */
 917 static void
 918 avma1pp2_hscx_int_handler(struct l1_softc *sc)
 919 {
 920         u_int stat;
 921
 922         /* has to be a u_int because the byte count is in the 2nd byte */
 923         stat = hscx_read_reg_int(0, sc);
 924         if (stat & HSCX_INT_MASK)
 925           avma1pp2_hscx_intr(0, stat, sc);
 926         stat = hscx_read_reg_int(1, sc);
 927         if (stat & HSCX_INT_MASK)
 928           avma1pp2_hscx_intr(1, stat, sc);
 929 }
 930
 931 static void
 932 avma1pp2_disable(device_t dev)
 933 {
 934         struct l1_softc *sc = device_get_softc(dev);
 935         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 936         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 937
 938         /* could still be wrong, but it seems to help */
 939         bus_space_write_1(btag, bhandle, STAT0_OFFSET, 0x00);
 940 }
 941
 942 static void
 943 avma1pp2_intr(void *xsc)
 944 {
 945         u_char stat;
 946         struct l1_softc *sc;
 947         bus_space_handle_t bhandle;
 948         bus_space_tag_t btag;
 949
 950         sc = xsc;
 951         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 952         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 953
 954         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 955         NDBGL1(L1_H_IRQ, "stat %x", stat);
 956         /* was there an interrupt from this card ? */
 957         if ((stat & ASL_IRQ_Pending) == 0)
 958                 return; /* no */
 959         /* For slow machines loop as long as an interrupt is active */
 960         for (; ((stat & ASL_IRQ_Pending) != 0) ;)
 961         {
 962                 /* interrupts are high active */
 963                 if (stat & ASL_IRQ_TIMER)
 964                         NDBGL1(L1_H_IRQ, "timer interrupt ???");
 965                 if (stat & ASL_IRQ_HSCX)
 966                 {
 967                         NDBGL1(L1_H_IRQ, "HSCX");
 968                         avma1pp2_hscx_int_handler(sc);
 969                 }
 970                 if (stat & ASL_IRQ_ISAC)
 971                 {
 972                        NDBGL1(L1_H_IRQ, "ISAC");
 973                        ifpi2_isacsx_intr(sc);
 974                 }
 975                 stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
 976                 NDBGL1(L1_H_IRQ, "stat %x", stat);
 977
 978         }
 979 }
 980
 981 static void
 982 avma1pp2_hscx_init(struct l1_softc *sc, int h_chan, int activate)
 983 {
 984         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 985         u_int param = 0;
 986
 987         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
 988                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
 989
 990         sc->avma1pp_cmd = sc->avma1pp_prot = sc->avma1pp_txl = 0;
 991
 992         if (activate == 0)
 993         {
 994                 /* only deactivate if both channels are idle */
 995                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
 996                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
 997                 {
 998                         return;
 999                 }
1000                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1001                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1002                 AVMA1PPSETCMDLONG(param);
1003                 hscx_write_reg(h_chan, param, sc);
1004                 return;
1005         }
1006         if(chan->bprot == BPROT_RHDLC)
1007         {
1008                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1009
1010                 /* HDLC Frames, transparent mode 0 */
1011                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1012                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1013                 AVMA1PPSETCMDLONG(param);
1014                 hscx_write_reg(h_chan, param, sc);
1015                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1016                 AVMA1PPSETCMDLONG(param);
1017                 hscx_write_reg(h_chan, param, sc);
1018                 sc->avma1pp_cmd = 0;
1019         }
1020         else
1021         {
1022                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1023
1024                 /* Raw Telephony, extended transparent mode 1 */
1025                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1026                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1027                 AVMA1PPSETCMDLONG(param);
1028                 hscx_write_reg(h_chan, param, sc);
1029                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1030                 AVMA1PPSETCMDLONG(param);
1031                 hscx_write_reg(h_chan, param, sc);
1032                 sc->avma1pp_cmd = 0;
1033         }
1034 }
1035
1036 static void
1037 avma1pp2_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1038 {
1039         struct l1_softc *sc = ifpi2_scp[unit];
1040         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1041
1042         crit_enter();
1043
1044         if(activate == 0)
1045         {
1046                 /* deactivation */
1047                 chan->state = HSCX_IDLE;
1048                 avma1pp2_hscx_init(sc, h_chan, activate);
1049         }
1050
1051         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1052                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1053
1054         /* general part */
1055
1056         chan->unit = sc->sc_unit;       /* unit number */
1057         chan->channel = h_chan;         /* B channel */
1058         chan->bprot = bprot;            /* B channel protocol */
1059         chan->state = HSCX_IDLE;        /* B channel state */
1060
1061         /* receiver part */
1062
1063         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1064
1065         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1066
1067         chan->rxcount = 0;              /* reset rx counter */
1068
1069         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1070
1071         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1072         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1073         chan->in_len = 0;               /* reset mbuf data len */
1074
1075         /* transmitter part */
1076
1077         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1078
1079         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1080
1081         chan->txcount = 0;              /* reset tx counter */
1082
1083         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1084
1085         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1086         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1087         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1088         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1089
1090         if(activate != 0)
1091         {
1092                 /* activation */
1093                 avma1pp2_hscx_init(sc, h_chan, activate);
1094                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1095         }
1096
1097         crit_exit();
1098 }
1099
1100 static void
1101 avma1pp2_bchannel_start(int unit, int h_chan)
1102 {
1103         struct l1_softc *sc = ifpi2_scp[unit];
1104         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1105         int activity = -1;
1106
1107         crit_enter();
1108         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1109         {
1110                 crit_exit();
1111                 return;                         /* yes, leave */
1112         }
1113
1114         /* get next mbuf from queue */
1115
1116         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1117
1118         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1119         {
1120                 crit_exit();
1121                 return;                         /* yes, exit */
1122         }
1123
1124         /* init current mbuf values */
1125
1126         chan->out_mbuf_cur = chan->out_mbuf_head;
1127         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1128         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1129
1130         /* activity indicator for timeout handling */
1131
1132         if(chan->bprot == BPROT_NONE)
1133         {
1134                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1135                         activity = ACT_TX;
1136         }
1137         else
1138         {
1139                 activity = ACT_TX;
1140         }
1141
1142         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1143
1144         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1145         {
1146                 i4b_trace_hdr_t hdr;
1147                 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1148                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1149                 hdr.dir = FROM_TE;
1150                 hdr.count = ++sc->sc_trace_bcount;
1151                 MICROTIME(hdr.time);
1152                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1153         }
1154
1155         avma1pp2_hscx_fifo(chan, sc);
1156
1157         /* call timeout handling routine */
1158
1159         if(activity == ACT_RX || activity == ACT_TX)
1160                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1161
1162         crit_exit();
1163 }
1164
1165 /*---------------------------------------------------------------------------*
1166  *      return the address of isic drivers linktab
1167  *---------------------------------------------------------------------------*/
1168 static isdn_link_t *
1169 avma1pp2_ret_linktab(int unit, int channel)
1170 {
1171         struct l1_softc *sc = ifpi2_scp[unit];
1172         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1173
1174         return(&chan->isic_isdn_linktab);
1175 }
1176
1177 /*---------------------------------------------------------------------------*
1178  *      set the driver linktab in the b channel softc
1179  *---------------------------------------------------------------------------*/
1180 static void
1181 avma1pp2_set_linktab(int unit, int channel, drvr_link_t *dlt)
1182 {
1183         struct l1_softc *sc = ifpi2_scp[unit];
1184         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1185
1186         chan->isic_drvr_linktab = dlt;
1187 }
1188
1189
1190 /*---------------------------------------------------------------------------*
1191  *      initialize our local linktab
1192  *---------------------------------------------------------------------------*/
1193 static void
1194 avma1pp2_init_linktab(struct l1_softc *sc)
1195 {
1196         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1197         isdn_link_t *lt = &chan->isic_isdn_linktab;
1198
1199         /* make sure the hardware driver is known to layer 4 */
1200         /* avoid overwriting if already set */
1201         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1202         {
1203                 ctrl_types[CTRL_PASSIVE].set_linktab = i4b_l1_set_linktab;
1204                 ctrl_types[CTRL_PASSIVE].get_linktab = i4b_l1_ret_linktab;
1205         }
1206
1207         /* local setup */
1208         lt->unit = sc->sc_unit;
1209         lt->channel = HSCX_CH_A;
1210         lt->bch_config = avma1pp2_bchannel_setup;
1211         lt->bch_tx_start = avma1pp2_bchannel_start;
1212         lt->bch_stat = avma1pp2_bchannel_stat;
1213         lt->tx_queue = &chan->tx_queue;
1214
1215         /* used by non-HDLC data transfers, i.e. telephony drivers */
1216         lt->rx_queue = &chan->rx_queue;
1217
1218         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1219         lt->rx_mbuf = &chan->in_mbuf;
1220
1221         chan = &sc->sc_chan[HSCX_CH_B];
1222         lt = &chan->isic_isdn_linktab;
1223
1224         lt->unit = sc->sc_unit;
1225         lt->channel = HSCX_CH_B;
1226         lt->bch_config = avma1pp2_bchannel_setup;
1227         lt->bch_tx_start = avma1pp2_bchannel_start;
1228         lt->bch_stat = avma1pp2_bchannel_stat;
1229         lt->tx_queue = &chan->tx_queue;
1230
1231         /* used by non-HDLC data transfers, i.e. telephony drivers */
1232         lt->rx_queue = &chan->rx_queue;
1233
1234         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1235         lt->rx_mbuf = &chan->in_mbuf;
1236 }
1237
1238 /*
1239  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1240  */
1241 static void
1242 avma1pp2_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1243 {
1244         struct l1_softc *sc = ifpi2_scp[unit];
1245         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1246
1247         crit_enter();
1248
1249         bsp->outbytes = chan->txcount;
1250         bsp->inbytes = chan->rxcount;
1251
1252         chan->txcount = 0;
1253         chan->rxcount = 0;
1254
1255         crit_exit();
1256 }
1257
1258 /*---------------------------------------------------------------------------*
1259  *      fill HSCX fifo with data from the current mbuf
1260  *      Put this here until it can go into i4b_hscx.c
1261  *---------------------------------------------------------------------------*/
1262 static int
1263 avma1pp2_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1264 {
1265         int len;
1266         int nextlen;
1267         int i;
1268         int cmd = 0;
1269         /* using a scratch buffer simplifies writing to the FIFO */
1270         u_char scrbuf[HSCX_FIFO_LEN];
1271
1272         len = 0;
1273
1274         /*
1275          * fill the HSCX tx fifo with data from the current mbuf. if
1276          * current mbuf holds less data than HSCX fifo length, try to
1277          * get the next mbuf from (a possible) mbuf chain. if there is
1278          * not enough data in a single mbuf or in a chain, then this
1279          * is the last mbuf and we tell the HSCX that it has to send
1280          * CRC and closing flag
1281          */
1282
1283         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1284         {
1285                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1286
1287 #ifdef NOTDEF
1288                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1289                         chan->out_mbuf_head,
1290                         chan->out_mbuf_cur,
1291                         chan->out_mbuf_cur_ptr,
1292                         chan->out_mbuf_cur_len,
1293                         len,
1294                         nextlen);
1295 #endif
1296
1297                 cmd |= HSCX_CMDR_XTF;
1298                 /* collect the data in the scratch buffer */
1299                 for (i = 0; i < nextlen; i++)
1300                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1301
1302                 len += nextlen;
1303                 chan->txcount += nextlen;
1304
1305                 chan->out_mbuf_cur_ptr += nextlen;
1306                 chan->out_mbuf_cur_len -= nextlen;
1307
1308                 if(chan->out_mbuf_cur_len == 0)
1309                 {
1310                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1311                         {
1312                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1313                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1314
1315                                 if(sc->sc_trace & TRACE_B_TX)
1316                                 {
1317                                         i4b_trace_hdr_t hdr;
1318                                         hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1319                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1320                                         hdr.dir = FROM_TE;
1321                                         hdr.count = ++sc->sc_trace_bcount;
1322                                         MICROTIME(hdr.time);
1323                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1324                                 }
1325                         }
1326                         else
1327                         {
1328                                 if (chan->bprot != BPROT_NONE)
1329                                         cmd |= HSCX_CMDR_XME;
1330                                 i4b_Bfreembuf(chan->out_mbuf_head);
1331                                 chan->out_mbuf_head = NULL;
1332                         }
1333                 }
1334         }
1335         /* write what we have from the scratch buf to the HSCX fifo */
1336         if (len != 0)
1337                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1338         return(cmd);
1339 }
1340
1341 /*---------------------------------------------------------------------------*
1342  *      ifpi2 - ISAC interrupt routine
1343  *---------------------------------------------------------------------------*/
1344 static void
1345 ifpi2_isacsx_intr(struct l1_softc *sc)
1346 {
1347         u_char isacsx_irq_stat;
1348
1349         for(;;)
1350         {
1351                 /* get isac irq status */
1352                 /* ISTA tells us whether it was a C/I or HDLC int. */
1353                 isacsx_irq_stat = ISAC_READ(I_ISTA);
1354
1355                 if(isacsx_irq_stat)
1356                         ifpi2_isacsx_irq(sc, isacsx_irq_stat); /* isac handler */
1357                 else
1358                         break;
1359         }
1360
1361         ISAC_WRITE(I_MASKD, 0xff);
1362         ISAC_WRITE(I_MASK, 0xff);
1363
1364         DELAY(100);
1365
1366         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1367         ISAC_WRITE(I_MASK, isacsx_imask);
1368 }
1369
1370 /*---------------------------------------------------------------------------*
1371  *      ifpi2_recover - try to recover from irq lockup
1372  *---------------------------------------------------------------------------*/
1373 void
1374 ifpi2_recover(struct l1_softc *sc)
1375 {
1376         printf("ifpi2_recover %d\n", sc->sc_unit);
1377 #if 0 /* fix me later */
1378         u_char byte;
1379
1380         /* get isac irq status */
1381
1382         byte = ISAC_READ(I_ISTA);
1383
1384         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1385
1386         if(byte & ISACSX_ISTA_EXI)
1387                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1388
1389         if(byte & ISACSX_ISTA_CISQ)
1390         {
1391                 byte = ISAC_READ(I_CIRR);
1392
1393                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1394
1395                 if(byte & ISACSX_CIRR_SQC)
1396                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1397         }
1398
1399         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISACSX_IMASK);
1400
1401         ISAC_WRITE(I_MASKD, 0xff);
1402         ISAC_WRITE(I_MASK, 0xff);
1403         DELAY(100);
1404         ISAC_WRITE(I_MASKD, isacsx_imaskd);
1405         ISAC_WRITE(I_MASK, isacsx_imask);
1406 #endif
1407 }
1408
1409
1410 #endif /* NIFPI2 > 0 */