2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written consent.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
30 * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
34 * The following controllers are supported by this driver:
42 * The following controllers are not supported by this driver:
48 * BCM5709S A0, A1, B0, B1, B2, C0
52 #include "opt_polling.h"
54 #include <sys/param.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
63 #include <sys/random.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
72 #include <net/ethernet.h>
74 #include <net/if_arp.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/ifq_var.h>
79 #include <net/vlan/if_vlan_var.h>
80 #include <net/vlan/if_vlan_ether.h>
82 #include <dev/netif/mii_layer/mii.h>
83 #include <dev/netif/mii_layer/miivar.h>
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
88 #include "miibus_if.h"
90 #include <dev/netif/bce/if_bcereg.h>
91 #include <dev/netif/bce/if_bcefw.h>
93 /****************************************************************************/
94 /* BCE Debug Options */
95 /****************************************************************************/
98 static uint32_t bce_debug = BCE_WARN;
102 * 1 = 1 in 2,147,483,648
103 * 256 = 1 in 8,388,608
104 * 2048 = 1 in 1,048,576
105 * 65536 = 1 in 32,768
106 * 1048576 = 1 in 2,048
109 * 1073741824 = 1 in 2
111 * bce_debug_l2fhdr_status_check:
112 * How often the l2_fhdr frame error check will fail.
114 * bce_debug_unexpected_attention:
115 * How often the unexpected attention check will fail.
117 * bce_debug_mbuf_allocation_failure:
118 * How often to simulate an mbuf allocation failure.
120 * bce_debug_dma_map_addr_failure:
121 * How often to simulate a DMA mapping failure.
123 * bce_debug_bootcode_running_failure:
124 * How often to simulate a bootcode failure.
126 static int bce_debug_l2fhdr_status_check = 0;
127 static int bce_debug_unexpected_attention = 0;
128 static int bce_debug_mbuf_allocation_failure = 0;
129 static int bce_debug_dma_map_addr_failure = 0;
130 static int bce_debug_bootcode_running_failure = 0;
132 #endif /* BCE_DEBUG */
135 /****************************************************************************/
136 /* PCI Device ID Table */
138 /* Used by bce_probe() to identify the devices supported by this driver. */
139 /****************************************************************************/
140 #define BCE_DEVDESC_MAX 64
142 static struct bce_type bce_devs[] = {
143 /* BCM5706C Controllers and OEM boards. */
144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
145 "HP NC370T Multifunction Gigabit Server Adapter" },
146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
147 "HP NC370i Multifunction Gigabit Server Adapter" },
148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
149 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
151 "HP NC371i Multifunction Gigabit Server Adapter" },
152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
153 "Broadcom NetXtreme II BCM5706 1000Base-T" },
155 /* BCM5706S controllers and OEM boards. */
156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
157 "HP NC370F Multifunction Gigabit Server Adapter" },
158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
159 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
161 /* BCM5708C controllers and OEM boards. */
162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
163 "HP NC373T PCIe Multifunction Gig Server Adapter" },
164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
165 "HP NC373i Multifunction Gigabit Server Adapter" },
166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
167 "HP NC374m PCIe Multifunction Adapter" },
168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
169 "Broadcom NetXtreme II BCM5708 1000Base-T" },
171 /* BCM5708S controllers and OEM boards. */
172 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
173 "HP NC373m Multifunction Gigabit Server Adapter" },
174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
175 "HP NC373i Multifunction Gigabit Server Adapter" },
176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
177 "HP NC373F PCIe Multifunc Giga Server Adapter" },
178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
179 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
181 /* BCM5709C controllers and OEM boards. */
182 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
183 "HP NC382i DP Multifunction Gigabit Server Adapter" },
184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
185 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
187 "Broadcom NetXtreme II BCM5709 1000Base-T" },
189 /* BCM5709S controllers and OEM boards. */
190 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
191 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
193 "HP NC382i DP Multifunction Gigabit Server Adapter" },
194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
195 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
197 /* BCM5716 controllers and OEM boards. */
198 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
199 "Broadcom NetXtreme II BCM5716 1000Base-T" },
205 /****************************************************************************/
206 /* Supported Flash NVRAM device data. */
207 /****************************************************************************/
208 static const struct flash_spec flash_table[] =
210 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
211 #define NONBUFFERED_FLAGS (BCE_NV_WREN)
214 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
215 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
216 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
218 /* Expansion entry 0001 */
219 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
220 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
221 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
223 /* Saifun SA25F010 (non-buffered flash) */
224 /* strap, cfg1, & write1 need updates */
225 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
228 "Non-buffered flash (128kB)"},
229 /* Saifun SA25F020 (non-buffered flash) */
230 /* strap, cfg1, & write1 need updates */
231 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
232 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
233 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
234 "Non-buffered flash (256kB)"},
235 /* Expansion entry 0100 */
236 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
240 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
241 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
242 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
243 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
244 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
245 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
246 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
247 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
248 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
249 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
250 /* Saifun SA25F005 (non-buffered flash) */
251 /* strap, cfg1, & write1 need updates */
252 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
254 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
255 "Non-buffered flash (64kB)"},
257 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
258 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
259 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
261 /* Expansion entry 1001 */
262 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
263 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
264 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
266 /* Expansion entry 1010 */
267 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
268 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
269 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
271 /* ATMEL AT45DB011B (buffered flash) */
272 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
273 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
274 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
275 "Buffered flash (128kB)"},
276 /* Expansion entry 1100 */
277 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
278 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
279 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
281 /* Expansion entry 1101 */
282 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
283 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
284 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
286 /* Ateml Expansion entry 1110 */
287 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
288 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
289 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
290 "Entry 1110 (Atmel)"},
291 /* ATMEL AT45DB021B (buffered flash) */
292 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
293 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
294 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
295 "Buffered flash (256kB)"},
299 * The BCM5709 controllers transparently handle the
300 * differences between Atmel 264 byte pages and all
301 * flash devices which use 256 byte pages, so no
302 * logical-to-physical mapping is required in the
305 static struct flash_spec flash_5709 = {
306 .flags = BCE_NV_BUFFERED,
307 .page_bits = BCM5709_FLASH_PAGE_BITS,
308 .page_size = BCM5709_FLASH_PAGE_SIZE,
309 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
310 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
311 .name = "5709/5716 buffered flash (256kB)",
315 /****************************************************************************/
316 /* DragonFly device entry points. */
317 /****************************************************************************/
318 static int bce_probe(device_t);
319 static int bce_attach(device_t);
320 static int bce_detach(device_t);
321 static void bce_shutdown(device_t);
323 /****************************************************************************/
324 /* BCE Debug Data Structure Dump Routines */
325 /****************************************************************************/
327 static void bce_dump_mbuf(struct bce_softc *, struct mbuf *);
328 static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
329 static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
330 static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
331 static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
332 static void bce_dump_l2fhdr(struct bce_softc *, int,
333 struct l2_fhdr *) __unused;
334 static void bce_dump_tx_chain(struct bce_softc *, int, int);
335 static void bce_dump_rx_chain(struct bce_softc *, int, int);
336 static void bce_dump_status_block(struct bce_softc *);
337 static void bce_dump_driver_state(struct bce_softc *);
338 static void bce_dump_stats_block(struct bce_softc *) __unused;
339 static void bce_dump_hw_state(struct bce_softc *);
340 static void bce_dump_txp_state(struct bce_softc *);
341 static void bce_dump_rxp_state(struct bce_softc *) __unused;
342 static void bce_dump_tpat_state(struct bce_softc *) __unused;
343 static void bce_freeze_controller(struct bce_softc *) __unused;
344 static void bce_unfreeze_controller(struct bce_softc *) __unused;
345 static void bce_breakpoint(struct bce_softc *);
346 #endif /* BCE_DEBUG */
349 /****************************************************************************/
350 /* BCE Register/Memory Access Routines */
351 /****************************************************************************/
352 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
353 static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
354 static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
355 static int bce_miibus_read_reg(device_t, int, int);
356 static int bce_miibus_write_reg(device_t, int, int, int);
357 static void bce_miibus_statchg(device_t);
360 /****************************************************************************/
361 /* BCE NVRAM Access Routines */
362 /****************************************************************************/
363 static int bce_acquire_nvram_lock(struct bce_softc *);
364 static int bce_release_nvram_lock(struct bce_softc *);
365 static void bce_enable_nvram_access(struct bce_softc *);
366 static void bce_disable_nvram_access(struct bce_softc *);
367 static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
369 static int bce_init_nvram(struct bce_softc *);
370 static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
371 static int bce_nvram_test(struct bce_softc *);
373 /****************************************************************************/
374 /* BCE DMA Allocate/Free Routines */
375 /****************************************************************************/
376 static int bce_dma_alloc(struct bce_softc *);
377 static void bce_dma_free(struct bce_softc *);
378 static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
380 /****************************************************************************/
381 /* BCE Firmware Synchronization and Load */
382 /****************************************************************************/
383 static int bce_fw_sync(struct bce_softc *, uint32_t);
384 static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
386 static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
388 static void bce_init_rxp_cpu(struct bce_softc *);
389 static void bce_init_txp_cpu(struct bce_softc *);
390 static void bce_init_tpat_cpu(struct bce_softc *);
391 static void bce_init_cp_cpu(struct bce_softc *);
392 static void bce_init_com_cpu(struct bce_softc *);
393 static void bce_init_cpus(struct bce_softc *);
395 static void bce_stop(struct bce_softc *);
396 static int bce_reset(struct bce_softc *, uint32_t);
397 static int bce_chipinit(struct bce_softc *);
398 static int bce_blockinit(struct bce_softc *);
399 static int bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
401 static void bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
402 static void bce_probe_pci_caps(struct bce_softc *);
403 static void bce_print_adapter_info(struct bce_softc *);
404 static void bce_get_media(struct bce_softc *);
406 static void bce_init_tx_context(struct bce_softc *);
407 static int bce_init_tx_chain(struct bce_softc *);
408 static void bce_init_rx_context(struct bce_softc *);
409 static int bce_init_rx_chain(struct bce_softc *);
410 static void bce_free_rx_chain(struct bce_softc *);
411 static void bce_free_tx_chain(struct bce_softc *);
413 static int bce_encap(struct bce_softc *, struct mbuf **);
414 static void bce_start(struct ifnet *);
415 static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
416 static void bce_watchdog(struct ifnet *);
417 static int bce_ifmedia_upd(struct ifnet *);
418 static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
419 static void bce_init(void *);
420 static void bce_mgmt_init(struct bce_softc *);
422 static void bce_init_ctx(struct bce_softc *);
423 static void bce_get_mac_addr(struct bce_softc *);
424 static void bce_set_mac_addr(struct bce_softc *);
425 static void bce_phy_intr(struct bce_softc *);
426 static void bce_rx_intr(struct bce_softc *, int);
427 static void bce_tx_intr(struct bce_softc *);
428 static void bce_disable_intr(struct bce_softc *);
429 static void bce_enable_intr(struct bce_softc *, int);
431 #ifdef DEVICE_POLLING
432 static void bce_poll(struct ifnet *, enum poll_cmd, int);
434 static void bce_intr(void *);
435 static void bce_set_rx_mode(struct bce_softc *);
436 static void bce_stats_update(struct bce_softc *);
437 static void bce_tick(void *);
438 static void bce_tick_serialized(struct bce_softc *);
439 static void bce_pulse(void *);
440 static void bce_add_sysctls(struct bce_softc *);
442 static void bce_coal_change(struct bce_softc *);
443 static int bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
444 static int bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
445 static int bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
446 static int bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
447 static int bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
448 static int bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
449 static int bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
450 static int bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
451 static int bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
452 uint32_t *, uint32_t);
456 * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023. Linux's bnx2
457 * takes 1023 as the TX ticks limit. However, using 1023 will
458 * cause 5708(B2) to generate extra interrupts (~2000/s) even when
459 * there is _no_ network activity on the NIC.
461 static uint32_t bce_tx_bds_int = 255; /* bcm: 20 */
462 static uint32_t bce_tx_bds = 255; /* bcm: 20 */
463 static uint32_t bce_tx_ticks_int = 1022; /* bcm: 80 */
464 static uint32_t bce_tx_ticks = 1022; /* bcm: 80 */
465 static uint32_t bce_rx_bds_int = 128; /* bcm: 6 */
466 static uint32_t bce_rx_bds = 128; /* bcm: 6 */
467 static uint32_t bce_rx_ticks_int = 125; /* bcm: 18 */
468 static uint32_t bce_rx_ticks = 125; /* bcm: 18 */
470 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
471 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
472 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
473 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
474 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
475 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
476 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
477 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
479 /****************************************************************************/
480 /* DragonFly device dispatch table. */
481 /****************************************************************************/
482 static device_method_t bce_methods[] = {
483 /* Device interface */
484 DEVMETHOD(device_probe, bce_probe),
485 DEVMETHOD(device_attach, bce_attach),
486 DEVMETHOD(device_detach, bce_detach),
487 DEVMETHOD(device_shutdown, bce_shutdown),
490 DEVMETHOD(bus_print_child, bus_generic_print_child),
491 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
494 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
495 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
496 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
501 static driver_t bce_driver = {
504 sizeof(struct bce_softc)
507 static devclass_t bce_devclass;
510 DECLARE_DUMMY_MODULE(if_bce);
511 MODULE_DEPEND(bce, miibus, 1, 1, 1);
512 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
513 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
516 /****************************************************************************/
517 /* Device probe function. */
519 /* Compares the device to the driver's list of supported devices and */
520 /* reports back to the OS whether this is the right driver for the device. */
523 /* BUS_PROBE_DEFAULT on success, positive value on failure. */
524 /****************************************************************************/
526 bce_probe(device_t dev)
529 uint16_t vid, did, svid, sdid;
531 /* Get the data for the device to be probed. */
532 vid = pci_get_vendor(dev);
533 did = pci_get_device(dev);
534 svid = pci_get_subvendor(dev);
535 sdid = pci_get_subdevice(dev);
537 /* Look through the list of known devices for a match. */
538 for (t = bce_devs; t->bce_name != NULL; ++t) {
539 if (vid == t->bce_vid && did == t->bce_did &&
540 (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
541 (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
542 uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
545 descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
547 /* Print out the device identity. */
548 ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
550 ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
552 device_set_desc_copy(dev, descbuf);
553 kfree(descbuf, M_TEMP);
561 /****************************************************************************/
562 /* PCI Capabilities Probe Function. */
564 /* Walks the PCI capabiites list for the device to find what features are */
569 /****************************************************************************/
571 bce_print_adapter_info(struct bce_softc *sc)
573 device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
575 kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
576 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
579 if (sc->bce_flags & BCE_PCIE_FLAG) {
580 kprintf("Bus (PCIe x%d, ", sc->link_width);
581 switch (sc->link_speed) {
583 kprintf("2.5Gbps); ");
589 kprintf("Unknown link speed); ");
593 kprintf("Bus (PCI%s, %s, %dMHz); ",
594 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
595 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
599 /* Firmware version and device features. */
600 kprintf("F/W (0x%08X); Flags( ", sc->bce_fw_ver);
602 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
604 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
610 /****************************************************************************/
611 /* PCI Capabilities Probe Function. */
613 /* Walks the PCI capabiites list for the device to find what features are */
618 /****************************************************************************/
620 bce_probe_pci_caps(struct bce_softc *sc)
622 device_t dev = sc->bce_dev;
625 if (pci_is_pcix(dev))
626 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
628 ptr = pci_get_pciecap_ptr(dev);
630 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
632 sc->link_speed = link_status & 0xf;
633 sc->link_width = (link_status >> 4) & 0x3f;
634 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
635 sc->bce_flags |= BCE_PCIE_FLAG;
640 /****************************************************************************/
641 /* Device attach function. */
643 /* Allocates device resources, performs secondary chip identification, */
644 /* resets and initializes the hardware, and initializes driver instance */
648 /* 0 on success, positive value on failure. */
649 /****************************************************************************/
651 bce_attach(device_t dev)
653 struct bce_softc *sc = device_get_softc(dev);
654 struct ifnet *ifp = &sc->arpcom.ac_if;
662 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
664 pci_enable_busmaster(dev);
666 bce_probe_pci_caps(sc);
668 /* Allocate PCI memory resources. */
670 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
671 RF_ACTIVE | PCI_RF_DENSE);
672 if (sc->bce_res_mem == NULL) {
673 device_printf(dev, "PCI memory allocation failed\n");
676 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
677 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
679 /* Allocate PCI IRQ resources. */
681 count = pci_msi_count(dev);
682 if (count == 1 && pci_alloc_msi(dev, &count) == 0) {
684 sc->bce_flags |= BCE_USING_MSI_FLAG;
688 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
689 RF_SHAREABLE | RF_ACTIVE);
690 if (sc->bce_res_irq == NULL) {
691 device_printf(dev, "PCI map interrupt failed\n");
697 * Configure byte swap and enable indirect register access.
698 * Rely on CPU to do target byte swapping on big endian systems.
699 * Access to registers outside of PCI configurtion space are not
700 * valid until this is done.
702 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
703 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
704 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
706 /* Save ASIC revsion info. */
707 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
709 /* Weed out any non-production controller revisions. */
710 switch(BCE_CHIP_ID(sc)) {
711 case BCE_CHIP_ID_5706_A0:
712 case BCE_CHIP_ID_5706_A1:
713 case BCE_CHIP_ID_5708_A0:
714 case BCE_CHIP_ID_5708_B0:
715 case BCE_CHIP_ID_5709_A0:
716 case BCE_CHIP_ID_5709_B0:
717 case BCE_CHIP_ID_5709_B1:
719 /* 5709C B2 seems to work fine */
720 case BCE_CHIP_ID_5709_B2:
722 device_printf(dev, "Unsupported chip id 0x%08x!\n",
729 * Find the base address for shared memory access.
730 * Newer versions of bootcode use a signature and offset
731 * while older versions use a fixed address.
733 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
734 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
735 BCE_SHM_HDR_SIGNATURE_SIG) {
736 /* Multi-port devices use different offsets in shared memory. */
737 sc->bce_shmem_base = REG_RD_IND(sc,
738 BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
740 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
742 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
744 /* Fetch the bootcode revision. */
745 sc->bce_fw_ver = REG_RD_IND(sc, sc->bce_shmem_base +
746 BCE_DEV_INFO_BC_REV);
748 /* Check if any management firmware is running. */
749 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
750 if (val & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED))
751 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
753 /* Get PCI bus information (speed and type). */
754 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
755 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
758 sc->bce_flags |= BCE_PCIX_FLAG;
760 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
761 BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
763 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
764 sc->bus_speed_mhz = 133;
767 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
768 sc->bus_speed_mhz = 100;
771 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
772 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
773 sc->bus_speed_mhz = 66;
776 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
777 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
778 sc->bus_speed_mhz = 50;
781 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
782 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
783 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
784 sc->bus_speed_mhz = 33;
788 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
789 sc->bus_speed_mhz = 66;
791 sc->bus_speed_mhz = 33;
794 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
795 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
797 /* Reset the controller. */
798 rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
802 /* Initialize the controller. */
803 rc = bce_chipinit(sc);
805 device_printf(dev, "Controller initialization failed!\n");
809 /* Perform NVRAM test. */
810 rc = bce_nvram_test(sc);
812 device_printf(dev, "NVRAM test failed!\n");
816 /* Fetch the permanent Ethernet MAC address. */
817 bce_get_mac_addr(sc);
820 * Trip points control how many BDs
821 * should be ready before generating an
822 * interrupt while ticks control how long
823 * a BD can sit in the chain before
824 * generating an interrupt. Set the default
825 * values for the RX and TX rings.
829 /* Force more frequent interrupts. */
830 sc->bce_tx_quick_cons_trip_int = 1;
831 sc->bce_tx_quick_cons_trip = 1;
832 sc->bce_tx_ticks_int = 0;
833 sc->bce_tx_ticks = 0;
835 sc->bce_rx_quick_cons_trip_int = 1;
836 sc->bce_rx_quick_cons_trip = 1;
837 sc->bce_rx_ticks_int = 0;
838 sc->bce_rx_ticks = 0;
840 sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
841 sc->bce_tx_quick_cons_trip = bce_tx_bds;
842 sc->bce_tx_ticks_int = bce_tx_ticks_int;
843 sc->bce_tx_ticks = bce_tx_ticks;
845 sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
846 sc->bce_rx_quick_cons_trip = bce_rx_bds;
847 sc->bce_rx_ticks_int = bce_rx_ticks_int;
848 sc->bce_rx_ticks = bce_rx_ticks;
851 /* Update statistics once every second. */
852 sc->bce_stats_ticks = 1000000 & 0xffff00;
854 /* Find the media type for the adapter. */
857 /* Allocate DMA memory resources. */
858 rc = bce_dma_alloc(sc);
860 device_printf(dev, "DMA resource allocation failed!\n");
864 /* Initialize the ifnet interface. */
866 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
867 ifp->if_ioctl = bce_ioctl;
868 ifp->if_start = bce_start;
869 ifp->if_init = bce_init;
870 ifp->if_watchdog = bce_watchdog;
871 #ifdef DEVICE_POLLING
872 ifp->if_poll = bce_poll;
874 ifp->if_mtu = ETHERMTU;
875 ifp->if_hwassist = BCE_IF_HWASSIST;
876 ifp->if_capabilities = BCE_IF_CAPABILITIES;
877 ifp->if_capenable = ifp->if_capabilities;
878 ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
879 ifq_set_ready(&ifp->if_snd);
881 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
882 ifp->if_baudrate = IF_Gbps(2.5);
884 ifp->if_baudrate = IF_Gbps(1);
886 /* Assume a standard 1500 byte MTU size for mbuf allocations. */
887 sc->mbuf_alloc_size = MCLBYTES;
889 /* Look for our PHY. */
890 rc = mii_phy_probe(dev, &sc->bce_miibus,
891 bce_ifmedia_upd, bce_ifmedia_sts);
893 device_printf(dev, "PHY probe failed!\n");
897 /* Attach to the Ethernet interface list. */
898 ether_ifattach(ifp, sc->eaddr, NULL);
900 callout_init(&sc->bce_tick_callout);
901 callout_init(&sc->bce_pulse_callout);
903 /* Hookup IRQ last. */
904 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
905 &sc->bce_intrhand, ifp->if_serializer);
907 device_printf(dev, "Failed to setup IRQ!\n");
912 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
913 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
915 /* Print some important debugging info. */
916 DBRUN(BCE_INFO, bce_dump_driver_state(sc));
918 /* Add the supported sysctls to the kernel. */
922 * The chip reset earlier notified the bootcode that
923 * a driver is present. We now need to start our pulse
924 * routine so that the bootcode is reminded that we're
929 /* Get the firmware running so IPMI still works */
932 bce_print_adapter_info(sc);
941 /****************************************************************************/
942 /* Device detach function. */
944 /* Stops the controller, resets the controller, and releases resources. */
947 /* 0 on success, positive value on failure. */
948 /****************************************************************************/
950 bce_detach(device_t dev)
952 struct bce_softc *sc = device_get_softc(dev);
954 if (device_is_attached(dev)) {
955 struct ifnet *ifp = &sc->arpcom.ac_if;
958 /* Stop and reset the controller. */
959 lwkt_serialize_enter(ifp->if_serializer);
960 callout_stop(&sc->bce_pulse_callout);
962 if (sc->bce_flags & BCE_NO_WOL_FLAG)
963 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
965 msg = BCE_DRV_MSG_CODE_UNLOAD;
967 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
968 lwkt_serialize_exit(ifp->if_serializer);
973 /* If we have a child device on the MII bus remove it too. */
975 device_delete_child(dev, sc->bce_miibus);
976 bus_generic_detach(dev);
978 if (sc->bce_res_irq != NULL) {
979 bus_release_resource(dev, SYS_RES_IRQ,
980 sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0,
985 if (sc->bce_flags & BCE_USING_MSI_FLAG)
986 pci_release_msi(dev);
989 if (sc->bce_res_mem != NULL) {
990 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
996 if (sc->bce_sysctl_tree != NULL)
997 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1003 /****************************************************************************/
1004 /* Device shutdown function. */
1006 /* Stops and resets the controller. */
1010 /****************************************************************************/
1012 bce_shutdown(device_t dev)
1014 struct bce_softc *sc = device_get_softc(dev);
1015 struct ifnet *ifp = &sc->arpcom.ac_if;
1018 lwkt_serialize_enter(ifp->if_serializer);
1020 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1021 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1023 msg = BCE_DRV_MSG_CODE_UNLOAD;
1025 lwkt_serialize_exit(ifp->if_serializer);
1029 /****************************************************************************/
1030 /* Indirect register read. */
1032 /* Reads NetXtreme II registers using an index/data register pair in PCI */
1033 /* configuration space. Using this mechanism avoids issues with posted */
1034 /* reads but is much slower than memory-mapped I/O. */
1037 /* The value of the register. */
1038 /****************************************************************************/
1040 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1042 device_t dev = sc->bce_dev;
1044 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1048 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1049 DBPRINT(sc, BCE_EXCESSIVE,
1050 "%s(); offset = 0x%08X, val = 0x%08X\n",
1051 __func__, offset, val);
1055 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1060 /****************************************************************************/
1061 /* Indirect register write. */
1063 /* Writes NetXtreme II registers using an index/data register pair in PCI */
1064 /* configuration space. Using this mechanism avoids issues with posted */
1065 /* writes but is muchh slower than memory-mapped I/O. */
1069 /****************************************************************************/
1071 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1073 device_t dev = sc->bce_dev;
1075 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1076 __func__, offset, val);
1078 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1079 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1083 /****************************************************************************/
1084 /* Context memory write. */
1086 /* The NetXtreme II controller uses context memory to track connection */
1087 /* information for L2 and higher network protocols. */
1091 /****************************************************************************/
1093 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1096 uint32_t idx, offset = ctx_offset + cid_addr;
1097 uint32_t val, retry_cnt = 5;
1099 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1100 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1101 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1102 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1104 for (idx = 0; idx < retry_cnt; idx++) {
1105 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1106 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1111 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1112 device_printf(sc->bce_dev,
1113 "Unable to write CTX memory: "
1114 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1115 cid_addr, ctx_offset);
1118 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1119 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1124 /****************************************************************************/
1125 /* PHY register read. */
1127 /* Implements register reads on the MII bus. */
1130 /* The value of the register. */
1131 /****************************************************************************/
1133 bce_miibus_read_reg(device_t dev, int phy, int reg)
1135 struct bce_softc *sc = device_get_softc(dev);
1139 /* Make sure we are accessing the correct PHY address. */
1140 if (phy != sc->bce_phy_addr) {
1141 DBPRINT(sc, BCE_VERBOSE,
1142 "Invalid PHY address %d for PHY read!\n", phy);
1146 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1147 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1148 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1150 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1151 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1156 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1157 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1158 BCE_EMAC_MDIO_COMM_START_BUSY;
1159 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1161 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1164 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1165 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1168 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1169 val &= BCE_EMAC_MDIO_COMM_DATA;
1174 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1175 if_printf(&sc->arpcom.ac_if,
1176 "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1180 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1183 DBPRINT(sc, BCE_EXCESSIVE,
1184 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1185 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1187 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1188 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1189 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1191 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1192 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1196 return (val & 0xffff);
1200 /****************************************************************************/
1201 /* PHY register write. */
1203 /* Implements register writes on the MII bus. */
1206 /* The value of the register. */
1207 /****************************************************************************/
1209 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1211 struct bce_softc *sc = device_get_softc(dev);
1215 /* Make sure we are accessing the correct PHY address. */
1216 if (phy != sc->bce_phy_addr) {
1217 DBPRINT(sc, BCE_WARN,
1218 "Invalid PHY address %d for PHY write!\n", phy);
1222 DBPRINT(sc, BCE_EXCESSIVE,
1223 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1224 __func__, phy, (uint16_t)(reg & 0xffff),
1225 (uint16_t)(val & 0xffff));
1227 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1228 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1229 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1231 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1232 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1237 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1238 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1239 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1240 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1242 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1245 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1246 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1252 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1253 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1255 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1256 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1257 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1259 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1260 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1268 /****************************************************************************/
1269 /* MII bus status change. */
1271 /* Called by the MII bus driver when the PHY establishes link to set the */
1272 /* MAC interface registers. */
1276 /****************************************************************************/
1278 bce_miibus_statchg(device_t dev)
1280 struct bce_softc *sc = device_get_softc(dev);
1281 struct mii_data *mii = device_get_softc(sc->bce_miibus);
1283 DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1284 mii->mii_media_active);
1287 /* Decode the interface media flags. */
1288 if_printf(&sc->arpcom.ac_if, "Media: ( ");
1289 switch(IFM_TYPE(mii->mii_media_active)) {
1291 kprintf("Ethernet )");
1294 kprintf("Unknown )");
1298 kprintf(" Media Options: ( ");
1299 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1301 kprintf("Autoselect )");
1304 kprintf("Manual )");
1310 kprintf("10Base-T )");
1313 kprintf("100Base-TX )");
1316 kprintf("1000Base-SX )");
1319 kprintf("1000Base-T )");
1326 kprintf(" Global Options: (");
1327 if (mii->mii_media_active & IFM_FDX)
1328 kprintf(" FullDuplex");
1329 if (mii->mii_media_active & IFM_HDX)
1330 kprintf(" HalfDuplex");
1331 if (mii->mii_media_active & IFM_LOOP)
1332 kprintf(" Loopback");
1333 if (mii->mii_media_active & IFM_FLAG0)
1335 if (mii->mii_media_active & IFM_FLAG1)
1337 if (mii->mii_media_active & IFM_FLAG2)
1342 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1345 * Set MII or GMII interface based on the speed negotiated
1348 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1349 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1350 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1351 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1353 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1354 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1358 * Set half or full duplex based on the duplicity negotiated
1361 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1362 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1363 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1365 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1366 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1371 /****************************************************************************/
1372 /* Acquire NVRAM lock. */
1374 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1375 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1376 /* for use by the driver. */
1379 /* 0 on success, positive value on failure. */
1380 /****************************************************************************/
1382 bce_acquire_nvram_lock(struct bce_softc *sc)
1387 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1389 /* Request access to the flash interface. */
1390 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1391 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1392 val = REG_RD(sc, BCE_NVM_SW_ARB);
1393 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1399 if (j >= NVRAM_TIMEOUT_COUNT) {
1400 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1407 /****************************************************************************/
1408 /* Release NVRAM lock. */
1410 /* When the caller is finished accessing NVRAM the lock must be released. */
1411 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1412 /* for use by the driver. */
1415 /* 0 on success, positive value on failure. */
1416 /****************************************************************************/
1418 bce_release_nvram_lock(struct bce_softc *sc)
1423 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1426 * Relinquish nvram interface.
1428 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1430 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1431 val = REG_RD(sc, BCE_NVM_SW_ARB);
1432 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1438 if (j >= NVRAM_TIMEOUT_COUNT) {
1439 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1446 /****************************************************************************/
1447 /* Enable NVRAM access. */
1449 /* Before accessing NVRAM for read or write operations the caller must */
1450 /* enabled NVRAM access. */
1454 /****************************************************************************/
1456 bce_enable_nvram_access(struct bce_softc *sc)
1460 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1462 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1463 /* Enable both bits, even on read. */
1464 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1465 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1469 /****************************************************************************/
1470 /* Disable NVRAM access. */
1472 /* When the caller is finished accessing NVRAM access must be disabled. */
1476 /****************************************************************************/
1478 bce_disable_nvram_access(struct bce_softc *sc)
1482 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1484 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1486 /* Disable both bits, even after read. */
1487 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1488 val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1492 /****************************************************************************/
1493 /* Read a dword (32 bits) from NVRAM. */
1495 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */
1496 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */
1499 /* 0 on success and the 32 bit value read, positive value on failure. */
1500 /****************************************************************************/
1502 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1508 /* Build the command word. */
1509 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1511 /* Calculate the offset for buffered flash. */
1512 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1513 offset = ((offset / sc->bce_flash_info->page_size) <<
1514 sc->bce_flash_info->page_bits) +
1515 (offset % sc->bce_flash_info->page_size);
1519 * Clear the DONE bit separately, set the address to read,
1520 * and issue the read.
1522 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1523 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1524 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1526 /* Wait for completion. */
1527 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1532 val = REG_RD(sc, BCE_NVM_COMMAND);
1533 if (val & BCE_NVM_COMMAND_DONE) {
1534 val = REG_RD(sc, BCE_NVM_READ);
1537 memcpy(ret_val, &val, 4);
1542 /* Check for errors. */
1543 if (i >= NVRAM_TIMEOUT_COUNT) {
1544 if_printf(&sc->arpcom.ac_if,
1545 "Timeout error reading NVRAM at offset 0x%08X!\n",
1553 /****************************************************************************/
1554 /* Initialize NVRAM access. */
1556 /* Identify the NVRAM device in use and prepare the NVRAM interface to */
1557 /* access that device. */
1560 /* 0 on success, positive value on failure. */
1561 /****************************************************************************/
1563 bce_init_nvram(struct bce_softc *sc)
1566 int j, entry_count, rc = 0;
1567 const struct flash_spec *flash;
1569 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1571 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1572 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1573 sc->bce_flash_info = &flash_5709;
1574 goto bce_init_nvram_get_flash_size;
1577 /* Determine the selected interface. */
1578 val = REG_RD(sc, BCE_NVM_CFG1);
1580 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1583 * Flash reconfiguration is required to support additional
1584 * NVRAM devices not directly supported in hardware.
1585 * Check if the flash interface was reconfigured
1589 if (val & 0x40000000) {
1590 /* Flash interface reconfigured by bootcode. */
1592 DBPRINT(sc, BCE_INFO_LOAD,
1593 "%s(): Flash WAS reconfigured.\n", __func__);
1595 for (j = 0, flash = flash_table; j < entry_count;
1597 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1598 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1599 sc->bce_flash_info = flash;
1604 /* Flash interface not yet reconfigured. */
1607 DBPRINT(sc, BCE_INFO_LOAD,
1608 "%s(): Flash was NOT reconfigured.\n", __func__);
1610 if (val & (1 << 23))
1611 mask = FLASH_BACKUP_STRAP_MASK;
1613 mask = FLASH_STRAP_MASK;
1615 /* Look for the matching NVRAM device configuration data. */
1616 for (j = 0, flash = flash_table; j < entry_count;
1618 /* Check if the device matches any of the known devices. */
1619 if ((val & mask) == (flash->strapping & mask)) {
1620 /* Found a device match. */
1621 sc->bce_flash_info = flash;
1623 /* Request access to the flash interface. */
1624 rc = bce_acquire_nvram_lock(sc);
1628 /* Reconfigure the flash interface. */
1629 bce_enable_nvram_access(sc);
1630 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1631 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1632 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1633 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1634 bce_disable_nvram_access(sc);
1635 bce_release_nvram_lock(sc);
1641 /* Check if a matching device was found. */
1642 if (j == entry_count) {
1643 sc->bce_flash_info = NULL;
1644 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1648 bce_init_nvram_get_flash_size:
1649 /* Write the flash config data to the shared memory interface. */
1650 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2) &
1651 BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1653 sc->bce_flash_size = val;
1655 sc->bce_flash_size = sc->bce_flash_info->total_size;
1657 DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1658 __func__, sc->bce_flash_info->total_size);
1660 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1666 /****************************************************************************/
1667 /* Read an arbitrary range of data from NVRAM. */
1669 /* Prepares the NVRAM interface for access and reads the requested data */
1670 /* into the supplied buffer. */
1673 /* 0 on success and the data read, positive value on failure. */
1674 /****************************************************************************/
1676 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1679 uint32_t cmd_flags, offset32, len32, extra;
1685 /* Request access to the flash interface. */
1686 rc = bce_acquire_nvram_lock(sc);
1690 /* Enable access to flash interface */
1691 bce_enable_nvram_access(sc);
1699 /* XXX should we release nvram lock if read_dword() fails? */
1705 pre_len = 4 - (offset & 3);
1707 if (pre_len >= len32) {
1709 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1711 cmd_flags = BCE_NVM_COMMAND_FIRST;
1714 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1718 memcpy(ret_buf, buf + (offset & 3), pre_len);
1726 extra = 4 - (len32 & 3);
1727 len32 = (len32 + 4) & ~3;
1734 cmd_flags = BCE_NVM_COMMAND_LAST;
1736 cmd_flags = BCE_NVM_COMMAND_FIRST |
1737 BCE_NVM_COMMAND_LAST;
1739 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1741 memcpy(ret_buf, buf, 4 - extra);
1742 } else if (len32 > 0) {
1745 /* Read the first word. */
1749 cmd_flags = BCE_NVM_COMMAND_FIRST;
1751 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1753 /* Advance to the next dword. */
1758 while (len32 > 4 && rc == 0) {
1759 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1761 /* Advance to the next dword. */
1768 goto bce_nvram_read_locked_exit;
1770 cmd_flags = BCE_NVM_COMMAND_LAST;
1771 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1773 memcpy(ret_buf, buf, 4 - extra);
1776 bce_nvram_read_locked_exit:
1777 /* Disable access to flash interface and release the lock. */
1778 bce_disable_nvram_access(sc);
1779 bce_release_nvram_lock(sc);
1785 /****************************************************************************/
1786 /* Verifies that NVRAM is accessible and contains valid data. */
1788 /* Reads the configuration data from NVRAM and verifies that the CRC is */
1792 /* 0 on success, positive value on failure. */
1793 /****************************************************************************/
1795 bce_nvram_test(struct bce_softc *sc)
1797 uint32_t buf[BCE_NVRAM_SIZE / 4];
1798 uint32_t magic, csum;
1799 uint8_t *data = (uint8_t *)buf;
1803 * Check that the device NVRAM is valid by reading
1804 * the magic value at offset 0.
1806 rc = bce_nvram_read(sc, 0, data, 4);
1810 magic = be32toh(buf[0]);
1811 if (magic != BCE_NVRAM_MAGIC) {
1812 if_printf(&sc->arpcom.ac_if,
1813 "Invalid NVRAM magic value! Expected: 0x%08X, "
1814 "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1819 * Verify that the device NVRAM includes valid
1820 * configuration data.
1822 rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1826 csum = ether_crc32_le(data, 0x100);
1827 if (csum != BCE_CRC32_RESIDUAL) {
1828 if_printf(&sc->arpcom.ac_if,
1829 "Invalid Manufacturing Information NVRAM CRC! "
1830 "Expected: 0x%08X, Found: 0x%08X\n",
1831 BCE_CRC32_RESIDUAL, csum);
1835 csum = ether_crc32_le(data + 0x100, 0x100);
1836 if (csum != BCE_CRC32_RESIDUAL) {
1837 if_printf(&sc->arpcom.ac_if,
1838 "Invalid Feature Configuration Information "
1839 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1840 BCE_CRC32_RESIDUAL, csum);
1847 /****************************************************************************/
1848 /* Identifies the current media type of the controller and sets the PHY */
1853 /****************************************************************************/
1855 bce_get_media(struct bce_softc *sc)
1859 sc->bce_phy_addr = 1;
1861 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1862 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1863 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1864 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1868 * The BCM5709S is software configurable
1869 * for Copper or SerDes operation.
1871 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1873 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1874 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1878 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1879 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1882 (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1885 if (pci_get_function(sc->bce_dev) == 0) {
1890 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1898 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1902 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1903 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1906 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1907 sc->bce_flags |= BCE_NO_WOL_FLAG;
1908 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1909 sc->bce_phy_addr = 2;
1910 val = REG_RD_IND(sc, sc->bce_shmem_base +
1911 BCE_SHARED_HW_CFG_CONFIG);
1912 if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
1913 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
1915 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
1916 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
1917 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
1922 /****************************************************************************/
1923 /* Free any DMA memory owned by the driver. */
1925 /* Scans through each data structre that requires DMA memory and frees */
1926 /* the memory if allocated. */
1930 /****************************************************************************/
1932 bce_dma_free(struct bce_softc *sc)
1936 /* Destroy the status block. */
1937 if (sc->status_tag != NULL) {
1938 if (sc->status_block != NULL) {
1939 bus_dmamap_unload(sc->status_tag, sc->status_map);
1940 bus_dmamem_free(sc->status_tag, sc->status_block,
1943 bus_dma_tag_destroy(sc->status_tag);
1947 /* Destroy the statistics block. */
1948 if (sc->stats_tag != NULL) {
1949 if (sc->stats_block != NULL) {
1950 bus_dmamap_unload(sc->stats_tag, sc->stats_map);
1951 bus_dmamem_free(sc->stats_tag, sc->stats_block,
1954 bus_dma_tag_destroy(sc->stats_tag);
1957 /* Destroy the CTX DMA stuffs. */
1958 if (sc->ctx_tag != NULL) {
1959 for (i = 0; i < sc->ctx_pages; i++) {
1960 if (sc->ctx_block[i] != NULL) {
1961 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
1962 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
1966 bus_dma_tag_destroy(sc->ctx_tag);
1969 /* Destroy the TX buffer descriptor DMA stuffs. */
1970 if (sc->tx_bd_chain_tag != NULL) {
1971 for (i = 0; i < TX_PAGES; i++) {
1972 if (sc->tx_bd_chain[i] != NULL) {
1973 bus_dmamap_unload(sc->tx_bd_chain_tag,
1974 sc->tx_bd_chain_map[i]);
1975 bus_dmamem_free(sc->tx_bd_chain_tag,
1977 sc->tx_bd_chain_map[i]);
1980 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
1983 /* Destroy the RX buffer descriptor DMA stuffs. */
1984 if (sc->rx_bd_chain_tag != NULL) {
1985 for (i = 0; i < RX_PAGES; i++) {
1986 if (sc->rx_bd_chain[i] != NULL) {
1987 bus_dmamap_unload(sc->rx_bd_chain_tag,
1988 sc->rx_bd_chain_map[i]);
1989 bus_dmamem_free(sc->rx_bd_chain_tag,
1991 sc->rx_bd_chain_map[i]);
1994 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
1997 /* Destroy the TX mbuf DMA stuffs. */
1998 if (sc->tx_mbuf_tag != NULL) {
1999 for (i = 0; i < TOTAL_TX_BD; i++) {
2000 /* Must have been unloaded in bce_stop() */
2001 KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2002 bus_dmamap_destroy(sc->tx_mbuf_tag,
2003 sc->tx_mbuf_map[i]);
2005 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2008 /* Destroy the RX mbuf DMA stuffs. */
2009 if (sc->rx_mbuf_tag != NULL) {
2010 for (i = 0; i < TOTAL_RX_BD; i++) {
2011 /* Must have been unloaded in bce_stop() */
2012 KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2013 bus_dmamap_destroy(sc->rx_mbuf_tag,
2014 sc->rx_mbuf_map[i]);
2016 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2017 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2020 /* Destroy the parent tag */
2021 if (sc->parent_tag != NULL)
2022 bus_dma_tag_destroy(sc->parent_tag);
2026 /****************************************************************************/
2027 /* Get DMA memory from the OS. */
2029 /* Validates that the OS has provided DMA buffers in response to a */
2030 /* bus_dmamap_load() call and saves the physical address of those buffers. */
2031 /* When the callback is used the OS will return 0 for the mapping function */
2032 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
2033 /* failures back to the caller. */
2037 /****************************************************************************/
2039 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2041 bus_addr_t *busaddr = arg;
2044 * Simulate a mapping failure.
2047 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2048 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2049 __FILE__, __LINE__);
2052 /* Check for an error and signal the caller that an error occurred. */
2056 KASSERT(nseg == 1, ("only one segment is allowed\n"));
2057 *busaddr = segs->ds_addr;
2061 /****************************************************************************/
2062 /* Allocate any DMA memory needed by the driver. */
2064 /* Allocates DMA memory needed for the various global structures needed by */
2067 /* Memory alignment requirements: */
2068 /* -----------------+----------+----------+----------+----------+ */
2069 /* Data Structure | 5706 | 5708 | 5709 | 5716 | */
2070 /* -----------------+----------+----------+----------+----------+ */
2071 /* Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2072 /* Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2073 /* RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
2074 /* PG Buffers | none | none | none | none | */
2075 /* TX Buffers | none | none | none | none | */
2076 /* Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
2077 /* Context Pages(1) | N/A | N/A | 4KiB | 4KiB | */
2078 /* -----------------+----------+----------+----------+----------+ */
2080 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
2083 /* 0 for success, positive value for failure. */
2084 /****************************************************************************/
2086 bce_dma_alloc(struct bce_softc *sc)
2088 struct ifnet *ifp = &sc->arpcom.ac_if;
2090 bus_addr_t busaddr, max_busaddr;
2091 bus_size_t status_align, stats_align;
2094 * The embedded PCIe to PCI-X bridge (EPB)
2095 * in the 5708 cannot address memory above
2096 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2098 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2099 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2101 max_busaddr = BUS_SPACE_MAXADDR;
2104 * BCM5709 and BCM5716 uses host memory as cache for context memory.
2106 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2107 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2108 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2109 if (sc->ctx_pages == 0)
2111 if (sc->ctx_pages > BCE_CTX_PAGES) {
2112 device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2124 * Allocate the parent bus DMA tag appropriate for PCI.
2126 rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2127 max_busaddr, BUS_SPACE_MAXADDR,
2129 BUS_SPACE_MAXSIZE_32BIT, 0,
2130 BUS_SPACE_MAXSIZE_32BIT,
2131 0, &sc->parent_tag);
2133 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2138 * Allocate status block.
2140 sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2141 status_align, BCE_STATUS_BLK_SZ,
2142 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2143 &sc->status_tag, &sc->status_map,
2144 &sc->status_block_paddr);
2145 if (sc->status_block == NULL) {
2146 if_printf(ifp, "Could not allocate status block!\n");
2151 * Allocate statistics block.
2153 sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2154 stats_align, BCE_STATS_BLK_SZ,
2155 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2156 &sc->stats_tag, &sc->stats_map,
2157 &sc->stats_block_paddr);
2158 if (sc->stats_block == NULL) {
2159 if_printf(ifp, "Could not allocate statistics block!\n");
2164 * Allocate context block, if needed
2166 if (sc->ctx_pages != 0) {
2167 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2168 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2170 BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2173 if_printf(ifp, "Could not allocate "
2174 "context block DMA tag!\n");
2178 for (i = 0; i < sc->ctx_pages; i++) {
2179 rc = bus_dmamem_alloc(sc->ctx_tag,
2180 (void **)&sc->ctx_block[i],
2181 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2185 if_printf(ifp, "Could not allocate %dth context "
2186 "DMA memory!\n", i);
2190 rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2191 sc->ctx_block[i], BCM_PAGE_SIZE,
2192 bce_dma_map_addr, &busaddr,
2195 if (rc == EINPROGRESS) {
2196 panic("%s coherent memory loading "
2197 "is still in progress!", ifp->if_xname);
2199 if_printf(ifp, "Could not map %dth context "
2200 "DMA memory!\n", i);
2201 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2203 sc->ctx_block[i] = NULL;
2206 sc->ctx_paddr[i] = busaddr;
2211 * Create a DMA tag for the TX buffer descriptor chain,
2212 * allocate and clear the memory, and fetch the
2213 * physical address of the block.
2215 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2216 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2218 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2219 0, &sc->tx_bd_chain_tag);
2221 if_printf(ifp, "Could not allocate "
2222 "TX descriptor chain DMA tag!\n");
2226 for (i = 0; i < TX_PAGES; i++) {
2227 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2228 (void **)&sc->tx_bd_chain[i],
2229 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2231 &sc->tx_bd_chain_map[i]);
2233 if_printf(ifp, "Could not allocate %dth TX descriptor "
2234 "chain DMA memory!\n", i);
2238 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2239 sc->tx_bd_chain_map[i],
2240 sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2241 bce_dma_map_addr, &busaddr,
2244 if (rc == EINPROGRESS) {
2245 panic("%s coherent memory loading "
2246 "is still in progress!", ifp->if_xname);
2248 if_printf(ifp, "Could not map %dth TX descriptor "
2249 "chain DMA memory!\n", i);
2250 bus_dmamem_free(sc->tx_bd_chain_tag,
2252 sc->tx_bd_chain_map[i]);
2253 sc->tx_bd_chain[i] = NULL;
2257 sc->tx_bd_chain_paddr[i] = busaddr;
2258 /* DRC - Fix for 64 bit systems. */
2259 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2260 i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2263 /* Create a DMA tag for TX mbufs. */
2264 rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2265 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2267 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2268 BCE_MAX_SEGMENTS, MCLBYTES,
2269 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2273 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2277 /* Create DMA maps for the TX mbufs clusters. */
2278 for (i = 0; i < TOTAL_TX_BD; i++) {
2279 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2280 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2281 &sc->tx_mbuf_map[i]);
2283 for (j = 0; j < i; ++j) {
2284 bus_dmamap_destroy(sc->tx_mbuf_tag,
2285 sc->tx_mbuf_map[i]);
2287 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2288 sc->tx_mbuf_tag = NULL;
2290 if_printf(ifp, "Unable to create "
2291 "%dth TX mbuf DMA map!\n", i);
2297 * Create a DMA tag for the RX buffer descriptor chain,
2298 * allocate and clear the memory, and fetch the physical
2299 * address of the blocks.
2301 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2302 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2304 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2305 0, &sc->rx_bd_chain_tag);
2307 if_printf(ifp, "Could not allocate "
2308 "RX descriptor chain DMA tag!\n");
2312 for (i = 0; i < RX_PAGES; i++) {
2313 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2314 (void **)&sc->rx_bd_chain[i],
2315 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2317 &sc->rx_bd_chain_map[i]);
2319 if_printf(ifp, "Could not allocate %dth RX descriptor "
2320 "chain DMA memory!\n", i);
2324 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2325 sc->rx_bd_chain_map[i],
2326 sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2327 bce_dma_map_addr, &busaddr,
2330 if (rc == EINPROGRESS) {
2331 panic("%s coherent memory loading "
2332 "is still in progress!", ifp->if_xname);
2334 if_printf(ifp, "Could not map %dth RX descriptor "
2335 "chain DMA memory!\n", i);
2336 bus_dmamem_free(sc->rx_bd_chain_tag,
2338 sc->rx_bd_chain_map[i]);
2339 sc->rx_bd_chain[i] = NULL;
2343 sc->rx_bd_chain_paddr[i] = busaddr;
2344 /* DRC - Fix for 64 bit systems. */
2345 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2346 i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2349 /* Create a DMA tag for RX mbufs. */
2350 rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2351 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2353 MCLBYTES, 1, MCLBYTES,
2354 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2358 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2362 /* Create tmp DMA map for RX mbuf clusters. */
2363 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2364 &sc->rx_mbuf_tmpmap);
2366 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2367 sc->rx_mbuf_tag = NULL;
2369 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2373 /* Create DMA maps for the RX mbuf clusters. */
2374 for (i = 0; i < TOTAL_RX_BD; i++) {
2375 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2376 &sc->rx_mbuf_map[i]);
2378 for (j = 0; j < i; ++j) {
2379 bus_dmamap_destroy(sc->rx_mbuf_tag,
2380 sc->rx_mbuf_map[j]);
2382 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2383 sc->rx_mbuf_tag = NULL;
2385 if_printf(ifp, "Unable to create "
2386 "%dth RX mbuf DMA map!\n", i);
2394 /****************************************************************************/
2395 /* Firmware synchronization. */
2397 /* Before performing certain events such as a chip reset, synchronize with */
2398 /* the firmware first. */
2401 /* 0 for success, positive value for failure. */
2402 /****************************************************************************/
2404 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2409 /* Don't waste any time if we've timed out before. */
2410 if (sc->bce_fw_timed_out)
2413 /* Increment the message sequence number. */
2414 sc->bce_fw_wr_seq++;
2415 msg_data |= sc->bce_fw_wr_seq;
2417 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2419 /* Send the message to the bootcode driver mailbox. */
2420 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2422 /* Wait for the bootcode to acknowledge the message. */
2423 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2424 /* Check for a response in the bootcode firmware mailbox. */
2425 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB);
2426 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2431 /* If we've timed out, tell the bootcode that we've stopped waiting. */
2432 if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2433 (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2434 if_printf(&sc->arpcom.ac_if,
2435 "Firmware synchronization timeout! "
2436 "msg_data = 0x%08X\n", msg_data);
2438 msg_data &= ~BCE_DRV_MSG_CODE;
2439 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2441 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2443 sc->bce_fw_timed_out = 1;
2450 /****************************************************************************/
2451 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2455 /****************************************************************************/
2457 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2458 uint32_t rv2p_code_len, uint32_t rv2p_proc)
2463 for (i = 0; i < rv2p_code_len; i += 8) {
2464 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2466 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2469 if (rv2p_proc == RV2P_PROC1) {
2470 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2471 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2473 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2474 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2478 /* Reset the processor, un-stall is done later. */
2479 if (rv2p_proc == RV2P_PROC1)
2480 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2482 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2486 /****************************************************************************/
2487 /* Load RISC processor firmware. */
2489 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */
2490 /* associated with a particular processor. */
2494 /****************************************************************************/
2496 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2499 uint32_t offset, val;
2503 val = REG_RD_IND(sc, cpu_reg->mode);
2504 val |= cpu_reg->mode_value_halt;
2505 REG_WR_IND(sc, cpu_reg->mode, val);
2506 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2508 /* Load the Text area. */
2509 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2511 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2512 REG_WR_IND(sc, offset, fw->text[j]);
2515 /* Load the Data area. */
2516 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2518 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2519 REG_WR_IND(sc, offset, fw->data[j]);
2522 /* Load the SBSS area. */
2523 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2525 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2526 REG_WR_IND(sc, offset, fw->sbss[j]);
2529 /* Load the BSS area. */
2530 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2532 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2533 REG_WR_IND(sc, offset, fw->bss[j]);
2536 /* Load the Read-Only area. */
2537 offset = cpu_reg->spad_base +
2538 (fw->rodata_addr - cpu_reg->mips_view_base);
2540 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2541 REG_WR_IND(sc, offset, fw->rodata[j]);
2544 /* Clear the pre-fetch instruction. */
2545 REG_WR_IND(sc, cpu_reg->inst, 0);
2546 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2548 /* Start the CPU. */
2549 val = REG_RD_IND(sc, cpu_reg->mode);
2550 val &= ~cpu_reg->mode_value_halt;
2551 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2552 REG_WR_IND(sc, cpu_reg->mode, val);
2556 /****************************************************************************/
2557 /* Initialize the RX CPU. */
2561 /****************************************************************************/
2563 bce_init_rxp_cpu(struct bce_softc *sc)
2565 struct cpu_reg cpu_reg;
2568 cpu_reg.mode = BCE_RXP_CPU_MODE;
2569 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2570 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2571 cpu_reg.state = BCE_RXP_CPU_STATE;
2572 cpu_reg.state_value_clear = 0xffffff;
2573 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2574 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2575 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2576 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2577 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2578 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2579 cpu_reg.mips_view_base = 0x8000000;
2581 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2582 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2583 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2584 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2585 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2586 fw.start_addr = bce_RXP_b09FwStartAddr;
2588 fw.text_addr = bce_RXP_b09FwTextAddr;
2589 fw.text_len = bce_RXP_b09FwTextLen;
2591 fw.text = bce_RXP_b09FwText;
2593 fw.data_addr = bce_RXP_b09FwDataAddr;
2594 fw.data_len = bce_RXP_b09FwDataLen;
2596 fw.data = bce_RXP_b09FwData;
2598 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2599 fw.sbss_len = bce_RXP_b09FwSbssLen;
2601 fw.sbss = bce_RXP_b09FwSbss;
2603 fw.bss_addr = bce_RXP_b09FwBssAddr;
2604 fw.bss_len = bce_RXP_b09FwBssLen;
2606 fw.bss = bce_RXP_b09FwBss;
2608 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2609 fw.rodata_len = bce_RXP_b09FwRodataLen;
2610 fw.rodata_index = 0;
2611 fw.rodata = bce_RXP_b09FwRodata;
2613 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2614 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2615 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2616 fw.start_addr = bce_RXP_b06FwStartAddr;
2618 fw.text_addr = bce_RXP_b06FwTextAddr;
2619 fw.text_len = bce_RXP_b06FwTextLen;
2621 fw.text = bce_RXP_b06FwText;
2623 fw.data_addr = bce_RXP_b06FwDataAddr;
2624 fw.data_len = bce_RXP_b06FwDataLen;
2626 fw.data = bce_RXP_b06FwData;
2628 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2629 fw.sbss_len = bce_RXP_b06FwSbssLen;
2631 fw.sbss = bce_RXP_b06FwSbss;
2633 fw.bss_addr = bce_RXP_b06FwBssAddr;
2634 fw.bss_len = bce_RXP_b06FwBssLen;
2636 fw.bss = bce_RXP_b06FwBss;
2638 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2639 fw.rodata_len = bce_RXP_b06FwRodataLen;
2640 fw.rodata_index = 0;
2641 fw.rodata = bce_RXP_b06FwRodata;
2644 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2645 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2649 /****************************************************************************/
2650 /* Initialize the TX CPU. */
2654 /****************************************************************************/
2656 bce_init_txp_cpu(struct bce_softc *sc)
2658 struct cpu_reg cpu_reg;
2661 cpu_reg.mode = BCE_TXP_CPU_MODE;
2662 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2663 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2664 cpu_reg.state = BCE_TXP_CPU_STATE;
2665 cpu_reg.state_value_clear = 0xffffff;
2666 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2667 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2668 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2669 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2670 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2671 cpu_reg.spad_base = BCE_TXP_SCRATCH;
2672 cpu_reg.mips_view_base = 0x8000000;
2674 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2675 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2676 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2677 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2678 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2679 fw.start_addr = bce_TXP_b09FwStartAddr;
2681 fw.text_addr = bce_TXP_b09FwTextAddr;
2682 fw.text_len = bce_TXP_b09FwTextLen;
2684 fw.text = bce_TXP_b09FwText;
2686 fw.data_addr = bce_TXP_b09FwDataAddr;
2687 fw.data_len = bce_TXP_b09FwDataLen;
2689 fw.data = bce_TXP_b09FwData;
2691 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2692 fw.sbss_len = bce_TXP_b09FwSbssLen;
2694 fw.sbss = bce_TXP_b09FwSbss;
2696 fw.bss_addr = bce_TXP_b09FwBssAddr;
2697 fw.bss_len = bce_TXP_b09FwBssLen;
2699 fw.bss = bce_TXP_b09FwBss;
2701 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2702 fw.rodata_len = bce_TXP_b09FwRodataLen;
2703 fw.rodata_index = 0;
2704 fw.rodata = bce_TXP_b09FwRodata;
2706 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2707 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2708 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2709 fw.start_addr = bce_TXP_b06FwStartAddr;
2711 fw.text_addr = bce_TXP_b06FwTextAddr;
2712 fw.text_len = bce_TXP_b06FwTextLen;
2714 fw.text = bce_TXP_b06FwText;
2716 fw.data_addr = bce_TXP_b06FwDataAddr;
2717 fw.data_len = bce_TXP_b06FwDataLen;
2719 fw.data = bce_TXP_b06FwData;
2721 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2722 fw.sbss_len = bce_TXP_b06FwSbssLen;
2724 fw.sbss = bce_TXP_b06FwSbss;
2726 fw.bss_addr = bce_TXP_b06FwBssAddr;
2727 fw.bss_len = bce_TXP_b06FwBssLen;
2729 fw.bss = bce_TXP_b06FwBss;
2731 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2732 fw.rodata_len = bce_TXP_b06FwRodataLen;
2733 fw.rodata_index = 0;
2734 fw.rodata = bce_TXP_b06FwRodata;
2737 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2738 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2742 /****************************************************************************/
2743 /* Initialize the TPAT CPU. */
2747 /****************************************************************************/
2749 bce_init_tpat_cpu(struct bce_softc *sc)
2751 struct cpu_reg cpu_reg;
2754 cpu_reg.mode = BCE_TPAT_CPU_MODE;
2755 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2756 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2757 cpu_reg.state = BCE_TPAT_CPU_STATE;
2758 cpu_reg.state_value_clear = 0xffffff;
2759 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2760 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2761 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2762 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2763 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2764 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2765 cpu_reg.mips_view_base = 0x8000000;
2767 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2768 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2769 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2770 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2771 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2772 fw.start_addr = bce_TPAT_b09FwStartAddr;
2774 fw.text_addr = bce_TPAT_b09FwTextAddr;
2775 fw.text_len = bce_TPAT_b09FwTextLen;
2777 fw.text = bce_TPAT_b09FwText;
2779 fw.data_addr = bce_TPAT_b09FwDataAddr;
2780 fw.data_len = bce_TPAT_b09FwDataLen;
2782 fw.data = bce_TPAT_b09FwData;
2784 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2785 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2787 fw.sbss = bce_TPAT_b09FwSbss;
2789 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2790 fw.bss_len = bce_TPAT_b09FwBssLen;
2792 fw.bss = bce_TPAT_b09FwBss;
2794 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2795 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2796 fw.rodata_index = 0;
2797 fw.rodata = bce_TPAT_b09FwRodata;
2799 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2800 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2801 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2802 fw.start_addr = bce_TPAT_b06FwStartAddr;
2804 fw.text_addr = bce_TPAT_b06FwTextAddr;
2805 fw.text_len = bce_TPAT_b06FwTextLen;
2807 fw.text = bce_TPAT_b06FwText;
2809 fw.data_addr = bce_TPAT_b06FwDataAddr;
2810 fw.data_len = bce_TPAT_b06FwDataLen;
2812 fw.data = bce_TPAT_b06FwData;
2814 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2815 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2817 fw.sbss = bce_TPAT_b06FwSbss;
2819 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2820 fw.bss_len = bce_TPAT_b06FwBssLen;
2822 fw.bss = bce_TPAT_b06FwBss;
2824 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2825 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2826 fw.rodata_index = 0;
2827 fw.rodata = bce_TPAT_b06FwRodata;
2830 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2831 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2835 /****************************************************************************/
2836 /* Initialize the CP CPU. */
2840 /****************************************************************************/
2842 bce_init_cp_cpu(struct bce_softc *sc)
2844 struct cpu_reg cpu_reg;
2847 cpu_reg.mode = BCE_CP_CPU_MODE;
2848 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2849 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
2850 cpu_reg.state = BCE_CP_CPU_STATE;
2851 cpu_reg.state_value_clear = 0xffffff;
2852 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
2853 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
2854 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
2855 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
2856 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
2857 cpu_reg.spad_base = BCE_CP_SCRATCH;
2858 cpu_reg.mips_view_base = 0x8000000;
2860 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2861 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2862 fw.ver_major = bce_CP_b09FwReleaseMajor;
2863 fw.ver_minor = bce_CP_b09FwReleaseMinor;
2864 fw.ver_fix = bce_CP_b09FwReleaseFix;
2865 fw.start_addr = bce_CP_b09FwStartAddr;
2867 fw.text_addr = bce_CP_b09FwTextAddr;
2868 fw.text_len = bce_CP_b09FwTextLen;
2870 fw.text = bce_CP_b09FwText;
2872 fw.data_addr = bce_CP_b09FwDataAddr;
2873 fw.data_len = bce_CP_b09FwDataLen;
2875 fw.data = bce_CP_b09FwData;
2877 fw.sbss_addr = bce_CP_b09FwSbssAddr;
2878 fw.sbss_len = bce_CP_b09FwSbssLen;
2880 fw.sbss = bce_CP_b09FwSbss;
2882 fw.bss_addr = bce_CP_b09FwBssAddr;
2883 fw.bss_len = bce_CP_b09FwBssLen;
2885 fw.bss = bce_CP_b09FwBss;
2887 fw.rodata_addr = bce_CP_b09FwRodataAddr;
2888 fw.rodata_len = bce_CP_b09FwRodataLen;
2889 fw.rodata_index = 0;
2890 fw.rodata = bce_CP_b09FwRodata;
2892 fw.ver_major = bce_CP_b06FwReleaseMajor;
2893 fw.ver_minor = bce_CP_b06FwReleaseMinor;
2894 fw.ver_fix = bce_CP_b06FwReleaseFix;
2895 fw.start_addr = bce_CP_b06FwStartAddr;
2897 fw.text_addr = bce_CP_b06FwTextAddr;
2898 fw.text_len = bce_CP_b06FwTextLen;
2900 fw.text = bce_CP_b06FwText;
2902 fw.data_addr = bce_CP_b06FwDataAddr;
2903 fw.data_len = bce_CP_b06FwDataLen;
2905 fw.data = bce_CP_b06FwData;
2907 fw.sbss_addr = bce_CP_b06FwSbssAddr;
2908 fw.sbss_len = bce_CP_b06FwSbssLen;
2910 fw.sbss = bce_CP_b06FwSbss;
2912 fw.bss_addr = bce_CP_b06FwBssAddr;
2913 fw.bss_len = bce_CP_b06FwBssLen;
2915 fw.bss = bce_CP_b06FwBss;
2917 fw.rodata_addr = bce_CP_b06FwRodataAddr;
2918 fw.rodata_len = bce_CP_b06FwRodataLen;
2919 fw.rodata_index = 0;
2920 fw.rodata = bce_CP_b06FwRodata;
2923 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
2924 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2928 /****************************************************************************/
2929 /* Initialize the COM CPU. */
2933 /****************************************************************************/
2935 bce_init_com_cpu(struct bce_softc *sc)
2937 struct cpu_reg cpu_reg;
2940 cpu_reg.mode = BCE_COM_CPU_MODE;
2941 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
2942 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
2943 cpu_reg.state = BCE_COM_CPU_STATE;
2944 cpu_reg.state_value_clear = 0xffffff;
2945 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
2946 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
2947 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
2948 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
2949 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
2950 cpu_reg.spad_base = BCE_COM_SCRATCH;
2951 cpu_reg.mips_view_base = 0x8000000;
2953 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2954 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2955 fw.ver_major = bce_COM_b09FwReleaseMajor;
2956 fw.ver_minor = bce_COM_b09FwReleaseMinor;
2957 fw.ver_fix = bce_COM_b09FwReleaseFix;
2958 fw.start_addr = bce_COM_b09FwStartAddr;
2960 fw.text_addr = bce_COM_b09FwTextAddr;
2961 fw.text_len = bce_COM_b09FwTextLen;
2963 fw.text = bce_COM_b09FwText;
2965 fw.data_addr = bce_COM_b09FwDataAddr;
2966 fw.data_len = bce_COM_b09FwDataLen;
2968 fw.data = bce_COM_b09FwData;
2970 fw.sbss_addr = bce_COM_b09FwSbssAddr;
2971 fw.sbss_len = bce_COM_b09FwSbssLen;
2973 fw.sbss = bce_COM_b09FwSbss;
2975 fw.bss_addr = bce_COM_b09FwBssAddr;
2976 fw.bss_len = bce_COM_b09FwBssLen;
2978 fw.bss = bce_COM_b09FwBss;
2980 fw.rodata_addr = bce_COM_b09FwRodataAddr;
2981 fw.rodata_len = bce_COM_b09FwRodataLen;
2982 fw.rodata_index = 0;
2983 fw.rodata = bce_COM_b09FwRodata;
2985 fw.ver_major = bce_COM_b06FwReleaseMajor;
2986 fw.ver_minor = bce_COM_b06FwReleaseMinor;
2987 fw.ver_fix = bce_COM_b06FwReleaseFix;
2988 fw.start_addr = bce_COM_b06FwStartAddr;
2990 fw.text_addr = bce_COM_b06FwTextAddr;
2991 fw.text_len = bce_COM_b06FwTextLen;
2993 fw.text = bce_COM_b06FwText;
2995 fw.data_addr = bce_COM_b06FwDataAddr;
2996 fw.data_len = bce_COM_b06FwDataLen;
2998 fw.data = bce_COM_b06FwData;
3000 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3001 fw.sbss_len = bce_COM_b06FwSbssLen;
3003 fw.sbss = bce_COM_b06FwSbss;
3005 fw.bss_addr = bce_COM_b06FwBssAddr;
3006 fw.bss_len = bce_COM_b06FwBssLen;
3008 fw.bss = bce_COM_b06FwBss;
3010 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3011 fw.rodata_len = bce_COM_b06FwRodataLen;
3012 fw.rodata_index = 0;
3013 fw.rodata = bce_COM_b06FwRodata;
3016 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3017 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3021 /****************************************************************************/
3022 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
3024 /* Loads the firmware for each CPU and starts the CPU. */
3028 /****************************************************************************/
3030 bce_init_cpus(struct bce_softc *sc)
3032 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3033 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3034 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, sizeof(bce_xi_rv2p_proc1),
3036 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, sizeof(bce_xi_rv2p_proc2),
3039 bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1),
3041 bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2),
3045 bce_init_rxp_cpu(sc);
3046 bce_init_txp_cpu(sc);
3047 bce_init_tpat_cpu(sc);
3048 bce_init_com_cpu(sc);
3049 bce_init_cp_cpu(sc);
3053 /****************************************************************************/
3054 /* Initialize context memory. */
3056 /* Clears the memory associated with each Context ID (CID). */
3060 /****************************************************************************/
3062 bce_init_ctx(struct bce_softc *sc)
3064 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3065 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3066 /* DRC: Replace this constant value with a #define. */
3067 int i, retry_cnt = 10;
3071 * BCM5709 context memory may be cached
3072 * in host memory so prepare the host memory
3075 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3077 val |= (BCM_PAGE_BITS - 8) << 16;
3078 REG_WR(sc, BCE_CTX_COMMAND, val);
3080 /* Wait for mem init command to complete. */
3081 for (i = 0; i < retry_cnt; i++) {
3082 val = REG_RD(sc, BCE_CTX_COMMAND);
3083 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3088 for (i = 0; i < sc->ctx_pages; i++) {
3092 * Set the physical address of the context
3095 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3096 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3097 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3098 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3099 BCE_ADDR_HI(sc->ctx_paddr[i]));
3100 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3101 i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3104 * Verify that the context memory write was successful.
3106 for (j = 0; j < retry_cnt; j++) {
3107 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3109 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3115 uint32_t vcid_addr, offset;
3118 * For the 5706/5708, context memory is local to
3119 * the controller, so initialize the controller
3123 vcid_addr = GET_CID_ADDR(96);
3125 vcid_addr -= PHY_CTX_SIZE;
3127 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3128 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3130 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3131 CTX_WR(sc, 0x00, offset, 0);
3133 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3134 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3140 /****************************************************************************/
3141 /* Fetch the permanent MAC address of the controller. */
3145 /****************************************************************************/
3147 bce_get_mac_addr(struct bce_softc *sc)
3149 uint32_t mac_lo = 0, mac_hi = 0;
3152 * The NetXtreme II bootcode populates various NIC
3153 * power-on and runtime configuration items in a
3154 * shared memory area. The factory configured MAC
3155 * address is available from both NVRAM and the
3156 * shared memory area so we'll read the value from
3157 * shared memory for speed.
3160 mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_UPPER);
3161 mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_LOWER);
3163 if (mac_lo == 0 && mac_hi == 0) {
3164 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3166 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3167 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3168 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3169 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3170 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3171 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3174 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3178 /****************************************************************************/
3179 /* Program the MAC address. */
3183 /****************************************************************************/
3185 bce_set_mac_addr(struct bce_softc *sc)
3187 const uint8_t *mac_addr = sc->eaddr;
3190 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3193 val = (mac_addr[0] << 8) | mac_addr[1];
3194 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3196 val = (mac_addr[2] << 24) |
3197 (mac_addr[3] << 16) |
3198 (mac_addr[4] << 8) |
3200 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3204 /****************************************************************************/
3205 /* Stop the controller. */
3209 /****************************************************************************/
3211 bce_stop(struct bce_softc *sc)
3213 struct ifnet *ifp = &sc->arpcom.ac_if;
3214 struct mii_data *mii = device_get_softc(sc->bce_miibus);
3215 struct ifmedia_entry *ifm;
3218 ASSERT_SERIALIZED(ifp->if_serializer);
3220 callout_stop(&sc->bce_tick_callout);
3222 /* Disable the transmit/receive blocks. */
3223 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3224 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3227 bce_disable_intr(sc);
3229 /* Free the RX lists. */
3230 bce_free_rx_chain(sc);
3232 /* Free TX buffers. */
3233 bce_free_tx_chain(sc);
3236 * Isolate/power down the PHY, but leave the media selection
3237 * unchanged so that things will be put back to normal when
3238 * we bring the interface back up.
3240 * 'mii' may be NULL if bce_stop() is called by bce_detach().
3243 itmp = ifp->if_flags;
3244 ifp->if_flags |= IFF_UP;
3245 ifm = mii->mii_media.ifm_cur;
3246 mtmp = ifm->ifm_media;
3247 ifm->ifm_media = IFM_ETHER | IFM_NONE;
3249 ifm->ifm_media = mtmp;
3250 ifp->if_flags = itmp;
3254 sc->bce_coalchg_mask = 0;
3256 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3262 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3267 /* Wait for pending PCI transactions to complete. */
3268 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3269 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3270 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3271 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3272 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3273 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3277 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3278 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3279 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3280 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3281 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3284 /* Assume bootcode is running. */
3285 sc->bce_fw_timed_out = 0;
3287 /* Give the firmware a chance to prepare for the reset. */
3288 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3290 if_printf(&sc->arpcom.ac_if,
3291 "Firmware is not ready for reset\n");
3295 /* Set a firmware reminder that this is a soft reset. */
3296 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE,
3297 BCE_DRV_RESET_SIGNATURE_MAGIC);
3299 /* Dummy read to force the chip to complete all current transactions. */
3300 val = REG_RD(sc, BCE_MISC_ID);
3303 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3304 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3305 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3306 REG_RD(sc, BCE_MISC_COMMAND);
3309 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3310 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3312 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3314 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3315 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3316 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3317 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3319 /* Allow up to 30us for reset to complete. */
3320 for (i = 0; i < 10; i++) {
3321 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3322 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3323 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3328 /* Check that reset completed successfully. */
3329 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3330 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3331 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3336 /* Make sure byte swapping is properly configured. */
3337 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3338 if (val != 0x01020304) {
3339 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3343 /* Just completed a reset, assume that firmware is running again. */
3344 sc->bce_fw_timed_out = 0;
3346 /* Wait for the firmware to finish its initialization. */
3347 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3349 if_printf(&sc->arpcom.ac_if,
3350 "Firmware did not complete initialization!\n");
3357 bce_chipinit(struct bce_softc *sc)
3362 /* Make sure the interrupt is not active. */
3363 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3364 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3367 * Initialize DMA byte/word swapping, configure the number of DMA
3368 * channels and PCI clock compensation delay.
3370 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3371 BCE_DMA_CONFIG_DATA_WORD_SWAP |
3372 #if BYTE_ORDER == BIG_ENDIAN
3373 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3375 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3376 DMA_READ_CHANS << 12 |
3377 DMA_WRITE_CHANS << 16;
3379 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3381 if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3382 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3385 * This setting resolves a problem observed on certain Intel PCI
3386 * chipsets that cannot handle multiple outstanding DMA operations.
3387 * See errata E9_5706A1_65.
3389 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3390 BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3391 !(sc->bce_flags & BCE_PCIX_FLAG))
3392 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3394 REG_WR(sc, BCE_DMA_CONFIG, val);
3396 /* Enable the RX_V2P and Context state machines before access. */
3397 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3398 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3399 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3400 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3402 /* Initialize context mapping and zero out the quick contexts. */
3405 /* Initialize the on-boards CPUs */
3408 /* Prepare NVRAM for access. */
3409 rc = bce_init_nvram(sc);
3413 /* Set the kernel bypass block size */
3414 val = REG_RD(sc, BCE_MQ_CONFIG);
3415 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3416 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3418 /* Enable bins used on the 5709/5716. */
3419 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3420 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3421 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3422 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3423 val |= BCE_MQ_CONFIG_HALT_DIS;
3426 REG_WR(sc, BCE_MQ_CONFIG, val);
3428 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3429 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3430 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3432 /* Set the page size and clear the RV2P processor stall bits. */
3433 val = (BCM_PAGE_BITS - 8) << 24;
3434 REG_WR(sc, BCE_RV2P_CONFIG, val);
3436 /* Configure page size. */
3437 val = REG_RD(sc, BCE_TBDR_CONFIG);
3438 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3439 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3440 REG_WR(sc, BCE_TBDR_CONFIG, val);
3442 /* Set the perfect match control register to default. */
3443 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3449 /****************************************************************************/
3450 /* Initialize the controller in preparation to send/receive traffic. */
3453 /* 0 for success, positive value for failure. */
3454 /****************************************************************************/
3456 bce_blockinit(struct bce_softc *sc)
3461 /* Load the hardware default MAC address. */
3462 bce_set_mac_addr(sc);
3464 /* Set the Ethernet backoff seed value */
3465 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3466 sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3467 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3469 sc->last_status_idx = 0;
3470 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3472 /* Set up link change interrupt generation. */
3473 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3475 /* Program the physical address of the status block. */
3476 REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3477 REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3479 /* Program the physical address of the statistics block. */
3480 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3481 BCE_ADDR_LO(sc->stats_block_paddr));
3482 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3483 BCE_ADDR_HI(sc->stats_block_paddr));
3485 /* Program various host coalescing parameters. */
3486 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3487 (sc->bce_tx_quick_cons_trip_int << 16) |
3488 sc->bce_tx_quick_cons_trip);
3489 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3490 (sc->bce_rx_quick_cons_trip_int << 16) |
3491 sc->bce_rx_quick_cons_trip);
3492 REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3493 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3494 REG_WR(sc, BCE_HC_TX_TICKS,
3495 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3496 REG_WR(sc, BCE_HC_RX_TICKS,
3497 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3498 REG_WR(sc, BCE_HC_COM_TICKS,
3499 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3500 REG_WR(sc, BCE_HC_CMD_TICKS,
3501 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3502 REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3503 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3504 REG_WR(sc, BCE_HC_CONFIG,
3505 BCE_HC_CONFIG_TX_TMR_MODE |
3506 BCE_HC_CONFIG_COLLECT_STATS);
3508 /* Clear the internal statistics counters. */
3509 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3511 /* Verify that bootcode is running. */
3512 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
3514 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3515 if_printf(&sc->arpcom.ac_if,
3516 "%s(%d): Simulating bootcode failure.\n",
3517 __FILE__, __LINE__);
3520 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3521 BCE_DEV_INFO_SIGNATURE_MAGIC) {
3522 if_printf(&sc->arpcom.ac_if,
3523 "Bootcode not running! Found: 0x%08X, "
3524 "Expected: 08%08X\n",
3525 reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3526 BCE_DEV_INFO_SIGNATURE_MAGIC);
3531 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3532 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3533 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3534 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3535 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3538 /* Allow bootcode to apply any additional fixes before enabling MAC. */
3539 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3541 /* Enable link state change interrupt generation. */
3542 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3544 /* Enable all remaining blocks in the MAC. */
3545 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3546 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3547 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3548 BCE_MISC_ENABLE_DEFAULT_XI);
3550 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3552 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3555 /* Save the current host coalescing block settings. */
3556 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3562 /****************************************************************************/
3563 /* Encapsulate an mbuf cluster into the rx_bd chain. */
3565 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */
3566 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */
3570 /* 0 for success, positive value for failure. */
3571 /****************************************************************************/
3573 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3574 uint32_t *prod_bseq, int init)
3577 bus_dma_segment_t seg;
3581 uint16_t debug_chain_prod = *chain_prod;
3584 /* Make sure the inputs are valid. */
3585 DBRUNIF((*chain_prod > MAX_RX_BD),
3586 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3587 "RX producer out of range: 0x%04X > 0x%04X\n",
3589 *chain_prod, (uint16_t)MAX_RX_BD));
3591 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3592 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3594 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3595 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3596 "Simulating mbuf allocation failure.\n",
3597 __FILE__, __LINE__);
3598 sc->mbuf_alloc_failed++;
3601 /* This is a new mbuf allocation. */
3602 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3605 DBRUNIF(1, sc->rx_mbuf_alloc++);
3607 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3609 /* Map the mbuf cluster into device memory. */
3610 error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3611 sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3616 if_printf(&sc->arpcom.ac_if,
3617 "Error mapping mbuf into RX chain!\n");
3619 DBRUNIF(1, sc->rx_mbuf_alloc--);
3623 if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3624 bus_dmamap_unload(sc->rx_mbuf_tag,
3625 sc->rx_mbuf_map[*chain_prod]);
3628 map = sc->rx_mbuf_map[*chain_prod];
3629 sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3630 sc->rx_mbuf_tmpmap = map;
3632 /* Watch for overflow. */
3633 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3634 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3635 "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3636 __FILE__, __LINE__, sc->free_rx_bd,
3637 (uint16_t)USABLE_RX_BD));
3639 /* Update some debug statistic counters */
3640 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3641 sc->rx_low_watermark = sc->free_rx_bd);
3642 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3644 /* Save the mbuf and update our counter. */
3645 sc->rx_mbuf_ptr[*chain_prod] = m_new;
3646 sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3649 bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3651 DBRUN(BCE_VERBOSE_RECV,
3652 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3654 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3655 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3662 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3668 paddr = sc->rx_mbuf_paddr[chain_prod];
3669 len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3671 /* Setup the rx_bd for the first segment. */
3672 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3674 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3675 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3676 rxbd->rx_bd_len = htole32(len);
3677 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3680 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3684 /****************************************************************************/
3685 /* Initialize the TX context memory. */
3689 /****************************************************************************/
3691 bce_init_tx_context(struct bce_softc *sc)
3695 /* Initialize the context ID for an L2 TX chain. */
3696 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3697 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3698 /* Set the CID type to support an L2 connection. */
3699 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3700 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3701 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3702 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3704 /* Point the hardware to the first page in the chain. */
3705 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3706 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3707 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3708 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3709 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3710 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3712 /* Set the CID type to support an L2 connection. */
3713 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3714 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3715 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3716 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3718 /* Point the hardware to the first page in the chain. */
3719 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3720 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3721 BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3722 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3723 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3724 BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3729 /****************************************************************************/
3730 /* Allocate memory and initialize the TX data structures. */
3733 /* 0 for success, positive value for failure. */
3734 /****************************************************************************/
3736 bce_init_tx_chain(struct bce_softc *sc)
3741 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3743 /* Set the initial TX producer/consumer indices. */
3746 sc->tx_prod_bseq = 0;
3748 sc->max_tx_bd = USABLE_TX_BD;
3749 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3750 DBRUNIF(1, sc->tx_full_count = 0);
3753 * The NetXtreme II supports a linked-list structre called
3754 * a Buffer Descriptor Chain (or BD chain). A BD chain
3755 * consists of a series of 1 or more chain pages, each of which
3756 * consists of a fixed number of BD entries.
3757 * The last BD entry on each page is a pointer to the next page
3758 * in the chain, and the last pointer in the BD chain
3759 * points back to the beginning of the chain.
3762 /* Set the TX next pointer chain entries. */
3763 for (i = 0; i < TX_PAGES; i++) {
3766 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3768 /* Check if we've reached the last page. */
3769 if (i == (TX_PAGES - 1))
3774 txbd->tx_bd_haddr_hi =
3775 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3776 txbd->tx_bd_haddr_lo =
3777 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3779 bce_init_tx_context(sc);
3785 /****************************************************************************/
3786 /* Free memory and clear the TX data structures. */
3790 /****************************************************************************/
3792 bce_free_tx_chain(struct bce_softc *sc)
3796 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3798 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3799 for (i = 0; i < TOTAL_TX_BD; i++) {
3800 if (sc->tx_mbuf_ptr[i] != NULL) {
3801 bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3802 m_freem(sc->tx_mbuf_ptr[i]);
3803 sc->tx_mbuf_ptr[i] = NULL;
3804 DBRUNIF(1, sc->tx_mbuf_alloc--);
3808 /* Clear each TX chain page. */
3809 for (i = 0; i < TX_PAGES; i++)
3810 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3813 /* Check if we lost any mbufs in the process. */
3814 DBRUNIF((sc->tx_mbuf_alloc),
3815 if_printf(&sc->arpcom.ac_if,
3816 "%s(%d): Memory leak! "
3817 "Lost %d mbufs from tx chain!\n",
3818 __FILE__, __LINE__, sc->tx_mbuf_alloc));
3820 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3824 /****************************************************************************/
3825 /* Initialize the RX context memory. */
3829 /****************************************************************************/
3831 bce_init_rx_context(struct bce_softc *sc)
3835 /* Initialize the context ID for an L2 RX chain. */
3836 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
3837 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
3840 * Set the level for generating pause frames
3841 * when the number of available rx_bd's gets
3842 * too low (the low watermark) and the level
3843 * when pause frames can be stopped (the high
3846 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3847 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3848 uint32_t lo_water, hi_water;
3850 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
3851 hi_water = USABLE_RX_BD / 4;
3853 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
3854 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
3858 else if (hi_water == 0)
3861 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
3864 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
3866 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
3867 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3868 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3869 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
3870 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
3873 /* Point the hardware to the first page in the chain. */
3874 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
3875 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
3876 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
3877 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
3881 /****************************************************************************/
3882 /* Allocate memory and initialize the RX data structures. */
3885 /* 0 for success, positive value for failure. */
3886 /****************************************************************************/
3888 bce_init_rx_chain(struct bce_softc *sc)
3892 uint16_t prod, chain_prod;
3895 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3897 /* Initialize the RX producer and consumer indices. */
3900 sc->rx_prod_bseq = 0;
3901 sc->free_rx_bd = USABLE_RX_BD;
3902 sc->max_rx_bd = USABLE_RX_BD;
3903 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
3904 DBRUNIF(1, sc->rx_empty_count = 0);
3906 /* Initialize the RX next pointer chain entries. */
3907 for (i = 0; i < RX_PAGES; i++) {
3910 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
3912 /* Check if we've reached the last page. */
3913 if (i == (RX_PAGES - 1))
3918 /* Setup the chain page pointers. */
3919 rxbd->rx_bd_haddr_hi =
3920 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
3921 rxbd->rx_bd_haddr_lo =
3922 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
3925 /* Allocate mbuf clusters for the rx_bd chain. */
3926 prod = prod_bseq = 0;
3927 while (prod < TOTAL_RX_BD) {
3928 chain_prod = RX_CHAIN_IDX(prod);
3929 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
3930 if_printf(&sc->arpcom.ac_if,
3931 "Error filling RX chain: rx_bd[0x%04X]!\n",
3936 prod = NEXT_RX_BD(prod);
3939 /* Save the RX chain producer index. */
3941 sc->rx_prod_bseq = prod_bseq;
3943 /* Tell the chip about the waiting rx_bd's. */
3944 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
3946 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
3949 bce_init_rx_context(sc);
3955 /****************************************************************************/
3956 /* Free memory and clear the RX data structures. */
3960 /****************************************************************************/
3962 bce_free_rx_chain(struct bce_softc *sc)
3966 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3968 /* Free any mbufs still in the RX mbuf chain. */
3969 for (i = 0; i < TOTAL_RX_BD; i++) {
3970 if (sc->rx_mbuf_ptr[i] != NULL) {
3971 bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
3972 m_freem(sc->rx_mbuf_ptr[i]);
3973 sc->rx_mbuf_ptr[i] = NULL;
3974 DBRUNIF(1, sc->rx_mbuf_alloc--);
3978 /* Clear each RX chain page. */
3979 for (i = 0; i < RX_PAGES; i++)
3980 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
3982 /* Check if we lost any mbufs in the process. */
3983 DBRUNIF((sc->rx_mbuf_alloc),
3984 if_printf(&sc->arpcom.ac_if,
3985 "%s(%d): Memory leak! "
3986 "Lost %d mbufs from rx chain!\n",
3987 __FILE__, __LINE__, sc->rx_mbuf_alloc));
3989 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3993 /****************************************************************************/
3994 /* Set media options. */
3997 /* 0 for success, positive value for failure. */
3998 /****************************************************************************/
4000 bce_ifmedia_upd(struct ifnet *ifp)
4002 struct bce_softc *sc = ifp->if_softc;
4003 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4006 * 'mii' will be NULL, when this function is called on following
4007 * code path: bce_attach() -> bce_mgmt_init()
4010 /* Make sure the MII bus has been enumerated. */
4012 if (mii->mii_instance) {
4013 struct mii_softc *miisc;
4015 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4016 mii_phy_reset(miisc);
4024 /****************************************************************************/
4025 /* Reports current media status. */
4029 /****************************************************************************/
4031 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4033 struct bce_softc *sc = ifp->if_softc;
4034 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4037 ifmr->ifm_active = mii->mii_media_active;
4038 ifmr->ifm_status = mii->mii_media_status;
4042 /****************************************************************************/
4043 /* Handles PHY generated interrupt events. */
4047 /****************************************************************************/
4049 bce_phy_intr(struct bce_softc *sc)
4051 uint32_t new_link_state, old_link_state;
4052 struct ifnet *ifp = &sc->arpcom.ac_if;
4054 ASSERT_SERIALIZED(ifp->if_serializer);
4056 new_link_state = sc->status_block->status_attn_bits &
4057 STATUS_ATTN_BITS_LINK_STATE;
4058 old_link_state = sc->status_block->status_attn_bits_ack &
4059 STATUS_ATTN_BITS_LINK_STATE;
4061 /* Handle any changes if the link state has changed. */
4062 if (new_link_state != old_link_state) { /* XXX redundant? */
4063 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4065 /* Update the status_attn_bits_ack field in the status block. */
4066 if (new_link_state) {
4067 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4068 STATUS_ATTN_BITS_LINK_STATE);
4070 if_printf(ifp, "Link is now UP.\n");
4072 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4073 STATUS_ATTN_BITS_LINK_STATE);
4075 if_printf(ifp, "Link is now DOWN.\n");
4079 * Assume link is down and allow tick routine to
4080 * update the state based on the actual media state.
4083 callout_stop(&sc->bce_tick_callout);
4084 bce_tick_serialized(sc);
4087 /* Acknowledge the link change interrupt. */
4088 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4092 /****************************************************************************/
4093 /* Reads the receive consumer value from the status block (skipping over */
4094 /* chain page pointer if necessary). */
4098 /****************************************************************************/
4099 static __inline uint16_t
4100 bce_get_hw_rx_cons(struct bce_softc *sc)
4102 uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4104 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4110 /****************************************************************************/
4111 /* Handles received frame interrupt events. */
4115 /****************************************************************************/
4117 bce_rx_intr(struct bce_softc *sc, int count)
4119 struct ifnet *ifp = &sc->arpcom.ac_if;
4120 uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4121 uint32_t sw_prod_bseq;
4122 struct mbuf_chain chain[MAXCPU];
4124 ASSERT_SERIALIZED(ifp->if_serializer);
4126 ether_input_chain_init(chain);
4128 DBRUNIF(1, sc->rx_interrupts++);
4130 /* Get the hardware's view of the RX consumer index. */
4131 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4133 /* Get working copies of the driver's view of the RX indices. */
4134 sw_cons = sc->rx_cons;
4135 sw_prod = sc->rx_prod;
4136 sw_prod_bseq = sc->rx_prod_bseq;
4138 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
4139 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
4140 __func__, sw_prod, sw_cons, sw_prod_bseq);
4142 /* Prevent speculative reads from getting ahead of the status block. */
4143 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4144 BUS_SPACE_BARRIER_READ);
4146 /* Update some debug statistics counters */
4147 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4148 sc->rx_low_watermark = sc->free_rx_bd);
4149 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
4151 /* Scan through the receive chain as long as there is work to do. */
4152 while (sw_cons != hw_cons) {
4153 struct mbuf *m = NULL;
4154 struct l2_fhdr *l2fhdr = NULL;
4157 uint32_t status = 0;
4159 #ifdef DEVICE_POLLING
4160 if (count >= 0 && count-- == 0) {
4161 sc->hw_rx_cons = sw_cons;
4167 * Convert the producer/consumer indices
4168 * to an actual rx_bd index.
4170 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
4171 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
4173 /* Get the used rx_bd. */
4174 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4175 [RX_IDX(sw_chain_cons)];
4178 DBRUN(BCE_VERBOSE_RECV,
4179 if_printf(ifp, "%s(): ", __func__);
4180 bce_dump_rxbd(sc, sw_chain_cons, rxbd));
4182 /* The mbuf is stored with the last rx_bd entry of a packet. */
4183 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4184 /* Validate that this is the last rx_bd. */
4185 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
4186 if_printf(ifp, "%s(%d): "
4187 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
4188 __FILE__, __LINE__, sw_chain_cons);
4189 bce_breakpoint(sc));
4191 if (sw_chain_cons != sw_chain_prod) {
4192 if_printf(ifp, "RX cons(%d) != prod(%d), "
4193 "drop!\n", sw_chain_cons,
4197 bce_setup_rxdesc_std(sc, sw_chain_cons,
4200 goto bce_rx_int_next_rx;
4203 /* Unmap the mbuf from DMA space. */
4204 bus_dmamap_sync(sc->rx_mbuf_tag,
4205 sc->rx_mbuf_map[sw_chain_cons],
4206 BUS_DMASYNC_POSTREAD);
4208 /* Save the mbuf from the driver's chain. */
4209 m = sc->rx_mbuf_ptr[sw_chain_cons];
4212 * Frames received on the NetXteme II are prepended
4213 * with an l2_fhdr structure which provides status
4214 * information about the received frame (including
4215 * VLAN tags and checksum info). The frames are also
4216 * automatically adjusted to align the IP header
4217 * (i.e. two null bytes are inserted before the
4220 l2fhdr = mtod(m, struct l2_fhdr *);
4222 len = l2fhdr->l2_fhdr_pkt_len;
4223 status = l2fhdr->l2_fhdr_status;
4225 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4227 "Simulating l2_fhdr status error.\n");
4228 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4230 /* Watch for unusual sized frames. */
4231 DBRUNIF((len < BCE_MIN_MTU ||
4232 len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
4234 "%s(%d): Unusual frame size found. "
4235 "Min(%d), Actual(%d), Max(%d)\n",
4237 (int)BCE_MIN_MTU, len,
4238 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
4239 bce_dump_mbuf(sc, m);
4240 bce_breakpoint(sc));
4242 len -= ETHER_CRC_LEN;
4244 /* Check the received frame for errors. */
4245 if (status & (L2_FHDR_ERRORS_BAD_CRC |
4246 L2_FHDR_ERRORS_PHY_DECODE |
4247 L2_FHDR_ERRORS_ALIGNMENT |
4248 L2_FHDR_ERRORS_TOO_SHORT |
4249 L2_FHDR_ERRORS_GIANT_FRAME)) {
4251 DBRUNIF(1, sc->l2fhdr_status_errors++);
4253 /* Reuse the mbuf for a new frame. */
4254 bce_setup_rxdesc_std(sc, sw_chain_prod,
4257 goto bce_rx_int_next_rx;
4261 * Get a new mbuf for the rx_bd. If no new
4262 * mbufs are available then reuse the current mbuf,
4263 * log an ierror on the interface, and generate
4264 * an error in the system log.
4266 if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4267 &sw_prod_bseq, 0)) {
4270 "%s(%d): Failed to allocate new mbuf, "
4271 "incoming frame dropped!\n",
4272 __FILE__, __LINE__));
4276 /* Try and reuse the exisitng mbuf. */
4277 bce_setup_rxdesc_std(sc, sw_chain_prod,
4280 goto bce_rx_int_next_rx;
4284 * Skip over the l2_fhdr when passing
4285 * the data up the stack.
4287 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4289 m->m_pkthdr.len = m->m_len = len;
4290 m->m_pkthdr.rcvif = ifp;
4292 DBRUN(BCE_VERBOSE_RECV,
4293 struct ether_header *eh;
4294 eh = mtod(m, struct ether_header *);
4295 if_printf(ifp, "%s(): to: %6D, from: %6D, "
4296 "type: 0x%04X\n", __func__,
4297 eh->ether_dhost, ":",
4298 eh->ether_shost, ":",
4299 htons(eh->ether_type)));
4301 /* Validate the checksum if offload enabled. */
4302 if (ifp->if_capenable & IFCAP_RXCSUM) {
4303 /* Check for an IP datagram. */
4304 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4305 m->m_pkthdr.csum_flags |=
4308 /* Check if the IP checksum is valid. */
4309 if ((l2fhdr->l2_fhdr_ip_xsum ^
4311 m->m_pkthdr.csum_flags |=
4314 DBPRINT(sc, BCE_WARN_RECV,
4315 "%s(): Invalid IP checksum = 0x%04X!\n",
4316 __func__, l2fhdr->l2_fhdr_ip_xsum);
4320 /* Check for a valid TCP/UDP frame. */
4321 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4322 L2_FHDR_STATUS_UDP_DATAGRAM)) {
4324 /* Check for a good TCP/UDP checksum. */
4326 (L2_FHDR_ERRORS_TCP_XSUM |
4327 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4328 m->m_pkthdr.csum_data =
4329 l2fhdr->l2_fhdr_tcp_udp_xsum;
4330 m->m_pkthdr.csum_flags |=
4334 DBPRINT(sc, BCE_WARN_RECV,
4335 "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
4336 __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
4343 sw_prod = NEXT_RX_BD(sw_prod);
4346 sw_cons = NEXT_RX_BD(sw_cons);
4348 /* If we have a packet, pass it up the stack */
4350 DBPRINT(sc, BCE_VERBOSE_RECV,
4351 "%s(): Passing received frame up.\n", __func__);
4353 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4354 m->m_flags |= M_VLANTAG;
4355 m->m_pkthdr.ether_vlantag =
4356 l2fhdr->l2_fhdr_vlan_tag;
4358 ether_input_chain(ifp, m, NULL, chain);
4360 DBRUNIF(1, sc->rx_mbuf_alloc--);
4364 * If polling(4) is not enabled, refresh hw_cons to see
4365 * whether there's new work.
4367 * If polling(4) is enabled, i.e count >= 0, refreshing
4368 * should not be performed, so that we would not spend
4369 * too much time in RX processing.
4371 if (count < 0 && sw_cons == hw_cons)
4372 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4375 * Prevent speculative reads from getting ahead
4376 * of the status block.
4378 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4379 BUS_SPACE_BARRIER_READ);
4382 ether_input_dispatch(chain);
4384 sc->rx_cons = sw_cons;
4385 sc->rx_prod = sw_prod;
4386 sc->rx_prod_bseq = sw_prod_bseq;
4388 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4390 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4393 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4394 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4395 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4399 /****************************************************************************/
4400 /* Reads the transmit consumer value from the status block (skipping over */
4401 /* chain page pointer if necessary). */
4405 /****************************************************************************/
4406 static __inline uint16_t
4407 bce_get_hw_tx_cons(struct bce_softc *sc)
4409 uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4411 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4417 /****************************************************************************/
4418 /* Handles transmit completion interrupt events. */
4422 /****************************************************************************/
4424 bce_tx_intr(struct bce_softc *sc)
4426 struct ifnet *ifp = &sc->arpcom.ac_if;
4427 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4429 ASSERT_SERIALIZED(ifp->if_serializer);
4431 DBRUNIF(1, sc->tx_interrupts++);
4433 /* Get the hardware's view of the TX consumer index. */
4434 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4435 sw_tx_cons = sc->tx_cons;
4437 /* Prevent speculative reads from getting ahead of the status block. */
4438 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4439 BUS_SPACE_BARRIER_READ);
4441 /* Cycle through any completed TX chain page entries. */
4442 while (sw_tx_cons != hw_tx_cons) {
4444 struct tx_bd *txbd = NULL;
4446 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4448 DBPRINT(sc, BCE_INFO_SEND,
4449 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4450 "sw_tx_chain_cons = 0x%04X\n",
4451 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4453 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4454 if_printf(ifp, "%s(%d): "
4455 "TX chain consumer out of range! "
4456 " 0x%04X > 0x%04X\n",
4457 __FILE__, __LINE__, sw_tx_chain_cons,
4459 bce_breakpoint(sc));
4461 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4462 [TX_IDX(sw_tx_chain_cons)]);
4464 DBRUNIF((txbd == NULL),
4465 if_printf(ifp, "%s(%d): "
4466 "Unexpected NULL tx_bd[0x%04X]!\n",
4467 __FILE__, __LINE__, sw_tx_chain_cons);
4468 bce_breakpoint(sc));
4470 DBRUN(BCE_INFO_SEND,
4471 if_printf(ifp, "%s(): ", __func__);
4472 bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4475 * Free the associated mbuf. Remember
4476 * that only the last tx_bd of a packet
4477 * has an mbuf pointer and DMA map.
4479 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4480 /* Validate that this is the last tx_bd. */
4481 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4482 if_printf(ifp, "%s(%d): "
4483 "tx_bd END flag not set but "
4484 "txmbuf == NULL!\n", __FILE__, __LINE__);
4485 bce_breakpoint(sc));
4487 DBRUN(BCE_INFO_SEND,
4488 if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4489 "from tx_bd[0x%04X]\n", __func__,
4492 /* Unmap the mbuf. */
4493 bus_dmamap_unload(sc->tx_mbuf_tag,
4494 sc->tx_mbuf_map[sw_tx_chain_cons]);
4496 /* Free the mbuf. */
4497 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4498 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4499 DBRUNIF(1, sc->tx_mbuf_alloc--);
4505 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4507 if (sw_tx_cons == hw_tx_cons) {
4508 /* Refresh hw_cons to see if there's new work. */
4509 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4513 * Prevent speculative reads from getting
4514 * ahead of the status block.
4516 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4517 BUS_SPACE_BARRIER_READ);
4520 if (sc->used_tx_bd == 0) {
4521 /* Clear the TX timeout timer. */
4525 /* Clear the tx hardware queue full flag. */
4526 if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4527 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4528 DBPRINT(sc, BCE_WARN_SEND,
4529 "%s(): Open TX chain! %d/%d (used/total)\n",
4530 __func__, sc->used_tx_bd, sc->max_tx_bd));
4531 ifp->if_flags &= ~IFF_OACTIVE;
4533 sc->tx_cons = sw_tx_cons;
4537 /****************************************************************************/
4538 /* Disables interrupt generation. */
4542 /****************************************************************************/
4544 bce_disable_intr(struct bce_softc *sc)
4546 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4547 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4548 lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4552 /****************************************************************************/
4553 /* Enables interrupt generation. */
4557 /****************************************************************************/
4559 bce_enable_intr(struct bce_softc *sc, int coal_now)
4561 lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4563 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4564 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4565 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4567 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4568 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4571 REG_WR(sc, BCE_HC_COMMAND,
4572 sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4577 /****************************************************************************/
4578 /* Handles controller initialization. */
4582 /****************************************************************************/
4586 struct bce_softc *sc = xsc;
4587 struct ifnet *ifp = &sc->arpcom.ac_if;
4591 ASSERT_SERIALIZED(ifp->if_serializer);
4593 /* Check if the driver is still running and bail out if it is. */
4594 if (ifp->if_flags & IFF_RUNNING)
4599 error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4601 if_printf(ifp, "Controller reset failed!\n");
4605 error = bce_chipinit(sc);
4607 if_printf(ifp, "Controller initialization failed!\n");
4611 error = bce_blockinit(sc);
4613 if_printf(ifp, "Block initialization failed!\n");
4617 /* Load our MAC address. */
4618 bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4619 bce_set_mac_addr(sc);
4621 /* Calculate and program the Ethernet MTU size. */
4622 ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4624 DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4627 * Program the mtu, enabling jumbo frame
4628 * support if necessary. Also set the mbuf
4629 * allocation count for RX frames.
4631 if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4633 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4634 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4635 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4636 sc->mbuf_alloc_size = MJUM9BYTES;
4638 panic("jumbo buffer is not supported yet\n");
4641 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4642 sc->mbuf_alloc_size = MCLBYTES;
4645 /* Calculate the RX Ethernet frame size for rx_bd's. */
4646 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4648 DBPRINT(sc, BCE_INFO,
4649 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4650 "max_frame_size = %d\n",
4651 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4652 sc->max_frame_size);
4654 /* Program appropriate promiscuous/multicast filtering. */
4655 bce_set_rx_mode(sc);
4657 /* Init RX buffer descriptor chain. */
4658 bce_init_rx_chain(sc); /* XXX return value */
4660 /* Init TX buffer descriptor chain. */
4661 bce_init_tx_chain(sc); /* XXX return value */
4663 #ifdef DEVICE_POLLING
4664 /* Disable interrupts if we are polling. */
4665 if (ifp->if_flags & IFF_POLLING) {
4666 bce_disable_intr(sc);
4668 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4669 (1 << 16) | sc->bce_rx_quick_cons_trip);
4670 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4671 (1 << 16) | sc->bce_tx_quick_cons_trip);
4674 /* Enable host interrupts. */
4675 bce_enable_intr(sc, 1);
4677 bce_ifmedia_upd(ifp);
4679 ifp->if_flags |= IFF_RUNNING;
4680 ifp->if_flags &= ~IFF_OACTIVE;
4682 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4689 /****************************************************************************/
4690 /* Initialize the controller just enough so that any management firmware */
4691 /* running on the device will continue to operate corectly. */
4695 /****************************************************************************/
4697 bce_mgmt_init(struct bce_softc *sc)
4699 struct ifnet *ifp = &sc->arpcom.ac_if;
4701 /* Bail out if management firmware is not running. */
4702 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4705 /* Enable all critical blocks in the MAC. */
4706 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4707 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4708 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4709 BCE_MISC_ENABLE_DEFAULT_XI);
4711 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4713 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4716 bce_ifmedia_upd(ifp);
4720 /****************************************************************************/
4721 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4722 /* memory visible to the controller. */
4725 /* 0 for success, positive value for failure. */
4726 /****************************************************************************/
4728 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4730 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4731 bus_dmamap_t map, tmp_map;
4732 struct mbuf *m0 = *m_head;
4733 struct tx_bd *txbd = NULL;
4734 uint16_t vlan_tag = 0, flags = 0;
4735 uint16_t chain_prod, chain_prod_start, prod;
4737 int i, error, maxsegs, nsegs;
4739 uint16_t debug_prod;
4742 /* Transfer any checksum offload flags to the bd. */
4743 if (m0->m_pkthdr.csum_flags) {
4744 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4745 flags |= TX_BD_FLAGS_IP_CKSUM;
4746 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4747 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4750 /* Transfer any VLAN tags to the bd. */
4751 if (m0->m_flags & M_VLANTAG) {
4752 flags |= TX_BD_FLAGS_VLAN_TAG;
4753 vlan_tag = m0->m_pkthdr.ether_vlantag;
4757 chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4759 /* Map the mbuf into DMAable memory. */
4760 map = sc->tx_mbuf_map[chain_prod_start];
4762 maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4763 KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4764 ("not enough segements %d\n", maxsegs));
4765 if (maxsegs > BCE_MAX_SEGMENTS)
4766 maxsegs = BCE_MAX_SEGMENTS;
4768 /* Map the mbuf into our DMA address space. */
4769 error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4770 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4773 bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4778 /* prod points to an empty tx_bd at this point. */
4779 prod_bseq = sc->tx_prod_bseq;
4782 debug_prod = chain_prod;
4785 DBPRINT(sc, BCE_INFO_SEND,
4786 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4787 "prod_bseq = 0x%08X\n",
4788 __func__, prod, chain_prod, prod_bseq);
4791 * Cycle through each mbuf segment that makes up
4792 * the outgoing frame, gathering the mapping info
4793 * for that segment and creating a tx_bd to for
4796 for (i = 0; i < nsegs; i++) {
4797 chain_prod = TX_CHAIN_IDX(prod);
4798 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4800 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4801 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4802 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4803 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4804 txbd->tx_bd_flags = htole16(flags);
4805 prod_bseq += segs[i].ds_len;
4807 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4808 prod = NEXT_TX_BD(prod);
4811 /* Set the END flag on the last TX buffer descriptor. */
4812 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4814 DBRUN(BCE_EXCESSIVE_SEND,
4815 bce_dump_tx_chain(sc, debug_prod, nsegs));
4817 DBPRINT(sc, BCE_INFO_SEND,
4818 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4819 "prod_bseq = 0x%08X\n",
4820 __func__, prod, chain_prod, prod_bseq);
4823 * Ensure that the mbuf pointer for this transmission
4824 * is placed at the array index of the last
4825 * descriptor in this chain. This is done
4826 * because a single map is used for all
4827 * segments of the mbuf and we don't want to
4828 * unload the map before all of the segments
4831 sc->tx_mbuf_ptr[chain_prod] = m0;
4833 tmp_map = sc->tx_mbuf_map[chain_prod];
4834 sc->tx_mbuf_map[chain_prod] = map;
4835 sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4837 sc->used_tx_bd += nsegs;
4839 /* Update some debug statistic counters */
4840 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
4841 sc->tx_hi_watermark = sc->used_tx_bd);
4842 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
4843 DBRUNIF(1, sc->tx_mbuf_alloc++);
4845 DBRUN(BCE_VERBOSE_SEND,
4846 bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
4848 /* prod points to the next free tx_bd at this point. */
4850 sc->tx_prod_bseq = prod_bseq;
4860 /****************************************************************************/
4861 /* Main transmit routine when called from another routine with a lock. */
4865 /****************************************************************************/
4867 bce_start(struct ifnet *ifp)
4869 struct bce_softc *sc = ifp->if_softc;
4872 ASSERT_SERIALIZED(ifp->if_serializer);
4874 /* If there's no link or the transmit queue is empty then just exit. */
4875 if (!sc->bce_link) {
4876 ifq_purge(&ifp->if_snd);
4880 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
4883 DBPRINT(sc, BCE_INFO_SEND,
4884 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
4885 "tx_prod_bseq = 0x%08X\n",
4887 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4890 struct mbuf *m_head;
4893 * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
4896 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
4897 ifp->if_flags |= IFF_OACTIVE;
4901 /* Check for any frames to send. */
4902 m_head = ifq_dequeue(&ifp->if_snd, NULL);
4907 * Pack the data into the transmit ring. If we
4908 * don't have room, place the mbuf back at the
4909 * head of the queue and set the OACTIVE flag
4910 * to wait for the NIC to drain the chain.
4912 if (bce_encap(sc, &m_head)) {
4914 if (sc->used_tx_bd == 0) {
4917 ifp->if_flags |= IFF_OACTIVE;
4924 /* Send a copy of the frame to any BPF listeners. */
4925 ETHER_BPF_MTAP(ifp, m_head);
4929 /* no packets were dequeued */
4930 DBPRINT(sc, BCE_VERBOSE_SEND,
4931 "%s(): No packets were dequeued\n", __func__);
4935 DBPRINT(sc, BCE_INFO_SEND,
4936 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
4937 "tx_prod_bseq = 0x%08X\n",
4939 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4941 REG_WR(sc, BCE_MQ_COMMAND,
4942 REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
4944 /* Start the transmit. */
4945 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
4946 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
4948 /* Set the tx timeout. */
4949 ifp->if_timer = BCE_TX_TIMEOUT;
4953 /****************************************************************************/
4954 /* Handles any IOCTL calls from the operating system. */
4957 /* 0 for success, positive value for failure. */
4958 /****************************************************************************/
4960 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
4962 struct bce_softc *sc = ifp->if_softc;
4963 struct ifreq *ifr = (struct ifreq *)data;
4964 struct mii_data *mii;
4965 int mask, error = 0;
4967 ASSERT_SERIALIZED(ifp->if_serializer);
4971 /* Check that the MTU setting is supported. */
4972 if (ifr->ifr_mtu < BCE_MIN_MTU ||
4974 ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
4976 ifr->ifr_mtu > ETHERMTU
4983 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
4985 ifp->if_mtu = ifr->ifr_mtu;
4986 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
4991 if (ifp->if_flags & IFF_UP) {
4992 if (ifp->if_flags & IFF_RUNNING) {
4993 mask = ifp->if_flags ^ sc->bce_if_flags;
4995 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
4996 bce_set_rx_mode(sc);
5000 } else if (ifp->if_flags & IFF_RUNNING) {
5003 /* If MFW is running, restart the controller a bit. */
5004 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5005 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5010 sc->bce_if_flags = ifp->if_flags;
5015 if (ifp->if_flags & IFF_RUNNING)
5016 bce_set_rx_mode(sc);
5021 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5023 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5025 mii = device_get_softc(sc->bce_miibus);
5026 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5030 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5031 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5034 if (mask & IFCAP_HWCSUM) {
5035 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5036 if (IFCAP_HWCSUM & ifp->if_capenable)
5037 ifp->if_hwassist = BCE_IF_HWASSIST;
5039 ifp->if_hwassist = 0;
5044 error = ether_ioctl(ifp, command, data);
5051 /****************************************************************************/
5052 /* Transmit timeout handler. */
5056 /****************************************************************************/
5058 bce_watchdog(struct ifnet *ifp)
5060 struct bce_softc *sc = ifp->if_softc;
5062 ASSERT_SERIALIZED(ifp->if_serializer);
5064 DBRUN(BCE_VERBOSE_SEND,
5065 bce_dump_driver_state(sc);
5066 bce_dump_status_block(sc));
5069 * If we are in this routine because of pause frames, then
5070 * don't reset the hardware.
5072 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5075 if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5077 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5079 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5084 if (!ifq_is_empty(&ifp->if_snd))
5089 #ifdef DEVICE_POLLING
5092 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5094 struct bce_softc *sc = ifp->if_softc;
5095 struct status_block *sblk = sc->status_block;
5096 uint16_t hw_tx_cons, hw_rx_cons;
5098 ASSERT_SERIALIZED(ifp->if_serializer);
5102 bce_disable_intr(sc);
5104 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5105 (1 << 16) | sc->bce_rx_quick_cons_trip);
5106 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5107 (1 << 16) | sc->bce_tx_quick_cons_trip);
5109 case POLL_DEREGISTER:
5110 bce_enable_intr(sc, 1);
5112 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5113 (sc->bce_tx_quick_cons_trip_int << 16) |
5114 sc->bce_tx_quick_cons_trip);
5115 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5116 (sc->bce_rx_quick_cons_trip_int << 16) |
5117 sc->bce_rx_quick_cons_trip);
5123 if (cmd == POLL_AND_CHECK_STATUS) {
5124 uint32_t status_attn_bits;
5126 status_attn_bits = sblk->status_attn_bits;
5128 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5130 "Simulating unexpected status attention bit set.");
5131 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5133 /* Was it a link change interrupt? */
5134 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5135 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5138 /* Clear any transient status updates during link state change. */
5139 REG_WR(sc, BCE_HC_COMMAND,
5140 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5141 REG_RD(sc, BCE_HC_COMMAND);
5144 * If any other attention is asserted then
5145 * the chip is toast.
5147 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5148 (sblk->status_attn_bits_ack &
5149 ~STATUS_ATTN_BITS_LINK_STATE)) {
5150 DBRUN(1, sc->unexpected_attentions++);
5152 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5153 sblk->status_attn_bits);
5156 if (bce_debug_unexpected_attention == 0)
5157 bce_breakpoint(sc));
5164 hw_rx_cons = bce_get_hw_rx_cons(sc);
5165 hw_tx_cons = bce_get_hw_tx_cons(sc);
5167 /* Check for any completed RX frames. */
5168 if (hw_rx_cons != sc->hw_rx_cons)
5169 bce_rx_intr(sc, count);
5171 /* Check for any completed TX frames. */
5172 if (hw_tx_cons != sc->hw_tx_cons)
5175 /* Check for new frames to transmit. */
5176 if (!ifq_is_empty(&ifp->if_snd))
5180 #endif /* DEVICE_POLLING */
5184 * Interrupt handler.
5186 /****************************************************************************/
5187 /* Main interrupt entry point. Verifies that the controller generated the */
5188 /* interrupt and then calls a separate routine for handle the various */
5189 /* interrupt causes (PHY, TX, RX). */
5192 /* 0 for success, positive value for failure. */
5193 /****************************************************************************/
5197 struct bce_softc *sc = xsc;
5198 struct ifnet *ifp = &sc->arpcom.ac_if;
5199 struct status_block *sblk;
5200 uint16_t hw_rx_cons, hw_tx_cons;
5202 ASSERT_SERIALIZED(ifp->if_serializer);
5204 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5205 DBRUNIF(1, sc->interrupts_generated++);
5207 sblk = sc->status_block;
5210 * If the hardware status block index matches the last value
5211 * read by the driver and we haven't asserted our interrupt
5212 * then there's nothing to do.
5214 if (sblk->status_idx == sc->last_status_idx &&
5215 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5216 BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5219 /* Ack the interrupt and stop others from occuring. */
5220 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5221 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5222 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5224 /* Check if the hardware has finished any work. */
5225 hw_rx_cons = bce_get_hw_rx_cons(sc);
5226 hw_tx_cons = bce_get_hw_tx_cons(sc);
5228 /* Keep processing data as long as there is work to do. */
5230 uint32_t status_attn_bits;
5232 status_attn_bits = sblk->status_attn_bits;
5234 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5236 "Simulating unexpected status attention bit set.");
5237 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5239 /* Was it a link change interrupt? */
5240 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5241 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5245 * Clear any transient status updates during link state
5248 REG_WR(sc, BCE_HC_COMMAND,
5249 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5250 REG_RD(sc, BCE_HC_COMMAND);
5254 * If any other attention is asserted then
5255 * the chip is toast.
5257 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5258 (sblk->status_attn_bits_ack &
5259 ~STATUS_ATTN_BITS_LINK_STATE)) {
5260 DBRUN(1, sc->unexpected_attentions++);
5262 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5263 sblk->status_attn_bits);
5266 if (bce_debug_unexpected_attention == 0)
5267 bce_breakpoint(sc));
5273 /* Check for any completed RX frames. */
5274 if (hw_rx_cons != sc->hw_rx_cons)
5275 bce_rx_intr(sc, -1);
5277 /* Check for any completed TX frames. */
5278 if (hw_tx_cons != sc->hw_tx_cons)
5282 * Save the status block index value
5283 * for use during the next interrupt.
5285 sc->last_status_idx = sblk->status_idx;
5288 * Prevent speculative reads from getting
5289 * ahead of the status block.
5291 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5292 BUS_SPACE_BARRIER_READ);
5295 * If there's no work left then exit the
5296 * interrupt service routine.
5298 hw_rx_cons = bce_get_hw_rx_cons(sc);
5299 hw_tx_cons = bce_get_hw_tx_cons(sc);
5300 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5304 /* Re-enable interrupts. */
5305 bce_enable_intr(sc, 0);
5307 if (sc->bce_coalchg_mask)
5308 bce_coal_change(sc);
5310 /* Handle any frames that arrived while handling the interrupt. */
5311 if (!ifq_is_empty(&ifp->if_snd))
5316 /****************************************************************************/
5317 /* Programs the various packet receive modes (broadcast and multicast). */
5321 /****************************************************************************/
5323 bce_set_rx_mode(struct bce_softc *sc)
5325 struct ifnet *ifp = &sc->arpcom.ac_if;
5326 struct ifmultiaddr *ifma;
5327 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5328 uint32_t rx_mode, sort_mode;
5331 ASSERT_SERIALIZED(ifp->if_serializer);
5333 /* Initialize receive mode default settings. */
5334 rx_mode = sc->rx_mode &
5335 ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5336 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5337 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5340 * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5343 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5344 !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5345 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5348 * Check for promiscuous, all multicast, or selected
5349 * multicast address filtering.
5351 if (ifp->if_flags & IFF_PROMISC) {
5352 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5354 /* Enable promiscuous mode. */
5355 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5356 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5357 } else if (ifp->if_flags & IFF_ALLMULTI) {
5358 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5360 /* Enable all multicast addresses. */
5361 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5362 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5365 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5367 /* Accept one or more multicast(s). */
5368 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5370 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5371 if (ifma->ifma_addr->sa_family != AF_LINK)
5374 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5375 ETHER_ADDR_LEN) & 0xFF;
5376 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5379 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5380 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5383 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5386 /* Only make changes if the recive mode has actually changed. */
5387 if (rx_mode != sc->rx_mode) {
5388 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5391 sc->rx_mode = rx_mode;
5392 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5395 /* Disable and clear the exisitng sort before enabling a new sort. */
5396 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5397 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5398 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5402 /****************************************************************************/
5403 /* Called periodically to updates statistics from the controllers */
5404 /* statistics block. */
5408 /****************************************************************************/
5410 bce_stats_update(struct bce_softc *sc)
5412 struct ifnet *ifp = &sc->arpcom.ac_if;
5413 struct statistics_block *stats = sc->stats_block;
5415 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5417 ASSERT_SERIALIZED(ifp->if_serializer);
5420 * Certain controllers don't report carrier sense errors correctly.
5421 * See errata E11_5708CA0_1165.
5423 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5424 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5426 (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5430 * Update the sysctl statistics from the hardware statistics.
5432 sc->stat_IfHCInOctets =
5433 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5434 (uint64_t)stats->stat_IfHCInOctets_lo;
5436 sc->stat_IfHCInBadOctets =
5437 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5438 (uint64_t)stats->stat_IfHCInBadOctets_lo;
5440 sc->stat_IfHCOutOctets =
5441 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5442 (uint64_t)stats->stat_IfHCOutOctets_lo;
5444 sc->stat_IfHCOutBadOctets =
5445 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5446 (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5448 sc->stat_IfHCInUcastPkts =
5449 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5450 (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5452 sc->stat_IfHCInMulticastPkts =
5453 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5454 (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5456 sc->stat_IfHCInBroadcastPkts =
5457 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5458 (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5460 sc->stat_IfHCOutUcastPkts =
5461 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5462 (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5464 sc->stat_IfHCOutMulticastPkts =
5465 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5466 (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5468 sc->stat_IfHCOutBroadcastPkts =
5469 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5470 (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5472 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5473 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5475 sc->stat_Dot3StatsCarrierSenseErrors =
5476 stats->stat_Dot3StatsCarrierSenseErrors;
5478 sc->stat_Dot3StatsFCSErrors =
5479 stats->stat_Dot3StatsFCSErrors;
5481 sc->stat_Dot3StatsAlignmentErrors =
5482 stats->stat_Dot3StatsAlignmentErrors;
5484 sc->stat_Dot3StatsSingleCollisionFrames =
5485 stats->stat_Dot3StatsSingleCollisionFrames;
5487 sc->stat_Dot3StatsMultipleCollisionFrames =
5488 stats->stat_Dot3StatsMultipleCollisionFrames;
5490 sc->stat_Dot3StatsDeferredTransmissions =
5491 stats->stat_Dot3StatsDeferredTransmissions;
5493 sc->stat_Dot3StatsExcessiveCollisions =
5494 stats->stat_Dot3StatsExcessiveCollisions;
5496 sc->stat_Dot3StatsLateCollisions =
5497 stats->stat_Dot3StatsLateCollisions;
5499 sc->stat_EtherStatsCollisions =
5500 stats->stat_EtherStatsCollisions;
5502 sc->stat_EtherStatsFragments =
5503 stats->stat_EtherStatsFragments;
5505 sc->stat_EtherStatsJabbers =
5506 stats->stat_EtherStatsJabbers;
5508 sc->stat_EtherStatsUndersizePkts =
5509 stats->stat_EtherStatsUndersizePkts;
5511 sc->stat_EtherStatsOverrsizePkts =
5512 stats->stat_EtherStatsOverrsizePkts;
5514 sc->stat_EtherStatsPktsRx64Octets =
5515 stats->stat_EtherStatsPktsRx64Octets;
5517 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5518 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5520 sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5521 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5523 sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5524 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5526 sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5527 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5529 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5530 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5532 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5533 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5535 sc->stat_EtherStatsPktsTx64Octets =
5536 stats->stat_EtherStatsPktsTx64Octets;
5538 sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5539 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5541 sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5542 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5544 sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5545 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5547 sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5548 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5550 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5551 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5553 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5554 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5556 sc->stat_XonPauseFramesReceived =
5557 stats->stat_XonPauseFramesReceived;
5559 sc->stat_XoffPauseFramesReceived =
5560 stats->stat_XoffPauseFramesReceived;
5562 sc->stat_OutXonSent =
5563 stats->stat_OutXonSent;
5565 sc->stat_OutXoffSent =
5566 stats->stat_OutXoffSent;
5568 sc->stat_FlowControlDone =
5569 stats->stat_FlowControlDone;
5571 sc->stat_MacControlFramesReceived =
5572 stats->stat_MacControlFramesReceived;
5574 sc->stat_XoffStateEntered =
5575 stats->stat_XoffStateEntered;
5577 sc->stat_IfInFramesL2FilterDiscards =
5578 stats->stat_IfInFramesL2FilterDiscards;
5580 sc->stat_IfInRuleCheckerDiscards =
5581 stats->stat_IfInRuleCheckerDiscards;
5583 sc->stat_IfInFTQDiscards =
5584 stats->stat_IfInFTQDiscards;
5586 sc->stat_IfInMBUFDiscards =
5587 stats->stat_IfInMBUFDiscards;
5589 sc->stat_IfInRuleCheckerP4Hit =
5590 stats->stat_IfInRuleCheckerP4Hit;
5592 sc->stat_CatchupInRuleCheckerDiscards =
5593 stats->stat_CatchupInRuleCheckerDiscards;
5595 sc->stat_CatchupInFTQDiscards =
5596 stats->stat_CatchupInFTQDiscards;
5598 sc->stat_CatchupInMBUFDiscards =
5599 stats->stat_CatchupInMBUFDiscards;
5601 sc->stat_CatchupInRuleCheckerP4Hit =
5602 stats->stat_CatchupInRuleCheckerP4Hit;
5604 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5607 * Update the interface statistics from the
5608 * hardware statistics.
5610 ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5612 ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5613 (u_long)sc->stat_EtherStatsOverrsizePkts +
5614 (u_long)sc->stat_IfInMBUFDiscards +
5615 (u_long)sc->stat_Dot3StatsAlignmentErrors +
5616 (u_long)sc->stat_Dot3StatsFCSErrors +
5617 (u_long)sc->stat_IfInRuleCheckerDiscards +
5618 (u_long)sc->stat_IfInFTQDiscards +
5619 (u_long)sc->com_no_buffers;
5622 (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5623 (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5624 (u_long)sc->stat_Dot3StatsLateCollisions;
5626 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5630 /****************************************************************************/
5631 /* Periodic function to notify the bootcode that the driver is still */
5636 /****************************************************************************/
5638 bce_pulse(void *xsc)
5640 struct bce_softc *sc = xsc;
5641 struct ifnet *ifp = &sc->arpcom.ac_if;
5644 lwkt_serialize_enter(ifp->if_serializer);
5646 /* Tell the firmware that the driver is still running. */
5647 msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5648 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg);
5650 /* Schedule the next pulse. */
5651 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5653 lwkt_serialize_exit(ifp->if_serializer);
5657 /****************************************************************************/
5658 /* Periodic function to perform maintenance tasks. */
5662 /****************************************************************************/
5664 bce_tick_serialized(struct bce_softc *sc)
5666 struct ifnet *ifp = &sc->arpcom.ac_if;
5667 struct mii_data *mii;
5669 ASSERT_SERIALIZED(ifp->if_serializer);
5671 /* Update the statistics from the hardware statistics block. */
5672 bce_stats_update(sc);
5674 /* Schedule the next tick. */
5675 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
5677 /* If link is up already up then we're done. */
5681 mii = device_get_softc(sc->bce_miibus);
5684 /* Check if the link has come up. */
5685 if ((mii->mii_media_status & IFM_ACTIVE) &&
5686 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5688 /* Now that link is up, handle any outstanding TX traffic. */
5689 if (!ifq_is_empty(&ifp->if_snd))
5698 struct bce_softc *sc = xsc;
5699 struct ifnet *ifp = &sc->arpcom.ac_if;
5701 lwkt_serialize_enter(ifp->if_serializer);
5702 bce_tick_serialized(sc);
5703 lwkt_serialize_exit(ifp->if_serializer);
5708 /****************************************************************************/
5709 /* Allows the driver state to be dumped through the sysctl interface. */
5712 /* 0 for success, positive value for failure. */
5713 /****************************************************************************/
5715 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5719 struct bce_softc *sc;
5722 error = sysctl_handle_int(oidp, &result, 0, req);
5724 if (error || !req->newptr)
5728 sc = (struct bce_softc *)arg1;
5729 bce_dump_driver_state(sc);
5736 /****************************************************************************/
5737 /* Allows the hardware state to be dumped through the sysctl interface. */
5740 /* 0 for success, positive value for failure. */
5741 /****************************************************************************/
5743 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5747 struct bce_softc *sc;
5750 error = sysctl_handle_int(oidp, &result, 0, req);
5752 if (error || !req->newptr)
5756 sc = (struct bce_softc *)arg1;
5757 bce_dump_hw_state(sc);
5764 /****************************************************************************/
5765 /* Provides a sysctl interface to allows dumping the RX chain. */
5768 /* 0 for success, positive value for failure. */
5769 /****************************************************************************/
5771 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5775 struct bce_softc *sc;
5778 error = sysctl_handle_int(oidp, &result, 0, req);
5780 if (error || !req->newptr)
5784 sc = (struct bce_softc *)arg1;
5785 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
5792 /****************************************************************************/
5793 /* Provides a sysctl interface to allows dumping the TX chain. */
5796 /* 0 for success, positive value for failure. */
5797 /****************************************************************************/
5799 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5803 struct bce_softc *sc;
5806 error = sysctl_handle_int(oidp, &result, 0, req);
5808 if (error || !req->newptr)
5812 sc = (struct bce_softc *)arg1;
5813 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
5820 /****************************************************************************/
5821 /* Provides a sysctl interface to allow reading arbitrary registers in the */
5822 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
5825 /* 0 for success, positive value for failure. */
5826 /****************************************************************************/
5828 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5830 struct bce_softc *sc;
5832 uint32_t val, result;
5835 error = sysctl_handle_int(oidp, &result, 0, req);
5836 if (error || (req->newptr == NULL))
5839 /* Make sure the register is accessible. */
5840 if (result < 0x8000) {
5841 sc = (struct bce_softc *)arg1;
5842 val = REG_RD(sc, result);
5843 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5845 } else if (result < 0x0280000) {
5846 sc = (struct bce_softc *)arg1;
5847 val = REG_RD_IND(sc, result);
5848 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5855 /****************************************************************************/
5856 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */
5857 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
5860 /* 0 for success, positive value for failure. */
5861 /****************************************************************************/
5863 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
5865 struct bce_softc *sc;
5871 error = sysctl_handle_int(oidp, &result, 0, req);
5872 if (error || (req->newptr == NULL))
5875 /* Make sure the register is accessible. */
5876 if (result < 0x20) {
5877 sc = (struct bce_softc *)arg1;
5879 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
5880 if_printf(&sc->arpcom.ac_if,
5881 "phy 0x%02X = 0x%04X\n", result, val);
5887 /****************************************************************************/
5888 /* Provides a sysctl interface to forcing the driver to dump state and */
5889 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
5892 /* 0 for success, positive value for failure. */
5893 /****************************************************************************/
5895 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
5899 struct bce_softc *sc;
5902 error = sysctl_handle_int(oidp, &result, 0, req);
5904 if (error || !req->newptr)
5908 sc = (struct bce_softc *)arg1;
5917 /****************************************************************************/
5918 /* Adds any sysctl parameters for tuning or debugging purposes. */
5921 /* 0 for success, positive value for failure. */
5922 /****************************************************************************/
5924 bce_add_sysctls(struct bce_softc *sc)
5926 struct sysctl_ctx_list *ctx;
5927 struct sysctl_oid_list *children;
5929 sysctl_ctx_init(&sc->bce_sysctl_ctx);
5930 sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
5931 SYSCTL_STATIC_CHILDREN(_hw),
5933 device_get_nameunit(sc->bce_dev),
5935 if (sc->bce_sysctl_tree == NULL) {
5936 device_printf(sc->bce_dev, "can't add sysctl node\n");
5940 ctx = &sc->bce_sysctl_ctx;
5941 children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
5943 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
5944 CTLTYPE_INT | CTLFLAG_RW,
5945 sc, 0, bce_sysctl_tx_bds_int, "I",
5946 "Send max coalesced BD count during interrupt");
5947 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
5948 CTLTYPE_INT | CTLFLAG_RW,
5949 sc, 0, bce_sysctl_tx_bds, "I",
5950 "Send max coalesced BD count");
5951 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
5952 CTLTYPE_INT | CTLFLAG_RW,
5953 sc, 0, bce_sysctl_tx_ticks_int, "I",
5954 "Send coalescing ticks during interrupt");
5955 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
5956 CTLTYPE_INT | CTLFLAG_RW,
5957 sc, 0, bce_sysctl_tx_ticks, "I",
5958 "Send coalescing ticks");
5960 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
5961 CTLTYPE_INT | CTLFLAG_RW,
5962 sc, 0, bce_sysctl_rx_bds_int, "I",
5963 "Receive max coalesced BD count during interrupt");
5964 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
5965 CTLTYPE_INT | CTLFLAG_RW,
5966 sc, 0, bce_sysctl_rx_bds, "I",
5967 "Receive max coalesced BD count");
5968 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
5969 CTLTYPE_INT | CTLFLAG_RW,
5970 sc, 0, bce_sysctl_rx_ticks_int, "I",
5971 "Receive coalescing ticks during interrupt");
5972 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
5973 CTLTYPE_INT | CTLFLAG_RW,
5974 sc, 0, bce_sysctl_rx_ticks, "I",
5975 "Receive coalescing ticks");
5978 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5980 CTLFLAG_RD, &sc->rx_low_watermark,
5981 0, "Lowest level of free rx_bd's");
5983 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5985 CTLFLAG_RD, &sc->rx_empty_count,
5986 0, "Number of times the RX chain was empty");
5988 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5990 CTLFLAG_RD, &sc->tx_hi_watermark,
5991 0, "Highest level of used tx_bd's");
5993 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5995 CTLFLAG_RD, &sc->tx_full_count,
5996 0, "Number of times the TX chain was full");
5998 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5999 "l2fhdr_status_errors",
6000 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6001 0, "l2_fhdr status errors");
6003 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6004 "unexpected_attentions",
6005 CTLFLAG_RD, &sc->unexpected_attentions,
6006 0, "unexpected attentions");
6008 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6009 "lost_status_block_updates",
6010 CTLFLAG_RD, &sc->lost_status_block_updates,
6011 0, "lost status block updates");
6013 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6014 "mbuf_alloc_failed",
6015 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6016 0, "mbuf cluster allocation failures");
6019 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6020 "stat_IfHCInOctets",
6021 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6024 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6025 "stat_IfHCInBadOctets",
6026 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6027 "Bad bytes received");
6029 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6030 "stat_IfHCOutOctets",
6031 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6034 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6035 "stat_IfHCOutBadOctets",
6036 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6039 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6040 "stat_IfHCInUcastPkts",
6041 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6042 "Unicast packets received");
6044 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6045 "stat_IfHCInMulticastPkts",
6046 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6047 "Multicast packets received");
6049 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6050 "stat_IfHCInBroadcastPkts",
6051 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6052 "Broadcast packets received");
6054 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6055 "stat_IfHCOutUcastPkts",
6056 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6057 "Unicast packets sent");
6059 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6060 "stat_IfHCOutMulticastPkts",
6061 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6062 "Multicast packets sent");
6064 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6065 "stat_IfHCOutBroadcastPkts",
6066 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6067 "Broadcast packets sent");
6069 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6070 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6071 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6072 0, "Internal MAC transmit errors");
6074 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6075 "stat_Dot3StatsCarrierSenseErrors",
6076 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6077 0, "Carrier sense errors");
6079 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6080 "stat_Dot3StatsFCSErrors",
6081 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6082 0, "Frame check sequence errors");
6084 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6085 "stat_Dot3StatsAlignmentErrors",
6086 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6087 0, "Alignment errors");
6089 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6090 "stat_Dot3StatsSingleCollisionFrames",
6091 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6092 0, "Single Collision Frames");
6094 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6095 "stat_Dot3StatsMultipleCollisionFrames",
6096 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6097 0, "Multiple Collision Frames");
6099 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6100 "stat_Dot3StatsDeferredTransmissions",
6101 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6102 0, "Deferred Transmissions");
6104 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6105 "stat_Dot3StatsExcessiveCollisions",
6106 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6107 0, "Excessive Collisions");
6109 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6110 "stat_Dot3StatsLateCollisions",
6111 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6112 0, "Late Collisions");
6114 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6115 "stat_EtherStatsCollisions",
6116 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6119 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6120 "stat_EtherStatsFragments",
6121 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6124 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6125 "stat_EtherStatsJabbers",
6126 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6129 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6130 "stat_EtherStatsUndersizePkts",
6131 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6132 0, "Undersize packets");
6134 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6135 "stat_EtherStatsOverrsizePkts",
6136 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6137 0, "stat_EtherStatsOverrsizePkts");
6139 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6140 "stat_EtherStatsPktsRx64Octets",
6141 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6142 0, "Bytes received in 64 byte packets");
6144 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6145 "stat_EtherStatsPktsRx65Octetsto127Octets",
6146 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6147 0, "Bytes received in 65 to 127 byte packets");
6149 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6150 "stat_EtherStatsPktsRx128Octetsto255Octets",
6151 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6152 0, "Bytes received in 128 to 255 byte packets");
6154 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6155 "stat_EtherStatsPktsRx256Octetsto511Octets",
6156 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6157 0, "Bytes received in 256 to 511 byte packets");
6159 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6160 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6161 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6162 0, "Bytes received in 512 to 1023 byte packets");
6164 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6165 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6166 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6167 0, "Bytes received in 1024 t0 1522 byte packets");
6169 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6170 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6171 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6172 0, "Bytes received in 1523 to 9022 byte packets");
6174 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6175 "stat_EtherStatsPktsTx64Octets",
6176 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6177 0, "Bytes sent in 64 byte packets");
6179 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6180 "stat_EtherStatsPktsTx65Octetsto127Octets",
6181 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6182 0, "Bytes sent in 65 to 127 byte packets");
6184 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6185 "stat_EtherStatsPktsTx128Octetsto255Octets",
6186 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6187 0, "Bytes sent in 128 to 255 byte packets");
6189 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6190 "stat_EtherStatsPktsTx256Octetsto511Octets",
6191 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6192 0, "Bytes sent in 256 to 511 byte packets");
6194 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6195 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6196 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6197 0, "Bytes sent in 512 to 1023 byte packets");
6199 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6200 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6201 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6202 0, "Bytes sent in 1024 to 1522 byte packets");
6204 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6205 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6206 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6207 0, "Bytes sent in 1523 to 9022 byte packets");
6209 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6210 "stat_XonPauseFramesReceived",
6211 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6212 0, "XON pause frames receved");
6214 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6215 "stat_XoffPauseFramesReceived",
6216 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6217 0, "XOFF pause frames received");
6219 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6221 CTLFLAG_RD, &sc->stat_OutXonSent,
6222 0, "XON pause frames sent");
6224 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6226 CTLFLAG_RD, &sc->stat_OutXoffSent,
6227 0, "XOFF pause frames sent");
6229 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6230 "stat_FlowControlDone",
6231 CTLFLAG_RD, &sc->stat_FlowControlDone,
6232 0, "Flow control done");
6234 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6235 "stat_MacControlFramesReceived",
6236 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6237 0, "MAC control frames received");
6239 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6240 "stat_XoffStateEntered",
6241 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6242 0, "XOFF state entered");
6244 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6245 "stat_IfInFramesL2FilterDiscards",
6246 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6247 0, "Received L2 packets discarded");
6249 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6250 "stat_IfInRuleCheckerDiscards",
6251 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6252 0, "Received packets discarded by rule");
6254 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6255 "stat_IfInFTQDiscards",
6256 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6257 0, "Received packet FTQ discards");
6259 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6260 "stat_IfInMBUFDiscards",
6261 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6262 0, "Received packets discarded due to lack of controller buffer memory");
6264 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6265 "stat_IfInRuleCheckerP4Hit",
6266 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6267 0, "Received packets rule checker hits");
6269 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6270 "stat_CatchupInRuleCheckerDiscards",
6271 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6272 0, "Received packets discarded in Catchup path");
6274 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6275 "stat_CatchupInFTQDiscards",
6276 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6277 0, "Received packets discarded in FTQ in Catchup path");
6279 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6280 "stat_CatchupInMBUFDiscards",
6281 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6282 0, "Received packets discarded in controller buffer memory in Catchup path");
6284 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6285 "stat_CatchupInRuleCheckerP4Hit",
6286 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6287 0, "Received packets rule checker hits in Catchup path");
6289 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6291 CTLFLAG_RD, &sc->com_no_buffers,
6292 0, "Valid packets received but no RX buffers available");
6295 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6296 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6298 bce_sysctl_driver_state, "I", "Drive state information");
6300 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6301 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6303 bce_sysctl_hw_state, "I", "Hardware state information");
6305 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6306 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6308 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6310 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6311 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6313 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6315 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6316 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6318 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6320 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6321 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6323 bce_sysctl_reg_read, "I", "Register read");
6325 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6326 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6328 bce_sysctl_phy_read, "I", "PHY register read");
6335 /****************************************************************************/
6336 /* BCE Debug Routines */
6337 /****************************************************************************/
6340 /****************************************************************************/
6341 /* Freezes the controller to allow for a cohesive state dump. */
6345 /****************************************************************************/
6347 bce_freeze_controller(struct bce_softc *sc)
6351 val = REG_RD(sc, BCE_MISC_COMMAND);
6352 val |= BCE_MISC_COMMAND_DISABLE_ALL;
6353 REG_WR(sc, BCE_MISC_COMMAND, val);
6357 /****************************************************************************/
6358 /* Unfreezes the controller after a freeze operation. This may not always */
6359 /* work and the controller will require a reset! */
6363 /****************************************************************************/
6365 bce_unfreeze_controller(struct bce_softc *sc)
6369 val = REG_RD(sc, BCE_MISC_COMMAND);
6370 val |= BCE_MISC_COMMAND_ENABLE_ALL;
6371 REG_WR(sc, BCE_MISC_COMMAND, val);
6375 /****************************************************************************/
6376 /* Prints out information about an mbuf. */
6380 /****************************************************************************/
6382 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6384 struct ifnet *ifp = &sc->arpcom.ac_if;
6385 uint32_t val_hi, val_lo;
6386 struct mbuf *mp = m;
6389 /* Index out of range. */
6390 if_printf(ifp, "mbuf: null pointer\n");
6395 val_hi = BCE_ADDR_HI(mp);
6396 val_lo = BCE_ADDR_LO(mp);
6397 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6398 "m_flags = ( ", val_hi, val_lo, mp->m_len);
6400 if (mp->m_flags & M_EXT)
6402 if (mp->m_flags & M_PKTHDR)
6403 kprintf("M_PKTHDR ");
6404 if (mp->m_flags & M_EOR)
6407 if (mp->m_flags & M_RDONLY)
6408 kprintf("M_RDONLY ");
6411 val_hi = BCE_ADDR_HI(mp->m_data);
6412 val_lo = BCE_ADDR_LO(mp->m_data);
6413 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6415 if (mp->m_flags & M_PKTHDR) {
6416 if_printf(ifp, "- m_pkthdr: flags = ( ");
6417 if (mp->m_flags & M_BCAST)
6418 kprintf("M_BCAST ");
6419 if (mp->m_flags & M_MCAST)
6420 kprintf("M_MCAST ");
6421 if (mp->m_flags & M_FRAG)
6423 if (mp->m_flags & M_FIRSTFRAG)
6424 kprintf("M_FIRSTFRAG ");
6425 if (mp->m_flags & M_LASTFRAG)
6426 kprintf("M_LASTFRAG ");
6428 if (mp->m_flags & M_VLANTAG)
6429 kprintf("M_VLANTAG ");
6432 if (mp->m_flags & M_PROMISC)
6433 kprintf("M_PROMISC ");
6435 kprintf(") csum_flags = ( ");
6436 if (mp->m_pkthdr.csum_flags & CSUM_IP)
6437 kprintf("CSUM_IP ");
6438 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6439 kprintf("CSUM_TCP ");
6440 if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6441 kprintf("CSUM_UDP ");
6442 if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6443 kprintf("CSUM_IP_FRAGS ");
6444 if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6445 kprintf("CSUM_FRAGMENT ");
6447 if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6448 kprintf("CSUM_TSO ");
6450 if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6451 kprintf("CSUM_IP_CHECKED ");
6452 if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6453 kprintf("CSUM_IP_VALID ");
6454 if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6455 kprintf("CSUM_DATA_VALID ");
6459 if (mp->m_flags & M_EXT) {
6460 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6461 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6462 if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6464 val_hi, val_lo, mp->m_ext.ext_size);
6471 /****************************************************************************/
6472 /* Prints out the mbufs in the TX mbuf chain. */
6476 /****************************************************************************/
6478 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6480 struct ifnet *ifp = &sc->arpcom.ac_if;
6484 "----------------------------"
6486 "----------------------------\n");
6488 for (i = 0; i < count; i++) {
6489 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6490 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6491 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6495 "----------------------------"
6497 "----------------------------\n");
6501 /****************************************************************************/
6502 /* Prints out the mbufs in the RX mbuf chain. */
6506 /****************************************************************************/
6508 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6510 struct ifnet *ifp = &sc->arpcom.ac_if;
6514 "----------------------------"
6516 "----------------------------\n");
6518 for (i = 0; i < count; i++) {
6519 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6520 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6521 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6525 "----------------------------"
6527 "----------------------------\n");
6531 /****************************************************************************/
6532 /* Prints out a tx_bd structure. */
6536 /****************************************************************************/
6538 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6540 struct ifnet *ifp = &sc->arpcom.ac_if;
6542 if (idx > MAX_TX_BD) {
6543 /* Index out of range. */
6544 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6545 } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6546 /* TX Chain page pointer. */
6547 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6548 "chain page pointer\n",
6549 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6551 /* Normal tx_bd entry. */
6552 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6554 "vlan tag= 0x%04X, flags = 0x%04X (",
6555 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6556 txbd->tx_bd_mss_nbytes,
6557 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6559 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6560 kprintf(" CONN_FAULT");
6562 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6563 kprintf(" TCP_UDP_CKSUM");
6565 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6566 kprintf(" IP_CKSUM");
6568 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6571 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6572 kprintf(" COAL_NOW");
6574 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6575 kprintf(" DONT_GEN_CRC");
6577 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6580 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6583 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6586 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6587 kprintf(" OPTION_WORD");
6589 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6592 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6600 /****************************************************************************/
6601 /* Prints out a rx_bd structure. */
6605 /****************************************************************************/
6607 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6609 struct ifnet *ifp = &sc->arpcom.ac_if;
6611 if (idx > MAX_RX_BD) {
6612 /* Index out of range. */
6613 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6614 } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6615 /* TX Chain page pointer. */
6616 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6617 "chain page pointer\n",
6618 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6620 /* Normal tx_bd entry. */
6621 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6622 "nbytes = 0x%08X, flags = 0x%08X\n",
6623 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6624 rxbd->rx_bd_len, rxbd->rx_bd_flags);
6629 /****************************************************************************/
6630 /* Prints out a l2_fhdr structure. */
6634 /****************************************************************************/
6636 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6638 if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6639 "pkt_len = 0x%04X, vlan = 0x%04x, "
6640 "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6641 idx, l2fhdr->l2_fhdr_status,
6642 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6643 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6647 /****************************************************************************/
6648 /* Prints out the tx chain. */
6652 /****************************************************************************/
6654 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6656 struct ifnet *ifp = &sc->arpcom.ac_if;
6659 /* First some info about the tx_bd chain structure. */
6661 "----------------------------"
6663 "----------------------------\n");
6665 if_printf(ifp, "page size = 0x%08X, "
6666 "tx chain pages = 0x%08X\n",
6667 (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6669 if_printf(ifp, "tx_bd per page = 0x%08X, "
6670 "usable tx_bd per page = 0x%08X\n",
6671 (uint32_t)TOTAL_TX_BD_PER_PAGE,
6672 (uint32_t)USABLE_TX_BD_PER_PAGE);
6674 if_printf(ifp, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6677 "----------------------------"
6679 "----------------------------\n");
6681 /* Now print out the tx_bd's themselves. */
6682 for (i = 0; i < count; i++) {
6685 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6686 bce_dump_txbd(sc, tx_prod, txbd);
6687 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6691 "----------------------------"
6693 "----------------------------\n");
6697 /****************************************************************************/
6698 /* Prints out the rx chain. */
6702 /****************************************************************************/
6704 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6706 struct ifnet *ifp = &sc->arpcom.ac_if;
6709 /* First some info about the tx_bd chain structure. */
6711 "----------------------------"
6713 "----------------------------\n");
6715 if_printf(ifp, "page size = 0x%08X, "
6716 "rx chain pages = 0x%08X\n",
6717 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
6719 if_printf(ifp, "rx_bd per page = 0x%08X, "
6720 "usable rx_bd per page = 0x%08X\n",
6721 (uint32_t)TOTAL_RX_BD_PER_PAGE,
6722 (uint32_t)USABLE_RX_BD_PER_PAGE);
6724 if_printf(ifp, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
6727 "----------------------------"
6729 "----------------------------\n");
6731 /* Now print out the rx_bd's themselves. */
6732 for (i = 0; i < count; i++) {
6735 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6736 bce_dump_rxbd(sc, rx_prod, rxbd);
6737 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
6741 "----------------------------"
6743 "----------------------------\n");
6747 /****************************************************************************/
6748 /* Prints out the status block from host memory. */
6752 /****************************************************************************/
6754 bce_dump_status_block(struct bce_softc *sc)
6756 struct status_block *sblk = sc->status_block;
6757 struct ifnet *ifp = &sc->arpcom.ac_if;
6760 "----------------------------"
6762 "----------------------------\n");
6764 if_printf(ifp, " 0x%08X - attn_bits\n", sblk->status_attn_bits);
6766 if_printf(ifp, " 0x%08X - attn_bits_ack\n",
6767 sblk->status_attn_bits_ack);
6769 if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6770 sblk->status_rx_quick_consumer_index0,
6771 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
6773 if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6774 sblk->status_tx_quick_consumer_index0,
6775 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
6777 if_printf(ifp, " 0x%04X - status_idx\n", sblk->status_idx);
6779 /* Theses indices are not used for normal L2 drivers. */
6780 if (sblk->status_rx_quick_consumer_index1) {
6781 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6782 sblk->status_rx_quick_consumer_index1,
6783 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
6786 if (sblk->status_tx_quick_consumer_index1) {
6787 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6788 sblk->status_tx_quick_consumer_index1,
6789 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
6792 if (sblk->status_rx_quick_consumer_index2) {
6793 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6794 sblk->status_rx_quick_consumer_index2,
6795 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
6798 if (sblk->status_tx_quick_consumer_index2) {
6799 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6800 sblk->status_tx_quick_consumer_index2,
6801 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
6804 if (sblk->status_rx_quick_consumer_index3) {
6805 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
6806 sblk->status_rx_quick_consumer_index3,
6807 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
6810 if (sblk->status_tx_quick_consumer_index3) {
6811 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
6812 sblk->status_tx_quick_consumer_index3,
6813 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
6816 if (sblk->status_rx_quick_consumer_index4 ||
6817 sblk->status_rx_quick_consumer_index5) {
6818 if_printf(ifp, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n",
6819 sblk->status_rx_quick_consumer_index4,
6820 sblk->status_rx_quick_consumer_index5);
6823 if (sblk->status_rx_quick_consumer_index6 ||
6824 sblk->status_rx_quick_consumer_index7) {
6825 if_printf(ifp, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n",
6826 sblk->status_rx_quick_consumer_index6,
6827 sblk->status_rx_quick_consumer_index7);
6830 if (sblk->status_rx_quick_consumer_index8 ||
6831 sblk->status_rx_quick_consumer_index9) {
6832 if_printf(ifp, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n",
6833 sblk->status_rx_quick_consumer_index8,
6834 sblk->status_rx_quick_consumer_index9);
6837 if (sblk->status_rx_quick_consumer_index10 ||
6838 sblk->status_rx_quick_consumer_index11) {
6839 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n",
6840 sblk->status_rx_quick_consumer_index10,
6841 sblk->status_rx_quick_consumer_index11);
6844 if (sblk->status_rx_quick_consumer_index12 ||
6845 sblk->status_rx_quick_consumer_index13) {
6846 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n",
6847 sblk->status_rx_quick_consumer_index12,
6848 sblk->status_rx_quick_consumer_index13);
6851 if (sblk->status_rx_quick_consumer_index14 ||
6852 sblk->status_rx_quick_consumer_index15) {
6853 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n",
6854 sblk->status_rx_quick_consumer_index14,
6855 sblk->status_rx_quick_consumer_index15);
6858 if (sblk->status_completion_producer_index ||
6859 sblk->status_cmd_consumer_index) {
6860 if_printf(ifp, "com_prod = 0x%08X, cmd_cons = 0x%08X\n",
6861 sblk->status_completion_producer_index,
6862 sblk->status_cmd_consumer_index);
6866 "----------------------------"
6868 "----------------------------\n");
6872 /****************************************************************************/
6873 /* Prints out the statistics block. */
6877 /****************************************************************************/
6879 bce_dump_stats_block(struct bce_softc *sc)
6881 struct statistics_block *sblk = sc->stats_block;
6882 struct ifnet *ifp = &sc->arpcom.ac_if;
6886 " Stats Block (All Stats Not Shown Are 0) "
6887 "---------------\n");
6889 if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
6890 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
6891 sblk->stat_IfHCInOctets_hi,
6892 sblk->stat_IfHCInOctets_lo);
6895 if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
6896 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
6897 sblk->stat_IfHCInBadOctets_hi,
6898 sblk->stat_IfHCInBadOctets_lo);
6901 if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
6902 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
6903 sblk->stat_IfHCOutOctets_hi,
6904 sblk->stat_IfHCOutOctets_lo);
6907 if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
6908 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
6909 sblk->stat_IfHCOutBadOctets_hi,
6910 sblk->stat_IfHCOutBadOctets_lo);
6913 if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
6914 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
6915 sblk->stat_IfHCInUcastPkts_hi,
6916 sblk->stat_IfHCInUcastPkts_lo);
6919 if (sblk->stat_IfHCInBroadcastPkts_hi ||
6920 sblk->stat_IfHCInBroadcastPkts_lo) {
6921 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
6922 sblk->stat_IfHCInBroadcastPkts_hi,
6923 sblk->stat_IfHCInBroadcastPkts_lo);
6926 if (sblk->stat_IfHCInMulticastPkts_hi ||
6927 sblk->stat_IfHCInMulticastPkts_lo) {
6928 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
6929 sblk->stat_IfHCInMulticastPkts_hi,
6930 sblk->stat_IfHCInMulticastPkts_lo);
6933 if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
6934 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
6935 sblk->stat_IfHCOutUcastPkts_hi,
6936 sblk->stat_IfHCOutUcastPkts_lo);
6939 if (sblk->stat_IfHCOutBroadcastPkts_hi ||
6940 sblk->stat_IfHCOutBroadcastPkts_lo) {
6941 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
6942 sblk->stat_IfHCOutBroadcastPkts_hi,
6943 sblk->stat_IfHCOutBroadcastPkts_lo);
6946 if (sblk->stat_IfHCOutMulticastPkts_hi ||
6947 sblk->stat_IfHCOutMulticastPkts_lo) {
6948 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
6949 sblk->stat_IfHCOutMulticastPkts_hi,
6950 sblk->stat_IfHCOutMulticastPkts_lo);
6953 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
6954 if_printf(ifp, " 0x%08X : "
6955 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
6956 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
6959 if (sblk->stat_Dot3StatsCarrierSenseErrors) {
6960 if_printf(ifp, " 0x%08X : "
6961 "Dot3StatsCarrierSenseErrors\n",
6962 sblk->stat_Dot3StatsCarrierSenseErrors);
6965 if (sblk->stat_Dot3StatsFCSErrors) {
6966 if_printf(ifp, " 0x%08X : Dot3StatsFCSErrors\n",
6967 sblk->stat_Dot3StatsFCSErrors);
6970 if (sblk->stat_Dot3StatsAlignmentErrors) {
6971 if_printf(ifp, " 0x%08X : Dot3StatsAlignmentErrors\n",
6972 sblk->stat_Dot3StatsAlignmentErrors);
6975 if (sblk->stat_Dot3StatsSingleCollisionFrames) {
6976 if_printf(ifp, " 0x%08X : "
6977 "Dot3StatsSingleCollisionFrames\n",
6978 sblk->stat_Dot3StatsSingleCollisionFrames);
6981 if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
6982 if_printf(ifp, " 0x%08X : "
6983 "Dot3StatsMultipleCollisionFrames\n",
6984 sblk->stat_Dot3StatsMultipleCollisionFrames);
6987 if (sblk->stat_Dot3StatsDeferredTransmissions) {
6988 if_printf(ifp, " 0x%08X : "
6989 "Dot3StatsDeferredTransmissions\n",
6990 sblk->stat_Dot3StatsDeferredTransmissions);
6993 if (sblk->stat_Dot3StatsExcessiveCollisions) {
6994 if_printf(ifp, " 0x%08X : "
6995 "Dot3StatsExcessiveCollisions\n",
6996 sblk->stat_Dot3StatsExcessiveCollisions);
6999 if (sblk->stat_Dot3StatsLateCollisions) {
7000 if_printf(ifp, " 0x%08X : Dot3StatsLateCollisions\n",
7001 sblk->stat_Dot3StatsLateCollisions);
7004 if (sblk->stat_EtherStatsCollisions) {
7005 if_printf(ifp, " 0x%08X : EtherStatsCollisions\n",
7006 sblk->stat_EtherStatsCollisions);
7009 if (sblk->stat_EtherStatsFragments) {
7010 if_printf(ifp, " 0x%08X : EtherStatsFragments\n",
7011 sblk->stat_EtherStatsFragments);
7014 if (sblk->stat_EtherStatsJabbers) {
7015 if_printf(ifp, " 0x%08X : EtherStatsJabbers\n",
7016 sblk->stat_EtherStatsJabbers);
7019 if (sblk->stat_EtherStatsUndersizePkts) {
7020 if_printf(ifp, " 0x%08X : EtherStatsUndersizePkts\n",
7021 sblk->stat_EtherStatsUndersizePkts);
7024 if (sblk->stat_EtherStatsOverrsizePkts) {
7025 if_printf(ifp, " 0x%08X : EtherStatsOverrsizePkts\n",
7026 sblk->stat_EtherStatsOverrsizePkts);
7029 if (sblk->stat_EtherStatsPktsRx64Octets) {
7030 if_printf(ifp, " 0x%08X : EtherStatsPktsRx64Octets\n",
7031 sblk->stat_EtherStatsPktsRx64Octets);
7034 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7035 if_printf(ifp, " 0x%08X : "
7036 "EtherStatsPktsRx65Octetsto127Octets\n",
7037 sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7040 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7041 if_printf(ifp, " 0x%08X : "
7042 "EtherStatsPktsRx128Octetsto255Octets\n",
7043 sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7046 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7047 if_printf(ifp, " 0x%08X : "
7048 "EtherStatsPktsRx256Octetsto511Octets\n",
7049 sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7052 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7053 if_printf(ifp, " 0x%08X : "
7054 "EtherStatsPktsRx512Octetsto1023Octets\n",
7055 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7058 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7059 if_printf(ifp, " 0x%08X : "
7060 "EtherStatsPktsRx1024Octetsto1522Octets\n",
7061 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7064 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7065 if_printf(ifp, " 0x%08X : "
7066 "EtherStatsPktsRx1523Octetsto9022Octets\n",
7067 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7070 if (sblk->stat_EtherStatsPktsTx64Octets) {
7071 if_printf(ifp, " 0x%08X : EtherStatsPktsTx64Octets\n",
7072 sblk->stat_EtherStatsPktsTx64Octets);
7075 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7076 if_printf(ifp, " 0x%08X : "
7077 "EtherStatsPktsTx65Octetsto127Octets\n",
7078 sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7081 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7082 if_printf(ifp, " 0x%08X : "
7083 "EtherStatsPktsTx128Octetsto255Octets\n",
7084 sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7087 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7088 if_printf(ifp, " 0x%08X : "
7089 "EtherStatsPktsTx256Octetsto511Octets\n",
7090 sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7093 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7094 if_printf(ifp, " 0x%08X : "
7095 "EtherStatsPktsTx512Octetsto1023Octets\n",
7096 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7099 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7100 if_printf(ifp, " 0x%08X : "
7101 "EtherStatsPktsTx1024Octetsto1522Octets\n",
7102 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7105 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7106 if_printf(ifp, " 0x%08X : "
7107 "EtherStatsPktsTx1523Octetsto9022Octets\n",
7108 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7111 if (sblk->stat_XonPauseFramesReceived) {
7112 if_printf(ifp, " 0x%08X : XonPauseFramesReceived\n",
7113 sblk->stat_XonPauseFramesReceived);
7116 if (sblk->stat_XoffPauseFramesReceived) {
7117 if_printf(ifp, " 0x%08X : XoffPauseFramesReceived\n",
7118 sblk->stat_XoffPauseFramesReceived);
7121 if (sblk->stat_OutXonSent) {
7122 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7123 sblk->stat_OutXonSent);
7126 if (sblk->stat_OutXoffSent) {
7127 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7128 sblk->stat_OutXoffSent);
7131 if (sblk->stat_FlowControlDone) {
7132 if_printf(ifp, " 0x%08X : FlowControlDone\n",
7133 sblk->stat_FlowControlDone);
7136 if (sblk->stat_MacControlFramesReceived) {
7137 if_printf(ifp, " 0x%08X : MacControlFramesReceived\n",
7138 sblk->stat_MacControlFramesReceived);
7141 if (sblk->stat_XoffStateEntered) {
7142 if_printf(ifp, " 0x%08X : XoffStateEntered\n",
7143 sblk->stat_XoffStateEntered);
7146 if (sblk->stat_IfInFramesL2FilterDiscards) {
7147 if_printf(ifp, " 0x%08X : IfInFramesL2FilterDiscards\n", sblk->stat_IfInFramesL2FilterDiscards);
7150 if (sblk->stat_IfInRuleCheckerDiscards) {
7151 if_printf(ifp, " 0x%08X : IfInRuleCheckerDiscards\n",
7152 sblk->stat_IfInRuleCheckerDiscards);
7155 if (sblk->stat_IfInFTQDiscards) {
7156 if_printf(ifp, " 0x%08X : IfInFTQDiscards\n",
7157 sblk->stat_IfInFTQDiscards);
7160 if (sblk->stat_IfInMBUFDiscards) {
7161 if_printf(ifp, " 0x%08X : IfInMBUFDiscards\n",
7162 sblk->stat_IfInMBUFDiscards);
7165 if (sblk->stat_IfInRuleCheckerP4Hit) {
7166 if_printf(ifp, " 0x%08X : IfInRuleCheckerP4Hit\n",
7167 sblk->stat_IfInRuleCheckerP4Hit);
7170 if (sblk->stat_CatchupInRuleCheckerDiscards) {
7171 if_printf(ifp, " 0x%08X : "
7172 "CatchupInRuleCheckerDiscards\n",
7173 sblk->stat_CatchupInRuleCheckerDiscards);
7176 if (sblk->stat_CatchupInFTQDiscards) {
7177 if_printf(ifp, " 0x%08X : CatchupInFTQDiscards\n",
7178 sblk->stat_CatchupInFTQDiscards);
7181 if (sblk->stat_CatchupInMBUFDiscards) {
7182 if_printf(ifp, " 0x%08X : CatchupInMBUFDiscards\n",
7183 sblk->stat_CatchupInMBUFDiscards);
7186 if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7187 if_printf(ifp, " 0x%08X : CatchupInRuleCheckerP4Hit\n",
7188 sblk->stat_CatchupInRuleCheckerP4Hit);
7192 "----------------------------"
7194 "----------------------------\n");
7198 /****************************************************************************/
7199 /* Prints out a summary of the driver state. */
7203 /****************************************************************************/
7205 bce_dump_driver_state(struct bce_softc *sc)
7207 struct ifnet *ifp = &sc->arpcom.ac_if;
7208 uint32_t val_hi, val_lo;
7211 "-----------------------------"
7213 "-----------------------------\n");
7215 val_hi = BCE_ADDR_HI(sc);
7216 val_lo = BCE_ADDR_LO(sc);
7217 if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7218 "virtual address\n", val_hi, val_lo);
7220 val_hi = BCE_ADDR_HI(sc->status_block);
7221 val_lo = BCE_ADDR_LO(sc->status_block);
7222 if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7223 "virtual address\n", val_hi, val_lo);
7225 val_hi = BCE_ADDR_HI(sc->stats_block);
7226 val_lo = BCE_ADDR_LO(sc->stats_block);
7227 if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7228 "virtual address\n", val_hi, val_lo);
7230 val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7231 val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7232 if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7233 "virtual adddress\n", val_hi, val_lo);
7235 val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7236 val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7237 if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7238 "virtual address\n", val_hi, val_lo);
7240 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7241 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7242 if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7243 "virtual address\n", val_hi, val_lo);
7245 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7246 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7247 if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7248 "virtual address\n", val_hi, val_lo);
7250 if_printf(ifp, " 0x%08X - (sc->interrupts_generated) "
7251 "h/w intrs\n", sc->interrupts_generated);
7253 if_printf(ifp, " 0x%08X - (sc->rx_interrupts) "
7254 "rx interrupts handled\n", sc->rx_interrupts);
7256 if_printf(ifp, " 0x%08X - (sc->tx_interrupts) "
7257 "tx interrupts handled\n", sc->tx_interrupts);
7259 if_printf(ifp, " 0x%08X - (sc->last_status_idx) "
7260 "status block index\n", sc->last_status_idx);
7262 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_prod) "
7263 "tx producer index\n",
7264 sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
7266 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_cons) "
7267 "tx consumer index\n",
7268 sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
7270 if_printf(ifp, " 0x%08X - (sc->tx_prod_bseq) "
7271 "tx producer bseq index\n", sc->tx_prod_bseq);
7273 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_prod) "
7274 "rx producer index\n",
7275 sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
7277 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_cons) "
7278 "rx consumer index\n",
7279 sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
7281 if_printf(ifp, " 0x%08X - (sc->rx_prod_bseq) "
7282 "rx producer bseq index\n", sc->rx_prod_bseq);
7284 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7285 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7287 if_printf(ifp, " 0x%08X - (sc->free_rx_bd) "
7288 "free rx_bd's\n", sc->free_rx_bd);
7290 if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7291 "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7293 if_printf(ifp, " 0x%08X - (sc->txmbuf_alloc) "
7294 "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7296 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7297 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7299 if_printf(ifp, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7302 if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7303 sc->tx_hi_watermark, sc->max_tx_bd);
7305 if_printf(ifp, " 0x%08X - (sc->mbuf_alloc_failed) "
7306 "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7309 "----------------------------"
7311 "----------------------------\n");
7315 /****************************************************************************/
7316 /* Prints out the hardware state through a summary of important registers, */
7317 /* followed by a complete register dump. */
7321 /****************************************************************************/
7323 bce_dump_hw_state(struct bce_softc *sc)
7325 struct ifnet *ifp = &sc->arpcom.ac_if;
7330 "----------------------------"
7332 "----------------------------\n");
7334 if_printf(ifp, "0x%08X - bootcode version\n", sc->bce_fw_ver);
7336 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7337 if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7338 val1, BCE_MISC_ENABLE_STATUS_BITS);
7340 val1 = REG_RD(sc, BCE_DMA_STATUS);
7341 if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7343 val1 = REG_RD(sc, BCE_CTX_STATUS);
7344 if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7346 val1 = REG_RD(sc, BCE_EMAC_STATUS);
7347 if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7348 val1, BCE_EMAC_STATUS);
7350 val1 = REG_RD(sc, BCE_RPM_STATUS);
7351 if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7353 val1 = REG_RD(sc, BCE_TBDR_STATUS);
7354 if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7355 val1, BCE_TBDR_STATUS);
7357 val1 = REG_RD(sc, BCE_TDMA_STATUS);
7358 if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7359 val1, BCE_TDMA_STATUS);
7361 val1 = REG_RD(sc, BCE_HC_STATUS);
7362 if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7364 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7365 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7366 val1, BCE_TXP_CPU_STATE);
7368 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7369 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7370 val1, BCE_TPAT_CPU_STATE);
7372 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7373 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7374 val1, BCE_RXP_CPU_STATE);
7376 val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7377 if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7378 val1, BCE_COM_CPU_STATE);
7380 val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7381 if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7382 val1, BCE_MCP_CPU_STATE);
7384 val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7385 if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7386 val1, BCE_CP_CPU_STATE);
7389 "----------------------------"
7391 "----------------------------\n");
7394 "----------------------------"
7396 "----------------------------\n");
7398 for (i = 0x400; i < 0x8000; i += 0x10) {
7399 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7401 REG_RD(sc, i + 0x4),
7402 REG_RD(sc, i + 0x8),
7403 REG_RD(sc, i + 0xc));
7407 "----------------------------"
7409 "----------------------------\n");
7413 /****************************************************************************/
7414 /* Prints out the TXP state. */
7418 /****************************************************************************/
7420 bce_dump_txp_state(struct bce_softc *sc)
7422 struct ifnet *ifp = &sc->arpcom.ac_if;
7427 "----------------------------"
7429 "----------------------------\n");
7431 val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7432 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7433 val1, BCE_TXP_CPU_MODE);
7435 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7436 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7437 val1, BCE_TXP_CPU_STATE);
7439 val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7440 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7441 val1, BCE_TXP_CPU_EVENT_MASK);
7444 "----------------------------"
7446 "----------------------------\n");
7448 for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7449 /* Skip the big blank spaces */
7450 if (i < 0x454000 && i > 0x5ffff) {
7451 if_printf(ifp, "0x%04X: "
7452 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7454 REG_RD_IND(sc, i + 0x4),
7455 REG_RD_IND(sc, i + 0x8),
7456 REG_RD_IND(sc, i + 0xc));
7461 "----------------------------"
7463 "----------------------------\n");
7467 /****************************************************************************/
7468 /* Prints out the RXP state. */
7472 /****************************************************************************/
7474 bce_dump_rxp_state(struct bce_softc *sc)
7476 struct ifnet *ifp = &sc->arpcom.ac_if;
7481 "----------------------------"
7483 "----------------------------\n");
7485 val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7486 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7487 val1, BCE_RXP_CPU_MODE);
7489 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7490 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7491 val1, BCE_RXP_CPU_STATE);
7493 val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7494 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7495 val1, BCE_RXP_CPU_EVENT_MASK);
7498 "----------------------------"
7500 "----------------------------\n");
7502 for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7503 /* Skip the big blank sapces */
7504 if (i < 0xc5400 && i > 0xdffff) {
7505 if_printf(ifp, "0x%04X: "
7506 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7508 REG_RD_IND(sc, i + 0x4),
7509 REG_RD_IND(sc, i + 0x8),
7510 REG_RD_IND(sc, i + 0xc));
7515 "----------------------------"
7517 "----------------------------\n");
7521 /****************************************************************************/
7522 /* Prints out the TPAT state. */
7526 /****************************************************************************/
7528 bce_dump_tpat_state(struct bce_softc *sc)
7530 struct ifnet *ifp = &sc->arpcom.ac_if;
7535 "----------------------------"
7537 "----------------------------\n");
7539 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7540 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7541 val1, BCE_TPAT_CPU_MODE);
7543 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7544 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7545 val1, BCE_TPAT_CPU_STATE);
7547 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7548 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7549 val1, BCE_TPAT_CPU_EVENT_MASK);
7552 "----------------------------"
7554 "----------------------------\n");
7556 for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7557 /* Skip the big blank spaces */
7558 if (i < 0x854000 && i > 0x9ffff) {
7559 if_printf(ifp, "0x%04X: "
7560 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7562 REG_RD_IND(sc, i + 0x4),
7563 REG_RD_IND(sc, i + 0x8),
7564 REG_RD_IND(sc, i + 0xc));
7569 "----------------------------"
7571 "----------------------------\n");
7575 /****************************************************************************/
7576 /* Prints out the driver state and then enters the debugger. */
7580 /****************************************************************************/
7582 bce_breakpoint(struct bce_softc *sc)
7585 bce_freeze_controller(sc);
7588 bce_dump_driver_state(sc);
7589 bce_dump_status_block(sc);
7590 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7591 bce_dump_hw_state(sc);
7592 bce_dump_txp_state(sc);
7595 bce_unfreeze_controller(sc);
7598 /* Call the debugger. */
7602 #endif /* BCE_DEBUG */
7605 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7607 struct bce_softc *sc = arg1;
7609 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7610 &sc->bce_tx_quick_cons_trip_int,
7611 BCE_COALMASK_TX_BDS_INT);
7615 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7617 struct bce_softc *sc = arg1;
7619 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7620 &sc->bce_tx_quick_cons_trip,
7621 BCE_COALMASK_TX_BDS);
7625 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7627 struct bce_softc *sc = arg1;
7629 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7630 &sc->bce_tx_ticks_int,
7631 BCE_COALMASK_TX_TICKS_INT);
7635 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7637 struct bce_softc *sc = arg1;
7639 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7641 BCE_COALMASK_TX_TICKS);
7645 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7647 struct bce_softc *sc = arg1;
7649 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7650 &sc->bce_rx_quick_cons_trip_int,
7651 BCE_COALMASK_RX_BDS_INT);
7655 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7657 struct bce_softc *sc = arg1;
7659 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7660 &sc->bce_rx_quick_cons_trip,
7661 BCE_COALMASK_RX_BDS);
7665 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7667 struct bce_softc *sc = arg1;
7669 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7670 &sc->bce_rx_ticks_int,
7671 BCE_COALMASK_RX_TICKS_INT);
7675 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7677 struct bce_softc *sc = arg1;
7679 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7681 BCE_COALMASK_RX_TICKS);
7685 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7686 uint32_t coalchg_mask)
7688 struct bce_softc *sc = arg1;
7689 struct ifnet *ifp = &sc->arpcom.ac_if;
7692 lwkt_serialize_enter(ifp->if_serializer);
7695 error = sysctl_handle_int(oidp, &v, 0, req);
7696 if (!error && req->newptr != NULL) {
7701 sc->bce_coalchg_mask |= coalchg_mask;
7705 lwkt_serialize_exit(ifp->if_serializer);
7710 bce_coal_change(struct bce_softc *sc)
7712 struct ifnet *ifp = &sc->arpcom.ac_if;
7714 ASSERT_SERIALIZED(ifp->if_serializer);
7716 if ((ifp->if_flags & IFF_RUNNING) == 0) {
7717 sc->bce_coalchg_mask = 0;
7721 if (sc->bce_coalchg_mask &
7722 (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7723 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7724 (sc->bce_tx_quick_cons_trip_int << 16) |
7725 sc->bce_tx_quick_cons_trip);
7727 if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7728 sc->bce_tx_quick_cons_trip,
7729 sc->bce_tx_quick_cons_trip_int);
7733 if (sc->bce_coalchg_mask &
7734 (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7735 REG_WR(sc, BCE_HC_TX_TICKS,
7736 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7738 if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7739 sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7743 if (sc->bce_coalchg_mask &
7744 (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7745 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7746 (sc->bce_rx_quick_cons_trip_int << 16) |
7747 sc->bce_rx_quick_cons_trip);
7749 if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7750 sc->bce_rx_quick_cons_trip,
7751 sc->bce_rx_quick_cons_trip_int);
7755 if (sc->bce_coalchg_mask &
7756 (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7757 REG_WR(sc, BCE_HC_RX_TICKS,
7758 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7760 if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7761 sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7765 sc->bce_coalchg_mask = 0;