2 * Copyright (c) 2001-2011, Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
40 #define IGB_MAX_RING_82575 4
41 #define IGB_MAX_RING_I350 8
42 #define IGB_MAX_RING_82580 8
43 #define IGB_MAX_RING_82576 16
44 #define IGB_MIN_RING 1
45 #define IGB_MIN_RING_RSS 2
48 * Max TX/RX interrupt bits
50 #define IGB_MAX_TXRXINT_82575 4 /* XXX not used */
51 #define IGB_MAX_TXRXINT_I350 8
52 #define IGB_MAX_TXRXINT_82580 8
53 #define IGB_MAX_TXRXINT_82576 16
54 #define IGB_MIN_TXRXINT 2 /* XXX VF? */
57 * IGB_TXD: Maximum number of Transmit Descriptors
59 * This value is the number of transmit descriptors allocated by the driver.
60 * Increasing this value allows the driver to queue more transmits. Each
61 * descriptor is 16 bytes.
62 * Since TDLEN should be multiple of 128bytes, the number of transmit
63 * desscriptors should meet the following condition.
64 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
66 #define IGB_MIN_TXD 256
67 #define IGB_DEFAULT_TXD 1024
68 #define IGB_MAX_TXD 4096
71 * IGB_RXD: Maximum number of Transmit Descriptors
73 * This value is the number of receive descriptors allocated by the driver.
74 * Increasing this value allows the driver to buffer more incoming packets.
75 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
76 * descriptor. The maximum MTU size is 16110.
77 * Since TDLEN should be multiple of 128bytes, the number of transmit
78 * desscriptors should meet the following condition.
79 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
81 #define IGB_MIN_RXD 256
82 #define IGB_DEFAULT_RXD 1024
83 #define IGB_MAX_RXD 4096
86 * This parameter controls when the driver calls the routine to reclaim
87 * transmit descriptors. Cleaning earlier seems a win.
89 #define IGB_TX_CLEANUP_THRESHOLD(sc) ((sc)->num_tx_desc / 2)
92 * This parameter controls whether or not autonegotation is enabled.
93 * 0 - Disable autonegotiation
94 * 1 - Enable autonegotiation
99 * This parameter control whether or not the driver will wait for
100 * autonegotiation to complete.
101 * 1 - Wait for autonegotiation to complete
102 * 0 - Don't wait for autonegotiation to complete
104 #define WAIT_FOR_AUTO_NEG_DEFAULT 0
106 /* Tunables -- End */
108 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
109 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
112 #define AUTO_ALL_MODES 0
114 /* PHY master/slave setting */
115 #define IGB_MASTER_SLAVE e1000_ms_hw_default
118 * Micellaneous constants
120 #define IGB_VENDOR_ID 0x8086
122 #define IGB_JUMBO_PBA 0x00000028
123 #define IGB_DEFAULT_PBA 0x00000030
124 #define IGB_SMARTSPEED_DOWNSHIFT 3
125 #define IGB_SMARTSPEED_MAX 15
126 #define IGB_MAX_LOOP 10
128 #define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8)
129 #define IGB_RX_HTHRESH 8
130 #define IGB_RX_WTHRESH 1
132 #define IGB_TX_PTHRESH 8
133 #define IGB_TX_HTHRESH 1
134 #define IGB_TX_WTHRESH 16
136 #define MAX_NUM_MULTICAST_ADDRESSES 128
137 #define IGB_FC_PAUSE_TIME 0x0680
139 #define IGB_INTR_RATE 10000
142 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
143 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
144 * also optimize cache line size effect. H/W supports up to cache line size 128.
146 #define IGB_DBA_ALIGN 128
148 /* PCI Config defines */
149 #define IGB_MSIX_BAR 3
151 #define IGB_MAX_SCATTER 64
152 #define IGB_VFTA_SIZE 128
153 #define IGB_TSO_SIZE (65535 + \
154 sizeof(struct ether_vlan_header))
155 #define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */
156 #define IGB_HDR_BUF 128
157 #define IGB_PKTTYPE_MASK 0x0000FFF0
159 #define IGB_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
160 #define IGB_IPVHL_SIZE 1 /* sizeof(ip.ip_vhl) */
161 #define IGB_TXCSUM_MINHL (ETHER_HDR_LEN + EVL_ENCAPLEN + \
164 /* One for TX csum offloading desc, the other 2 are reserved */
165 #define IGB_TX_RESERVED 3
167 /* Large enough for 64K TSO */
168 #define IGB_TX_SPARE 32
170 #define IGB_TX_OACTIVE_MAX 64
172 /* main + 16x RX + 16x TX */
173 #define IGB_NSERIALIZE 33
175 #define IGB_NRSSRK 10
176 #define IGB_RSSRK_SIZE 4
177 #define IGB_RSSRK_VAL(key, i) (key[(i) * IGB_RSSRK_SIZE] | \
178 key[(i) * IGB_RSSRK_SIZE + 1] << 8 | \
179 key[(i) * IGB_RSSRK_SIZE + 2] << 16 | \
180 key[(i) * IGB_RSSRK_SIZE + 3] << 24)
183 #define IGB_RETA_SIZE 4
184 #define IGB_RETA_SHIFT 0
185 #define IGB_RETA_SHIFT_82575 6
190 * Bus dma information structure
193 bus_addr_t dma_paddr;
195 bus_dma_tag_t dma_tag;
196 bus_dmamap_t dma_map;
200 * Transmit ring: one per queue
203 struct lwkt_serialize tx_serialize;
204 struct igb_softc *sc;
206 struct igb_dma txdma;
207 bus_dma_tag_t tx_hdr_dtag;
208 bus_dmamap_t tx_hdr_dmap;
209 bus_addr_t tx_hdr_paddr;
210 struct e1000_tx_desc *tx_base;
212 uint32_t next_avail_desc;
213 uint32_t next_to_clean;
216 struct igb_tx_buf *tx_buf;
217 bus_dma_tag_t tx_tag;
224 uint32_t tx_intr_mask;
226 u_long no_desc_avail;
229 u_long ctx_try_pullup;
233 u_long ctx_pullup1_failed;
235 u_long ctx_pullup2_failed;
239 * Receive ring: one per queue
242 struct lwkt_serialize rx_serialize;
243 struct igb_softc *sc;
245 struct igb_dma rxdma;
246 union e1000_adv_rx_desc *rx_base;
249 uint32_t next_to_check;
250 struct igb_rx_buf *rx_buf;
251 bus_dma_tag_t rx_tag;
252 bus_dmamap_t rx_sparemap;
254 uint32_t rx_intr_mask;
257 * First/last mbuf pointers, for
258 * collecting multisegment RX packets.
268 struct arpcom arpcom;
271 struct e1000_osdep osdep;
274 #define IGB_FLAG_SHARED_INTR 0x1
275 #define IGB_FLAG_HAS_MGMT 0x2
277 bus_dma_tag_t parent_tag;
280 struct resource *mem_res;
282 struct ifmedia media;
283 struct callout timer;
287 struct resource *intr_res;
293 uint16_t vf_ifp; /* a VF interface */
295 /* Management and WOL features */
298 /* Info about the interface */
301 uint16_t link_duplex;
303 uint32_t dma_coalesce;
305 /* Multicast array pointer */
311 struct lwkt_serialize *serializes[IGB_NSERIALIZE];
312 struct lwkt_serialize main_serialize;
321 struct igb_tx_ring *tx_rings;
329 struct igb_rx_ring *rx_rings;
331 /* Misc stats maintained by the driver */
333 u_long mbuf_defrag_failed;
334 u_long no_tx_dma_setup;
335 u_long watchdog_events;
337 u_long device_control;
341 u_long packet_buf_alloc_rx;
342 u_long packet_buf_alloc_tx;
344 /* sysctl tree glue */
345 struct sysctl_ctx_list sysctl_ctx;
346 struct sysctl_oid *sysctl_tree;
351 #define IGB_ENABLE_HWRSS(sc) ((sc)->rx_ring_cnt > 1)
355 bus_dmamap_t map; /* bus_dma map for packet */
360 bus_dmamap_t map; /* bus_dma map for packet */
364 #define UPDATE_VF_REG(reg, last, cur) \
366 uint32_t new = E1000_READ_REG(hw, reg); \
368 cur += 0x100000000LL; \
370 cur &= 0xFFFFFFFF00000000LL; \
374 #define IGB_IS_OACTIVE(txr) ((txr)->tx_avail < (txr)->oact_lo_desc)
375 #define IGB_IS_NOT_OACTIVE(txr) ((txr)->tx_avail >= (txr)->oact_hi_desc)
377 #endif /* _IF_IGB_H_ */