2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_SIZE (0x10000)
75 #define BIOS_COUNT (BIOS_SIZE/4)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
82 #define PROCENTRY_FLAG_EN 0x01
83 #define PROCENTRY_FLAG_BP 0x02
84 #define IOAPICENTRY_FLAG_EN 0x01
87 /* MP Floating Pointer Structure */
88 typedef struct MPFPS {
101 /* MP Configuration Table Header */
102 typedef struct MPCTH {
104 u_short base_table_length;
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
119 typedef struct PROCENTRY {
124 u_long cpu_signature;
125 u_long feature_flags;
130 typedef struct BUSENTRY {
136 typedef struct IOAPICENTRY {
142 } *io_apic_entry_ptr;
144 typedef struct INTENTRY {
154 /* descriptions of MP basetable entries */
155 typedef struct BASETABLE_ENTRY {
164 vm_size_t mp_cth_mapsz;
167 typedef int (*mptable_iter_func)(void *, const void *, int);
170 * this code MUST be enabled here and in mpboot.s.
171 * it follows the very early stages of AP boot by placing values in CMOS ram.
172 * it NORMALLY will never be needed and thus the primitive method for enabling.
175 #if defined(CHECK_POINTS)
176 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
177 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
179 #define CHECK_INIT(D); \
180 CHECK_WRITE(0x34, (D)); \
181 CHECK_WRITE(0x35, (D)); \
182 CHECK_WRITE(0x36, (D)); \
183 CHECK_WRITE(0x37, (D)); \
184 CHECK_WRITE(0x38, (D)); \
185 CHECK_WRITE(0x39, (D));
187 #define CHECK_PRINT(S); \
188 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
197 #else /* CHECK_POINTS */
199 #define CHECK_INIT(D)
200 #define CHECK_PRINT(S)
202 #endif /* CHECK_POINTS */
205 * Values to send to the POST hardware.
207 #define MP_BOOTADDRESS_POST 0x10
208 #define MP_PROBE_POST 0x11
209 #define MPTABLE_PASS1_POST 0x12
211 #define MP_START_POST 0x13
212 #define MP_ENABLE_POST 0x14
213 #define MPTABLE_PASS2_POST 0x15
215 #define START_ALL_APS_POST 0x16
216 #define INSTALL_AP_TRAMP_POST 0x17
217 #define START_AP_POST 0x18
219 #define MP_ANNOUNCE_POST 0x19
221 static int madt_probe_test;
222 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
224 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
225 int current_postcode;
227 /** XXX FIXME: what system files declare these??? */
228 extern struct region_descriptor r_gdt, r_idt;
230 int mp_naps; /* # of Applications processors */
232 static int mp_nbusses; /* # of busses */
233 int mp_napics; /* # of IO APICs */
235 static vm_offset_t cpu_apic_address;
237 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
238 u_int32_t *io_apic_versions;
242 u_int32_t cpu_apic_versions[MAXCPU];
244 extern int64_t tsc_offsets[];
246 extern u_long ebda_addr;
249 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
253 * APIC ID logical/physical mapping structures.
254 * We oversize these to simplify boot-time config.
256 int cpu_num_to_apic_id[NAPICID];
258 int io_num_to_apic_id[NAPICID];
260 int apic_id_to_logical[NAPICID];
262 /* AP uses this during bootstrap. Do not staticize. */
266 /* Hotwire a 0->4MB V==P mapping */
267 extern pt_entry_t *KPTphys;
270 * SMP page table page. Setup by locore to point to a page table
271 * page from which we allocate per-cpu privatespace areas io_apics,
275 #define IO_MAPPING_START_INDEX \
276 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
278 extern pt_entry_t *SMPpt;
279 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
281 struct pcb stoppcbs[MAXCPU];
283 static basetable_entry basetable_entry_types[] =
285 {0, 20, "Processor"},
293 * Local data and functions.
296 static u_int boot_address;
297 static u_int base_memory;
298 static int mp_finish;
300 static void mp_enable(u_int boot_addr);
302 static int mptable_iterate_entries(const mpcth_t,
303 mptable_iter_func, void *);
304 static int mptable_probe(void);
305 static int mptable_search(void);
306 static int mptable_check(vm_paddr_t);
307 static int mptable_search_sig(u_int32_t target, int count);
308 static int mptable_hyperthread_fixup(u_int, int);
309 static void mptable_pass1(struct mptable_pos *);
310 static void mptable_pass2(struct mptable_pos *);
311 static void mptable_default(int type);
312 static void mptable_fix(void);
313 static int mptable_map(struct mptable_pos *, vm_paddr_t);
314 static void mptable_unmap(struct mptable_pos *);
315 static void mptable_lapic_enumerate(struct mptable_pos *);
316 static void mptable_lapic_default(void);
317 static void mptable_imcr(struct mptable_pos *);
320 static void setup_apic_irq_mapping(void);
321 static int apic_int_is_bus_type(int intr, int bus_type);
323 static int start_all_aps(u_int boot_addr);
324 static void install_ap_tramp(u_int boot_addr);
325 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
326 static void lapic_init(vm_offset_t);
328 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
329 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
330 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
333 * Calculate usable address in base memory for AP trampoline code.
336 mp_bootaddress(u_int basemem)
338 POSTCODE(MP_BOOTADDRESS_POST);
340 base_memory = basemem;
342 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
343 if ((base_memory - boot_address) < bootMP_size)
344 boot_address -= 4096; /* not enough, lower by 4k */
355 mpfps_paddr = mptable_search();
356 if (mptable_check(mpfps_paddr))
363 * Look for an Intel MP spec table (ie, SMP capable hardware).
372 * Make sure our SMPpt[] page table is big enough to hold all the
375 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
377 POSTCODE(MP_PROBE_POST);
379 /* see if EBDA exists */
380 if (ebda_addr != 0) {
381 /* search first 1K of EBDA */
382 target = (u_int32_t)ebda_addr;
383 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
386 /* last 1K of base memory, effective 'top of base' passed in */
387 target = (u_int32_t)(base_memory - 0x400);
388 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
392 /* search the BIOS */
393 target = (u_int32_t)BIOS_BASE;
394 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
401 struct mptable_check_cbarg {
407 mptable_check_callback(void *xarg, const void *pos, int type)
409 const struct PROCENTRY *ent;
410 struct mptable_check_cbarg *arg = xarg;
416 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
420 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
421 if (arg->found_bsp) {
422 kprintf("more than one BSP in base MP table\n");
431 mptable_check(vm_paddr_t mpfps_paddr)
433 struct mptable_pos mpt;
434 struct mptable_check_cbarg arg;
438 if (mpfps_paddr == 0)
441 error = mptable_map(&mpt, mpfps_paddr);
445 if (mpt.mp_fps->mpfb1 != 0)
453 if (cth->apic_address == 0)
456 bzero(&arg, sizeof(arg));
457 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
459 if (arg.cpu_count == 0) {
460 kprintf("MP table contains no processor entries\n");
462 } else if (!arg.found_bsp) {
463 kprintf("MP table does not contains BSP entry\n");
473 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
475 int count, total_size;
476 const void *position;
478 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
479 total_size = cth->base_table_length - sizeof(struct MPCTH);
480 position = (const uint8_t *)cth + sizeof(struct MPCTH);
481 count = cth->entry_count;
486 KKASSERT(total_size >= 0);
487 if (total_size == 0) {
488 kprintf("invalid base MP table, "
489 "entry count and length mismatch\n");
493 type = *(const uint8_t *)position;
495 case 0: /* processor_entry */
496 case 1: /* bus_entry */
497 case 2: /* io_apic_entry */
498 case 3: /* int_entry */
499 case 4: /* int_entry */
502 kprintf("unknown base MP table entry type %d\n", type);
506 if (total_size < basetable_entry_types[type].length) {
507 kprintf("invalid base MP table length, "
508 "does not contain all entries\n");
511 total_size -= basetable_entry_types[type].length;
513 error = func(arg, position, type);
517 position = (const uint8_t *)position +
518 basetable_entry_types[type].length;
525 * Startup the SMP processors.
530 POSTCODE(MP_START_POST);
531 mp_enable(boot_address);
536 * Print various information about the SMP system hardware and setup.
543 POSTCODE(MP_ANNOUNCE_POST);
545 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
546 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
547 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
548 kprintf(", at 0x%08x\n", cpu_apic_address);
549 for (x = 1; x <= mp_naps; ++x) {
550 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
551 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
552 kprintf(", at 0x%08x\n", cpu_apic_address);
556 for (x = 0; x < mp_napics; ++x) {
557 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
558 kprintf(", version: 0x%08x", io_apic_versions[x]);
559 kprintf(", at 0x%08x\n", io_apic_address[x]);
562 kprintf(" Warning: APIC I/O disabled\n");
567 * AP cpu's call this to sync up protected mode.
569 * WARNING! We must ensure that the cpu is sufficiently initialized to
570 * be able to use to the FP for our optimized bzero/bcopy code before
571 * we enter more mainstream C code.
573 * WARNING! %fs is not set up on entry. This routine sets up %fs.
579 int x, myid = bootAP;
581 struct mdglobaldata *md;
582 struct privatespace *ps;
584 ps = &CPU_prvspace[myid];
586 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
587 gdt_segs[GPROC0_SEL].ssd_base =
588 (int) &ps->mdglobaldata.gd_common_tss;
589 ps->mdglobaldata.mi.gd_prvspace = ps;
591 for (x = 0; x < NGDT; x++) {
592 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
595 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
596 r_gdt.rd_base = (int) &gdt[myid * NGDT];
597 lgdt(&r_gdt); /* does magic intra-segment return */
602 mdcpu->gd_currentldt = _default_ldt;
604 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
605 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
607 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
609 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
610 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
611 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
612 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
613 md->gd_common_tssd = *md->gd_tss_gdt;
617 * Set to a known state:
618 * Set by mpboot.s: CR0_PG, CR0_PE
619 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
622 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
624 pmap_set_opt(); /* PSE/4MB pages, etc */
626 /* set up CPU registers and state */
629 /* set up FPU state on the AP */
630 npxinit(__INITIAL_NPXCW__);
632 /* set up SSE registers */
636 /*******************************************************************
637 * local functions and data
641 * start the SMP system
644 mp_enable(u_int boot_addr)
650 vm_paddr_t mpfps_paddr;
652 POSTCODE(MP_ENABLE_POST);
654 if (madt_probe_test) {
657 mpfps_paddr = mptable_probe();
661 struct mptable_pos mpt;
663 mptable_map(&mpt, mpfps_paddr);
665 mptable_lapic_enumerate(&mpt);
670 * Examine the MP table for needed info
677 /* Post scan cleanup */
680 vm_paddr_t madt_paddr;
681 vm_offset_t lapic_addr;
684 madt_paddr = madt_probe();
686 panic("mp_enable: madt_probe failed\n");
688 lapic_addr = madt_pass1(madt_paddr);
690 panic("mp_enable: no local apic (madt)!\n");
692 lapic_init(lapic_addr);
694 bsp_apic_id = APIC_ID(lapic.id);
695 if (madt_pass2(madt_paddr, bsp_apic_id))
696 panic("mp_enable: madt_pass2 failed\n");
701 setup_apic_irq_mapping();
703 /* fill the LOGICAL io_apic_versions table */
704 for (apic = 0; apic < mp_napics; ++apic) {
705 ux = io_apic_read(apic, IOAPIC_VER);
706 io_apic_versions[apic] = ux;
707 io_apic_set_id(apic, IO_TO_ID(apic));
710 /* program each IO APIC in the system */
711 for (apic = 0; apic < mp_napics; ++apic)
712 if (io_apic_setup(apic) < 0)
713 panic("IO APIC setup failure");
718 * These are required for SMP operation
721 /* install a 'Spurious INTerrupt' vector */
722 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
723 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
725 /* install an inter-CPU IPI for TLB invalidation */
726 setidt(XINVLTLB_OFFSET, Xinvltlb,
727 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
729 /* install an inter-CPU IPI for IPIQ messaging */
730 setidt(XIPIQ_OFFSET, Xipiq,
731 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
733 /* install a timer vector */
734 setidt(XTIMER_OFFSET, Xtimer,
735 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
737 /* install an inter-CPU IPI for CPU stop/restart */
738 setidt(XCPUSTOP_OFFSET, Xcpustop,
739 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
741 /* start each Application Processor */
742 start_all_aps(boot_addr);
747 * look for the MP spec signature
750 /* string defined by the Intel MP Spec as identifying the MP table */
751 #define MP_SIG 0x5f504d5f /* _MP_ */
752 #define NEXT(X) ((X) += 4)
754 mptable_search_sig(u_int32_t target, int count)
760 KKASSERT(target != 0);
762 map_size = count * sizeof(u_int32_t);
763 addr = pmap_mapdev((vm_paddr_t)target, map_size);
766 for (x = 0; x < count; NEXT(x)) {
767 if (addr[x] == MP_SIG) {
768 /* make array index a byte index */
769 ret = target + (x * sizeof(u_int32_t));
774 pmap_unmapdev((vm_offset_t)addr, map_size);
779 typedef struct BUSDATA {
781 enum busTypes bus_type;
784 typedef struct INTDATA {
794 typedef struct BUSTYPENAME {
799 static bus_type_name bus_type_table[] =
805 {UNKNOWN_BUSTYPE, "---"},
808 {UNKNOWN_BUSTYPE, "---"},
809 {UNKNOWN_BUSTYPE, "---"},
810 {UNKNOWN_BUSTYPE, "---"},
811 {UNKNOWN_BUSTYPE, "---"},
812 {UNKNOWN_BUSTYPE, "---"},
814 {UNKNOWN_BUSTYPE, "---"},
815 {UNKNOWN_BUSTYPE, "---"},
816 {UNKNOWN_BUSTYPE, "---"},
817 {UNKNOWN_BUSTYPE, "---"},
819 {UNKNOWN_BUSTYPE, "---"}
821 /* from MP spec v1.4, table 5-1 */
822 static int default_data[7][5] =
824 /* nbus, id0, type0, id1, type1 */
825 {1, 0, ISA, 255, 255},
826 {1, 0, EISA, 255, 255},
827 {1, 0, EISA, 255, 255},
828 {1, 0, MCA, 255, 255},
830 {2, 0, EISA, 1, PCI},
838 static bus_datum *bus_data;
840 /* the IO INT data, one entry per possible APIC INTerrupt */
841 static io_int *io_apic_ints;
846 static int processor_entry (const struct PROCENTRY *entry, int cpu);
848 static int bus_entry (const struct BUSENTRY *entry, int bus);
849 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
850 static int int_entry (const struct INTENTRY *entry, int intr);
852 static int lookup_bus_type (char *name);
857 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
859 const struct IOAPICENTRY *ioapic_ent;
862 case 1: /* bus_entry */
866 case 2: /* io_apic_entry */
868 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
869 io_apic_address[mp_napics++] =
870 (vm_offset_t)ioapic_ent->apic_address;
874 case 3: /* int_entry */
884 * 1st pass on motherboard's Intel MP specification table.
893 mptable_pass1(struct mptable_pos *mpt)
899 POSTCODE(MPTABLE_PASS1_POST);
902 KKASSERT(fps != NULL);
904 /* clear various tables */
905 for (x = 0; x < NAPICID; ++x)
906 io_apic_address[x] = ~0; /* IO APIC address table */
912 /* check for use of 'default' configuration */
913 if (fps->mpfb1 != 0) {
914 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
915 mp_nbusses = default_data[fps->mpfb1 - 1][0];
921 error = mptable_iterate_entries(mpt->mp_cth,
922 mptable_ioapic_pass1_callback, NULL);
924 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
931 struct mptable_ioapic2_cbarg {
938 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
940 struct mptable_ioapic2_cbarg *arg = xarg;
944 if (bus_entry(pos, arg->bus))
949 if (io_apic_entry(pos, arg->apic))
954 if (int_entry(pos, arg->intr))
964 * 2nd pass on motherboard's Intel MP specification table.
967 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
968 * IO_TO_ID(N), logical IO to APIC ID table
973 mptable_pass2(struct mptable_pos *mpt)
976 struct mptable_ioapic2_cbarg arg;
980 POSTCODE(MPTABLE_PASS2_POST);
983 KKASSERT(fps != NULL);
985 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
987 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
988 M_DEVBUF, M_WAITOK | M_ZERO);
989 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
991 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
994 for (x = 0; x < mp_napics; x++)
995 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
997 /* clear various tables */
998 for (x = 0; x < NAPICID; ++x) {
999 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1000 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1003 /* clear bus data table */
1004 for (x = 0; x < mp_nbusses; ++x)
1005 bus_data[x].bus_id = 0xff;
1007 /* clear IO APIC INT table */
1008 for (x = 0; x < (nintrs + 1); ++x) {
1009 io_apic_ints[x].int_type = 0xff;
1010 io_apic_ints[x].int_vector = 0xff;
1013 /* check for use of 'default' configuration */
1014 if (fps->mpfb1 != 0) {
1015 mptable_default(fps->mpfb1);
1019 bzero(&arg, sizeof(arg));
1020 error = mptable_iterate_entries(mpt->mp_cth,
1021 mptable_ioapic_pass2_callback, &arg);
1023 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1028 * Check if we should perform a hyperthreading "fix-up" to
1029 * enumerate any logical CPU's that aren't already listed
1032 * XXX: We assume that all of the physical CPUs in the
1033 * system have the same number of logical CPUs.
1035 * XXX: We assume that APIC ID's are allocated such that
1036 * the APIC ID's for a physical processor are aligned
1037 * with the number of logical CPU's in the processor.
1040 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1042 int i, id, lcpus_max, logical_cpus;
1044 if ((cpu_feature & CPUID_HTT) == 0)
1047 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1051 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1053 * INSTRUCTION SET REFERENCE, A-M (#253666)
1054 * Page 3-181, Table 3-20
1055 * "The nearest power-of-2 integer that is not smaller
1056 * than EBX[23:16] is the number of unique initial APIC
1057 * IDs reserved for addressing different logical
1058 * processors in a physical package."
1060 for (i = 0; ; ++i) {
1061 if ((1 << i) >= lcpus_max) {
1068 KKASSERT(cpu_count != 0);
1069 if (cpu_count == lcpus_max) {
1070 /* We have nothing to fix */
1072 } else if (cpu_count == 1) {
1073 /* XXX this may be incorrect */
1074 logical_cpus = lcpus_max;
1076 int cur, prev, dist;
1079 * Calculate the distances between two nearest
1080 * APIC IDs. If all such distances are same,
1081 * then it is the number of missing cpus that
1082 * we are going to fill later.
1084 dist = cur = prev = -1;
1085 for (id = 0; id < MAXCPU; ++id) {
1086 if ((id_mask & 1 << id) == 0)
1091 int new_dist = cur - prev;
1097 * Make sure that all distances
1098 * between two nearest APIC IDs
1101 if (dist != new_dist)
1109 /* Must be power of 2 */
1110 if (dist & (dist - 1))
1113 /* Can't exceed CPU package capacity */
1114 if (dist > lcpus_max)
1115 logical_cpus = lcpus_max;
1117 logical_cpus = dist;
1121 * For each APIC ID of a CPU that is set in the mask,
1122 * scan the other candidate APIC ID's for this
1123 * physical processor. If any of those ID's are
1124 * already in the table, then kill the fixup.
1126 for (id = 0; id < MAXCPU; id++) {
1127 if ((id_mask & 1 << id) == 0)
1129 /* First, make sure we are on a logical_cpus boundary. */
1130 if (id % logical_cpus != 0)
1132 for (i = id + 1; i < id + logical_cpus; i++)
1133 if ((id_mask & 1 << i) != 0)
1136 return logical_cpus;
1140 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1144 vm_size_t cth_mapsz = 0;
1146 bzero(mpt, sizeof(*mpt));
1148 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1149 if (fps->pap != 0) {
1151 * Map configuration table header to get
1152 * the base table size
1154 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1155 cth_mapsz = cth->base_table_length;
1156 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1158 if (cth_mapsz < sizeof(*cth)) {
1159 kprintf("invalid base MP table length %d\n",
1161 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1166 * Map the base table
1168 cth = pmap_mapdev(fps->pap, cth_mapsz);
1173 mpt->mp_cth_mapsz = cth_mapsz;
1179 mptable_unmap(struct mptable_pos *mpt)
1181 if (mpt->mp_cth != NULL) {
1182 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1184 mpt->mp_cth_mapsz = 0;
1186 if (mpt->mp_fps != NULL) {
1187 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1195 assign_apic_irq(int apic, int intpin, int irq)
1199 if (int_to_apicintpin[irq].ioapic != -1)
1200 panic("assign_apic_irq: inconsistent table");
1202 int_to_apicintpin[irq].ioapic = apic;
1203 int_to_apicintpin[irq].int_pin = intpin;
1204 int_to_apicintpin[irq].apic_address = ioapic[apic];
1205 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1207 for (x = 0; x < nintrs; x++) {
1208 if ((io_apic_ints[x].int_type == 0 ||
1209 io_apic_ints[x].int_type == 3) &&
1210 io_apic_ints[x].int_vector == 0xff &&
1211 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1212 io_apic_ints[x].dst_apic_int == intpin)
1213 io_apic_ints[x].int_vector = irq;
1218 revoke_apic_irq(int irq)
1224 if (int_to_apicintpin[irq].ioapic == -1)
1225 panic("revoke_apic_irq: inconsistent table");
1227 oldapic = int_to_apicintpin[irq].ioapic;
1228 oldintpin = int_to_apicintpin[irq].int_pin;
1230 int_to_apicintpin[irq].ioapic = -1;
1231 int_to_apicintpin[irq].int_pin = 0;
1232 int_to_apicintpin[irq].apic_address = NULL;
1233 int_to_apicintpin[irq].redirindex = 0;
1235 for (x = 0; x < nintrs; x++) {
1236 if ((io_apic_ints[x].int_type == 0 ||
1237 io_apic_ints[x].int_type == 3) &&
1238 io_apic_ints[x].int_vector != 0xff &&
1239 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1240 io_apic_ints[x].dst_apic_int == oldintpin)
1241 io_apic_ints[x].int_vector = 0xff;
1249 allocate_apic_irq(int intr)
1255 if (io_apic_ints[intr].int_vector != 0xff)
1256 return; /* Interrupt handler already assigned */
1258 if (io_apic_ints[intr].int_type != 0 &&
1259 (io_apic_ints[intr].int_type != 3 ||
1260 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1261 io_apic_ints[intr].dst_apic_int == 0)))
1262 return; /* Not INT or ExtInt on != (0, 0) */
1265 while (irq < APIC_INTMAPSIZE &&
1266 int_to_apicintpin[irq].ioapic != -1)
1269 if (irq >= APIC_INTMAPSIZE)
1270 return; /* No free interrupt handlers */
1272 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1273 intpin = io_apic_ints[intr].dst_apic_int;
1275 assign_apic_irq(apic, intpin, irq);
1276 io_apic_setup_intpin(apic, intpin);
1281 swap_apic_id(int apic, int oldid, int newid)
1288 return; /* Nothing to do */
1290 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1291 apic, oldid, newid);
1293 /* Swap physical APIC IDs in interrupt entries */
1294 for (x = 0; x < nintrs; x++) {
1295 if (io_apic_ints[x].dst_apic_id == oldid)
1296 io_apic_ints[x].dst_apic_id = newid;
1297 else if (io_apic_ints[x].dst_apic_id == newid)
1298 io_apic_ints[x].dst_apic_id = oldid;
1301 /* Swap physical APIC IDs in IO_TO_ID mappings */
1302 for (oapic = 0; oapic < mp_napics; oapic++)
1303 if (IO_TO_ID(oapic) == newid)
1306 if (oapic < mp_napics) {
1307 kprintf("Changing APIC ID for IO APIC #%d from "
1308 "%d to %d in MP table\n",
1309 oapic, newid, oldid);
1310 IO_TO_ID(oapic) = oldid;
1312 IO_TO_ID(apic) = newid;
1317 fix_id_to_io_mapping(void)
1321 for (x = 0; x < NAPICID; x++)
1324 for (x = 0; x <= mp_naps; x++)
1325 if (CPU_TO_ID(x) < NAPICID)
1326 ID_TO_IO(CPU_TO_ID(x)) = x;
1328 for (x = 0; x < mp_napics; x++)
1329 if (IO_TO_ID(x) < NAPICID)
1330 ID_TO_IO(IO_TO_ID(x)) = x;
1335 first_free_apic_id(void)
1339 for (freeid = 0; freeid < NAPICID; freeid++) {
1340 for (x = 0; x <= mp_naps; x++)
1341 if (CPU_TO_ID(x) == freeid)
1345 for (x = 0; x < mp_napics; x++)
1346 if (IO_TO_ID(x) == freeid)
1357 io_apic_id_acceptable(int apic, int id)
1359 int cpu; /* Logical CPU number */
1360 int oapic; /* Logical IO APIC number for other IO APIC */
1363 return 0; /* Out of range */
1365 for (cpu = 0; cpu <= mp_naps; cpu++)
1366 if (CPU_TO_ID(cpu) == id)
1367 return 0; /* Conflict with CPU */
1369 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1370 if (IO_TO_ID(oapic) == id)
1371 return 0; /* Conflict with other APIC */
1373 return 1; /* ID is acceptable for IO APIC */
1378 io_apic_find_int_entry(int apic, int pin)
1382 /* search each of the possible INTerrupt sources */
1383 for (x = 0; x < nintrs; ++x) {
1384 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1385 (pin == io_apic_ints[x].dst_apic_int))
1386 return (&io_apic_ints[x]);
1394 * parse an Intel MP specification table
1402 int apic; /* IO APIC unit number */
1403 int freeid; /* Free physical APIC ID */
1404 int physid; /* Current physical IO APIC ID */
1406 int bus_0 = 0; /* Stop GCC warning */
1407 int bus_pci = 0; /* Stop GCC warning */
1411 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1412 * did it wrong. The MP spec says that when more than 1 PCI bus
1413 * exists the BIOS must begin with bus entries for the PCI bus and use
1414 * actual PCI bus numbering. This implies that when only 1 PCI bus
1415 * exists the BIOS can choose to ignore this ordering, and indeed many
1416 * MP motherboards do ignore it. This causes a problem when the PCI
1417 * sub-system makes requests of the MP sub-system based on PCI bus
1418 * numbers. So here we look for the situation and renumber the
1419 * busses and associated INTs in an effort to "make it right".
1422 /* find bus 0, PCI bus, count the number of PCI busses */
1423 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1424 if (bus_data[x].bus_id == 0) {
1427 if (bus_data[x].bus_type == PCI) {
1433 * bus_0 == slot of bus with ID of 0
1434 * bus_pci == slot of last PCI bus encountered
1437 /* check the 1 PCI bus case for sanity */
1438 /* if it is number 0 all is well */
1439 if (num_pci_bus == 1 &&
1440 bus_data[bus_pci].bus_id != 0) {
1442 /* mis-numbered, swap with whichever bus uses slot 0 */
1444 /* swap the bus entry types */
1445 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1446 bus_data[bus_0].bus_type = PCI;
1448 /* swap each relavant INTerrupt entry */
1449 id = bus_data[bus_pci].bus_id;
1450 for (x = 0; x < nintrs; ++x) {
1451 if (io_apic_ints[x].src_bus_id == id) {
1452 io_apic_ints[x].src_bus_id = 0;
1454 else if (io_apic_ints[x].src_bus_id == 0) {
1455 io_apic_ints[x].src_bus_id = id;
1460 /* Assign IO APIC IDs.
1462 * First try the existing ID. If a conflict is detected, try
1463 * the ID in the MP table. If a conflict is still detected, find
1466 * We cannot use the ID_TO_IO table before all conflicts has been
1467 * resolved and the table has been corrected.
1469 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1471 /* First try to use the value set by the BIOS */
1472 physid = io_apic_get_id(apic);
1473 if (io_apic_id_acceptable(apic, physid)) {
1474 if (IO_TO_ID(apic) != physid)
1475 swap_apic_id(apic, IO_TO_ID(apic), physid);
1479 /* Then check if the value in the MP table is acceptable */
1480 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1483 /* Last resort, find a free APIC ID and use it */
1484 freeid = first_free_apic_id();
1485 if (freeid >= NAPICID)
1486 panic("No free physical APIC IDs found");
1488 if (io_apic_id_acceptable(apic, freeid)) {
1489 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1492 panic("Free physical APIC ID not usable");
1494 fix_id_to_io_mapping();
1496 /* detect and fix broken Compaq MP table */
1497 if (apic_int_type(0, 0) == -1) {
1498 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1499 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1500 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1501 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1502 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1503 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1505 } else if (apic_int_type(0, 0) == 0) {
1506 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1507 for (x = 0; x < nintrs; ++x)
1508 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1509 (0 == io_apic_ints[x].dst_apic_int)) {
1510 io_apic_ints[x].int_type = 3;
1511 io_apic_ints[x].int_vector = 0xff;
1517 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1518 * controllers universally come in pairs. If IRQ 14 is specified
1519 * as an ISA interrupt, then IRQ 15 had better be too.
1521 * [ Shuttle XPC / AMD Athlon X2 ]
1522 * The MPTable is missing an entry for IRQ 15. Note that the
1523 * ACPI table has an entry for both 14 and 15.
1525 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1526 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1527 io14 = io_apic_find_int_entry(0, 14);
1528 io_apic_ints[nintrs] = *io14;
1529 io_apic_ints[nintrs].src_bus_irq = 15;
1530 io_apic_ints[nintrs].dst_apic_int = 15;
1538 /* Assign low level interrupt handlers */
1540 setup_apic_irq_mapping(void)
1546 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1547 int_to_apicintpin[x].ioapic = -1;
1548 int_to_apicintpin[x].int_pin = 0;
1549 int_to_apicintpin[x].apic_address = NULL;
1550 int_to_apicintpin[x].redirindex = 0;
1553 /* First assign ISA/EISA interrupts */
1554 for (x = 0; x < nintrs; x++) {
1555 int_vector = io_apic_ints[x].src_bus_irq;
1556 if (int_vector < APIC_INTMAPSIZE &&
1557 io_apic_ints[x].int_vector == 0xff &&
1558 int_to_apicintpin[int_vector].ioapic == -1 &&
1559 (apic_int_is_bus_type(x, ISA) ||
1560 apic_int_is_bus_type(x, EISA)) &&
1561 io_apic_ints[x].int_type == 0) {
1562 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1563 io_apic_ints[x].dst_apic_int,
1568 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1569 for (x = 0; x < nintrs; x++) {
1570 if (io_apic_ints[x].dst_apic_int == 0 &&
1571 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1572 io_apic_ints[x].int_vector == 0xff &&
1573 int_to_apicintpin[0].ioapic == -1 &&
1574 io_apic_ints[x].int_type == 3) {
1575 assign_apic_irq(0, 0, 0);
1579 /* PCI interrupt assignment is deferred */
1585 mp_set_cpuids(int cpu_id, int apic_id)
1587 CPU_TO_ID(cpu_id) = apic_id;
1588 ID_TO_CPU(apic_id) = cpu_id;
1592 processor_entry(const struct PROCENTRY *entry, int cpu)
1596 /* check for usability */
1597 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1600 /* check for BSP flag */
1601 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1602 mp_set_cpuids(0, entry->apic_id);
1603 return 0; /* its already been counted */
1606 /* add another AP to list, if less than max number of CPUs */
1607 else if (cpu < MAXCPU) {
1608 mp_set_cpuids(cpu, entry->apic_id);
1618 bus_entry(const struct BUSENTRY *entry, int bus)
1623 /* encode the name into an index */
1624 for (x = 0; x < 6; ++x) {
1625 if ((c = entry->bus_type[x]) == ' ')
1631 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1632 panic("unknown bus type: '%s'", name);
1634 bus_data[bus].bus_id = entry->bus_id;
1635 bus_data[bus].bus_type = x;
1641 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1643 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1646 IO_TO_ID(apic) = entry->apic_id;
1647 ID_TO_IO(entry->apic_id) = apic;
1655 lookup_bus_type(char *name)
1659 for (x = 0; x < MAX_BUSTYPE; ++x)
1660 if (strcmp(bus_type_table[x].name, name) == 0)
1661 return bus_type_table[x].type;
1663 return UNKNOWN_BUSTYPE;
1669 int_entry(const struct INTENTRY *entry, int intr)
1673 io_apic_ints[intr].int_type = entry->int_type;
1674 io_apic_ints[intr].int_flags = entry->int_flags;
1675 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1676 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1677 if (entry->dst_apic_id == 255) {
1678 /* This signal goes to all IO APICS. Select an IO APIC
1679 with sufficient number of interrupt pins */
1680 for (apic = 0; apic < mp_napics; apic++)
1681 if (((io_apic_read(apic, IOAPIC_VER) &
1682 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1683 entry->dst_apic_int)
1685 if (apic < mp_napics)
1686 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1688 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1690 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1691 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1697 apic_int_is_bus_type(int intr, int bus_type)
1701 for (bus = 0; bus < mp_nbusses; ++bus)
1702 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1703 && ((int) bus_data[bus].bus_type == bus_type))
1710 * Given a traditional ISA INT mask, return an APIC mask.
1713 isa_apic_mask(u_int isa_mask)
1718 #if defined(SKIP_IRQ15_REDIRECT)
1719 if (isa_mask == (1 << 15)) {
1720 kprintf("skipping ISA IRQ15 redirect\n");
1723 #endif /* SKIP_IRQ15_REDIRECT */
1725 isa_irq = ffs(isa_mask); /* find its bit position */
1726 if (isa_irq == 0) /* doesn't exist */
1728 --isa_irq; /* make it zero based */
1730 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1734 return (1 << apic_pin); /* convert pin# to a mask */
1738 * Determine which APIC pin an ISA/EISA INT is attached to.
1740 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1741 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1742 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1743 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1745 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1747 isa_apic_irq(int isa_irq)
1751 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1752 if (INTTYPE(intr) == 0) { /* standard INT */
1753 if (SRCBUSIRQ(intr) == isa_irq) {
1754 if (apic_int_is_bus_type(intr, ISA) ||
1755 apic_int_is_bus_type(intr, EISA)) {
1756 if (INTIRQ(intr) == 0xff)
1757 return -1; /* unassigned */
1758 return INTIRQ(intr); /* found */
1763 return -1; /* NOT found */
1768 * Determine which APIC pin a PCI INT is attached to.
1770 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1771 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1772 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1774 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1778 --pciInt; /* zero based */
1780 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1781 if ((INTTYPE(intr) == 0) /* standard INT */
1782 && (SRCBUSID(intr) == pciBus)
1783 && (SRCBUSDEVICE(intr) == pciDevice)
1784 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1785 if (apic_int_is_bus_type(intr, PCI)) {
1786 if (INTIRQ(intr) == 0xff)
1787 allocate_apic_irq(intr);
1788 if (INTIRQ(intr) == 0xff)
1789 return -1; /* unassigned */
1790 return INTIRQ(intr); /* exact match */
1795 return -1; /* NOT found */
1799 next_apic_irq(int irq)
1806 for (intr = 0; intr < nintrs; intr++) {
1807 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1809 bus = SRCBUSID(intr);
1810 bustype = apic_bus_type(bus);
1811 if (bustype != ISA &&
1817 if (intr >= nintrs) {
1820 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1821 if (INTTYPE(ointr) != 0)
1823 if (bus != SRCBUSID(ointr))
1825 if (bustype == PCI) {
1826 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1828 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1831 if (bustype == ISA || bustype == EISA) {
1832 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1835 if (INTPIN(intr) == INTPIN(ointr))
1839 if (ointr >= nintrs) {
1842 return INTIRQ(ointr);
1857 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1860 * Exactly what this means is unclear at this point. It is a solution
1861 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1862 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1863 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1867 undirect_isa_irq(int rirq)
1871 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1872 /** FIXME: tickle the MB redirector chip */
1876 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1883 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1886 undirect_pci_irq(int rirq)
1890 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1892 /** FIXME: tickle the MB redirector chip */
1896 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1906 * given a bus ID, return:
1907 * the bus type if found
1911 apic_bus_type(int id)
1915 for (x = 0; x < mp_nbusses; ++x)
1916 if (bus_data[x].bus_id == id)
1917 return bus_data[x].bus_type;
1923 * given a LOGICAL APIC# and pin#, return:
1924 * the associated src bus ID if found
1928 apic_src_bus_id(int apic, int pin)
1932 /* search each of the possible INTerrupt sources */
1933 for (x = 0; x < nintrs; ++x)
1934 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1935 (pin == io_apic_ints[x].dst_apic_int))
1936 return (io_apic_ints[x].src_bus_id);
1938 return -1; /* NOT found */
1942 * given a LOGICAL APIC# and pin#, return:
1943 * the associated src bus IRQ if found
1947 apic_src_bus_irq(int apic, int pin)
1951 for (x = 0; x < nintrs; x++)
1952 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1953 (pin == io_apic_ints[x].dst_apic_int))
1954 return (io_apic_ints[x].src_bus_irq);
1956 return -1; /* NOT found */
1961 * given a LOGICAL APIC# and pin#, return:
1962 * the associated INTerrupt type if found
1966 apic_int_type(int apic, int pin)
1970 /* search each of the possible INTerrupt sources */
1971 for (x = 0; x < nintrs; ++x) {
1972 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1973 (pin == io_apic_ints[x].dst_apic_int))
1974 return (io_apic_ints[x].int_type);
1976 return -1; /* NOT found */
1980 * Return the IRQ associated with an APIC pin
1983 apic_irq(int apic, int pin)
1988 for (x = 0; x < nintrs; ++x) {
1989 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1990 (pin == io_apic_ints[x].dst_apic_int)) {
1991 res = io_apic_ints[x].int_vector;
1994 if (apic != int_to_apicintpin[res].ioapic)
1995 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1996 if (pin != int_to_apicintpin[res].int_pin)
1997 panic("apic_irq inconsistent table (2)");
2006 * given a LOGICAL APIC# and pin#, return:
2007 * the associated trigger mode if found
2011 apic_trigger(int apic, int pin)
2015 /* search each of the possible INTerrupt sources */
2016 for (x = 0; x < nintrs; ++x)
2017 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2018 (pin == io_apic_ints[x].dst_apic_int))
2019 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2021 return -1; /* NOT found */
2026 * given a LOGICAL APIC# and pin#, return:
2027 * the associated 'active' level if found
2031 apic_polarity(int apic, int pin)
2035 /* search each of the possible INTerrupt sources */
2036 for (x = 0; x < nintrs; ++x)
2037 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2038 (pin == io_apic_ints[x].dst_apic_int))
2039 return (io_apic_ints[x].int_flags & 0x03);
2041 return -1; /* NOT found */
2047 * set data according to MP defaults
2048 * FIXME: probably not complete yet...
2051 mptable_default(int type)
2053 #if defined(APIC_IO)
2058 kprintf(" MP default config type: %d\n", type);
2061 kprintf(" bus: ISA, APIC: 82489DX\n");
2064 kprintf(" bus: EISA, APIC: 82489DX\n");
2067 kprintf(" bus: EISA, APIC: 82489DX\n");
2070 kprintf(" bus: MCA, APIC: 82489DX\n");
2073 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2076 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2079 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2082 kprintf(" future type\n");
2088 /* one and only IO APIC */
2089 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2092 * sanity check, refer to MP spec section 3.6.6, last paragraph
2093 * necessary as some hardware isn't properly setting up the IO APIC
2095 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2096 if (io_apic_id != 2) {
2098 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2099 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2100 io_apic_set_id(0, 2);
2103 IO_TO_ID(0) = io_apic_id;
2104 ID_TO_IO(io_apic_id) = 0;
2106 /* fill out bus entries */
2115 bus_data[0].bus_id = default_data[type - 1][1];
2116 bus_data[0].bus_type = default_data[type - 1][2];
2117 bus_data[1].bus_id = default_data[type - 1][3];
2118 bus_data[1].bus_type = default_data[type - 1][4];
2121 /* case 4: case 7: MCA NOT supported */
2122 default: /* illegal/reserved */
2123 panic("BAD default MP config: %d", type);
2127 /* general cases from MP v1.4, table 5-2 */
2128 for (pin = 0; pin < 16; ++pin) {
2129 io_apic_ints[pin].int_type = 0;
2130 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2131 io_apic_ints[pin].src_bus_id = 0;
2132 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2133 io_apic_ints[pin].dst_apic_id = io_apic_id;
2134 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2137 /* special cases from MP v1.4, table 5-2 */
2139 io_apic_ints[2].int_type = 0xff; /* N/C */
2140 io_apic_ints[13].int_type = 0xff; /* N/C */
2141 #if !defined(APIC_MIXED_MODE)
2143 panic("sorry, can't support type 2 default yet");
2144 #endif /* APIC_MIXED_MODE */
2147 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2150 io_apic_ints[0].int_type = 0xff; /* N/C */
2152 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2153 #endif /* APIC_IO */
2157 * Map a physical memory address representing I/O into KVA. The I/O
2158 * block is assumed not to cross a page boundary.
2161 permanent_io_mapping(vm_paddr_t pa)
2167 KKASSERT(pa < 0x100000000LL);
2169 pgeflag = 0; /* not used for SMP yet */
2172 * If the requested physical address has already been incidently
2173 * mapped, just use the existing mapping. Otherwise create a new
2176 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2177 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2178 ((vm_offset_t)pa & PG_FRAME)) {
2182 if (i == SMPpt_alloc_index) {
2183 if (i == NPTEPG - 2) {
2184 panic("permanent_io_mapping: We ran out of space"
2187 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2188 ((vm_offset_t)pa & PG_FRAME));
2189 ++SMPpt_alloc_index;
2191 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2192 ((vm_offset_t)pa & PAGE_MASK);
2193 return ((void *)vaddr);
2197 * start each AP in our list
2200 start_all_aps(u_int boot_addr)
2204 u_char mpbiosreason;
2205 u_long mpbioswarmvec;
2206 struct mdglobaldata *gd;
2207 struct privatespace *ps;
2211 POSTCODE(START_ALL_APS_POST);
2213 /* Initialize BSP's local APIC */
2214 apic_initialize(TRUE);
2216 /* install the AP 1st level boot code */
2217 install_ap_tramp(boot_addr);
2220 /* save the current value of the warm-start vector */
2221 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2222 outb(CMOS_REG, BIOS_RESET);
2223 mpbiosreason = inb(CMOS_DATA);
2225 /* set up temporary P==V mapping for AP boot */
2226 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2227 kptbase = (uintptr_t)(void *)KPTphys;
2228 for (x = 0; x < NKPT; x++) {
2229 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2230 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2235 for (x = 1; x <= mp_naps; ++x) {
2237 /* This is a bit verbose, it will go away soon. */
2239 /* first page of AP's private space */
2240 pg = x * i386_btop(sizeof(struct privatespace));
2242 /* allocate new private data page(s) */
2243 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2244 MDGLOBALDATA_BASEALLOC_SIZE);
2245 /* wire it into the private page table page */
2246 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2247 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2248 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2250 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2252 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2253 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2254 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2255 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2257 /* allocate and set up an idle stack data page */
2258 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2259 for (i = 0; i < UPAGES; i++) {
2260 SMPpt[pg + 4 + i] = (pt_entry_t)
2261 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2264 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2265 bzero(gd, sizeof(*gd));
2266 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2268 /* prime data page for it to use */
2269 mi_gdinit(&gd->mi, x);
2271 gd->gd_CMAP1 = &SMPpt[pg + 0];
2272 gd->gd_CMAP2 = &SMPpt[pg + 1];
2273 gd->gd_CMAP3 = &SMPpt[pg + 2];
2274 gd->gd_PMAP1 = &SMPpt[pg + 3];
2275 gd->gd_CADDR1 = ps->CPAGE1;
2276 gd->gd_CADDR2 = ps->CPAGE2;
2277 gd->gd_CADDR3 = ps->CPAGE3;
2278 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2279 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2280 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2282 /* setup a vector to our boot code */
2283 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2284 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2285 outb(CMOS_REG, BIOS_RESET);
2286 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2289 * Setup the AP boot stack
2291 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2294 /* attempt to start the Application Processor */
2295 CHECK_INIT(99); /* setup checkpoints */
2296 if (!start_ap(gd, boot_addr)) {
2297 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2298 CHECK_PRINT("trace"); /* show checkpoints */
2299 /* better panic as the AP may be running loose */
2300 kprintf("panic y/n? [y] ");
2301 if (cngetc() != 'n')
2304 CHECK_PRINT("trace"); /* show checkpoints */
2306 /* record its version info */
2307 cpu_apic_versions[x] = cpu_apic_versions[0];
2310 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2313 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2314 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2317 ncpus2_shift = shift;
2318 ncpus2 = 1 << shift;
2319 ncpus2_mask = ncpus2 - 1;
2321 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2322 if ((1 << shift) < ncpus)
2324 ncpus_fit = 1 << shift;
2325 ncpus_fit_mask = ncpus_fit - 1;
2327 /* build our map of 'other' CPUs */
2328 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2329 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2330 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2332 /* fill in our (BSP) APIC version */
2333 cpu_apic_versions[0] = lapic.version;
2335 /* restore the warmstart vector */
2336 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2337 outb(CMOS_REG, BIOS_RESET);
2338 outb(CMOS_DATA, mpbiosreason);
2341 * NOTE! The idlestack for the BSP was setup by locore. Finish
2342 * up, clean out the P==V mapping we did earlier.
2344 for (x = 0; x < NKPT; x++)
2348 /* number of APs actually started */
2354 * load the 1st level AP boot code into base memory.
2357 /* targets for relocation */
2358 extern void bigJump(void);
2359 extern void bootCodeSeg(void);
2360 extern void bootDataSeg(void);
2361 extern void MPentry(void);
2362 extern u_int MP_GDT;
2363 extern u_int mp_gdtbase;
2366 install_ap_tramp(u_int boot_addr)
2369 int size = *(int *) ((u_long) & bootMP_size);
2370 u_char *src = (u_char *) ((u_long) bootMP);
2371 u_char *dst = (u_char *) boot_addr + KERNBASE;
2372 u_int boot_base = (u_int) bootMP;
2377 POSTCODE(INSTALL_AP_TRAMP_POST);
2379 for (x = 0; x < size; ++x)
2383 * modify addresses in code we just moved to basemem. unfortunately we
2384 * need fairly detailed info about mpboot.s for this to work. changes
2385 * to mpboot.s might require changes here.
2388 /* boot code is located in KERNEL space */
2389 dst = (u_char *) boot_addr + KERNBASE;
2391 /* modify the lgdt arg */
2392 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2393 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2395 /* modify the ljmp target for MPentry() */
2396 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2397 *dst32 = ((u_int) MPentry - KERNBASE);
2399 /* modify the target for boot code segment */
2400 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2401 dst8 = (u_int8_t *) (dst16 + 1);
2402 *dst16 = (u_int) boot_addr & 0xffff;
2403 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2405 /* modify the target for boot data segment */
2406 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2407 dst8 = (u_int8_t *) (dst16 + 1);
2408 *dst16 = (u_int) boot_addr & 0xffff;
2409 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2414 * this function starts the AP (application processor) identified
2415 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2416 * to accomplish this. This is necessary because of the nuances
2417 * of the different hardware we might encounter. It ain't pretty,
2418 * but it seems to work.
2420 * NOTE: eventually an AP gets to ap_init(), which is called just
2421 * before the AP goes into the LWKT scheduler's idle loop.
2424 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2428 u_long icr_lo, icr_hi;
2430 POSTCODE(START_AP_POST);
2432 /* get the PHYSICAL APIC ID# */
2433 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2435 /* calculate the vector */
2436 vector = (boot_addr >> 12) & 0xff;
2438 /* Make sure the target cpu sees everything */
2442 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2443 * and running the target CPU. OR this INIT IPI might be latched (P5
2444 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2448 /* setup the address for the target AP */
2449 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2450 icr_hi |= (physical_cpu << 24);
2451 lapic.icr_hi = icr_hi;
2453 /* do an INIT IPI: assert RESET */
2454 icr_lo = lapic.icr_lo & 0xfff00000;
2455 lapic.icr_lo = icr_lo | 0x0000c500;
2457 /* wait for pending status end */
2458 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2461 /* do an INIT IPI: deassert RESET */
2462 lapic.icr_lo = icr_lo | 0x00008500;
2464 /* wait for pending status end */
2465 u_sleep(10000); /* wait ~10mS */
2466 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2470 * next we do a STARTUP IPI: the previous INIT IPI might still be
2471 * latched, (P5 bug) this 1st STARTUP would then terminate
2472 * immediately, and the previously started INIT IPI would continue. OR
2473 * the previous INIT IPI has already run. and this STARTUP IPI will
2474 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2478 /* do a STARTUP IPI */
2479 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2480 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2482 u_sleep(200); /* wait ~200uS */
2485 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2486 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2487 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2488 * recognized after hardware RESET or INIT IPI.
2491 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2492 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2494 u_sleep(200); /* wait ~200uS */
2496 /* wait for it to start, see ap_init() */
2497 set_apic_timer(5000000);/* == 5 seconds */
2498 while (read_apic_timer()) {
2499 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2500 return 1; /* return SUCCESS */
2502 return 0; /* return FAILURE */
2507 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2509 * If for some reason we were unable to start all cpus we cannot safely
2510 * use broadcast IPIs.
2516 if (smp_startup_mask == smp_active_mask) {
2517 all_but_self_ipi(XINVLTLB_OFFSET);
2519 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2520 APIC_DELMODE_FIXED);
2526 * When called the executing CPU will send an IPI to all other CPUs
2527 * requesting that they halt execution.
2529 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2531 * - Signals all CPUs in map to stop.
2532 * - Waits for each to stop.
2539 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2540 * from executing at same time.
2543 stop_cpus(u_int map)
2545 map &= smp_active_mask;
2547 /* send the Xcpustop IPI to all CPUs in map */
2548 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2550 while ((stopped_cpus & map) != map)
2558 * Called by a CPU to restart stopped CPUs.
2560 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2562 * - Signals all CPUs in map to restart.
2563 * - Waits for each to restart.
2571 restart_cpus(u_int map)
2573 /* signal other cpus to restart */
2574 started_cpus = map & smp_active_mask;
2576 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2583 * This is called once the mpboot code has gotten us properly relocated
2584 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2585 * and when it returns the scheduler will call the real cpu_idle() main
2586 * loop for the idlethread. Interrupts are disabled on entry and should
2587 * remain disabled at return.
2595 * Adjust smp_startup_mask to signal the BSP that we have started
2596 * up successfully. Note that we do not yet hold the BGL. The BSP
2597 * is waiting for our signal.
2599 * We can't set our bit in smp_active_mask yet because we are holding
2600 * interrupts physically disabled and remote cpus could deadlock
2601 * trying to send us an IPI.
2603 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2607 * Interlock for finalization. Wait until mp_finish is non-zero,
2608 * then get the MP lock.
2610 * Note: We are in a critical section.
2612 * Note: We have to synchronize td_mpcount to our desired MP state
2613 * before calling cpu_try_mplock().
2615 * Note: we are the idle thread, we can only spin.
2617 * Note: The load fence is memory volatile and prevents the compiler
2618 * from improperly caching mp_finish, and the cpu from improperly
2621 while (mp_finish == 0)
2623 ++curthread->td_mpcount;
2624 while (cpu_try_mplock() == 0)
2627 if (cpu_feature & CPUID_TSC) {
2629 * The BSP is constantly updating tsc0_offset, figure out the
2630 * relative difference to synchronize ktrdump.
2632 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2635 /* BSP may have changed PTD while we're waiting for the lock */
2638 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2642 /* Build our map of 'other' CPUs. */
2643 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2645 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2647 /* A quick check from sanity claus */
2648 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2649 if (mycpu->gd_cpuid != apic_id) {
2650 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2651 kprintf("SMP: apic_id = %d\n", apic_id);
2652 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2653 panic("cpuid mismatch! boom!!");
2656 /* Initialize AP's local APIC for irq's */
2657 apic_initialize(FALSE);
2659 /* Set memory range attributes for this CPU to match the BSP */
2660 mem_range_AP_init();
2663 * Once we go active we must process any IPIQ messages that may
2664 * have been queued, because no actual IPI will occur until we
2665 * set our bit in the smp_active_mask. If we don't the IPI
2666 * message interlock could be left set which would also prevent
2669 * The idle loop doesn't expect the BGL to be held and while
2670 * lwkt_switch() normally cleans things up this is a special case
2671 * because we returning almost directly into the idle loop.
2673 * The idle thread is never placed on the runq, make sure
2674 * nothing we've done put it there.
2676 KKASSERT(curthread->td_mpcount == 1);
2677 smp_active_mask |= 1 << mycpu->gd_cpuid;
2680 * Enable interrupts here. idle_restore will also do it, but
2681 * doing it here lets us clean up any strays that got posted to
2682 * the CPU during the AP boot while we are still in a critical
2685 __asm __volatile("sti; pause; pause"::);
2686 mdcpu->gd_fpending = 0;
2687 mdcpu->gd_ipending = 0;
2689 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2690 lwkt_process_ipiq();
2693 * Releasing the mp lock lets the BSP finish up the SMP init
2696 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2700 * Get SMP fully working before we start initializing devices.
2708 kprintf("Finish MP startup\n");
2709 if (cpu_feature & CPUID_TSC)
2710 tsc0_offset = rdtsc();
2713 while (smp_active_mask != smp_startup_mask) {
2715 if (cpu_feature & CPUID_TSC)
2716 tsc0_offset = rdtsc();
2718 while (try_mplock() == 0)
2721 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2724 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2727 cpu_send_ipiq(int dcpu)
2729 if ((1 << dcpu) & smp_active_mask)
2730 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2733 #if 0 /* single_apic_ipi_passive() not working yet */
2735 * Returns 0 on failure, 1 on success
2738 cpu_send_ipiq_passive(int dcpu)
2741 if ((1 << dcpu) & smp_active_mask) {
2742 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2743 APIC_DELMODE_FIXED);
2749 struct mptable_lapic_cbarg1 {
2752 u_int ht_apicid_mask;
2756 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2758 const struct PROCENTRY *ent;
2759 struct mptable_lapic_cbarg1 *arg = xarg;
2765 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2769 if (ent->apic_id < 32) {
2770 arg->ht_apicid_mask |= 1 << ent->apic_id;
2771 } else if (arg->ht_fixup) {
2772 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2778 struct mptable_lapic_cbarg2 {
2785 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2787 const struct PROCENTRY *ent;
2788 struct mptable_lapic_cbarg2 *arg = xarg;
2794 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2795 KKASSERT(!arg->found_bsp);
2799 if (processor_entry(ent, arg->cpu))
2802 if (arg->logical_cpus) {
2803 struct PROCENTRY proc;
2807 * Create fake mptable processor entries
2808 * and feed them to processor_entry() to
2809 * enumerate the logical CPUs.
2811 bzero(&proc, sizeof(proc));
2813 proc.cpu_flags = PROCENTRY_FLAG_EN;
2814 proc.apic_id = ent->apic_id;
2816 for (i = 1; i < arg->logical_cpus; i++) {
2818 processor_entry(&proc, arg->cpu);
2826 mptable_lapic_default(void)
2828 int ap_apicid, bsp_apicid;
2830 mp_naps = 1; /* exclude BSP */
2832 /* Map local apic before the id field is accessed */
2833 lapic_init(DEFAULT_APIC_BASE);
2835 bsp_apicid = APIC_ID(lapic.id);
2836 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2839 mp_set_cpuids(0, bsp_apicid);
2840 /* one and only AP */
2841 mp_set_cpuids(1, ap_apicid);
2846 * cpu_apic_address (common to all CPUs)
2848 * ID_TO_CPU(N), APIC ID to logical CPU table
2849 * CPU_TO_ID(N), logical CPU to APIC ID table
2852 mptable_lapic_enumerate(struct mptable_pos *mpt)
2854 struct mptable_lapic_cbarg1 arg1;
2855 struct mptable_lapic_cbarg2 arg2;
2857 int error, logical_cpus = 0;
2858 vm_offset_t lapic_addr;
2860 KKASSERT(mpt->mp_fps != NULL);
2863 * Check for use of 'default' configuration
2865 if (mpt->mp_fps->mpfb1 != 0) {
2866 mptable_lapic_default();
2871 KKASSERT(cth != NULL);
2873 /* Save local apic address */
2874 lapic_addr = (vm_offset_t)cth->apic_address;
2875 KKASSERT(lapic_addr != 0);
2878 * Find out how many CPUs do we have
2880 bzero(&arg1, sizeof(arg1));
2881 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2883 error = mptable_iterate_entries(cth,
2884 mptable_lapic_pass1_callback, &arg1);
2886 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2887 KKASSERT(arg1.cpu_count != 0);
2889 /* See if we need to fixup HT logical CPUs. */
2890 if (arg1.ht_fixup) {
2891 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2893 if (logical_cpus != 0)
2894 arg1.cpu_count *= logical_cpus;
2896 mp_naps = arg1.cpu_count;
2898 /* Qualify the numbers again, after possible HT fixup */
2899 if (mp_naps > MAXCPU) {
2900 kprintf("Warning: only using %d of %d available CPUs!\n",
2905 --mp_naps; /* subtract the BSP */
2908 * Link logical CPU id to local apic id
2910 bzero(&arg2, sizeof(arg2));
2912 arg2.logical_cpus = logical_cpus;
2914 error = mptable_iterate_entries(cth,
2915 mptable_lapic_pass2_callback, &arg2);
2917 panic("mptable_iterate_entries(lapic_pass2) failed\n");
2918 KKASSERT(arg2.found_bsp);
2920 /* Map local apic */
2921 lapic_init(lapic_addr);
2925 mptable_imcr(struct mptable_pos *mpt)
2927 /* record whether PIC or virtual-wire mode */
2928 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2929 mpt->mp_fps->mpfb2 & 0x80);
2933 lapic_init(vm_offset_t lapic_addr)
2935 /* Local apic is mapped on last page */
2936 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
2937 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
2939 /* Just for printing */
2940 cpu_apic_address = lapic_addr;