sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.80 2007/06/07 20:30:20 dillon Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include "opt_polling.h"
  76 #include <sys/param.h>
  77 #include <sys/bus.h>
  78 #include <sys/endian.h>
  79 #include <sys/kernel.h>
  80 #include <sys/mbuf.h>
  81 #include <sys/malloc.h>
  82 #include <sys/queue.h>
  83 #include <sys/rman.h>
  84 #include <sys/serialize.h>
  85 #include <sys/socket.h>
  86 #include <sys/sockio.h>
  87
  88 #include <net/bpf.h>
  89 #include <net/ethernet.h>
  90 #include <net/if.h>
  91 #include <net/if_arp.h>
  92 #include <net/if_dl.h>
  93 #include <net/if_media.h>
  94 #include <net/if_types.h>
  95 #include <net/ifq_var.h>
  96 #include <net/vlan/if_vlan_var.h>
  97
  98 #include <dev/netif/mii_layer/mii.h>
  99 #include <dev/netif/mii_layer/miivar.h>
 100 #include <dev/netif/mii_layer/brgphyreg.h>
 101
 102 #include <bus/pci/pcidevs.h>
 103 #include <bus/pci/pcireg.h>
 104 #include <bus/pci/pcivar.h>
 105
 106 #include <dev/netif/bge/if_bgereg.h>
 107
 108 /* "device miibus" required.  See GENERIC if you get errors here. */
 109 #include "miibus_if.h"
 110
 111 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 112 #define BGE_MIN_FRAME           60
 113
 114 /*
 115  * Various supported device vendors/types and their names. Note: the
 116  * spec seems to indicate that the hardware still has Alteon's vendor
 117  * ID burned into it, though it will always be overriden by the vendor
 118  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 119  */
 120 #define BGE_DEVDESC_MAX         64      /* Maximum device description length */
 121
 122 static struct bge_type bge_devs[] = {
 123         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 124                 "3COM 3C996 Gigabit Ethernet" },
 125
 126         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 127                 "Alteon BCM5700 Gigabit Ethernet" },
 128         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 129                 "Alteon BCM5701 Gigabit Ethernet" },
 130
 131         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 132                 "Altima AC1000 Gigabit Ethernet" },
 133         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 134                 "Altima AC1002 Gigabit Ethernet" },
 135         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 136                 "Altima AC9100 Gigabit Ethernet" },
 137
 138         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 139                 "Apple BCM5701 Gigabit Ethernet" },
 140
 141         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 142                 "Broadcom BCM5700 Gigabit Ethernet" },
 143         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 144                 "Broadcom BCM5701 Gigabit Ethernet" },
 145         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 146                 "Broadcom BCM5702 Gigabit Ethernet" },
 147         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 148                 "Broadcom BCM5702X Gigabit Ethernet" },
 149         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 150                 "Broadcom BCM5702 Gigabit Ethernet" },
 151         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 152                 "Broadcom BCM5703 Gigabit Ethernet" },
 153         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 154                 "Broadcom BCM5703X Gigabit Ethernet" },
 155         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 156                 "Broadcom BCM5703 Gigabit Ethernet" },
 157         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 158                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 159         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 160                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 161         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 162                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 163         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 164                 "Broadcom BCM5705 Gigabit Ethernet" },
 165         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 166                 "Broadcom BCM5705F Gigabit Ethernet" },
 167         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 168                 "Broadcom BCM5705K Gigabit Ethernet" },
 169         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 170                 "Broadcom BCM5705M Gigabit Ethernet" },
 171         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 172                 "Broadcom BCM5705M Gigabit Ethernet" },
 173         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 174                 "Broadcom BCM5714C Gigabit Ethernet" },
 175         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 176                 "Broadcom BCM5714S Gigabit Ethernet" },
 177         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 178                 "Broadcom BCM5715 Gigabit Ethernet" },
 179         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 180                 "Broadcom BCM5715S Gigabit Ethernet" },
 181         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 182                 "Broadcom BCM5720 Gigabit Ethernet" },
 183         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 184                 "Broadcom BCM5721 Gigabit Ethernet" },
 185         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 186                 "Broadcom BCM5722 Gigabit Ethernet" },
 187         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 188                 "Broadcom BCM5750 Gigabit Ethernet" },
 189         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 190                 "Broadcom BCM5750M Gigabit Ethernet" },
 191         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 192                 "Broadcom BCM5751 Gigabit Ethernet" },
 193         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 194                 "Broadcom BCM5751F Gigabit Ethernet" },
 195         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 196                 "Broadcom BCM5751M Gigabit Ethernet" },
 197         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 198                 "Broadcom BCM5752 Gigabit Ethernet" },
 199         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 200                 "Broadcom BCM5752M Gigabit Ethernet" },
 201         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 202                 "Broadcom BCM5753 Gigabit Ethernet" },
 203         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 204                 "Broadcom BCM5753F Gigabit Ethernet" },
 205         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 206                 "Broadcom BCM5753M Gigabit Ethernet" },
 207         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 208                 "Broadcom BCM5754 Gigabit Ethernet" },
 209         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 210                 "Broadcom BCM5754M Gigabit Ethernet" },
 211         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 212                 "Broadcom BCM5755 Gigabit Ethernet" },
 213         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 214                 "Broadcom BCM5755M Gigabit Ethernet" },
 215         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 216                 "Broadcom BCM5756 Gigabit Ethernet" },
 217         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 218                 "Broadcom BCM5780 Gigabit Ethernet" },
 219         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 220                 "Broadcom BCM5780S Gigabit Ethernet" },
 221         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 222                 "Broadcom BCM5781 Gigabit Ethernet" },
 223         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 224                 "Broadcom BCM5782 Gigabit Ethernet" },
 225         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 226                 "Broadcom BCM5786 Gigabit Ethernet" },
 227         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 228                 "Broadcom BCM5787 Gigabit Ethernet" },
 229         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 230                 "Broadcom BCM5787F Gigabit Ethernet" },
 231         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 232                 "Broadcom BCM5787M Gigabit Ethernet" },
 233         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 234                 "Broadcom BCM5788 Gigabit Ethernet" },
 235         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 236                 "Broadcom BCM5789 Gigabit Ethernet" },
 237         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 238                 "Broadcom BCM5901 Fast Ethernet" },
 239         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 240                 "Broadcom BCM5901A2 Fast Ethernet" },
 241         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 242                 "Broadcom BCM5903M Fast Ethernet" },
 243
 244         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 245                 "SysKonnect Gigabit Ethernet" },
 246
 247         { 0, 0, NULL }
 248 };
 249
 250 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 251 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 252 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 253 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 254 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 255
 256 static int      bge_probe(device_t);
 257 static int      bge_attach(device_t);
 258 static int      bge_detach(device_t);
 259 static void     bge_txeof(struct bge_softc *);
 260 static void     bge_rxeof(struct bge_softc *);
 261
 262 static void     bge_tick(void *);
 263 static void     bge_stats_update(struct bge_softc *);
 264 static void     bge_stats_update_regs(struct bge_softc *);
 265 static int      bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
 266
 267 #ifdef DEVICE_POLLING
 268 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 269 #endif
 270 static void     bge_intr(void *);
 271 static void     bge_start(struct ifnet *);
 272 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 273 static void     bge_init(void *);
 274 static void     bge_stop(struct bge_softc *);
 275 static void     bge_watchdog(struct ifnet *);
 276 static void     bge_shutdown(device_t);
 277 static int      bge_suspend(device_t);
 278 static int      bge_resume(device_t);
 279 static int      bge_ifmedia_upd(struct ifnet *);
 280 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 281
 282 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 283 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 284
 285 static void     bge_setmulti(struct bge_softc *);
 286 static void     bge_setpromisc(struct bge_softc *);
 287
 288 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 289 static void     bge_free_jumbo_mem(struct bge_softc *);
 290 static struct bge_jslot
 291                 *bge_jalloc(struct bge_softc *);
 292 static void     bge_jfree(void *);
 293 static void     bge_jref(void *);
 294 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 295 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 296 static int      bge_init_rx_ring_std(struct bge_softc *);
 297 static void     bge_free_rx_ring_std(struct bge_softc *);
 298 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 299 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 300 static void     bge_free_tx_ring(struct bge_softc *);
 301 static int      bge_init_tx_ring(struct bge_softc *);
 302
 303 static int      bge_chipinit(struct bge_softc *);
 304 static int      bge_blockinit(struct bge_softc *);
 305
 306 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 307 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 308 #ifdef notdef
 309 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 310 #endif
 311 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 312 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 313
 314 static int      bge_miibus_readreg(device_t, int, int);
 315 static int      bge_miibus_writereg(device_t, int, int, int);
 316 static void     bge_miibus_statchg(device_t);
 317 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 318 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 319 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 320
 321 static void     bge_reset(struct bge_softc *);
 322
 323 static void     bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 324 static void     bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
 325                                  bus_size_t, int);
 326 static int      bge_dma_alloc(struct bge_softc *);
 327 static void     bge_dma_free(struct bge_softc *);
 328 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 329                                     bus_dma_tag_t *, bus_dmamap_t *,
 330                                     void **, bus_addr_t *);
 331 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 332
 333 /*
 334  * Set following tunable to 1 for some IBM blade servers with the DNLK
 335  * switch module. Auto negotiation is broken for those configurations.
 336  */
 337 static int      bge_fake_autoneg = 0;
 338 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 339
 340 static device_method_t bge_methods[] = {
 341         /* Device interface */
 342         DEVMETHOD(device_probe,         bge_probe),
 343         DEVMETHOD(device_attach,        bge_attach),
 344         DEVMETHOD(device_detach,        bge_detach),
 345         DEVMETHOD(device_shutdown,      bge_shutdown),
 346         DEVMETHOD(device_suspend,       bge_suspend),
 347         DEVMETHOD(device_resume,        bge_resume),
 348
 349         /* bus interface */
 350         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 351         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 352
 353         /* MII interface */
 354         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 355         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 356         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 357
 358         { 0, 0 }
 359 };
 360
 361 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 362 static devclass_t bge_devclass;
 363
 364 DECLARE_DUMMY_MODULE(if_bge);
 365 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 366 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 367
 368 static uint32_t
 369 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 370 {
 371         device_t dev = sc->bge_dev;
 372         uint32_t val;
 373
 374         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 375         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 376         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 377         return (val);
 378 }
 379
 380 static void
 381 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 382 {
 383         device_t dev = sc->bge_dev;
 384
 385         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 386         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 387         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 388 }
 389
 390 #ifdef notdef
 391 static uint32_t
 392 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 393 {
 394         device_t dev = sc->bge_dev;
 395
 396         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 397         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 398 }
 399 #endif
 400
 401 static void
 402 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 403 {
 404         device_t dev = sc->bge_dev;
 405
 406         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 407         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 408 }
 409
 410 static void
 411 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 412 {
 413         CSR_WRITE_4(sc, off, val);
 414 }
 415
 416 /*
 417  * Read a byte of data stored in the EEPROM at address 'addr.' The
 418  * BCM570x supports both the traditional bitbang interface and an
 419  * auto access interface for reading the EEPROM. We use the auto
 420  * access method.
 421  */
 422 static uint8_t
 423 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 424 {
 425         int i;
 426         uint32_t byte = 0;
 427
 428         /*
 429          * Enable use of auto EEPROM access so we can avoid
 430          * having to use the bitbang method.
 431          */
 432         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 433
 434         /* Reset the EEPROM, load the clock period. */
 435         CSR_WRITE_4(sc, BGE_EE_ADDR,
 436             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 437         DELAY(20);
 438
 439         /* Issue the read EEPROM command. */
 440         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 441
 442         /* Wait for completion */
 443         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 444                 DELAY(10);
 445                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 446                         break;
 447         }
 448
 449         if (i == BGE_TIMEOUT) {
 450                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 451                 return(1);
 452         }
 453
 454         /* Get result. */
 455         byte = CSR_READ_4(sc, BGE_EE_DATA);
 456
 457         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 458
 459         return(0);
 460 }
 461
 462 /*
 463  * Read a sequence of bytes from the EEPROM.
 464  */
 465 static int
 466 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 467 {
 468         size_t i;
 469         int err;
 470         uint8_t byte;
 471
 472         for (byte = 0, err = 0, i = 0; i < len; i++) {
 473                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 474                 if (err)
 475                         break;
 476                 *(dest + i) = byte;
 477         }
 478
 479         return(err ? 1 : 0);
 480 }
 481
 482 static int
 483 bge_miibus_readreg(device_t dev, int phy, int reg)
 484 {
 485         struct bge_softc *sc;
 486         struct ifnet *ifp;
 487         uint32_t val, autopoll;
 488         int i;
 489
 490         sc = device_get_softc(dev);
 491         ifp = &sc->arpcom.ac_if;
 492
 493         /*
 494          * Broadcom's own driver always assumes the internal
 495          * PHY is at GMII address 1. On some chips, the PHY responds
 496          * to accesses at all addresses, which could cause us to
 497          * bogusly attach the PHY 32 times at probe type. Always
 498          * restricting the lookup to address 1 is simpler than
 499          * trying to figure out which chips revisions should be
 500          * special-cased.
 501          */
 502         if (phy != 1)
 503                 return(0);
 504
 505         /* Reading with autopolling on may trigger PCI errors */
 506         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 507         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 508                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 509                 DELAY(40);
 510         }
 511
 512         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 513             BGE_MIPHY(phy)|BGE_MIREG(reg));
 514
 515         for (i = 0; i < BGE_TIMEOUT; i++) {
 516                 val = CSR_READ_4(sc, BGE_MI_COMM);
 517                 if (!(val & BGE_MICOMM_BUSY))
 518                         break;
 519         }
 520
 521         if (i == BGE_TIMEOUT) {
 522                 if_printf(ifp, "PHY read timed out\n");
 523                 val = 0;
 524                 goto done;
 525         }
 526
 527         val = CSR_READ_4(sc, BGE_MI_COMM);
 528
 529 done:
 530         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 531                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 532                 DELAY(40);
 533         }
 534
 535         if (val & BGE_MICOMM_READFAIL)
 536                 return(0);
 537
 538         return(val & 0xFFFF);
 539 }
 540
 541 static int
 542 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 543 {
 544         struct bge_softc *sc;
 545         uint32_t autopoll;
 546         int i;
 547
 548         sc = device_get_softc(dev);
 549
 550         /* Reading with autopolling on may trigger PCI errors */
 551         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 552         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 553                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 554                 DELAY(40);
 555         }
 556
 557         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 558             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 559
 560         for (i = 0; i < BGE_TIMEOUT; i++) {
 561                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
 562                         break;
 563         }
 564
 565         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 566                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 567                 DELAY(40);
 568         }
 569
 570         if (i == BGE_TIMEOUT) {
 571                 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
 572                 return(0);
 573         }
 574
 575         return(0);
 576 }
 577
 578 static void
 579 bge_miibus_statchg(device_t dev)
 580 {
 581         struct bge_softc *sc;
 582         struct mii_data *mii;
 583
 584         sc = device_get_softc(dev);
 585         mii = device_get_softc(sc->bge_miibus);
 586
 587         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 588         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 589                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 590         } else {
 591                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 592         }
 593
 594         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 595                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 596         } else {
 597                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 598         }
 599 }
 600
 601 /*
 602  * Memory management for jumbo frames.
 603  */
 604 static int
 605 bge_alloc_jumbo_mem(struct bge_softc *sc)
 606 {
 607         struct ifnet *ifp = &sc->arpcom.ac_if;
 608         struct bge_jslot *entry;
 609         uint8_t *ptr;
 610         bus_addr_t paddr;
 611         int i, error;
 612
 613         /*
 614          * Create tag for jumbo mbufs.
 615          * This is really a bit of a kludge. We allocate a special
 616          * jumbo buffer pool which (thanks to the way our DMA
 617          * memory allocation works) will consist of contiguous
 618          * pages. This means that even though a jumbo buffer might
 619          * be larger than a page size, we don't really need to
 620          * map it into more than one DMA segment. However, the
 621          * default mbuf tag will result in multi-segment mappings,
 622          * so we have to create a special jumbo mbuf tag that
 623          * lets us get away with mapping the jumbo buffers as
 624          * a single segment. I think eventually the driver should
 625          * be changed so that it uses ordinary mbufs and cluster
 626          * buffers, i.e. jumbo frames can span multiple DMA
 627          * descriptors. But that's a project for another day.
 628          */
 629
 630         /*
 631          * Create DMA stuffs for jumbo RX ring.
 632          */
 633         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 634                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 635                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 636                                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
 637                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 638         if (error) {
 639                 if_printf(ifp, "could not create jumbo RX ring\n");
 640                 return error;
 641         }
 642
 643         /*
 644          * Create DMA stuffs for jumbo buffer block.
 645          */
 646         error = bge_dma_block_alloc(sc, BGE_JMEM,
 647                                     &sc->bge_cdata.bge_jumbo_tag,
 648                                     &sc->bge_cdata.bge_jumbo_map,
 649                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 650                                     &paddr);
 651         if (error) {
 652                 if_printf(ifp, "could not create jumbo buffer\n");
 653                 return error;
 654         }
 655
 656         SLIST_INIT(&sc->bge_jfree_listhead);
 657
 658         /*
 659          * Now divide it up into 9K pieces and save the addresses
 660          * in an array. Note that we play an evil trick here by using
 661          * the first few bytes in the buffer to hold the the address
 662          * of the softc structure for this interface. This is because
 663          * bge_jfree() needs it, but it is called by the mbuf management
 664          * code which will not pass it to us explicitly.
 665          */
 666         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 667                 entry = &sc->bge_cdata.bge_jslots[i];
 668                 entry->bge_sc = sc;
 669                 entry->bge_buf = ptr;
 670                 entry->bge_paddr = paddr;
 671                 entry->bge_inuse = 0;
 672                 entry->bge_slot = i;
 673                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 674
 675                 ptr += BGE_JLEN;
 676                 paddr += BGE_JLEN;
 677         }
 678         return 0;
 679 }
 680
 681 static void
 682 bge_free_jumbo_mem(struct bge_softc *sc)
 683 {
 684         /* Destroy jumbo RX ring. */
 685         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 686                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 687                            sc->bge_ldata.bge_rx_jumbo_ring);
 688
 689         /* Destroy jumbo buffer block. */
 690         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 691                            sc->bge_cdata.bge_jumbo_map,
 692                            sc->bge_ldata.bge_jumbo_buf);
 693 }
 694
 695 /*
 696  * Allocate a jumbo buffer.
 697  */
 698 static struct bge_jslot *
 699 bge_jalloc(struct bge_softc *sc)
 700 {
 701         struct bge_jslot *entry;
 702
 703         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 704         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 705         if (entry) {
 706                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 707                 entry->bge_inuse = 1;
 708         } else {
 709                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 710         }
 711         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 712         return(entry);
 713 }
 714
 715 /*
 716  * Adjust usage count on a jumbo buffer.
 717  */
 718 static void
 719 bge_jref(void *arg)
 720 {
 721         struct bge_jslot *entry = (struct bge_jslot *)arg;
 722         struct bge_softc *sc = entry->bge_sc;
 723
 724         if (sc == NULL)
 725                 panic("bge_jref: can't find softc pointer!");
 726
 727         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 728                 panic("bge_jref: asked to reference buffer "
 729                     "that we don't manage!");
 730         } else if (entry->bge_inuse == 0) {
 731                 panic("bge_jref: buffer already free!");
 732         } else {
 733                 atomic_add_int(&entry->bge_inuse, 1);
 734         }
 735 }
 736
 737 /*
 738  * Release a jumbo buffer.
 739  */
 740 static void
 741 bge_jfree(void *arg)
 742 {
 743         struct bge_jslot *entry = (struct bge_jslot *)arg;
 744         struct bge_softc *sc = entry->bge_sc;
 745
 746         if (sc == NULL)
 747                 panic("bge_jfree: can't find softc pointer!");
 748
 749         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 750                 panic("bge_jfree: asked to free buffer that we don't manage!");
 751         } else if (entry->bge_inuse == 0) {
 752                 panic("bge_jfree: buffer already free!");
 753         } else {
 754                 /*
 755                  * Possible MP race to 0, use the serializer.  The atomic insn
 756                  * is still needed for races against bge_jref().
 757                  */
 758                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 759                 atomic_subtract_int(&entry->bge_inuse, 1);
 760                 if (entry->bge_inuse == 0) {
 761                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 762                                           entry, jslot_link);
 763                 }
 764                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 765         }
 766 }
 767
 768
 769 /*
 770  * Intialize a standard receive ring descriptor.
 771  */
 772 static int
 773 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 774 {
 775         struct mbuf *m_new = NULL;
 776         struct bge_dmamap_arg ctx;
 777         bus_dma_segment_t seg;
 778         struct bge_rx_bd *r;
 779         int error;
 780
 781         if (m == NULL) {
 782                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
 783                 if (m_new == NULL)
 784                         return ENOBUFS;
 785         } else {
 786                 m_new = m;
 787                 m_new->m_data = m_new->m_ext.ext_buf;
 788         }
 789         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 790
 791         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 792                 m_adj(m_new, ETHER_ALIGN);
 793
 794         ctx.bge_maxsegs = 1;
 795         ctx.bge_segs = &seg;
 796         error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
 797                                      sc->bge_cdata.bge_rx_std_dmamap[i],
 798                                      m_new, bge_dma_map_mbuf, &ctx,
 799                                      BUS_DMA_NOWAIT);
 800         if (error || ctx.bge_maxsegs == 0) {
 801                 if (m == NULL)
 802                         m_freem(m_new);
 803                 return ENOMEM;
 804         }
 805
 806         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 807
 808         r = &sc->bge_ldata.bge_rx_std_ring[i];
 809         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
 810         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
 811         r->bge_flags = BGE_RXBDFLAG_END;
 812         r->bge_len = m_new->m_len;
 813         r->bge_idx = i;
 814
 815         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
 816                         sc->bge_cdata.bge_rx_std_dmamap[i],
 817                         BUS_DMASYNC_PREREAD);
 818         return 0;
 819 }
 820
 821 /*
 822  * Initialize a jumbo receive ring descriptor. This allocates
 823  * a jumbo buffer from the pool managed internally by the driver.
 824  */
 825 static int
 826 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 827 {
 828         struct mbuf *m_new = NULL;
 829         struct bge_jslot *buf;
 830         struct bge_rx_bd *r;
 831         bus_addr_t paddr;
 832
 833         if (m == NULL) {
 834                 /* Allocate the mbuf. */
 835                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 836                 if (m_new == NULL)
 837                         return(ENOBUFS);
 838
 839                 /* Allocate the jumbo buffer */
 840                 buf = bge_jalloc(sc);
 841                 if (buf == NULL) {
 842                         m_freem(m_new);
 843                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 844                             "-- packet dropped!\n");
 845                         return ENOBUFS;
 846                 }
 847
 848                 /* Attach the buffer to the mbuf. */
 849                 m_new->m_ext.ext_arg = buf;
 850                 m_new->m_ext.ext_buf = buf->bge_buf;
 851                 m_new->m_ext.ext_free = bge_jfree;
 852                 m_new->m_ext.ext_ref = bge_jref;
 853                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 854
 855                 m_new->m_flags |= M_EXT;
 856         } else {
 857                 KKASSERT(m->m_flags & M_EXT);
 858                 m_new = m;
 859                 buf = m_new->m_ext.ext_arg;
 860         }
 861         m_new->m_data = m_new->m_ext.ext_buf;
 862         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 863
 864         paddr = buf->bge_paddr;
 865         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
 866                 m_adj(m_new, ETHER_ALIGN);
 867                 paddr += ETHER_ALIGN;
 868         }
 869
 870         /* Set up the descriptor. */
 871         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
 872
 873         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
 874         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
 875         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
 876         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 877         r->bge_len = m_new->m_len;
 878         r->bge_idx = i;
 879
 880         return 0;
 881 }
 882
 883 /*
 884  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
 885  * that's 1MB or memory, which is a lot. For now, we fill only the first
 886  * 256 ring entries and hope that our CPU is fast enough to keep up with
 887  * the NIC.
 888  */
 889 static int
 890 bge_init_rx_ring_std(struct bge_softc *sc)
 891 {
 892         int i;
 893
 894         for (i = 0; i < BGE_SSLOTS; i++) {
 895                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
 896                         return(ENOBUFS);
 897         };
 898
 899         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
 900                         sc->bge_cdata.bge_rx_std_ring_map,
 901                         BUS_DMASYNC_PREWRITE);
 902
 903         sc->bge_std = i - 1;
 904         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 905
 906         return(0);
 907 }
 908
 909 static void
 910 bge_free_rx_ring_std(struct bge_softc *sc)
 911 {
 912         int i;
 913
 914         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 915                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 916                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
 917                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
 918                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
 919                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
 920                 }
 921                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
 922                     sizeof(struct bge_rx_bd));
 923         }
 924 }
 925
 926 static int
 927 bge_init_rx_ring_jumbo(struct bge_softc *sc)
 928 {
 929         int i;
 930         struct bge_rcb *rcb;
 931
 932         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 933                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 934                         return(ENOBUFS);
 935         };
 936
 937         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 938                         sc->bge_cdata.bge_rx_jumbo_ring_map,
 939                         BUS_DMASYNC_PREWRITE);
 940
 941         sc->bge_jumbo = i - 1;
 942
 943         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
 944         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 945         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 946
 947         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 948
 949         return(0);
 950 }
 951
 952 static void
 953 bge_free_rx_ring_jumbo(struct bge_softc *sc)
 954 {
 955         int i;
 956
 957         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 958                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
 959                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
 960                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
 961                 }
 962                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
 963                     sizeof(struct bge_rx_bd));
 964         }
 965 }
 966
 967 static void
 968 bge_free_tx_ring(struct bge_softc *sc)
 969 {
 970         int i;
 971
 972         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 973                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
 974                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
 975                                           sc->bge_cdata.bge_tx_dmamap[i]);
 976                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
 977                         sc->bge_cdata.bge_tx_chain[i] = NULL;
 978                 }
 979                 bzero(&sc->bge_ldata.bge_tx_ring[i],
 980                     sizeof(struct bge_tx_bd));
 981         }
 982 }
 983
 984 static int
 985 bge_init_tx_ring(struct bge_softc *sc)
 986 {
 987         sc->bge_txcnt = 0;
 988         sc->bge_tx_saved_considx = 0;
 989         sc->bge_tx_prodidx = 0;
 990
 991         /* Initialize transmit producer index for host-memory send ring. */
 992         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
 993
 994         /* 5700 b2 errata */
 995         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 996                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 997
 998         CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 999         /* 5700 b2 errata */
1000         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1001                 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1002
1003         return(0);
1004 }
1005
1006 static void
1007 bge_setmulti(struct bge_softc *sc)
1008 {
1009         struct ifnet *ifp;
1010         struct ifmultiaddr *ifma;
1011         uint32_t hashes[4] = { 0, 0, 0, 0 };
1012         int h, i;
1013
1014         ifp = &sc->arpcom.ac_if;
1015
1016         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1017                 for (i = 0; i < 4; i++)
1018                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1019                 return;
1020         }
1021
1022         /* First, zot all the existing filters. */
1023         for (i = 0; i < 4; i++)
1024                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1025
1026         /* Now program new ones. */
1027         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1028                 if (ifma->ifma_addr->sa_family != AF_LINK)
1029                         continue;
1030                 h = ether_crc32_le(
1031                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1032                     ETHER_ADDR_LEN) & 0x7f;
1033                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1034         }
1035
1036         for (i = 0; i < 4; i++)
1037                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1038 }
1039
1040 /*
1041  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1042  * self-test results.
1043  */
1044 static int
1045 bge_chipinit(struct bge_softc *sc)
1046 {
1047         int i;
1048         uint32_t dma_rw_ctl;
1049
1050         /* Set endian type before we access any non-PCI registers. */
1051         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1052
1053         /*
1054          * Check the 'ROM failed' bit on the RX CPU to see if
1055          * self-tests passed.
1056          */
1057         if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1058                 if_printf(&sc->arpcom.ac_if,
1059                           "RX CPU self-diagnostics failed!\n");
1060                 return(ENODEV);
1061         }
1062
1063         /* Clear the MAC control register */
1064         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1065
1066         /*
1067          * Clear the MAC statistics block in the NIC's
1068          * internal memory.
1069          */
1070         for (i = BGE_STATS_BLOCK;
1071             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1072                 BGE_MEMWIN_WRITE(sc, i, 0);
1073
1074         for (i = BGE_STATUS_BLOCK;
1075             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1076                 BGE_MEMWIN_WRITE(sc, i, 0);
1077
1078         /* Set up the PCI DMA control register. */
1079         if (sc->bge_flags & BGE_FLAG_PCIE) {
1080                 /* PCI Express */
1081                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1082                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1083                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1084         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1085                 /* PCI-X bus */
1086                 if (BGE_IS_5714_FAMILY(sc)) {
1087                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1088                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1089                         /* XXX magic values, Broadcom-supplied Linux driver */
1090                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1091                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1092                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1093                         } else {
1094                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1095                         }
1096                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1097                         /*
1098                          * The 5704 uses a different encoding of read/write
1099                          * watermarks.
1100                          */
1101                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1102                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1103                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1104                 } else {
1105                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1106                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1107                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1108                             (0x0F);
1109                 }
1110
1111                 /*
1112                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1113                  * for hardware bugs.
1114                  */
1115                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1116                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1117                         uint32_t tmp;
1118
1119                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1120                         if (tmp == 0x6 || tmp == 0x7)
1121                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1122                 }
1123         } else {
1124                 /* Conventional PCI bus */
1125                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1126                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1127                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1128                     (0x0F);
1129         }
1130
1131         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1132             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1133             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1134                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1135         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1136
1137         /*
1138          * Set up general mode register.
1139          */
1140         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1141             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1142             BGE_MODECTL_TX_NO_PHDR_CSUM);
1143
1144         /*
1145          * Disable memory write invalidate.  Apparently it is not supported
1146          * properly by these devices.
1147          */
1148         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1149
1150         /* Set the timer prescaler (always 66Mhz) */
1151         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1152
1153         return(0);
1154 }
1155
1156 static int
1157 bge_blockinit(struct bge_softc *sc)
1158 {
1159         struct bge_rcb *rcb;
1160         bus_size_t vrcb;
1161         bge_hostaddr taddr;
1162         uint32_t val;
1163         int i;
1164
1165         /*
1166          * Initialize the memory window pointer register so that
1167          * we can access the first 32K of internal NIC RAM. This will
1168          * allow us to set up the TX send ring RCBs and the RX return
1169          * ring RCBs, plus other things which live in NIC memory.
1170          */
1171         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1172
1173         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1174
1175         if (!BGE_IS_5705_PLUS(sc)) {
1176                 /* Configure mbuf memory pool */
1177                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1178                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1179                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1180                 else
1181                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1182
1183                 /* Configure DMA resource pool */
1184                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1185                     BGE_DMA_DESCRIPTORS);
1186                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1187         }
1188
1189         /* Configure mbuf pool watermarks */
1190         if (BGE_IS_5705_PLUS(sc)) {
1191                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1192                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1193         } else {
1194                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1195                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1196         }
1197         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1198
1199         /* Configure DMA resource watermarks */
1200         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1201         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1202
1203         /* Enable buffer manager */
1204         if (!BGE_IS_5705_PLUS(sc)) {
1205                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1206                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1207
1208                 /* Poll for buffer manager start indication */
1209                 for (i = 0; i < BGE_TIMEOUT; i++) {
1210                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1211                                 break;
1212                         DELAY(10);
1213                 }
1214
1215                 if (i == BGE_TIMEOUT) {
1216                         if_printf(&sc->arpcom.ac_if,
1217                                   "buffer manager failed to start\n");
1218                         return(ENXIO);
1219                 }
1220         }
1221
1222         /* Enable flow-through queues */
1223         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1224         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1225
1226         /* Wait until queue initialization is complete */
1227         for (i = 0; i < BGE_TIMEOUT; i++) {
1228                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1229                         break;
1230                 DELAY(10);
1231         }
1232
1233         if (i == BGE_TIMEOUT) {
1234                 if_printf(&sc->arpcom.ac_if,
1235                           "flow-through queue init failed\n");
1236                 return(ENXIO);
1237         }
1238
1239         /* Initialize the standard RX ring control block */
1240         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1241         rcb->bge_hostaddr.bge_addr_lo =
1242             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1243         rcb->bge_hostaddr.bge_addr_hi =
1244             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1245         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1246             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1247         if (BGE_IS_5705_PLUS(sc))
1248                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1249         else
1250                 rcb->bge_maxlen_flags =
1251                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1252         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1253         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1254         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1255         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1256         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1257
1258         /*
1259          * Initialize the jumbo RX ring control block
1260          * We set the 'ring disabled' bit in the flags
1261          * field until we're actually ready to start
1262          * using this ring (i.e. once we set the MTU
1263          * high enough to require it).
1264          */
1265         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1266                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1267
1268                 rcb->bge_hostaddr.bge_addr_lo =
1269                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1270                 rcb->bge_hostaddr.bge_addr_hi =
1271                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1272                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1273                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1274                     BUS_DMASYNC_PREREAD);
1275                 rcb->bge_maxlen_flags =
1276                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1277                     BGE_RCB_FLAG_RING_DISABLED);
1278                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1279                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1280                     rcb->bge_hostaddr.bge_addr_hi);
1281                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1282                     rcb->bge_hostaddr.bge_addr_lo);
1283                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1284                     rcb->bge_maxlen_flags);
1285                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1286
1287                 /* Set up dummy disabled mini ring RCB */
1288                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1289                 rcb->bge_maxlen_flags =
1290                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1291                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1292                     rcb->bge_maxlen_flags);
1293         }
1294
1295         /*
1296          * Set the BD ring replentish thresholds. The recommended
1297          * values are 1/8th the number of descriptors allocated to
1298          * each ring.
1299          */
1300         if (BGE_IS_5705_PLUS(sc))
1301                 val = 8;
1302         else
1303                 val = BGE_STD_RX_RING_CNT / 8;
1304         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1305         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1306
1307         /*
1308          * Disable all unused send rings by setting the 'ring disabled'
1309          * bit in the flags field of all the TX send ring control blocks.
1310          * These are located in NIC memory.
1311          */
1312         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1313         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1314                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1315                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1316                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1317                 vrcb += sizeof(struct bge_rcb);
1318         }
1319
1320         /* Configure TX RCB 0 (we use only the first ring) */
1321         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1322         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1323         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1324         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1325         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1326             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1327         if (!BGE_IS_5705_PLUS(sc)) {
1328                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1329                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1330         }
1331
1332         /* Disable all unused RX return rings */
1333         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1334         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1335                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1336                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1337                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1338                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1339                     BGE_RCB_FLAG_RING_DISABLED));
1340                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1341                 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1342                     (i * (sizeof(uint64_t))), 0);
1343                 vrcb += sizeof(struct bge_rcb);
1344         }
1345
1346         /* Initialize RX ring indexes */
1347         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1348         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1349         CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1350
1351         /*
1352          * Set up RX return ring 0
1353          * Note that the NIC address for RX return rings is 0x00000000.
1354          * The return rings live entirely within the host, so the
1355          * nicaddr field in the RCB isn't used.
1356          */
1357         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1358         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1359         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1360         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1361         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1362         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1363             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1364
1365         /* Set random backoff seed for TX */
1366         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1367             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1368             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1369             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1370             BGE_TX_BACKOFF_SEED_MASK);
1371
1372         /* Set inter-packet gap */
1373         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1374
1375         /*
1376          * Specify which ring to use for packets that don't match
1377          * any RX rules.
1378          */
1379         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1380
1381         /*
1382          * Configure number of RX lists. One interrupt distribution
1383          * list, sixteen active lists, one bad frames class.
1384          */
1385         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1386
1387         /* Inialize RX list placement stats mask. */
1388         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1389         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1390
1391         /* Disable host coalescing until we get it set up */
1392         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1393
1394         /* Poll to make sure it's shut down. */
1395         for (i = 0; i < BGE_TIMEOUT; i++) {
1396                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1397                         break;
1398                 DELAY(10);
1399         }
1400
1401         if (i == BGE_TIMEOUT) {
1402                 if_printf(&sc->arpcom.ac_if,
1403                           "host coalescing engine failed to idle\n");
1404                 return(ENXIO);
1405         }
1406
1407         /* Set up host coalescing defaults */
1408         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1409         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1410         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1411         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1412         if (!BGE_IS_5705_PLUS(sc)) {
1413                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1414                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1415         }
1416         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1417         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1418
1419         /* Set up address of statistics block */
1420         if (!BGE_IS_5705_PLUS(sc)) {
1421                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1422                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1423                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1424                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1425
1426                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1427                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1428                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1429         }
1430
1431         /* Set up address of status block */
1432         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1433             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1434         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1435             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1436         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1437         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1438
1439         /* Turn on host coalescing state machine */
1440         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1441
1442         /* Turn on RX BD completion state machine and enable attentions */
1443         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1444             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1445
1446         /* Turn on RX list placement state machine */
1447         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1448
1449         /* Turn on RX list selector state machine. */
1450         if (!BGE_IS_5705_PLUS(sc))
1451                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1452
1453         /* Turn on DMA, clear stats */
1454         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1455             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1456             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1457             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1458             ((sc->bge_flags & BGE_FLAG_TBI) ?
1459              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1460
1461         /* Set misc. local control, enable interrupts on attentions */
1462         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1463
1464 #ifdef notdef
1465         /* Assert GPIO pins for PHY reset */
1466         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1467             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1468         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1469             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1470 #endif
1471
1472         /* Turn on DMA completion state machine */
1473         if (!BGE_IS_5705_PLUS(sc))
1474                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1475
1476         /* Turn on write DMA state machine */
1477         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1478         if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1479             sc->bge_asicrev == BGE_ASICREV_BCM5787)
1480                 val |= (1 << 29);       /* Enable host coalescing bug fix. */
1481         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1482
1483         /* Turn on read DMA state machine */
1484         CSR_WRITE_4(sc, BGE_RDMA_MODE,
1485             BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1486
1487         /* Turn on RX data completion state machine */
1488         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1489
1490         /* Turn on RX BD initiator state machine */
1491         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1492
1493         /* Turn on RX data and RX BD initiator state machine */
1494         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1495
1496         /* Turn on Mbuf cluster free state machine */
1497         if (!BGE_IS_5705_PLUS(sc))
1498                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1499
1500         /* Turn on send BD completion state machine */
1501         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1502
1503         /* Turn on send data completion state machine */
1504         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1505
1506         /* Turn on send data initiator state machine */
1507         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1508
1509         /* Turn on send BD initiator state machine */
1510         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1511
1512         /* Turn on send BD selector state machine */
1513         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1514
1515         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1516         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1517             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1518
1519         /* ack/clear link change events */
1520         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1521             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1522             BGE_MACSTAT_LINK_CHANGED);
1523         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1524
1525         /* Enable PHY auto polling (for MII/GMII only) */
1526         if (sc->bge_flags & BGE_FLAG_TBI) {
1527                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1528         } else {
1529                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1530                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1531                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1532                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1533                             BGE_EVTENB_MI_INTERRUPT);
1534                 }
1535         }
1536
1537         /*
1538          * Clear any pending link state attention.
1539          * Otherwise some link state change events may be lost until attention
1540          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1541          * It's not necessary on newer BCM chips - perhaps enabling link
1542          * state change attentions implies clearing pending attention.
1543          */
1544         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1545             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1546             BGE_MACSTAT_LINK_CHANGED);
1547
1548         /* Enable link state change attentions. */
1549         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1550
1551         return(0);
1552 }
1553
1554 /*
1555  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1556  * against our list and return its name if we find a match. Note
1557  * that since the Broadcom controller contains VPD support, we
1558  * can get the device name string from the controller itself instead
1559  * of the compiled-in string. This is a little slow, but it guarantees
1560  * we'll always announce the right product name.
1561  */
1562 static int
1563 bge_probe(device_t dev)
1564 {
1565         struct bge_softc *sc;
1566         struct bge_type *t;
1567         char *descbuf;
1568         uint16_t product, vendor;
1569
1570         product = pci_get_device(dev);
1571         vendor = pci_get_vendor(dev);
1572
1573         for (t = bge_devs; t->bge_name != NULL; t++) {
1574                 if (vendor == t->bge_vid && product == t->bge_did)
1575                         break;
1576         }
1577
1578         if (t->bge_name == NULL)
1579                 return(ENXIO);
1580
1581         sc = device_get_softc(dev);
1582         descbuf = kmalloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1583         ksnprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1584             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1585         device_set_desc_copy(dev, descbuf);
1586         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1587                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1588         kfree(descbuf, M_TEMP);
1589         return(0);
1590 }
1591
1592 static int
1593 bge_attach(device_t dev)
1594 {
1595         struct ifnet *ifp;
1596         struct bge_softc *sc;
1597         uint32_t hwcfg = 0;
1598         uint32_t mac_addr = 0;
1599         int error = 0, rid;
1600         uint8_t ether_addr[ETHER_ADDR_LEN];
1601
1602         sc = device_get_softc(dev);
1603         sc->bge_dev = dev;
1604         callout_init(&sc->bge_stat_timer);
1605         lwkt_serialize_init(&sc->bge_jslot_serializer);
1606
1607         /*
1608          * Map control/status registers.
1609          */
1610         pci_enable_busmaster(dev);
1611
1612         rid = BGE_PCI_BAR0;
1613         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1614             RF_ACTIVE);
1615
1616         if (sc->bge_res == NULL) {
1617                 device_printf(dev, "couldn't map memory\n");
1618                 return ENXIO;
1619         }
1620
1621         sc->bge_btag = rman_get_bustag(sc->bge_res);
1622         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1623
1624         /* Save ASIC rev. */
1625         sc->bge_chipid =
1626             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1627             BGE_PCIMISCCTL_ASICREV;
1628         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1629         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1630
1631         /* Save chipset family. */
1632         switch (sc->bge_asicrev) {
1633         case BGE_ASICREV_BCM5700:
1634         case BGE_ASICREV_BCM5701:
1635         case BGE_ASICREV_BCM5703:
1636         case BGE_ASICREV_BCM5704:
1637                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1638                 break;
1639
1640         case BGE_ASICREV_BCM5714_A0:
1641         case BGE_ASICREV_BCM5780:
1642         case BGE_ASICREV_BCM5714:
1643                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1644                 /* Fall through */
1645
1646         case BGE_ASICREV_BCM5750:
1647         case BGE_ASICREV_BCM5752:
1648         case BGE_ASICREV_BCM5755:
1649         case BGE_ASICREV_BCM5787:
1650                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1651                 /* Fall through */
1652
1653         case BGE_ASICREV_BCM5705:
1654                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1655                 break;
1656         }
1657
1658         /*
1659          * Set various quirk flags.
1660          */
1661
1662         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1663         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1664             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1665              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1666               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1667             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1668                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1669
1670         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1671             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1672                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1673
1674         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1675             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1676                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1677
1678         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1679                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1680
1681         if (BGE_IS_5705_PLUS(sc)) {
1682                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1683                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1684                         uint32_t product = pci_get_device(dev);
1685
1686                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1687                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1688                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1689                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1690                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1691                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1692                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1693                 }
1694         }
1695
1696         /* Allocate interrupt */
1697         rid = 0;
1698
1699         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1700             RF_SHAREABLE | RF_ACTIVE);
1701
1702         if (sc->bge_irq == NULL) {
1703                 device_printf(dev, "couldn't map interrupt\n");
1704                 error = ENXIO;
1705                 goto fail;
1706         }
1707
1708         /*
1709          * Check if this is a PCI-X or PCI Express device.
1710          */
1711         if (BGE_IS_5705_PLUS(sc)) {
1712                 uint32_t reg;
1713
1714                 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
1715                 if ((reg & 0xff) == BGE_PCIE_CAPID)
1716                         sc->bge_flags |= BGE_FLAG_PCIE;
1717         } else {
1718                 /*
1719                  * Check if the device is in PCI-X Mode.
1720                  * (This bit is not valid on PCI Express controllers.)
1721                  */
1722                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1723                     BGE_PCISTATE_PCI_BUSMODE) == 0)
1724                         sc->bge_flags |= BGE_FLAG_PCIX;
1725         }
1726
1727         ifp = &sc->arpcom.ac_if;
1728         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1729
1730         /* Try to reset the chip. */
1731         bge_reset(sc);
1732
1733         if (bge_chipinit(sc)) {
1734                 device_printf(dev, "chip initialization failed\n");
1735                 error = ENXIO;
1736                 goto fail;
1737         }
1738
1739         /*
1740          * Get station address from the EEPROM.
1741          */
1742         mac_addr = bge_readmem_ind(sc, 0x0c14);
1743         if ((mac_addr >> 16) == 0x484b) {
1744                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1745                 ether_addr[1] = (uint8_t)mac_addr;
1746                 mac_addr = bge_readmem_ind(sc, 0x0c18);
1747                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1748                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1749                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1750                 ether_addr[5] = (uint8_t)mac_addr;
1751         } else if (bge_read_eeprom(sc, ether_addr,
1752             BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1753                 device_printf(dev, "failed to read station address\n");
1754                 error = ENXIO;
1755                 goto fail;
1756         }
1757
1758         /* 5705/5750 limits RX return ring to 512 entries. */
1759         if (BGE_IS_5705_PLUS(sc))
1760                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1761         else
1762                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1763
1764         error = bge_dma_alloc(sc);
1765         if (error)
1766                 goto fail;
1767
1768         /* Set default tuneable values. */
1769         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1770         sc->bge_rx_coal_ticks = 150;
1771         sc->bge_tx_coal_ticks = 150;
1772         sc->bge_rx_max_coal_bds = 10;
1773         sc->bge_tx_max_coal_bds = 10;
1774
1775         /* Set up ifnet structure */
1776         ifp->if_softc = sc;
1777         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1778         ifp->if_ioctl = bge_ioctl;
1779         ifp->if_start = bge_start;
1780 #ifdef DEVICE_POLLING
1781         ifp->if_poll = bge_poll;
1782 #endif
1783         ifp->if_watchdog = bge_watchdog;
1784         ifp->if_init = bge_init;
1785         ifp->if_mtu = ETHERMTU;
1786         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1787         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1788         ifq_set_ready(&ifp->if_snd);
1789
1790         /*
1791          * 5700 B0 chips do not support checksumming correctly due
1792          * to hardware bugs.
1793          */
1794         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1795                 ifp->if_capabilities |= IFCAP_HWCSUM;
1796                 ifp->if_hwassist = BGE_CSUM_FEATURES;
1797         }
1798         ifp->if_capenable = ifp->if_capabilities;
1799
1800         /*
1801          * Figure out what sort of media we have by checking the
1802          * hardware config word in the first 32k of NIC internal memory,
1803          * or fall back to examining the EEPROM if necessary.
1804          * Note: on some BCM5700 cards, this value appears to be unset.
1805          * If that's the case, we have to rely on identifying the NIC
1806          * by its PCI subsystem ID, as we do below for the SysKonnect
1807          * SK-9D41.
1808          */
1809         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1810                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1811         else {
1812                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1813                                     sizeof(hwcfg))) {
1814                         device_printf(dev, "failed to read EEPROM\n");
1815                         error = ENXIO;
1816                         goto fail;
1817                 }
1818                 hwcfg = ntohl(hwcfg);
1819         }
1820
1821         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1822                 sc->bge_flags |= BGE_FLAG_TBI;
1823
1824         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1825         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1826                 sc->bge_flags |= BGE_FLAG_TBI;
1827
1828         if (sc->bge_flags & BGE_FLAG_TBI) {
1829                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1830                     bge_ifmedia_upd, bge_ifmedia_sts);
1831                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1832                 ifmedia_add(&sc->bge_ifmedia,
1833                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1834                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1835                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1836                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1837         } else {
1838                 /*
1839                  * Do transceiver setup.
1840                  */
1841                 if (mii_phy_probe(dev, &sc->bge_miibus,
1842                     bge_ifmedia_upd, bge_ifmedia_sts)) {
1843                         device_printf(dev, "MII without any PHY!\n");
1844                         error = ENXIO;
1845                         goto fail;
1846                 }
1847         }
1848
1849         /*
1850          * When using the BCM5701 in PCI-X mode, data corruption has
1851          * been observed in the first few bytes of some received packets.
1852          * Aligning the packet buffer in memory eliminates the corruption.
1853          * Unfortunately, this misaligns the packet payloads.  On platforms
1854          * which do not support unaligned accesses, we will realign the
1855          * payloads by copying the received packets.
1856          */
1857         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1858             (sc->bge_flags & BGE_FLAG_PCIX))
1859                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
1860
1861         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1862             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1863                 sc->bge_link_upd = bge_bcm5700_link_upd;
1864                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
1865         } else if (sc->bge_flags & BGE_FLAG_TBI) {
1866                 sc->bge_link_upd = bge_tbi_link_upd;
1867                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1868         } else {
1869                 sc->bge_link_upd = bge_copper_link_upd;
1870                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1871         }
1872
1873         /*
1874          * Call MI attach routine.
1875          */
1876         ether_ifattach(ifp, ether_addr, NULL);
1877
1878         error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1879                                bge_intr, sc, &sc->bge_intrhand,
1880                                ifp->if_serializer);
1881         if (error) {
1882                 ether_ifdetach(ifp);
1883                 device_printf(dev, "couldn't set up irq\n");
1884                 goto fail;
1885         }
1886         return(0);
1887 fail:
1888         bge_detach(dev);
1889         return(error);
1890 }
1891
1892 static int
1893 bge_detach(device_t dev)
1894 {
1895         struct bge_softc *sc = device_get_softc(dev);
1896
1897         if (device_is_attached(dev)) {
1898                 struct ifnet *ifp = &sc->arpcom.ac_if;
1899
1900                 lwkt_serialize_enter(ifp->if_serializer);
1901                 bge_stop(sc);
1902                 bge_reset(sc);
1903                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1904                 lwkt_serialize_exit(ifp->if_serializer);
1905
1906                 ether_ifdetach(ifp);
1907         }
1908
1909         if (sc->bge_flags & BGE_FLAG_TBI)
1910                 ifmedia_removeall(&sc->bge_ifmedia);
1911         if (sc->bge_miibus)
1912                 device_delete_child(dev, sc->bge_miibus);
1913         bus_generic_detach(dev);
1914
1915         if (sc->bge_irq != NULL)
1916                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1917
1918         if (sc->bge_res != NULL)
1919                 bus_release_resource(dev, SYS_RES_MEMORY,
1920                     BGE_PCI_BAR0, sc->bge_res);
1921
1922         bge_dma_free(sc);
1923
1924         return 0;
1925 }
1926
1927 static void
1928 bge_reset(struct bge_softc *sc)
1929 {
1930         device_t dev;
1931         uint32_t cachesize, command, pcistate, reset;
1932         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
1933         int i, val = 0;
1934
1935         dev = sc->bge_dev;
1936
1937         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
1938                 if (sc->bge_flags & BGE_FLAG_PCIE)
1939                         write_op = bge_writemem_direct;
1940                 else
1941                         write_op = bge_writemem_ind;
1942         } else {
1943                 write_op = bge_writereg_ind;
1944         }
1945
1946         /* Save some important PCI state. */
1947         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1948         command = pci_read_config(dev, BGE_PCI_CMD, 4);
1949         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1950
1951         pci_write_config(dev, BGE_PCI_MISC_CTL,
1952             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1953             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1954
1955         /* Disable fastboot on controllers that support it. */
1956         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
1957             sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1958             sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1959                 if (bootverbose)
1960                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
1961                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
1962         }
1963
1964         /*
1965          * Write the magic number to SRAM at offset 0xB50.
1966          * When firmware finishes its initialization it will
1967          * write ~BGE_MAGIC_NUMBER to the same location.
1968          */
1969         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1970
1971         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
1972
1973         /* XXX: Broadcom Linux driver. */
1974         if (sc->bge_flags & BGE_FLAG_PCIE) {
1975                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
1976                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
1977                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1978                         /* Prevent PCIE link training during global reset */
1979                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
1980                         reset |= (1<<29);
1981                 }
1982         }
1983
1984         /*
1985          * Set GPHY Power Down Override to leave GPHY
1986          * powered up in D0 uninitialized.
1987          */
1988         if (BGE_IS_5705_PLUS(sc))
1989                 reset |= 0x04000000;
1990
1991         /* Issue global reset */
1992         write_op(sc, BGE_MISC_CFG, reset);
1993
1994         DELAY(1000);
1995
1996         /* XXX: Broadcom Linux driver. */
1997         if (sc->bge_flags & BGE_FLAG_PCIE) {
1998                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
1999                         uint32_t v;
2000
2001                         DELAY(500000); /* wait for link training to complete */
2002                         v = pci_read_config(dev, 0xc4, 4);
2003                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2004                 }
2005                 /*
2006                  * Set PCIE max payload size to 128 bytes and
2007                  * clear error status.
2008                  */
2009                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2010         }
2011
2012         /* Reset some of the PCI state that got zapped by reset */
2013         pci_write_config(dev, BGE_PCI_MISC_CTL,
2014             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2015             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2016         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2017         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2018         write_op(sc, BGE_MISC_CFG, (65 << 1));
2019
2020         /* Enable memory arbiter. */
2021         if (BGE_IS_5714_FAMILY(sc)) {
2022                 uint32_t val;
2023
2024                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2025                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2026         } else {
2027                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2028         }
2029
2030         /*
2031          * Poll until we see the 1's complement of the magic number.
2032          * This indicates that the firmware initialization
2033          * is complete.
2034          */
2035         for (i = 0; i < BGE_TIMEOUT; i++) {
2036                 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2037                 if (val == ~BGE_MAGIC_NUMBER)
2038                         break;
2039                 DELAY(10);
2040         }
2041
2042         if (i == BGE_TIMEOUT) {
2043                 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out,"
2044                           "found 0x%08x\n", val);
2045                 return;
2046         }
2047
2048         /*
2049          * XXX Wait for the value of the PCISTATE register to
2050          * return to its original pre-reset state. This is a
2051          * fairly good indicator of reset completion. If we don't
2052          * wait for the reset to fully complete, trying to read
2053          * from the device's non-PCI registers may yield garbage
2054          * results.
2055          */
2056         for (i = 0; i < BGE_TIMEOUT; i++) {
2057                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2058                         break;
2059                 DELAY(10);
2060         }
2061
2062         if (sc->bge_flags & BGE_FLAG_PCIE) {
2063                 reset = bge_readmem_ind(sc, 0x7c00);
2064                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2065         }
2066
2067         /* Fix up byte swapping */
2068         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2069             BGE_MODECTL_BYTESWAP_DATA);
2070
2071         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2072
2073         /*
2074          * The 5704 in TBI mode apparently needs some special
2075          * adjustment to insure the SERDES drive level is set
2076          * to 1.2V.
2077          */
2078         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2079             (sc->bge_flags & BGE_FLAG_TBI)) {
2080                 uint32_t serdescfg;
2081
2082                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2083                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2084                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2085         }
2086
2087         /* XXX: Broadcom Linux driver. */
2088         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2089             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2090                 uint32_t v;
2091
2092                 v = CSR_READ_4(sc, 0x7c00);
2093                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2094         }
2095
2096         DELAY(10000);
2097 }
2098
2099 /*
2100  * Frame reception handling. This is called if there's a frame
2101  * on the receive return list.
2102  *
2103  * Note: we have to be able to handle two possibilities here:
2104  * 1) the frame is from the jumbo recieve ring
2105  * 2) the frame is from the standard receive ring
2106  */
2107
2108 static void
2109 bge_rxeof(struct bge_softc *sc)
2110 {
2111         struct ifnet *ifp;
2112         int stdcnt = 0, jumbocnt = 0;
2113
2114         if (sc->bge_rx_saved_considx ==
2115             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2116                 return;
2117
2118         ifp = &sc->arpcom.ac_if;
2119
2120         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2121                         sc->bge_cdata.bge_rx_return_ring_map,
2122                         BUS_DMASYNC_POSTREAD);
2123         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2124                         sc->bge_cdata.bge_rx_std_ring_map,
2125                         BUS_DMASYNC_POSTREAD);
2126         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2127                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2128                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2129                                 BUS_DMASYNC_POSTREAD);
2130         }
2131
2132         while (sc->bge_rx_saved_considx !=
2133                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2134                 struct bge_rx_bd        *cur_rx;
2135                 uint32_t                rxidx;
2136                 struct mbuf             *m = NULL;
2137                 uint16_t                vlan_tag = 0;
2138                 int                     have_tag = 0;
2139
2140                 cur_rx =
2141             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2142
2143                 rxidx = cur_rx->bge_idx;
2144                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2145
2146                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2147                         have_tag = 1;
2148                         vlan_tag = cur_rx->bge_vlan_tag;
2149                 }
2150
2151                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2152                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2153                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2154                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2155                         jumbocnt++;
2156                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2157                                 ifp->if_ierrors++;
2158                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2159                                 continue;
2160                         }
2161                         if (bge_newbuf_jumbo(sc,
2162                             sc->bge_jumbo, NULL) == ENOBUFS) {
2163                                 ifp->if_ierrors++;
2164                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2165                                 continue;
2166                         }
2167                 } else {
2168                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2169                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2170                                         sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2171                                         BUS_DMASYNC_POSTREAD);
2172                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2173                                 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2174                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2175                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2176                         stdcnt++;
2177                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2178                                 ifp->if_ierrors++;
2179                                 bge_newbuf_std(sc, sc->bge_std, m);
2180                                 continue;
2181                         }
2182                         if (bge_newbuf_std(sc, sc->bge_std,
2183                             NULL) == ENOBUFS) {
2184                                 ifp->if_ierrors++;
2185                                 bge_newbuf_std(sc, sc->bge_std, m);
2186                                 continue;
2187                         }
2188                 }
2189
2190                 ifp->if_ipackets++;
2191 #ifndef __i386__
2192                 /*
2193                  * The i386 allows unaligned accesses, but for other
2194                  * platforms we must make sure the payload is aligned.
2195                  */
2196                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2197                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2198                             cur_rx->bge_len);
2199                         m->m_data += ETHER_ALIGN;
2200                 }
2201 #endif
2202                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2203                 m->m_pkthdr.rcvif = ifp;
2204
2205                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2206                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2207                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2208                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2209                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2210                         }
2211                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
2212                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2213                                 m->m_pkthdr.csum_data =
2214                                     cur_rx->bge_tcp_udp_csum;
2215                                 m->m_pkthdr.csum_flags |=
2216                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2217                         }
2218                 }
2219
2220                 /*
2221                  * If we received a packet with a vlan tag, pass it
2222                  * to vlan_input() instead of ether_input().
2223                  */
2224                 if (have_tag) {
2225                         VLAN_INPUT_TAG(m, vlan_tag);
2226                         have_tag = vlan_tag = 0;
2227                 } else {
2228                         ifp->if_input(ifp, m);
2229                 }
2230         }
2231
2232         if (stdcnt > 0) {
2233                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2234                                 sc->bge_cdata.bge_rx_std_ring_map,
2235                                 BUS_DMASYNC_PREWRITE);
2236         }
2237
2238         if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2239                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2240                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2241                                 BUS_DMASYNC_PREWRITE);
2242         }
2243
2244         CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2245         if (stdcnt)
2246                 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2247         if (jumbocnt)
2248                 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2249 }
2250
2251 static void
2252 bge_txeof(struct bge_softc *sc)
2253 {
2254         struct bge_tx_bd *cur_tx = NULL;
2255         struct ifnet *ifp;
2256
2257         if (sc->bge_tx_saved_considx ==
2258             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2259                 return;
2260
2261         ifp = &sc->arpcom.ac_if;
2262
2263         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2264                         sc->bge_cdata.bge_tx_ring_map,
2265                         BUS_DMASYNC_POSTREAD);
2266
2267         /*
2268          * Go through our tx ring and free mbufs for those
2269          * frames that have been sent.
2270          */
2271         while (sc->bge_tx_saved_considx !=
2272                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2273                 uint32_t idx = 0;
2274
2275                 idx = sc->bge_tx_saved_considx;
2276                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2277                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2278                         ifp->if_opackets++;
2279                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2280                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2281                                         sc->bge_cdata.bge_tx_dmamap[idx],
2282                                         BUS_DMASYNC_POSTWRITE);
2283                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2284                             sc->bge_cdata.bge_tx_dmamap[idx]);
2285                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2286                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2287                 }
2288                 sc->bge_txcnt--;
2289                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2290         }
2291
2292         if (cur_tx != NULL &&
2293             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2294             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2295                 ifp->if_flags &= ~IFF_OACTIVE;
2296
2297         if (sc->bge_txcnt == 0)
2298                 ifp->if_timer = 0;
2299
2300         if (!ifq_is_empty(&ifp->if_snd))
2301                 ifp->if_start(ifp);
2302 }
2303
2304 #ifdef DEVICE_POLLING
2305
2306 static void
2307 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2308 {
2309         struct bge_softc *sc = ifp->if_softc;
2310         uint32_t status;
2311
2312         switch(cmd) {
2313         case POLL_REGISTER:
2314                 /*
2315                  * Mask the interrupt when we start polling
2316                  */
2317                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2318                 break;
2319         case POLL_DEREGISTER:
2320                 /*
2321                  * Unmask the interrupt when we stop polling.
2322                  */
2323                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2324                 break;
2325         case POLL_AND_CHECK_STATUS:
2326                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2327                                 sc->bge_cdata.bge_status_map,
2328                                 BUS_DMASYNC_POSTREAD);
2329
2330                 /*
2331                  * Process link state changes.
2332                  */
2333                 status = CSR_READ_4(sc, BGE_MAC_STS);
2334                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2335                         sc->bge_link_evt = 0;
2336                         sc->bge_link_upd(sc, status);
2337                 }
2338                 /* fall through */
2339         case POLL_ONLY:
2340                 if (ifp->if_flags & IFF_RUNNING) {
2341                         bge_rxeof(sc);
2342                         bge_txeof(sc);
2343                 }
2344                 break;
2345         }
2346 }
2347
2348 #endif
2349
2350 static void
2351 bge_intr(void *xsc)
2352 {
2353         struct bge_softc *sc = xsc;
2354         struct ifnet *ifp = &sc->arpcom.ac_if;
2355         uint32_t status;
2356
2357         /*
2358          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2359          * disable interrupts by writing nonzero like we used to, since with
2360          * our current organization this just gives complications and
2361          * pessimizations for re-enabling interrupts.  We used to have races
2362          * instead of the necessary complications.  Disabling interrupts
2363          * would just reduce the chance of a status update while we are
2364          * running (by switching to the interrupt-mode coalescence
2365          * parameters), but this chance is already very low so it is more
2366          * efficient to get another interrupt than prevent it.
2367          *
2368          * We do the ack first to ensure another interrupt if there is a
2369          * status update after the ack.  We don't check for the status
2370          * changing later because it is more efficient to get another
2371          * interrupt than prevent it, not quite as above (not checking is
2372          * a smaller optimization than not toggling the interrupt enable,
2373          * since checking doesn't involve PCI accesses and toggling require
2374          * the status check).  So toggling would probably be a pessimization
2375          * even with MSI.  It would only be needed for using a task queue.
2376          */
2377         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2378
2379         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2380                         sc->bge_cdata.bge_status_map,
2381                         BUS_DMASYNC_POSTREAD);
2382
2383         /*
2384          * Process link state changes.
2385          */
2386         status = CSR_READ_4(sc, BGE_MAC_STS);
2387         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2388                 sc->bge_link_evt = 0;
2389                 sc->bge_link_upd(sc, status);
2390         }
2391
2392         if (ifp->if_flags & IFF_RUNNING) {
2393                 /* Check RX return ring producer/consumer */
2394                 bge_rxeof(sc);
2395
2396                 /* Check TX ring producer/consumer */
2397                 bge_txeof(sc);
2398         }
2399 }
2400
2401 static void
2402 bge_tick(void *xsc)
2403 {
2404         struct bge_softc *sc = xsc;
2405         struct ifnet *ifp = &sc->arpcom.ac_if;
2406
2407         lwkt_serialize_enter(ifp->if_serializer);
2408
2409         if (BGE_IS_5705_PLUS(sc))
2410                 bge_stats_update_regs(sc);
2411         else
2412                 bge_stats_update(sc);
2413
2414         if (sc->bge_flags & BGE_FLAG_TBI) {
2415                 /*
2416                  * Since in TBI mode auto-polling can't be used we should poll
2417                  * link status manually. Here we register pending link event
2418                  * and trigger interrupt.
2419                  */
2420                 sc->bge_link_evt++;
2421                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2422         } else if (!sc->bge_link) {
2423                 mii_tick(device_get_softc(sc->bge_miibus));
2424         }
2425
2426         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2427
2428         lwkt_serialize_exit(ifp->if_serializer);
2429 }
2430
2431 static void
2432 bge_stats_update_regs(struct bge_softc *sc)
2433 {
2434         struct ifnet *ifp = &sc->arpcom.ac_if;
2435         struct bge_mac_stats_regs stats;
2436         uint32_t *s;
2437         int i;
2438
2439         s = (uint32_t *)&stats;
2440         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2441                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2442                 s++;
2443         }
2444
2445         ifp->if_collisions +=
2446            (stats.dot3StatsSingleCollisionFrames +
2447            stats.dot3StatsMultipleCollisionFrames +
2448            stats.dot3StatsExcessiveCollisions +
2449            stats.dot3StatsLateCollisions) -
2450            ifp->if_collisions;
2451 }
2452
2453 static void
2454 bge_stats_update(struct bge_softc *sc)
2455 {
2456         struct ifnet *ifp = &sc->arpcom.ac_if;
2457         bus_size_t stats;
2458
2459         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2460
2461 #define READ_STAT(sc, stats, stat)      \
2462         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2463
2464         ifp->if_collisions +=
2465            (READ_STAT(sc, stats,
2466                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2467             READ_STAT(sc, stats,
2468                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2469             READ_STAT(sc, stats,
2470                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2471             READ_STAT(sc, stats,
2472                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2473            ifp->if_collisions;
2474
2475 #undef READ_STAT
2476
2477 #ifdef notdef
2478         ifp->if_collisions +=
2479            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2480            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2481            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2482            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2483            ifp->if_collisions;
2484 #endif
2485 }
2486
2487 /*
2488  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2489  * pointers to descriptors.
2490  */
2491 static int
2492 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2493 {
2494         struct bge_tx_bd *d = NULL;
2495         uint16_t csum_flags = 0;
2496         struct ifvlan *ifv = NULL;
2497         struct bge_dmamap_arg ctx;
2498         bus_dma_segment_t segs[BGE_NSEG_NEW];
2499         bus_dmamap_t map;
2500         int error, maxsegs, idx, i;
2501
2502         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2503             m_head->m_pkthdr.rcvif != NULL &&
2504             m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2505                 ifv = m_head->m_pkthdr.rcvif->if_softc;
2506
2507         if (m_head->m_pkthdr.csum_flags) {
2508                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2509                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2510                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2511                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2512                 if (m_head->m_flags & M_LASTFRAG)
2513                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2514                 else if (m_head->m_flags & M_FRAG)
2515                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2516         }
2517
2518         idx = *txidx;
2519         map = sc->bge_cdata.bge_tx_dmamap[idx];
2520
2521         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2522         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2523                 ("not enough segments %d\n", maxsegs));
2524
2525         if (maxsegs > BGE_NSEG_NEW)
2526                 maxsegs = BGE_NSEG_NEW;
2527
2528         /*
2529          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2530          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2531          * but when such padded frames employ the bge IP/TCP checksum
2532          * offload, the hardware checksum assist gives incorrect results
2533          * (possibly from incorporating its own padding into the UDP/TCP
2534          * checksum; who knows).  If we pad such runts with zeros, the
2535          * onboard checksum comes out correct.  We do this by pretending
2536          * the mbuf chain has too many fragments so the coalescing code
2537          * below can assemble the packet into a single buffer that's
2538          * padded out to the mininum frame size.
2539          */
2540         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2541             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2542                 error = EFBIG;
2543         } else {
2544                 ctx.bge_segs = segs;
2545                 ctx.bge_maxsegs = maxsegs;
2546                 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2547                                              m_head, bge_dma_map_mbuf, &ctx,
2548                                              BUS_DMA_NOWAIT);
2549         }
2550         if (error == EFBIG || ctx.bge_maxsegs == 0) {
2551                 struct mbuf *m_new;
2552
2553                 m_new = m_defrag(m_head, MB_DONTWAIT);
2554                 if (m_new == NULL) {
2555                         if_printf(&sc->arpcom.ac_if,
2556                                   "could not defrag TX mbuf\n");
2557                         error = ENOBUFS;
2558                         goto back;
2559                 } else {
2560                         m_head = m_new;
2561                 }
2562
2563                 /*
2564                  * Manually pad short frames, and zero the pad space
2565                  * to avoid leaking data.
2566                  */
2567                 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2568                     m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2569                         int pad_len = BGE_MIN_FRAME - m_head->m_pkthdr.len;
2570
2571                         bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
2572                               pad_len);
2573                         m_head->m_pkthdr.len += pad_len;
2574                         m_head->m_len = m_head->m_pkthdr.len;
2575                 }
2576
2577                 ctx.bge_segs = segs;
2578                 ctx.bge_maxsegs = maxsegs;
2579                 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2580                                              m_head, bge_dma_map_mbuf, &ctx,
2581                                              BUS_DMA_NOWAIT);
2582                 if (error || ctx.bge_maxsegs == 0) {
2583                         if_printf(&sc->arpcom.ac_if,
2584                                   "could not defrag TX mbuf\n");
2585                         if (error == 0)
2586                                 error = EFBIG;
2587                         goto back;
2588                 }
2589         } else if (error) {
2590                 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2591                 goto back;
2592         }
2593
2594         bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
2595
2596         for (i = 0; ; i++) {
2597                 d = &sc->bge_ldata.bge_tx_ring[idx];
2598
2599                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2600                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2601                 d->bge_len = segs[i].ds_len;
2602                 d->bge_flags = csum_flags;
2603
2604                 if (i == ctx.bge_maxsegs - 1)
2605                         break;
2606                 BGE_INC(idx, BGE_TX_RING_CNT);
2607         }
2608         /* Mark the last segment as end of packet... */
2609         d->bge_flags |= BGE_TXBDFLAG_END;
2610
2611         /* Set vlan tag to the first segment of the packet. */
2612         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2613         if (ifv != NULL) {
2614                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2615                 d->bge_vlan_tag = ifv->ifv_tag;
2616         } else {
2617                 d->bge_vlan_tag = 0;
2618         }
2619
2620         /*
2621          * Insure that the map for this transmission is placed at
2622          * the array index of the last descriptor in this chain.
2623          */
2624         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2625         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2626         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2627         sc->bge_txcnt += ctx.bge_maxsegs;
2628
2629         BGE_INC(idx, BGE_TX_RING_CNT);
2630         *txidx = idx;
2631 back:
2632         if (error)
2633                 m_freem(m_head);
2634         return error;
2635 }
2636
2637 /*
2638  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2639  * to the mbuf data regions directly in the transmit descriptors.
2640  */
2641 static void
2642 bge_start(struct ifnet *ifp)
2643 {
2644         struct bge_softc *sc = ifp->if_softc;
2645         struct mbuf *m_head = NULL;
2646         uint32_t prodidx;
2647         int need_trans;
2648
2649         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING ||
2650             !sc->bge_link)
2651                 return;
2652
2653         prodidx = sc->bge_tx_prodidx;
2654
2655         need_trans = 0;
2656         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2657                 m_head = ifq_poll(&ifp->if_snd);
2658                 if (m_head == NULL)
2659                         break;
2660
2661                 /*
2662                  * XXX
2663                  * The code inside the if() block is never reached since we
2664                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2665                  * requests to checksum TCP/UDP in a fragmented packet.
2666                  *
2667                  * XXX
2668                  * safety overkill.  If this is a fragmented packet chain
2669                  * with delayed TCP/UDP checksums, then only encapsulate
2670                  * it if we have enough descriptors to handle the entire
2671                  * chain at once.
2672                  * (paranoia -- may not actually be needed)
2673                  */
2674                 if (m_head->m_flags & M_FIRSTFRAG &&
2675                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2676                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2677                             m_head->m_pkthdr.csum_data + 16) {
2678                                 ifp->if_flags |= IFF_OACTIVE;
2679                                 break;
2680                         }
2681                 }
2682
2683                 /*
2684                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2685                  * descriptors of the end of the ring.  Also make
2686                  * sure there are BGE_NSEG_SPARE descriptors for
2687                  * jumbo buffers' defragmentation.
2688                  */
2689                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2690                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2691                         ifp->if_flags |= IFF_OACTIVE;
2692                         break;
2693                 }
2694
2695                 /*
2696                  * Dequeue the packet before encapsulation, since
2697                  * bge_encap() may free the packet if error happens.
2698                  */
2699                 ifq_dequeue(&ifp->if_snd, m_head);
2700
2701                 /*
2702                  * Pack the data into the transmit ring. If we
2703                  * don't have room, set the OACTIVE flag and wait
2704                  * for the NIC to drain the ring.
2705                  */
2706                 if (bge_encap(sc, m_head, &prodidx)) {
2707                         ifp->if_flags |= IFF_OACTIVE;
2708                         break;
2709                 }
2710                 need_trans = 1;
2711
2712                 BPF_MTAP(ifp, m_head);
2713         }
2714
2715         if (!need_trans)
2716                 return;
2717
2718         /* Transmit */
2719         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2720         /* 5700 b2 errata */
2721         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2722                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2723
2724         sc->bge_tx_prodidx = prodidx;
2725
2726         /*
2727          * Set a timeout in case the chip goes out to lunch.
2728          */
2729         ifp->if_timer = 5;
2730 }
2731
2732 static void
2733 bge_init(void *xsc)
2734 {
2735         struct bge_softc *sc = xsc;
2736         struct ifnet *ifp = &sc->arpcom.ac_if;
2737         uint16_t *m;
2738
2739         ASSERT_SERIALIZED(ifp->if_serializer);
2740
2741         if (ifp->if_flags & IFF_RUNNING)
2742                 return;
2743
2744         /* Cancel pending I/O and flush buffers. */
2745         bge_stop(sc);
2746         bge_reset(sc);
2747         bge_chipinit(sc);
2748
2749         /*
2750          * Init the various state machines, ring
2751          * control blocks and firmware.
2752          */
2753         if (bge_blockinit(sc)) {
2754                 if_printf(ifp, "initialization failure\n");
2755                 return;
2756         }
2757
2758         /* Specify MTU. */
2759         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2760             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2761
2762         /* Load our MAC address. */
2763         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2764         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2765         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2766
2767         /* Enable or disable promiscuous mode as needed. */
2768         bge_setpromisc(sc);
2769
2770         /* Program multicast filter. */
2771         bge_setmulti(sc);
2772
2773         /* Init RX ring. */
2774         bge_init_rx_ring_std(sc);
2775
2776         /*
2777          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2778          * memory to insure that the chip has in fact read the first
2779          * entry of the ring.
2780          */
2781         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2782                 uint32_t                v, i;
2783                 for (i = 0; i < 10; i++) {
2784                         DELAY(20);
2785                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2786                         if (v == (MCLBYTES - ETHER_ALIGN))
2787                                 break;
2788                 }
2789                 if (i == 10)
2790                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2791         }
2792
2793         /* Init jumbo RX ring. */
2794         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2795                 bge_init_rx_ring_jumbo(sc);
2796
2797         /* Init our RX return ring index */
2798         sc->bge_rx_saved_considx = 0;
2799
2800         /* Init TX ring. */
2801         bge_init_tx_ring(sc);
2802
2803         /* Turn on transmitter */
2804         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2805
2806         /* Turn on receiver */
2807         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2808
2809         /* Tell firmware we're alive. */
2810         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2811
2812         /* Enable host interrupts. */
2813         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2814 #ifdef DEVICE_POLLING
2815         if ((ifp->if_flags & IFF_POLLING) == 0)
2816 #endif
2817                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2818         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2819
2820         bge_ifmedia_upd(ifp);
2821
2822         ifp->if_flags |= IFF_RUNNING;
2823         ifp->if_flags &= ~IFF_OACTIVE;
2824
2825         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2826 }
2827
2828 /*
2829  * Set media options.
2830  */
2831 static int
2832 bge_ifmedia_upd(struct ifnet *ifp)
2833 {
2834         struct bge_softc *sc = ifp->if_softc;
2835
2836         /* If this is a 1000baseX NIC, enable the TBI port. */
2837         if (sc->bge_flags & BGE_FLAG_TBI) {
2838                 struct ifmedia *ifm = &sc->bge_ifmedia;
2839
2840                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2841                         return(EINVAL);
2842
2843                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2844                 case IFM_AUTO:
2845                         /*
2846                          * The BCM5704 ASIC appears to have a special
2847                          * mechanism for programming the autoneg
2848                          * advertisement registers in TBI mode.
2849                          */
2850                         if (!bge_fake_autoneg &&
2851                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2852                                 uint32_t sgdig;
2853
2854                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2855                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2856                                 sgdig |= BGE_SGDIGCFG_AUTO |
2857                                          BGE_SGDIGCFG_PAUSE_CAP |
2858                                          BGE_SGDIGCFG_ASYM_PAUSE;
2859                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2860                                             sgdig | BGE_SGDIGCFG_SEND);
2861                                 DELAY(5);
2862                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2863                         }
2864                         break;
2865                 case IFM_1000_SX:
2866                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2867                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
2868                                     BGE_MACMODE_HALF_DUPLEX);
2869                         } else {
2870                                 BGE_SETBIT(sc, BGE_MAC_MODE,
2871                                     BGE_MACMODE_HALF_DUPLEX);
2872                         }
2873                         break;
2874                 default:
2875                         return(EINVAL);
2876                 }
2877         } else {
2878                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2879
2880                 sc->bge_link_evt++;
2881                 sc->bge_link = 0;
2882                 if (mii->mii_instance) {
2883                         struct mii_softc *miisc;
2884
2885                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2886                                 mii_phy_reset(miisc);
2887                 }
2888                 mii_mediachg(mii);
2889         }
2890         return(0);
2891 }
2892
2893 /*
2894  * Report current media status.
2895  */
2896 static void
2897 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2898 {
2899         struct bge_softc *sc = ifp->if_softc;
2900
2901         if (sc->bge_flags & BGE_FLAG_TBI) {
2902                 ifmr->ifm_status = IFM_AVALID;
2903                 ifmr->ifm_active = IFM_ETHER;
2904                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2905                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
2906                         ifmr->ifm_status |= IFM_ACTIVE;
2907                 } else {
2908                         ifmr->ifm_active |= IFM_NONE;
2909                         return;
2910                 }
2911
2912                 ifmr->ifm_active |= IFM_1000_SX;
2913                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2914                         ifmr->ifm_active |= IFM_HDX;
2915                 else
2916                         ifmr->ifm_active |= IFM_FDX;
2917         } else {
2918                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2919
2920                 mii_pollstat(mii);
2921                 ifmr->ifm_active = mii->mii_media_active;
2922                 ifmr->ifm_status = mii->mii_media_status;
2923         }
2924 }
2925
2926 static int
2927 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2928 {
2929         struct bge_softc *sc = ifp->if_softc;
2930         struct ifreq *ifr = (struct ifreq *)data;
2931         int mask, error = 0;
2932
2933         ASSERT_SERIALIZED(ifp->if_serializer);
2934
2935         switch (command) {
2936         case SIOCSIFMTU:
2937                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
2938                     (BGE_IS_JUMBO_CAPABLE(sc) &&
2939                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
2940                         error = EINVAL;
2941                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
2942                         ifp->if_mtu = ifr->ifr_mtu;
2943                         ifp->if_flags &= ~IFF_RUNNING;
2944                         bge_init(sc);
2945                 }
2946                 break;
2947         case SIOCSIFFLAGS:
2948                 if (ifp->if_flags & IFF_UP) {
2949                         if (ifp->if_flags & IFF_RUNNING) {
2950                                 mask = ifp->if_flags ^ sc->bge_if_flags;
2951
2952                                 /*
2953                                  * If only the state of the PROMISC flag
2954                                  * changed, then just use the 'set promisc
2955                                  * mode' command instead of reinitializing
2956                                  * the entire NIC. Doing a full re-init
2957                                  * means reloading the firmware and waiting
2958                                  * for it to start up, which may take a
2959                                  * second or two.  Similarly for ALLMULTI.
2960                                  */
2961                                 if (mask & IFF_PROMISC)
2962                                         bge_setpromisc(sc);
2963                                 if (mask & IFF_ALLMULTI)
2964                                         bge_setmulti(sc);
2965                         } else {
2966                                 bge_init(sc);
2967                         }
2968                 } else {
2969                         if (ifp->if_flags & IFF_RUNNING)
2970                                 bge_stop(sc);
2971                 }
2972                 sc->bge_if_flags = ifp->if_flags;
2973                 break;
2974         case SIOCADDMULTI:
2975         case SIOCDELMULTI:
2976                 if (ifp->if_flags & IFF_RUNNING)
2977                         bge_setmulti(sc);
2978                 break;
2979         case SIOCSIFMEDIA:
2980         case SIOCGIFMEDIA:
2981                 if (sc->bge_flags & BGE_FLAG_TBI) {
2982                         error = ifmedia_ioctl(ifp, ifr,
2983                             &sc->bge_ifmedia, command);
2984                 } else {
2985                         struct mii_data *mii;
2986
2987                         mii = device_get_softc(sc->bge_miibus);
2988                         error = ifmedia_ioctl(ifp, ifr,
2989                                               &mii->mii_media, command);
2990                 }
2991                 break;
2992         case SIOCSIFCAP:
2993                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2994                 if (mask & IFCAP_HWCSUM) {
2995                         ifp->if_capenable ^= IFCAP_HWCSUM;
2996                         if (IFCAP_HWCSUM & ifp->if_capenable)
2997                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2998                         else
2999                                 ifp->if_hwassist = 0;
3000                 }
3001                 break;
3002         default:
3003                 error = ether_ioctl(ifp, command, data);
3004                 break;
3005         }
3006         return error;
3007 }
3008
3009 static void
3010 bge_watchdog(struct ifnet *ifp)
3011 {
3012         struct bge_softc *sc = ifp->if_softc;
3013
3014         if_printf(ifp, "watchdog timeout -- resetting\n");
3015
3016         ifp->if_flags &= ~IFF_RUNNING;
3017         bge_init(sc);
3018
3019         ifp->if_oerrors++;
3020
3021         if (!ifq_is_empty(&ifp->if_snd))
3022                 ifp->if_start(ifp);
3023 }
3024
3025 /*
3026  * Stop the adapter and free any mbufs allocated to the
3027  * RX and TX lists.
3028  */
3029 static void
3030 bge_stop(struct bge_softc *sc)
3031 {
3032         struct ifnet *ifp = &sc->arpcom.ac_if;
3033         struct ifmedia_entry *ifm;
3034         struct mii_data *mii = NULL;
3035         int mtmp, itmp;
3036
3037         ASSERT_SERIALIZED(ifp->if_serializer);
3038
3039         if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3040                 mii = device_get_softc(sc->bge_miibus);
3041
3042         callout_stop(&sc->bge_stat_timer);
3043
3044         /*
3045          * Disable all of the receiver blocks
3046          */
3047         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3048         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3049         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3050         if (!BGE_IS_5705_PLUS(sc))
3051                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3052         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3053         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3054         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3055
3056         /*
3057          * Disable all of the transmit blocks
3058          */
3059         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3060         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3061         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3062         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3063         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3064         if (!BGE_IS_5705_PLUS(sc))
3065                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3066         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3067
3068         /*
3069          * Shut down all of the memory managers and related
3070          * state machines.
3071          */
3072         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3073         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3074         if (!BGE_IS_5705_PLUS(sc))
3075                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3076         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3077         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3078         if (!BGE_IS_5705_PLUS(sc)) {
3079                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3080                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3081         }
3082
3083         /* Disable host interrupts. */
3084         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3085         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3086
3087         /*
3088          * Tell firmware we're shutting down.
3089          */
3090         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3091
3092         /* Free the RX lists. */
3093         bge_free_rx_ring_std(sc);
3094
3095         /* Free jumbo RX list. */
3096         if (BGE_IS_JUMBO_CAPABLE(sc))
3097                 bge_free_rx_ring_jumbo(sc);
3098
3099         /* Free TX buffers. */
3100         bge_free_tx_ring(sc);
3101
3102         /*
3103          * Isolate/power down the PHY, but leave the media selection
3104          * unchanged so that things will be put back to normal when
3105          * we bring the interface back up.
3106          */
3107         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3108                 itmp = ifp->if_flags;
3109                 ifp->if_flags |= IFF_UP;
3110                 ifm = mii->mii_media.ifm_cur;
3111                 mtmp = ifm->ifm_media;
3112                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3113                 mii_mediachg(mii);
3114                 ifm->ifm_media = mtmp;
3115                 ifp->if_flags = itmp;
3116         }
3117
3118         sc->bge_link = 0;
3119
3120         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3121
3122         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3123         ifp->if_timer = 0;
3124 }
3125
3126 /*
3127  * Stop all chip I/O so that the kernel's probe routines don't
3128  * get confused by errant DMAs when rebooting.
3129  */
3130 static void
3131 bge_shutdown(device_t dev)
3132 {
3133         struct bge_softc *sc = device_get_softc(dev);
3134         struct ifnet *ifp = &sc->arpcom.ac_if;
3135
3136         lwkt_serialize_enter(ifp->if_serializer);
3137         bge_stop(sc);
3138         bge_reset(sc);
3139         lwkt_serialize_exit(ifp->if_serializer);
3140 }
3141
3142 static int
3143 bge_suspend(device_t dev)
3144 {
3145         struct bge_softc *sc = device_get_softc(dev);
3146         struct ifnet *ifp = &sc->arpcom.ac_if;
3147
3148         lwkt_serialize_enter(ifp->if_serializer);
3149         bge_stop(sc);
3150         lwkt_serialize_exit(ifp->if_serializer);
3151
3152         return 0;
3153 }
3154
3155 static int
3156 bge_resume(device_t dev)
3157 {
3158         struct bge_softc *sc = device_get_softc(dev);
3159         struct ifnet *ifp = &sc->arpcom.ac_if;
3160
3161         lwkt_serialize_enter(ifp->if_serializer);
3162
3163         if (ifp->if_flags & IFF_UP) {
3164                 bge_init(sc);
3165
3166                 if (!ifq_is_empty(&ifp->if_snd))
3167                         ifp->if_start(ifp);
3168         }
3169
3170         lwkt_serialize_exit(ifp->if_serializer);
3171
3172         return 0;
3173 }
3174
3175 static void
3176 bge_setpromisc(struct bge_softc *sc)
3177 {
3178         struct ifnet *ifp = &sc->arpcom.ac_if;
3179
3180         if (ifp->if_flags & IFF_PROMISC)
3181                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3182         else
3183                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3184 }
3185
3186 static void
3187 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3188 {
3189         struct bge_dmamap_arg *ctx = arg;
3190
3191         if (error)
3192                 return;
3193
3194         KASSERT(nsegs == 1 && ctx->bge_maxsegs == 1,
3195                 ("only one segment is allowed\n"));
3196
3197         ctx->bge_segs[0] = *segs;
3198 }
3199
3200 static void
3201 bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3202                  bus_size_t mapsz __unused, int error)
3203 {
3204         struct bge_dmamap_arg *ctx = arg;
3205         int i;
3206
3207         if (error)
3208                 return;
3209
3210         if (nsegs > ctx->bge_maxsegs) {
3211                 ctx->bge_maxsegs = 0;
3212                 return;
3213         }
3214
3215         ctx->bge_maxsegs = nsegs;
3216         for (i = 0; i < nsegs; ++i)
3217                 ctx->bge_segs[i] = segs[i];
3218 }
3219
3220 static void
3221 bge_dma_free(struct bge_softc *sc)
3222 {
3223         int i;
3224
3225         /* Destroy RX/TX mbuf DMA stuffs. */
3226         if (sc->bge_cdata.bge_mtag != NULL) {
3227                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3228                         if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3229                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3230                                     sc->bge_cdata.bge_rx_std_dmamap[i]);
3231                         }
3232                 }
3233
3234                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3235                         if (sc->bge_cdata.bge_tx_dmamap[i]) {
3236                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3237                                     sc->bge_cdata.bge_tx_dmamap[i]);
3238                         }
3239                 }
3240                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3241         }
3242
3243         /* Destroy standard RX ring */
3244         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3245                            sc->bge_cdata.bge_rx_std_ring_map,
3246                            sc->bge_ldata.bge_rx_std_ring);
3247
3248         if (BGE_IS_JUMBO_CAPABLE(sc))
3249                 bge_free_jumbo_mem(sc);
3250
3251         /* Destroy RX return ring */
3252         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3253                            sc->bge_cdata.bge_rx_return_ring_map,
3254                            sc->bge_ldata.bge_rx_return_ring);
3255
3256         /* Destroy TX ring */
3257         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3258                            sc->bge_cdata.bge_tx_ring_map,
3259                            sc->bge_ldata.bge_tx_ring);
3260
3261         /* Destroy status block */
3262         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3263                            sc->bge_cdata.bge_status_map,
3264                            sc->bge_ldata.bge_status_block);
3265
3266         /* Destroy statistics block */
3267         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3268                            sc->bge_cdata.bge_stats_map,
3269                            sc->bge_ldata.bge_stats);
3270
3271         /* Destroy the parent tag */
3272         if (sc->bge_cdata.bge_parent_tag != NULL)
3273                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3274 }
3275
3276 static int
3277 bge_dma_alloc(struct bge_softc *sc)
3278 {
3279         struct ifnet *ifp = &sc->arpcom.ac_if;
3280         int nseg, i, error;
3281
3282         /*
3283          * Allocate the parent bus DMA tag appropriate for PCI.
3284          */
3285         error = bus_dma_tag_create(NULL, 1, 0,
3286                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3287                                    NULL, NULL,
3288                                    MAXBSIZE, BGE_NSEG_NEW,
3289                                    BUS_SPACE_MAXSIZE_32BIT,
3290                                    0, &sc->bge_cdata.bge_parent_tag);
3291         if (error) {
3292                 if_printf(ifp, "could not allocate parent dma tag\n");
3293                 return error;
3294         }
3295
3296         /*
3297          * Create DMA tag for mbufs.
3298          */
3299         nseg = BGE_NSEG_NEW;
3300         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3301                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3302                                    NULL, NULL,
3303                                    MCLBYTES * nseg, nseg, MCLBYTES,
3304                                    BUS_DMA_ALLOCNOW, &sc->bge_cdata.bge_mtag);
3305         if (error) {
3306                 if_printf(ifp, "could not allocate mbuf dma tag\n");
3307                 return error;
3308         }
3309
3310         /*
3311          * Create DMA maps for TX/RX mbufs.
3312          */
3313         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3314                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3315                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3316                 if (error) {
3317                         int j;
3318
3319                         for (j = 0; j < i; ++j) {
3320                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3321                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3322                         }
3323                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3324                         sc->bge_cdata.bge_mtag = NULL;
3325
3326                         if_printf(ifp, "could not create DMA map for RX\n");
3327                         return error;
3328                 }
3329         }
3330
3331         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3332                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3333                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3334                 if (error) {
3335                         int j;
3336
3337                         for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3338                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3339                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3340                         }
3341                         for (j = 0; j < i; ++j) {
3342                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3343                                         sc->bge_cdata.bge_tx_dmamap[j]);
3344                         }
3345                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3346                         sc->bge_cdata.bge_mtag = NULL;
3347
3348                         if_printf(ifp, "could not create DMA map for TX\n");
3349                         return error;
3350                 }
3351         }
3352
3353         /*
3354          * Create DMA stuffs for standard RX ring.
3355          */
3356         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3357                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3358                                     &sc->bge_cdata.bge_rx_std_ring_map,
3359                                     (void **)&sc->bge_ldata.bge_rx_std_ring,
3360                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3361         if (error) {
3362                 if_printf(ifp, "could not create std RX ring\n");
3363                 return error;
3364         }
3365
3366         /*
3367          * Create jumbo buffer pool.
3368          */
3369         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3370                 error = bge_alloc_jumbo_mem(sc);
3371                 if (error) {
3372                         if_printf(ifp, "could not create jumbo buffer pool\n");
3373                         return error;
3374                 }
3375         }
3376
3377         /*
3378          * Create DMA stuffs for RX return ring.
3379          */
3380         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3381                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3382                                     &sc->bge_cdata.bge_rx_return_ring_map,
3383                                     (void **)&sc->bge_ldata.bge_rx_return_ring,
3384                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3385         if (error) {
3386                 if_printf(ifp, "could not create RX ret ring\n");
3387                 return error;
3388         }
3389
3390         /*
3391          * Create DMA stuffs for TX ring.
3392          */
3393         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3394                                     &sc->bge_cdata.bge_tx_ring_tag,
3395                                     &sc->bge_cdata.bge_tx_ring_map,
3396                                     (void **)&sc->bge_ldata.bge_tx_ring,
3397                                     &sc->bge_ldata.bge_tx_ring_paddr);
3398         if (error) {
3399                 if_printf(ifp, "could not create TX ring\n");
3400                 return error;
3401         }
3402
3403         /*
3404          * Create DMA stuffs for status block.
3405          */
3406         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3407                                     &sc->bge_cdata.bge_status_tag,
3408                                     &sc->bge_cdata.bge_status_map,
3409                                     (void **)&sc->bge_ldata.bge_status_block,
3410                                     &sc->bge_ldata.bge_status_block_paddr);
3411         if (error) {
3412                 if_printf(ifp, "could not create status block\n");
3413                 return error;
3414         }
3415
3416         /*
3417          * Create DMA stuffs for statistics block.
3418          */
3419         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3420                                     &sc->bge_cdata.bge_stats_tag,
3421                                     &sc->bge_cdata.bge_stats_map,
3422                                     (void **)&sc->bge_ldata.bge_stats,
3423                                     &sc->bge_ldata.bge_stats_paddr);
3424         if (error) {
3425                 if_printf(ifp, "could not create stats block\n");
3426                 return error;
3427         }
3428         return 0;
3429 }
3430
3431 static int
3432 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3433                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3434 {
3435         struct ifnet *ifp = &sc->arpcom.ac_if;
3436         struct bge_dmamap_arg ctx;
3437         bus_dma_segment_t seg;
3438         int error;
3439
3440         /*
3441          * Create DMA tag
3442          */
3443         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3444                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3445                                    NULL, NULL, size, 1, size, 0, tag);
3446         if (error) {
3447                 if_printf(ifp, "could not allocate dma tag\n");
3448                 return error;
3449         }
3450
3451         /*
3452          * Allocate DMA'able memory
3453          */
3454         error = bus_dmamem_alloc(*tag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3455                                  map);
3456         if (error) {
3457                 if_printf(ifp, "could not allocate dma memory\n");
3458                 bus_dma_tag_destroy(*tag);
3459                 *tag = NULL;
3460                 return error;
3461         }
3462
3463         /*
3464          * Load the DMA'able memory
3465          */
3466         ctx.bge_maxsegs = 1;
3467         ctx.bge_segs = &seg;
3468         error = bus_dmamap_load(*tag, *map, *addr, size, bge_dma_map_addr, &ctx,
3469                                 BUS_DMA_WAITOK);
3470         if (error) {
3471                 if_printf(ifp, "could not load dma memory\n");
3472                 bus_dmamem_free(*tag, *addr, *map);
3473                 bus_dma_tag_destroy(*tag);
3474                 *tag = NULL;
3475                 return error;
3476         }
3477         *paddr = ctx.bge_segs[0].ds_addr;
3478
3479         return 0;
3480 }
3481
3482 static void
3483 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3484 {
3485         if (tag != NULL) {
3486                 bus_dmamap_unload(tag, map);
3487                 bus_dmamem_free(tag, addr, map);
3488                 bus_dma_tag_destroy(tag);
3489         }
3490 }
3491
3492 /*
3493  * Grrr. The link status word in the status block does
3494  * not work correctly on the BCM5700 rev AX and BX chips,
3495  * according to all available information. Hence, we have
3496  * to enable MII interrupts in order to properly obtain
3497  * async link changes. Unfortunately, this also means that
3498  * we have to read the MAC status register to detect link
3499  * changes, thereby adding an additional register access to
3500  * the interrupt handler.
3501  *
3502  * XXX: perhaps link state detection procedure used for
3503  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3504  */
3505 static void
3506 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3507 {
3508         struct ifnet *ifp = &sc->arpcom.ac_if;
3509         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3510
3511         mii_pollstat(mii);
3512
3513         if (!sc->bge_link &&
3514             (mii->mii_media_status & IFM_ACTIVE) &&
3515             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3516                 sc->bge_link++;
3517                 if (bootverbose)
3518                         if_printf(ifp, "link UP\n");
3519         } else if (sc->bge_link &&
3520             (!(mii->mii_media_status & IFM_ACTIVE) ||
3521             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3522                 sc->bge_link = 0;
3523                 if (bootverbose)
3524                         if_printf(ifp, "link DOWN\n");
3525         }
3526
3527         /* Clear the interrupt. */
3528         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3529         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3530         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3531 }
3532
3533 static void
3534 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3535 {
3536         struct ifnet *ifp = &sc->arpcom.ac_if;
3537
3538 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3539
3540         /*
3541          * Sometimes PCS encoding errors are detected in
3542          * TBI mode (on fiber NICs), and for some reason
3543          * the chip will signal them as link changes.
3544          * If we get a link change event, but the 'PCS
3545          * encoding error' bit in the MAC status register
3546          * is set, don't bother doing a link check.
3547          * This avoids spurious "gigabit link up" messages
3548          * that sometimes appear on fiber NICs during
3549          * periods of heavy traffic.
3550          */
3551         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3552                 if (!sc->bge_link) {
3553                         sc->bge_link++;
3554                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3555                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3556                                     BGE_MACMODE_TBI_SEND_CFGS);
3557                         }
3558                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3559
3560                         if (bootverbose)
3561                                 if_printf(ifp, "link UP\n");
3562
3563                         ifp->if_link_state = LINK_STATE_UP;
3564                         if_link_state_change(ifp);
3565                 }
3566         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3567                 if (sc->bge_link) {
3568                         sc->bge_link = 0;
3569
3570                         if (bootverbose)
3571                                 if_printf(ifp, "link DOWN\n");
3572
3573                         ifp->if_link_state = LINK_STATE_DOWN;
3574                         if_link_state_change(ifp);
3575                 }
3576         }
3577
3578 #undef PCS_ENCODE_ERR
3579
3580         /* Clear the attention. */
3581         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3582             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3583             BGE_MACSTAT_LINK_CHANGED);
3584 }
3585
3586 static void
3587 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3588 {
3589         /*
3590          * Check that the AUTOPOLL bit is set before
3591          * processing the event as a real link change.
3592          * Turning AUTOPOLL on and off in the MII read/write
3593          * functions will often trigger a link status
3594          * interrupt for no reason.
3595          */
3596         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3597                 struct ifnet *ifp = &sc->arpcom.ac_if;
3598                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3599
3600                 mii_pollstat(mii);
3601
3602                 if (!sc->bge_link &&
3603                     (mii->mii_media_status & IFM_ACTIVE) &&
3604                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3605                         sc->bge_link++;
3606                         if (bootverbose)
3607                                 if_printf(ifp, "link UP\n");
3608                 } else if (sc->bge_link &&
3609                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3610                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3611                         sc->bge_link = 0;
3612                         if (bootverbose)
3613                                 if_printf(ifp, "link DOWN\n");
3614                 }
3615         }
3616
3617         /* Clear the attention. */
3618         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3619             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3620             BGE_MACSTAT_LINK_CHANGED);
3621 }