2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <machine_base/icu/icu.h> /* IPIs */
67 #include <machine_base/isa/intr_machdep.h> /* IPIs */
69 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
71 #define WARMBOOT_TARGET 0
72 #define WARMBOOT_OFF (KERNBASE + 0x0467)
73 #define WARMBOOT_SEG (KERNBASE + 0x0469)
75 #define BIOS_BASE (0xf0000)
76 #define BIOS_SIZE (0x10000)
77 #define BIOS_COUNT (BIOS_SIZE/4)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
84 #define PROCENTRY_FLAG_EN 0x01
85 #define PROCENTRY_FLAG_BP 0x02
86 #define IOAPICENTRY_FLAG_EN 0x01
89 /* MP Floating Pointer Structure */
90 typedef struct MPFPS {
103 /* MP Configuration Table Header */
104 typedef struct MPCTH {
106 u_short base_table_length;
110 u_char product_id[12];
111 u_int32_t oem_table_pointer;
112 u_short oem_table_size;
114 u_int32_t apic_address;
115 u_short extended_table_length;
116 u_char extended_table_checksum;
121 typedef struct PROCENTRY {
126 u_int32_t cpu_signature;
127 u_int32_t feature_flags;
132 typedef struct BUSENTRY {
138 typedef struct IOAPICENTRY {
143 u_int32_t apic_address;
144 } *io_apic_entry_ptr;
146 typedef struct INTENTRY {
156 /* descriptions of MP basetable entries */
157 typedef struct BASETABLE_ENTRY {
164 * this code MUST be enabled here and in mpboot.s.
165 * it follows the very early stages of AP boot by placing values in CMOS ram.
166 * it NORMALLY will never be needed and thus the primitive method for enabling.
169 #if defined(CHECK_POINTS)
170 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
171 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
173 #define CHECK_INIT(D); \
174 CHECK_WRITE(0x34, (D)); \
175 CHECK_WRITE(0x35, (D)); \
176 CHECK_WRITE(0x36, (D)); \
177 CHECK_WRITE(0x37, (D)); \
178 CHECK_WRITE(0x38, (D)); \
179 CHECK_WRITE(0x39, (D));
181 #define CHECK_PRINT(S); \
182 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
191 #else /* CHECK_POINTS */
193 #define CHECK_INIT(D)
194 #define CHECK_PRINT(S)
196 #endif /* CHECK_POINTS */
199 * Values to send to the POST hardware.
201 #define MP_BOOTADDRESS_POST 0x10
202 #define MP_PROBE_POST 0x11
203 #define MPTABLE_PASS1_POST 0x12
205 #define MP_START_POST 0x13
206 #define MP_ENABLE_POST 0x14
207 #define MPTABLE_PASS2_POST 0x15
209 #define START_ALL_APS_POST 0x16
210 #define INSTALL_AP_TRAMP_POST 0x17
211 #define START_AP_POST 0x18
213 #define MP_ANNOUNCE_POST 0x19
215 static int need_hyperthreading_fixup;
216 static u_int logical_cpus;
217 u_int logical_cpus_mask;
219 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
220 int current_postcode;
222 /** XXX FIXME: what system files declare these??? */
223 extern struct region_descriptor r_gdt, r_idt;
225 int bsp_apic_ready = 0; /* flags useability of BSP apic */
226 int mp_naps; /* # of Applications processors */
227 int mp_nbusses; /* # of busses */
229 int mp_napics; /* # of IO APICs */
231 int boot_cpu_id; /* designated BSP */
232 vm_offset_t cpu_apic_address;
234 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
235 u_int32_t *io_apic_versions;
239 u_int32_t cpu_apic_versions[MAXCPU];
241 extern int64_t tsc_offsets[];
243 extern u_long ebda_addr;
246 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
250 * APIC ID logical/physical mapping structures.
251 * We oversize these to simplify boot-time config.
253 int cpu_num_to_apic_id[NAPICID];
255 int io_num_to_apic_id[NAPICID];
257 int apic_id_to_logical[NAPICID];
259 /* AP uses this during bootstrap. Do not staticize. */
264 * SMP page table page. Setup by locore to point to a page table
265 * page from which we allocate per-cpu privatespace areas io_apics,
269 #define IO_MAPPING_START_INDEX \
270 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
272 extern pt_entry_t *SMPpt;
274 struct pcb stoppcbs[MAXCPU];
276 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
279 * Local data and functions.
282 static u_int boot_address;
283 static u_int base_memory;
284 static int mp_finish;
286 static mpfps_t mpfps;
287 static long search_for_sig(u_int32_t target, int count);
288 static void mp_enable(u_int boot_addr);
290 static void mptable_hyperthread_fixup(u_int id_mask);
291 static void mptable_pass1(void);
292 static int mptable_pass2(void);
293 static void default_mp_table(int type);
294 static void fix_mp_table(void);
296 static void setup_apic_irq_mapping(void);
297 static int apic_int_is_bus_type(int intr, int bus_type);
299 static int start_all_aps(u_int boot_addr);
301 static void install_ap_tramp(u_int boot_addr);
303 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
304 static int smitest(void);
306 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
307 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
308 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
309 static u_int bootMP_size;
312 * Calculate usable address in base memory for AP trampoline code.
315 mp_bootaddress(u_int basemem)
317 POSTCODE(MP_BOOTADDRESS_POST);
319 base_memory = basemem;
321 bootMP_size = mptramp_end - mptramp_start;
322 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
323 if (((basemem * 1024) - boot_address) < bootMP_size)
324 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
325 /* 3 levels of page table pages */
326 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
328 return mptramp_pagetables;
333 * Look for an Intel MP spec table (ie, SMP capable hardware).
342 * Make sure our SMPpt[] page table is big enough to hold all the
345 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
347 POSTCODE(MP_PROBE_POST);
349 /* see if EBDA exists */
350 if (ebda_addr != 0) {
351 /* search first 1K of EBDA */
352 target = (u_int32_t)ebda_addr;
353 if ((x = search_for_sig(target, 1024 / 4)) > 0)
356 /* last 1K of base memory, effective 'top of base' passed in */
357 target = (u_int32_t)(base_memory - 0x400);
358 if ((x = search_for_sig(target, 1024 / 4)) > 0)
362 /* search the BIOS */
363 target = (u_int32_t)BIOS_BASE;
364 if ((x = search_for_sig(target, BIOS_COUNT)) > 0)
373 * Startup the SMP processors.
378 POSTCODE(MP_START_POST);
379 mp_enable(boot_address);
384 * Print various information about the SMP system hardware and setup.
391 POSTCODE(MP_ANNOUNCE_POST);
393 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
394 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
395 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
396 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
397 for (x = 1; x <= mp_naps; ++x) {
398 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
399 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
400 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
404 for (x = 0; x < mp_napics; ++x) {
405 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
406 kprintf(", version: 0x%08x", io_apic_versions[x]);
407 kprintf(", at 0x%08lx\n", io_apic_address[x]);
410 kprintf(" Warning: APIC I/O disabled\n");
415 * AP cpu's call this to sync up protected mode.
417 * WARNING! %gs is not set up on entry. This routine sets up %gs.
423 int x, myid = bootAP;
425 struct mdglobaldata *md;
426 struct privatespace *ps;
428 ps = &CPU_prvspace[myid];
430 gdt_segs[GPROC0_SEL].ssd_base =
431 (long) &ps->mdglobaldata.gd_common_tss;
432 ps->mdglobaldata.mi.gd_prvspace = ps;
434 /* We fill the 32-bit segment descriptors */
435 for (x = 0; x < NGDT; x++) {
436 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
437 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
439 /* And now a 64-bit one */
440 ssdtosyssd(&gdt_segs[GPROC0_SEL],
441 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
443 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
444 r_gdt.rd_base = (long) &gdt[myid * NGDT];
445 lgdt(&r_gdt); /* does magic intra-segment return */
447 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
448 wrmsr(MSR_FSBASE, 0); /* User value */
449 wrmsr(MSR_GSBASE, (u_int64_t)ps);
450 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
456 mdcpu->gd_currentldt = _default_ldt;
459 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
460 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
462 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
464 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
466 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
468 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
469 md->gd_common_tssd = *md->gd_tss_gdt;
471 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
476 * Set to a known state:
477 * Set by mpboot.s: CR0_PG, CR0_PE
478 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
481 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
484 /* Set up the fast syscall stuff */
485 msr = rdmsr(MSR_EFER) | EFER_SCE;
486 wrmsr(MSR_EFER, msr);
487 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
488 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
489 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
490 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
491 wrmsr(MSR_STAR, msr);
492 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
494 pmap_set_opt(); /* PSE/4MB pages, etc */
496 /* Initialize the PAT MSR. */
500 /* set up CPU registers and state */
503 /* set up SSE/NX registers */
506 /* set up FPU state on the AP */
507 npxinit(__INITIAL_NPXCW__);
509 /* disable the APIC, just to be SURE */
510 lapic->svr &= ~APIC_SVR_ENABLE;
512 /* data returned to BSP */
513 cpu_apic_versions[0] = lapic->version;
516 /*******************************************************************
517 * local functions and data
521 * start the SMP system
524 mp_enable(u_int boot_addr)
532 POSTCODE(MP_ENABLE_POST);
534 mpfps = (mpfps_t)mp_probe();
536 panic("mp_enable: mp_probe failed\n");
539 /* turn on 4MB of V == P addressing so we can get to MP table */
540 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
545 * We can safely map physical memory into SMPpt after
546 * mptable_pass1() completes.
550 if (cpu_apic_address == 0)
551 panic("mp_enable: no local apic!\n");
553 /* examine the MP table for needed info, uses physical addresses */
561 /* can't process default configs till the CPU APIC is pmapped */
565 /* post scan cleanup */
570 setup_apic_irq_mapping();
572 /* fill the LOGICAL io_apic_versions table */
573 for (apic = 0; apic < mp_napics; ++apic) {
574 ux = io_apic_read(apic, IOAPIC_VER);
575 io_apic_versions[apic] = ux;
576 io_apic_set_id(apic, IO_TO_ID(apic));
579 /* program each IO APIC in the system */
580 for (apic = 0; apic < mp_napics; ++apic)
581 if (io_apic_setup(apic) < 0)
582 panic("IO APIC setup failure");
587 * These are required for SMP operation
590 /* install a 'Spurious INTerrupt' vector */
591 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
592 SDT_SYSIGT, SEL_KPL, 0);
594 /* install an inter-CPU IPI for TLB invalidation */
595 setidt(XINVLTLB_OFFSET, Xinvltlb,
596 SDT_SYSIGT, SEL_KPL, 0);
598 /* install an inter-CPU IPI for IPIQ messaging */
599 setidt(XIPIQ_OFFSET, Xipiq,
600 SDT_SYSIGT, SEL_KPL, 0);
602 /* install a timer vector */
603 setidt(XTIMER_OFFSET, Xtimer,
604 SDT_SYSIGT, SEL_KPL, 0);
606 /* install an inter-CPU IPI for CPU stop/restart */
607 setidt(XCPUSTOP_OFFSET, Xcpustop,
608 SDT_SYSIGT, SEL_KPL, 0);
610 /* start each Application Processor */
611 start_all_aps(boot_addr);
616 * look for the MP spec signature
619 /* string defined by the Intel MP Spec as identifying the MP table */
620 #define MP_SIG 0x5f504d5f /* _MP_ */
621 #define NEXT(X) ((X) += 4)
623 search_for_sig(u_int32_t target, int count)
629 KKASSERT(target != 0);
631 map_size = count * sizeof(u_int32_t);
632 addr = pmap_mapdev((vm_paddr_t)target, map_size);
635 for (x = 0; x < count; NEXT(x)) {
636 if (addr[x] == MP_SIG) {
637 /* make array index a byte index */
638 ret = target + (x * sizeof(u_int32_t));
643 pmap_unmapdev((vm_offset_t)addr, map_size);
648 static basetable_entry basetable_entry_types[] =
650 {0, 20, "Processor"},
657 typedef struct BUSDATA {
659 enum busTypes bus_type;
662 typedef struct INTDATA {
672 typedef struct BUSTYPENAME {
677 static bus_type_name bus_type_table[] =
683 {UNKNOWN_BUSTYPE, "---"},
686 {UNKNOWN_BUSTYPE, "---"},
687 {UNKNOWN_BUSTYPE, "---"},
688 {UNKNOWN_BUSTYPE, "---"},
689 {UNKNOWN_BUSTYPE, "---"},
690 {UNKNOWN_BUSTYPE, "---"},
692 {UNKNOWN_BUSTYPE, "---"},
693 {UNKNOWN_BUSTYPE, "---"},
694 {UNKNOWN_BUSTYPE, "---"},
695 {UNKNOWN_BUSTYPE, "---"},
697 {UNKNOWN_BUSTYPE, "---"}
699 /* from MP spec v1.4, table 5-1 */
700 static int default_data[7][5] =
702 /* nbus, id0, type0, id1, type1 */
703 {1, 0, ISA, 255, 255},
704 {1, 0, EISA, 255, 255},
705 {1, 0, EISA, 255, 255},
706 {1, 0, MCA, 255, 255},
708 {2, 0, EISA, 1, PCI},
714 static bus_datum *bus_data;
717 /* the IO INT data, one entry per possible APIC INTerrupt */
718 static io_int *io_apic_ints;
722 static int processor_entry (proc_entry_ptr entry, int cpu);
723 static int bus_entry (bus_entry_ptr entry, int bus);
725 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
726 static int int_entry (int_entry_ptr entry, int intr);
728 static int lookup_bus_type (char *name);
732 * 1st pass on motherboard's Intel MP specification table.
738 * cpu_apic_address (common to all CPUs)
758 POSTCODE(MPTABLE_PASS1_POST);
761 panic("mptable_pass1: MP float pointer is not found\n");
764 /* clear various tables */
765 for (x = 0; x < NAPICID; ++x) {
766 io_apic_address[x] = ~0; /* IO APIC address table */
770 /* init everything to empty */
779 /* check for use of 'default' configuration */
780 if (mpfps->mpfb1 != 0) {
781 /* use default addresses */
782 cpu_apic_address = DEFAULT_APIC_BASE;
784 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
787 /* fill in with defaults */
788 mp_naps = 2; /* includes BSP */
789 mp_nbusses = default_data[mpfps->mpfb1 - 1][0];
797 panic("MP Configuration Table Header MISSING!");
798 cth = (void *)PHYS_TO_DMAP(mpfps->pap);
800 cpu_apic_address = (vm_offset_t) cth->apic_address;
802 /* walk the table, recording info of interest */
803 totalSize = cth->base_table_length - sizeof(struct MPCTH);
804 position = (u_char *) cth + sizeof(struct MPCTH);
805 count = cth->entry_count;
808 switch (type = *(u_char *) position) {
809 case 0: /* processor_entry */
810 if (((proc_entry_ptr)position)->cpu_flags
811 & PROCENTRY_FLAG_EN) {
814 ((proc_entry_ptr)position)->apic_id;
817 case 1: /* bus_entry */
820 case 2: /* io_apic_entry */
822 if (((io_apic_entry_ptr)position)->apic_flags
823 & IOAPICENTRY_FLAG_EN)
824 io_apic_address[mp_napics++] =
825 (vm_offset_t)((io_apic_entry_ptr)
826 position)->apic_address;
829 case 3: /* int_entry */
834 case 4: /* int_entry */
837 panic("mpfps Base Table HOSED!");
841 totalSize -= basetable_entry_types[type].length;
842 position = (uint8_t *)position +
843 basetable_entry_types[type].length;
847 /* qualify the numbers */
848 if (mp_naps > MAXCPU) {
849 kprintf("Warning: only using %d of %d available CPUs!\n",
854 /* See if we need to fixup HT logical CPUs. */
855 mptable_hyperthread_fixup(id_mask);
857 --mp_naps; /* subtract the BSP */
862 * 2nd pass on motherboard's Intel MP specification table.
866 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
867 * CPU_TO_ID(N), logical CPU to APIC ID table
868 * IO_TO_ID(N), logical IO to APIC ID table
875 struct PROCENTRY proc;
882 int apic, bus, cpu, intr;
885 POSTCODE(MPTABLE_PASS2_POST);
887 /* Initialize fake proc entry for use with HT fixup. */
888 bzero(&proc, sizeof(proc));
890 proc.cpu_flags = PROCENTRY_FLAG_EN;
893 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
895 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
896 M_DEVBUF, M_WAITOK | M_ZERO);
897 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
900 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
904 for (i = 0; i < mp_napics; i++) {
905 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
909 /* clear various tables */
910 for (x = 0; x < NAPICID; ++x) {
911 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
913 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
914 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
918 /* clear bus data table */
919 for (x = 0; x < mp_nbusses; ++x)
920 bus_data[x].bus_id = 0xff;
923 /* clear IO APIC INT table */
924 for (x = 0; x < (nintrs + 1); ++x) {
925 io_apic_ints[x].int_type = 0xff;
926 io_apic_ints[x].int_vector = 0xff;
930 /* setup the cpu/apic mapping arrays */
933 /* record whether PIC or virtual-wire mode */
934 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, mpfps->mpfb2 & 0x80);
936 /* check for use of 'default' configuration */
937 if (mpfps->mpfb1 != 0)
938 return mpfps->mpfb1; /* return default configuration type */
941 panic("MP Configuration Table Header MISSING!");
943 cth = (void *)PHYS_TO_DMAP(mpfps->pap);
944 /* walk the table, recording info of interest */
945 totalSize = cth->base_table_length - sizeof(struct MPCTH);
946 position = (u_char *) cth + sizeof(struct MPCTH);
947 count = cth->entry_count;
948 apic = bus = intr = 0;
949 cpu = 1; /* pre-count the BSP */
952 switch (type = *(u_char *) position) {
954 if (processor_entry(position, cpu))
957 if (need_hyperthreading_fixup) {
959 * Create fake mptable processor entries
960 * and feed them to processor_entry() to
961 * enumerate the logical CPUs.
963 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
964 for (i = 1; i < logical_cpus; i++) {
966 processor_entry(&proc, cpu);
967 logical_cpus_mask |= (1 << cpu);
973 if (bus_entry(position, bus))
978 if (io_apic_entry(position, apic))
984 if (int_entry(position, intr))
989 /* int_entry(position); */
992 panic("mpfps Base Table HOSED!");
996 totalSize -= basetable_entry_types[type].length;
997 position = (uint8_t *)position + basetable_entry_types[type].length;
1000 if (boot_cpu_id == -1)
1001 panic("NO BSP found!");
1003 /* report fact that its NOT a default configuration */
1008 * Check if we should perform a hyperthreading "fix-up" to
1009 * enumerate any logical CPU's that aren't already listed
1012 * XXX: We assume that all of the physical CPUs in the
1013 * system have the same number of logical CPUs.
1015 * XXX: We assume that APIC ID's are allocated such that
1016 * the APIC ID's for a physical processor are aligned
1017 * with the number of logical CPU's in the processor.
1020 mptable_hyperthread_fixup(u_int id_mask)
1024 /* Nothing to do if there is no HTT support. */
1025 if ((cpu_feature & CPUID_HTT) == 0)
1027 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1028 if (logical_cpus <= 1)
1032 * For each APIC ID of a CPU that is set in the mask,
1033 * scan the other candidate APIC ID's for this
1034 * physical processor. If any of those ID's are
1035 * already in the table, then kill the fixup.
1037 for (id = 0; id <= MAXCPU; id++) {
1038 if ((id_mask & 1 << id) == 0)
1040 /* First, make sure we are on a logical_cpus boundary. */
1041 if (id % logical_cpus != 0)
1043 for (i = id + 1; i < id + logical_cpus; i++)
1044 if ((id_mask & 1 << i) != 0)
1049 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1050 * mp_naps right now.
1052 need_hyperthreading_fixup = 1;
1053 mp_naps *= logical_cpus;
1059 assign_apic_irq(int apic, int intpin, int irq)
1063 if (int_to_apicintpin[irq].ioapic != -1)
1064 panic("assign_apic_irq: inconsistent table");
1066 int_to_apicintpin[irq].ioapic = apic;
1067 int_to_apicintpin[irq].int_pin = intpin;
1068 int_to_apicintpin[irq].apic_address = ioapic[apic];
1069 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1071 for (x = 0; x < nintrs; x++) {
1072 if ((io_apic_ints[x].int_type == 0 ||
1073 io_apic_ints[x].int_type == 3) &&
1074 io_apic_ints[x].int_vector == 0xff &&
1075 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1076 io_apic_ints[x].dst_apic_int == intpin)
1077 io_apic_ints[x].int_vector = irq;
1082 revoke_apic_irq(int irq)
1088 if (int_to_apicintpin[irq].ioapic == -1)
1089 panic("revoke_apic_irq: inconsistent table");
1091 oldapic = int_to_apicintpin[irq].ioapic;
1092 oldintpin = int_to_apicintpin[irq].int_pin;
1094 int_to_apicintpin[irq].ioapic = -1;
1095 int_to_apicintpin[irq].int_pin = 0;
1096 int_to_apicintpin[irq].apic_address = NULL;
1097 int_to_apicintpin[irq].redirindex = 0;
1099 for (x = 0; x < nintrs; x++) {
1100 if ((io_apic_ints[x].int_type == 0 ||
1101 io_apic_ints[x].int_type == 3) &&
1102 io_apic_ints[x].int_vector != 0xff &&
1103 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1104 io_apic_ints[x].dst_apic_int == oldintpin)
1105 io_apic_ints[x].int_vector = 0xff;
1113 allocate_apic_irq(int intr)
1119 if (io_apic_ints[intr].int_vector != 0xff)
1120 return; /* Interrupt handler already assigned */
1122 if (io_apic_ints[intr].int_type != 0 &&
1123 (io_apic_ints[intr].int_type != 3 ||
1124 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1125 io_apic_ints[intr].dst_apic_int == 0)))
1126 return; /* Not INT or ExtInt on != (0, 0) */
1129 while (irq < APIC_INTMAPSIZE &&
1130 int_to_apicintpin[irq].ioapic != -1)
1133 if (irq >= APIC_INTMAPSIZE)
1134 return; /* No free interrupt handlers */
1136 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1137 intpin = io_apic_ints[intr].dst_apic_int;
1139 assign_apic_irq(apic, intpin, irq);
1144 swap_apic_id(int apic, int oldid, int newid)
1151 return; /* Nothing to do */
1153 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1154 apic, oldid, newid);
1156 /* Swap physical APIC IDs in interrupt entries */
1157 for (x = 0; x < nintrs; x++) {
1158 if (io_apic_ints[x].dst_apic_id == oldid)
1159 io_apic_ints[x].dst_apic_id = newid;
1160 else if (io_apic_ints[x].dst_apic_id == newid)
1161 io_apic_ints[x].dst_apic_id = oldid;
1164 /* Swap physical APIC IDs in IO_TO_ID mappings */
1165 for (oapic = 0; oapic < mp_napics; oapic++)
1166 if (IO_TO_ID(oapic) == newid)
1169 if (oapic < mp_napics) {
1170 kprintf("Changing APIC ID for IO APIC #%d from "
1171 "%d to %d in MP table\n",
1172 oapic, newid, oldid);
1173 IO_TO_ID(oapic) = oldid;
1175 IO_TO_ID(apic) = newid;
1180 fix_id_to_io_mapping(void)
1184 for (x = 0; x < NAPICID; x++)
1187 for (x = 0; x <= mp_naps; x++)
1188 if (CPU_TO_ID(x) < NAPICID)
1189 ID_TO_IO(CPU_TO_ID(x)) = x;
1191 for (x = 0; x < mp_napics; x++)
1192 if (IO_TO_ID(x) < NAPICID)
1193 ID_TO_IO(IO_TO_ID(x)) = x;
1198 first_free_apic_id(void)
1202 for (freeid = 0; freeid < NAPICID; freeid++) {
1203 for (x = 0; x <= mp_naps; x++)
1204 if (CPU_TO_ID(x) == freeid)
1208 for (x = 0; x < mp_napics; x++)
1209 if (IO_TO_ID(x) == freeid)
1220 io_apic_id_acceptable(int apic, int id)
1222 int cpu; /* Logical CPU number */
1223 int oapic; /* Logical IO APIC number for other IO APIC */
1226 return 0; /* Out of range */
1228 for (cpu = 0; cpu <= mp_naps; cpu++)
1229 if (CPU_TO_ID(cpu) == id)
1230 return 0; /* Conflict with CPU */
1232 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1233 if (IO_TO_ID(oapic) == id)
1234 return 0; /* Conflict with other APIC */
1236 return 1; /* ID is acceptable for IO APIC */
1241 io_apic_find_int_entry(int apic, int pin)
1245 /* search each of the possible INTerrupt sources */
1246 for (x = 0; x < nintrs; ++x) {
1247 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1248 (pin == io_apic_ints[x].dst_apic_int))
1249 return (&io_apic_ints[x]);
1257 * parse an Intel MP specification table
1265 int apic; /* IO APIC unit number */
1266 int freeid; /* Free physical APIC ID */
1267 int physid; /* Current physical IO APIC ID */
1270 int bus_0 = 0; /* Stop GCC warning */
1271 int bus_pci = 0; /* Stop GCC warning */
1275 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1276 * did it wrong. The MP spec says that when more than 1 PCI bus
1277 * exists the BIOS must begin with bus entries for the PCI bus and use
1278 * actual PCI bus numbering. This implies that when only 1 PCI bus
1279 * exists the BIOS can choose to ignore this ordering, and indeed many
1280 * MP motherboards do ignore it. This causes a problem when the PCI
1281 * sub-system makes requests of the MP sub-system based on PCI bus
1282 * numbers. So here we look for the situation and renumber the
1283 * busses and associated INTs in an effort to "make it right".
1286 /* find bus 0, PCI bus, count the number of PCI busses */
1287 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1288 if (bus_data[x].bus_id == 0) {
1291 if (bus_data[x].bus_type == PCI) {
1297 * bus_0 == slot of bus with ID of 0
1298 * bus_pci == slot of last PCI bus encountered
1301 /* check the 1 PCI bus case for sanity */
1302 /* if it is number 0 all is well */
1303 if (num_pci_bus == 1 &&
1304 bus_data[bus_pci].bus_id != 0) {
1306 /* mis-numbered, swap with whichever bus uses slot 0 */
1308 /* swap the bus entry types */
1309 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1310 bus_data[bus_0].bus_type = PCI;
1313 /* swap each relavant INTerrupt entry */
1314 id = bus_data[bus_pci].bus_id;
1315 for (x = 0; x < nintrs; ++x) {
1316 if (io_apic_ints[x].src_bus_id == id) {
1317 io_apic_ints[x].src_bus_id = 0;
1319 else if (io_apic_ints[x].src_bus_id == 0) {
1320 io_apic_ints[x].src_bus_id = id;
1327 /* Assign IO APIC IDs.
1329 * First try the existing ID. If a conflict is detected, try
1330 * the ID in the MP table. If a conflict is still detected, find
1333 * We cannot use the ID_TO_IO table before all conflicts has been
1334 * resolved and the table has been corrected.
1336 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1338 /* First try to use the value set by the BIOS */
1339 physid = io_apic_get_id(apic);
1340 if (io_apic_id_acceptable(apic, physid)) {
1341 if (IO_TO_ID(apic) != physid)
1342 swap_apic_id(apic, IO_TO_ID(apic), physid);
1346 /* Then check if the value in the MP table is acceptable */
1347 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1350 /* Last resort, find a free APIC ID and use it */
1351 freeid = first_free_apic_id();
1352 if (freeid >= NAPICID)
1353 panic("No free physical APIC IDs found");
1355 if (io_apic_id_acceptable(apic, freeid)) {
1356 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1359 panic("Free physical APIC ID not usable");
1361 fix_id_to_io_mapping();
1365 /* detect and fix broken Compaq MP table */
1366 if (apic_int_type(0, 0) == -1) {
1367 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1368 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1369 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1370 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1371 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1372 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1374 } else if (apic_int_type(0, 0) == 0) {
1375 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1376 for (x = 0; x < nintrs; ++x)
1377 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1378 (0 == io_apic_ints[x].dst_apic_int)) {
1379 io_apic_ints[x].int_type = 3;
1380 io_apic_ints[x].int_vector = 0xff;
1386 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1387 * controllers universally come in pairs. If IRQ 14 is specified
1388 * as an ISA interrupt, then IRQ 15 had better be too.
1390 * [ Shuttle XPC / AMD Athlon X2 ]
1391 * The MPTable is missing an entry for IRQ 15. Note that the
1392 * ACPI table has an entry for both 14 and 15.
1394 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1395 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1396 io14 = io_apic_find_int_entry(0, 14);
1397 io_apic_ints[nintrs] = *io14;
1398 io_apic_ints[nintrs].src_bus_irq = 15;
1399 io_apic_ints[nintrs].dst_apic_int = 15;
1407 /* Assign low level interrupt handlers */
1409 setup_apic_irq_mapping(void)
1415 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1416 int_to_apicintpin[x].ioapic = -1;
1417 int_to_apicintpin[x].int_pin = 0;
1418 int_to_apicintpin[x].apic_address = NULL;
1419 int_to_apicintpin[x].redirindex = 0;
1422 /* First assign ISA/EISA interrupts */
1423 for (x = 0; x < nintrs; x++) {
1424 int_vector = io_apic_ints[x].src_bus_irq;
1425 if (int_vector < APIC_INTMAPSIZE &&
1426 io_apic_ints[x].int_vector == 0xff &&
1427 int_to_apicintpin[int_vector].ioapic == -1 &&
1428 (apic_int_is_bus_type(x, ISA) ||
1429 apic_int_is_bus_type(x, EISA)) &&
1430 io_apic_ints[x].int_type == 0) {
1431 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1432 io_apic_ints[x].dst_apic_int,
1437 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1438 for (x = 0; x < nintrs; x++) {
1439 if (io_apic_ints[x].dst_apic_int == 0 &&
1440 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1441 io_apic_ints[x].int_vector == 0xff &&
1442 int_to_apicintpin[0].ioapic == -1 &&
1443 io_apic_ints[x].int_type == 3) {
1444 assign_apic_irq(0, 0, 0);
1449 /* Assign PCI interrupts */
1450 for (x = 0; x < nintrs; ++x) {
1451 if (io_apic_ints[x].int_type == 0 &&
1452 io_apic_ints[x].int_vector == 0xff &&
1453 apic_int_is_bus_type(x, PCI))
1454 allocate_apic_irq(x);
1461 processor_entry(proc_entry_ptr entry, int cpu)
1463 /* check for usability */
1464 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1467 if(entry->apic_id >= NAPICID)
1468 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1469 /* check for BSP flag */
1470 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1471 boot_cpu_id = entry->apic_id;
1472 CPU_TO_ID(0) = entry->apic_id;
1473 ID_TO_CPU(entry->apic_id) = 0;
1474 return 0; /* its already been counted */
1477 /* add another AP to list, if less than max number of CPUs */
1478 else if (cpu < MAXCPU) {
1479 CPU_TO_ID(cpu) = entry->apic_id;
1480 ID_TO_CPU(entry->apic_id) = cpu;
1489 bus_entry(bus_entry_ptr entry, int bus)
1494 /* encode the name into an index */
1495 for (x = 0; x < 6; ++x) {
1496 if ((c = entry->bus_type[x]) == ' ')
1502 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1503 panic("unknown bus type: '%s'", name);
1505 bus_data[bus].bus_id = entry->bus_id;
1506 bus_data[bus].bus_type = x;
1514 io_apic_entry(io_apic_entry_ptr entry, int apic)
1516 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1519 IO_TO_ID(apic) = entry->apic_id;
1520 if (entry->apic_id < NAPICID)
1521 ID_TO_IO(entry->apic_id) = apic;
1529 lookup_bus_type(char *name)
1533 for (x = 0; x < MAX_BUSTYPE; ++x)
1534 if (strcmp(bus_type_table[x].name, name) == 0)
1535 return bus_type_table[x].type;
1537 return UNKNOWN_BUSTYPE;
1543 int_entry(int_entry_ptr entry, int intr)
1547 io_apic_ints[intr].int_type = entry->int_type;
1548 io_apic_ints[intr].int_flags = entry->int_flags;
1549 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1550 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1551 if (entry->dst_apic_id == 255) {
1552 /* This signal goes to all IO APICS. Select an IO APIC
1553 with sufficient number of interrupt pins */
1554 for (apic = 0; apic < mp_napics; apic++)
1555 if (((io_apic_read(apic, IOAPIC_VER) &
1556 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1557 entry->dst_apic_int)
1559 if (apic < mp_napics)
1560 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1562 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1564 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1565 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1571 apic_int_is_bus_type(int intr, int bus_type)
1575 for (bus = 0; bus < mp_nbusses; ++bus)
1576 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1577 && ((int) bus_data[bus].bus_type == bus_type))
1584 * Given a traditional ISA INT mask, return an APIC mask.
1587 isa_apic_mask(u_int isa_mask)
1592 #if defined(SKIP_IRQ15_REDIRECT)
1593 if (isa_mask == (1 << 15)) {
1594 kprintf("skipping ISA IRQ15 redirect\n");
1597 #endif /* SKIP_IRQ15_REDIRECT */
1599 isa_irq = ffs(isa_mask); /* find its bit position */
1600 if (isa_irq == 0) /* doesn't exist */
1602 --isa_irq; /* make it zero based */
1604 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1608 return (1 << apic_pin); /* convert pin# to a mask */
1612 * Determine which APIC pin an ISA/EISA INT is attached to.
1614 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1615 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1616 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1617 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1619 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1621 isa_apic_irq(int isa_irq)
1625 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1626 if (INTTYPE(intr) == 0) { /* standard INT */
1627 if (SRCBUSIRQ(intr) == isa_irq) {
1628 if (apic_int_is_bus_type(intr, ISA) ||
1629 apic_int_is_bus_type(intr, EISA)) {
1630 if (INTIRQ(intr) == 0xff)
1631 return -1; /* unassigned */
1632 return INTIRQ(intr); /* found */
1637 return -1; /* NOT found */
1642 * Determine which APIC pin a PCI INT is attached to.
1644 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1645 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1646 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1648 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1652 --pciInt; /* zero based */
1654 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1655 if ((INTTYPE(intr) == 0) /* standard INT */
1656 && (SRCBUSID(intr) == pciBus)
1657 && (SRCBUSDEVICE(intr) == pciDevice)
1658 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1659 if (apic_int_is_bus_type(intr, PCI)) {
1660 if (INTIRQ(intr) == 0xff) {
1661 kprintf("IOAPIC: pci_apic_irq() "
1663 return -1; /* unassigned */
1665 return INTIRQ(intr); /* exact match */
1670 return -1; /* NOT found */
1674 next_apic_irq(int irq)
1681 for (intr = 0; intr < nintrs; intr++) {
1682 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1684 bus = SRCBUSID(intr);
1685 bustype = apic_bus_type(bus);
1686 if (bustype != ISA &&
1692 if (intr >= nintrs) {
1695 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1696 if (INTTYPE(ointr) != 0)
1698 if (bus != SRCBUSID(ointr))
1700 if (bustype == PCI) {
1701 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1703 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1706 if (bustype == ISA || bustype == EISA) {
1707 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1710 if (INTPIN(intr) == INTPIN(ointr))
1714 if (ointr >= nintrs) {
1717 return INTIRQ(ointr);
1732 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1735 * Exactly what this means is unclear at this point. It is a solution
1736 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1737 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1738 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1742 undirect_isa_irq(int rirq)
1746 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1747 /** FIXME: tickle the MB redirector chip */
1751 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1758 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1761 undirect_pci_irq(int rirq)
1765 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1767 /** FIXME: tickle the MB redirector chip */
1771 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1779 * given a bus ID, return:
1780 * the bus type if found
1784 apic_bus_type(int id)
1788 for (x = 0; x < mp_nbusses; ++x)
1789 if (bus_data[x].bus_id == id)
1790 return bus_data[x].bus_type;
1798 * given a LOGICAL APIC# and pin#, return:
1799 * the associated src bus ID if found
1803 apic_src_bus_id(int apic, int pin)
1807 /* search each of the possible INTerrupt sources */
1808 for (x = 0; x < nintrs; ++x)
1809 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1810 (pin == io_apic_ints[x].dst_apic_int))
1811 return (io_apic_ints[x].src_bus_id);
1813 return -1; /* NOT found */
1817 * given a LOGICAL APIC# and pin#, return:
1818 * the associated src bus IRQ if found
1822 apic_src_bus_irq(int apic, int pin)
1826 for (x = 0; x < nintrs; x++)
1827 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1828 (pin == io_apic_ints[x].dst_apic_int))
1829 return (io_apic_ints[x].src_bus_irq);
1831 return -1; /* NOT found */
1836 * given a LOGICAL APIC# and pin#, return:
1837 * the associated INTerrupt type if found
1841 apic_int_type(int apic, int pin)
1845 /* search each of the possible INTerrupt sources */
1846 for (x = 0; x < nintrs; ++x) {
1847 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1848 (pin == io_apic_ints[x].dst_apic_int))
1849 return (io_apic_ints[x].int_type);
1851 return -1; /* NOT found */
1855 * Return the IRQ associated with an APIC pin
1858 apic_irq(int apic, int pin)
1863 for (x = 0; x < nintrs; ++x) {
1864 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1865 (pin == io_apic_ints[x].dst_apic_int)) {
1866 res = io_apic_ints[x].int_vector;
1869 if (apic != int_to_apicintpin[res].ioapic)
1870 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1871 if (pin != int_to_apicintpin[res].int_pin)
1872 panic("apic_irq inconsistent table (2)");
1881 * given a LOGICAL APIC# and pin#, return:
1882 * the associated trigger mode if found
1886 apic_trigger(int apic, int pin)
1890 /* search each of the possible INTerrupt sources */
1891 for (x = 0; x < nintrs; ++x)
1892 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1893 (pin == io_apic_ints[x].dst_apic_int))
1894 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1896 return -1; /* NOT found */
1901 * given a LOGICAL APIC# and pin#, return:
1902 * the associated 'active' level if found
1906 apic_polarity(int apic, int pin)
1910 /* search each of the possible INTerrupt sources */
1911 for (x = 0; x < nintrs; ++x)
1912 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1913 (pin == io_apic_ints[x].dst_apic_int))
1914 return (io_apic_ints[x].int_flags & 0x03);
1916 return -1; /* NOT found */
1922 * set data according to MP defaults
1923 * FIXME: probably not complete yet...
1926 default_mp_table(int type)
1929 #if defined(APIC_IO)
1932 #endif /* APIC_IO */
1935 kprintf(" MP default config type: %d\n", type);
1938 kprintf(" bus: ISA, APIC: 82489DX\n");
1941 kprintf(" bus: EISA, APIC: 82489DX\n");
1944 kprintf(" bus: EISA, APIC: 82489DX\n");
1947 kprintf(" bus: MCA, APIC: 82489DX\n");
1950 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
1953 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
1956 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
1959 kprintf(" future type\n");
1965 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
1966 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1969 CPU_TO_ID(0) = boot_cpu_id;
1970 ID_TO_CPU(boot_cpu_id) = 0;
1972 /* one and only AP */
1973 CPU_TO_ID(1) = ap_cpu_id;
1974 ID_TO_CPU(ap_cpu_id) = 1;
1976 #if defined(APIC_IO)
1977 /* one and only IO APIC */
1978 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1981 * sanity check, refer to MP spec section 3.6.6, last paragraph
1982 * necessary as some hardware isn't properly setting up the IO APIC
1984 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1985 if (io_apic_id != 2) {
1987 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1988 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1989 io_apic_set_id(0, 2);
1992 IO_TO_ID(0) = io_apic_id;
1993 ID_TO_IO(io_apic_id) = 0;
1994 #endif /* APIC_IO */
1996 /* fill out bus entries */
2005 bus_data[0].bus_id = default_data[type - 1][1];
2006 bus_data[0].bus_type = default_data[type - 1][2];
2007 bus_data[1].bus_id = default_data[type - 1][3];
2008 bus_data[1].bus_type = default_data[type - 1][4];
2011 /* case 4: case 7: MCA NOT supported */
2012 default: /* illegal/reserved */
2013 panic("BAD default MP config: %d", type);
2017 #if defined(APIC_IO)
2018 /* general cases from MP v1.4, table 5-2 */
2019 for (pin = 0; pin < 16; ++pin) {
2020 io_apic_ints[pin].int_type = 0;
2021 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2022 io_apic_ints[pin].src_bus_id = 0;
2023 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2024 io_apic_ints[pin].dst_apic_id = io_apic_id;
2025 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2028 /* special cases from MP v1.4, table 5-2 */
2030 io_apic_ints[2].int_type = 0xff; /* N/C */
2031 io_apic_ints[13].int_type = 0xff; /* N/C */
2032 #if !defined(APIC_MIXED_MODE)
2034 panic("sorry, can't support type 2 default yet");
2035 #endif /* APIC_MIXED_MODE */
2038 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2041 io_apic_ints[0].int_type = 0xff; /* N/C */
2043 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2044 #endif /* APIC_IO */
2048 * Map a physical memory address representing I/O into KVA. The I/O
2049 * block is assumed not to cross a page boundary.
2052 permanent_io_mapping(vm_paddr_t pa)
2054 KKASSERT(pa < 0x100000000LL);
2056 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2060 * start each AP in our list
2063 start_all_aps(u_int boot_addr)
2065 vm_offset_t va = boot_address + KERNBASE;
2066 u_int64_t *pt4, *pt3, *pt2;
2072 u_char mpbiosreason;
2073 u_long mpbioswarmvec;
2074 struct mdglobaldata *gd;
2075 struct privatespace *ps;
2077 POSTCODE(START_ALL_APS_POST);
2079 /* Initialize BSP's local APIC */
2080 apic_initialize(TRUE);
2083 /* install the AP 1st level boot code */
2084 pmap_kenter(va, boot_address);
2085 cpu_invlpg((void *)va); /* JG XXX */
2086 bcopy(mptramp_start, (void *)va, bootMP_size);
2088 /* Locate the page tables, they'll be below the trampoline */
2089 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2090 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2091 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2093 /* Create the initial 1GB replicated page tables */
2094 for (i = 0; i < 512; i++) {
2095 /* Each slot of the level 4 pages points to the same level 3 page */
2096 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2097 pt4[i] |= PG_V | PG_RW | PG_U;
2099 /* Each slot of the level 3 pages points to the same level 2 page */
2100 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2101 pt3[i] |= PG_V | PG_RW | PG_U;
2103 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2104 pt2[i] = i * (2 * 1024 * 1024);
2105 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2108 /* save the current value of the warm-start vector */
2109 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2110 outb(CMOS_REG, BIOS_RESET);
2111 mpbiosreason = inb(CMOS_DATA);
2113 /* setup a vector to our boot code */
2114 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2115 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2116 outb(CMOS_REG, BIOS_RESET);
2117 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2120 * If we have a TSC we can figure out the SMI interrupt rate.
2121 * The SMI does not necessarily use a constant rate. Spend
2122 * up to 250ms trying to figure it out.
2125 if (cpu_feature & CPUID_TSC) {
2126 set_apic_timer(275000);
2127 smilast = read_apic_timer();
2128 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2129 smicount = smitest();
2130 if (smibest == 0 || smilast - smicount < smibest)
2131 smibest = smilast - smicount;
2134 if (smibest > 250000)
2137 smibest = smibest * (int64_t)1000000 /
2138 get_apic_timer_frequency();
2142 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2143 1000000 / smibest, smibest);
2146 for (x = 1; x <= mp_naps; ++x) {
2148 /* This is a bit verbose, it will go away soon. */
2150 /* first page of AP's private space */
2151 pg = x * x86_64_btop(sizeof(struct privatespace));
2153 /* allocate new private data page(s) */
2154 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2155 MDGLOBALDATA_BASEALLOC_SIZE);
2157 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2158 bzero(gd, sizeof(*gd));
2159 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2161 /* prime data page for it to use */
2162 mi_gdinit(&gd->mi, x);
2164 gd->gd_CMAP1 = &SMPpt[pg + 0];
2165 gd->gd_CMAP2 = &SMPpt[pg + 1];
2166 gd->gd_CMAP3 = &SMPpt[pg + 2];
2167 gd->gd_PMAP1 = &SMPpt[pg + 3];
2168 gd->gd_CADDR1 = ps->CPAGE1;
2169 gd->gd_CADDR2 = ps->CPAGE2;
2170 gd->gd_CADDR3 = ps->CPAGE3;
2171 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2172 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2173 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2175 /* setup a vector to our boot code */
2176 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2177 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2178 outb(CMOS_REG, BIOS_RESET);
2179 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2182 * Setup the AP boot stack
2184 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2187 /* attempt to start the Application Processor */
2188 CHECK_INIT(99); /* setup checkpoints */
2189 if (!start_ap(gd, boot_addr, smibest)) {
2190 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2191 CHECK_PRINT("trace"); /* show checkpoints */
2192 /* better panic as the AP may be running loose */
2193 kprintf("panic y/n? [y] ");
2194 if (cngetc() != 'n')
2197 CHECK_PRINT("trace"); /* show checkpoints */
2199 /* record its version info */
2200 cpu_apic_versions[x] = cpu_apic_versions[0];
2203 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2206 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2207 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2210 ncpus2_shift = shift;
2211 ncpus2 = 1 << shift;
2212 ncpus2_mask = ncpus2 - 1;
2214 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2215 if ((1 << shift) < ncpus)
2217 ncpus_fit = 1 << shift;
2218 ncpus_fit_mask = ncpus_fit - 1;
2220 /* build our map of 'other' CPUs */
2221 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2222 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2223 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2225 /* fill in our (BSP) APIC version */
2226 cpu_apic_versions[0] = lapic->version;
2228 /* restore the warmstart vector */
2229 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2230 outb(CMOS_REG, BIOS_RESET);
2231 outb(CMOS_DATA, mpbiosreason);
2234 * NOTE! The idlestack for the BSP was setup by locore. Finish
2235 * up, clean out the P==V mapping we did earlier.
2239 /* number of APs actually started */
2245 * load the 1st level AP boot code into base memory.
2248 /* targets for relocation */
2249 extern void bigJump(void);
2250 extern void bootCodeSeg(void);
2251 extern void bootDataSeg(void);
2252 extern void MPentry(void);
2253 extern u_int MP_GDT;
2254 extern u_int mp_gdtbase;
2259 install_ap_tramp(u_int boot_addr)
2262 int size = *(int *) ((u_long) & bootMP_size);
2263 u_char *src = (u_char *) ((u_long) bootMP);
2264 u_char *dst = (u_char *) boot_addr + KERNBASE;
2265 u_int boot_base = (u_int) bootMP;
2270 POSTCODE(INSTALL_AP_TRAMP_POST);
2272 for (x = 0; x < size; ++x)
2276 * modify addresses in code we just moved to basemem. unfortunately we
2277 * need fairly detailed info about mpboot.s for this to work. changes
2278 * to mpboot.s might require changes here.
2281 /* boot code is located in KERNEL space */
2282 dst = (u_char *) boot_addr + KERNBASE;
2284 /* modify the lgdt arg */
2285 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2286 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2288 /* modify the ljmp target for MPentry() */
2289 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2290 *dst32 = ((u_int) MPentry - KERNBASE);
2292 /* modify the target for boot code segment */
2293 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2294 dst8 = (u_int8_t *) (dst16 + 1);
2295 *dst16 = (u_int) boot_addr & 0xffff;
2296 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2298 /* modify the target for boot data segment */
2299 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2300 dst8 = (u_int8_t *) (dst16 + 1);
2301 *dst16 = (u_int) boot_addr & 0xffff;
2302 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2308 * This function starts the AP (application processor) identified
2309 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2310 * to accomplish this. This is necessary because of the nuances
2311 * of the different hardware we might encounter. It ain't pretty,
2312 * but it seems to work.
2314 * NOTE: eventually an AP gets to ap_init(), which is called just
2315 * before the AP goes into the LWKT scheduler's idle loop.
2318 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2322 u_long icr_lo, icr_hi;
2324 POSTCODE(START_AP_POST);
2326 /* get the PHYSICAL APIC ID# */
2327 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2329 /* calculate the vector */
2330 vector = (boot_addr >> 12) & 0xff;
2332 /* We don't want anything interfering */
2335 /* Make sure the target cpu sees everything */
2339 * Try to detect when a SMI has occurred, wait up to 200ms.
2341 * If a SMI occurs during an AP reset but before we issue
2342 * the STARTUP command, the AP may brick. To work around
2343 * this problem we hold off doing the AP startup until
2344 * after we have detected the SMI. Hopefully another SMI
2345 * will not occur before we finish the AP startup.
2347 * Retries don't seem to help. SMIs have a window of opportunity
2348 * and if USB->legacy keyboard emulation is enabled in the BIOS
2349 * the interrupt rate can be quite high.
2351 * NOTE: Don't worry about the L1 cache load, it might bloat
2352 * ldelta a little but ndelta will be so huge when the SMI
2353 * occurs the detection logic will still work fine.
2356 set_apic_timer(200000);
2361 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2362 * and running the target CPU. OR this INIT IPI might be latched (P5
2363 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2366 * see apic/apicreg.h for icr bit definitions.
2368 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2372 * Setup the address for the target AP. We can setup
2373 * icr_hi once and then just trigger operations with
2376 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2377 icr_hi |= (physical_cpu << 24);
2378 icr_lo = lapic->icr_lo & 0xfff00000;
2379 lapic->icr_hi = icr_hi;
2382 * Do an INIT IPI: assert RESET
2384 * Use edge triggered mode to assert INIT
2386 lapic->icr_lo = icr_lo | 0x00004500;
2387 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2391 * The spec calls for a 10ms delay but we may have to use a
2392 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2393 * interrupt. We have other loops here too and dividing by 2
2394 * doesn't seem to be enough even after subtracting 350us,
2395 * so we divide by 4.
2397 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2398 * interrupt was detected we use the full 10ms.
2402 else if (smibest < 150 * 4 + 350)
2404 else if ((smibest - 350) / 4 < 10000)
2405 u_sleep((smibest - 350) / 4);
2410 * Do an INIT IPI: deassert RESET
2412 * Use level triggered mode to deassert. It is unclear
2413 * why we need to do this.
2415 lapic->icr_lo = icr_lo | 0x00008500;
2416 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2418 u_sleep(150); /* wait 150us */
2421 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2422 * latched, (P5 bug) this 1st STARTUP would then terminate
2423 * immediately, and the previously started INIT IPI would continue. OR
2424 * the previous INIT IPI has already run. and this STARTUP IPI will
2425 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2428 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2429 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2431 u_sleep(200); /* wait ~200uS */
2434 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2435 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2436 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2437 * recognized after hardware RESET or INIT IPI.
2439 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2440 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2443 /* Resume normal operation */
2446 /* wait for it to start, see ap_init() */
2447 set_apic_timer(5000000);/* == 5 seconds */
2448 while (read_apic_timer()) {
2449 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2450 return 1; /* return SUCCESS */
2453 return 0; /* return FAILURE */
2468 while (read_apic_timer()) {
2470 for (count = 0; count < 100; ++count)
2471 ntsc = rdtsc(); /* force loop to occur */
2473 ndelta = ntsc - ltsc;
2474 if (ldelta > ndelta)
2476 if (ndelta > ldelta * 2)
2479 ldelta = ntsc - ltsc;
2482 return(read_apic_timer());
2486 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2488 * If for some reason we were unable to start all cpus we cannot safely
2489 * use broadcast IPIs.
2495 if (smp_startup_mask == smp_active_mask) {
2496 all_but_self_ipi(XINVLTLB_OFFSET);
2498 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2499 APIC_DELMODE_FIXED);
2505 * When called the executing CPU will send an IPI to all other CPUs
2506 * requesting that they halt execution.
2508 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2510 * - Signals all CPUs in map to stop.
2511 * - Waits for each to stop.
2518 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2519 * from executing at same time.
2522 stop_cpus(u_int map)
2524 map &= smp_active_mask;
2526 /* send the Xcpustop IPI to all CPUs in map */
2527 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2529 while ((stopped_cpus & map) != map)
2537 * Called by a CPU to restart stopped CPUs.
2539 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2541 * - Signals all CPUs in map to restart.
2542 * - Waits for each to restart.
2550 restart_cpus(u_int map)
2552 /* signal other cpus to restart */
2553 started_cpus = map & smp_active_mask;
2555 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2562 * This is called once the mpboot code has gotten us properly relocated
2563 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2564 * and when it returns the scheduler will call the real cpu_idle() main
2565 * loop for the idlethread. Interrupts are disabled on entry and should
2566 * remain disabled at return.
2574 * Adjust smp_startup_mask to signal the BSP that we have started
2575 * up successfully. Note that we do not yet hold the BGL. The BSP
2576 * is waiting for our signal.
2578 * We can't set our bit in smp_active_mask yet because we are holding
2579 * interrupts physically disabled and remote cpus could deadlock
2580 * trying to send us an IPI.
2582 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2586 * Interlock for finalization. Wait until mp_finish is non-zero,
2587 * then get the MP lock.
2589 * Note: We are in a critical section.
2591 * Note: We have to synchronize td_mpcount to our desired MP state
2592 * before calling cpu_try_mplock().
2594 * Note: we are the idle thread, we can only spin.
2596 * Note: The load fence is memory volatile and prevents the compiler
2597 * from improperly caching mp_finish, and the cpu from improperly
2600 while (mp_finish == 0)
2602 ++curthread->td_mpcount;
2603 while (cpu_try_mplock() == 0)
2606 if (cpu_feature & CPUID_TSC) {
2608 * The BSP is constantly updating tsc0_offset, figure out the
2609 * relative difference to synchronize ktrdump.
2611 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2614 /* BSP may have changed PTD while we're waiting for the lock */
2617 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2621 /* Build our map of 'other' CPUs. */
2622 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2624 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2626 /* A quick check from sanity claus */
2627 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2628 if (mycpu->gd_cpuid != apic_id) {
2629 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2630 kprintf("SMP: apic_id = %d\n", apic_id);
2632 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2634 panic("cpuid mismatch! boom!!");
2637 /* Initialize AP's local APIC for irq's */
2638 apic_initialize(FALSE);
2640 /* Set memory range attributes for this CPU to match the BSP */
2641 mem_range_AP_init();
2644 * Once we go active we must process any IPIQ messages that may
2645 * have been queued, because no actual IPI will occur until we
2646 * set our bit in the smp_active_mask. If we don't the IPI
2647 * message interlock could be left set which would also prevent
2650 * The idle loop doesn't expect the BGL to be held and while
2651 * lwkt_switch() normally cleans things up this is a special case
2652 * because we returning almost directly into the idle loop.
2654 * The idle thread is never placed on the runq, make sure
2655 * nothing we've done put it there.
2657 KKASSERT(curthread->td_mpcount == 1);
2658 smp_active_mask |= 1 << mycpu->gd_cpuid;
2661 * Enable interrupts here. idle_restore will also do it, but
2662 * doing it here lets us clean up any strays that got posted to
2663 * the CPU during the AP boot while we are still in a critical
2666 __asm __volatile("sti; pause; pause"::);
2667 mdcpu->gd_fpending = 0;
2669 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2670 lwkt_process_ipiq();
2673 * Releasing the mp lock lets the BSP finish up the SMP init
2676 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2680 * Get SMP fully working before we start initializing devices.
2688 kprintf("Finish MP startup\n");
2689 if (cpu_feature & CPUID_TSC)
2690 tsc0_offset = rdtsc();
2693 while (smp_active_mask != smp_startup_mask) {
2695 if (cpu_feature & CPUID_TSC)
2696 tsc0_offset = rdtsc();
2698 while (try_mplock() == 0)
2701 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2704 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2707 cpu_send_ipiq(int dcpu)
2709 if ((1 << dcpu) & smp_active_mask)
2710 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2713 #if 0 /* single_apic_ipi_passive() not working yet */
2715 * Returns 0 on failure, 1 on success
2718 cpu_send_ipiq_passive(int dcpu)
2721 if ((1 << dcpu) & smp_active_mask) {
2722 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2723 APIC_DELMODE_FIXED);