2 * Copyright (c) 1993 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * $FreeBSD: src/sys/i386/include/cpufunc.h,v 1.96.2.3 2002/04/28 22:50:54 dwmalone Exp $
34 * $DragonFly: src/sys/i386/include/Attic/cpufunc.h,v 1.13 2005/06/03 23:57:31 dillon Exp $
38 * Functions to provide access to special i386 instructions.
41 #ifndef _MACHINE_CPUFUNC_H_
42 #define _MACHINE_CPUFUNC_H_
44 #include <sys/cdefs.h>
47 #define readb(va) (*(volatile u_int8_t *) (va))
48 #define readw(va) (*(volatile u_int16_t *) (va))
49 #define readl(va) (*(volatile u_int32_t *) (va))
51 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
52 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
53 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
58 #include "lock.h" /* XXX */
61 #ifdef SWTCH_OPTIM_STATS
62 extern int tlb_flush_count; /* XXX */
68 __asm __volatile("int $3");
72 * Find the first 1 in mask, starting with bit 0 and return the
73 * bit number. If mask is 0 the result is undefined.
80 __asm __volatile("bsfl %0,%0" : "=r" (result) : "0" (mask));
85 * Find the last 1 in mask, starting with bit 31 and return the
86 * bit number. If mask is 0 the result is undefined.
93 __asm __volatile("bsrl %0,%0" : "=r" (result) : "0" (mask));
98 * Test and set the specified bit (1 << bit) in the integer. The
99 * previous value of the bit is returned (0 or 1).
102 btsl(u_int *mask, int bit)
106 __asm __volatile("btsl %2,%1; movl $0,%0; adcl $0,%0" :
107 "=r"(result), "=m"(*mask) : "r" (bit));
112 * Test and clear the specified bit (1 << bit) in the integer. The
113 * previous value of the bit is returned (0 or 1).
116 btrl(u_int *mask, int bit)
120 __asm __volatile("btrl %2,%1; movl $0,%0; adcl $0,%0" :
121 "=r"(result), "=m"(*mask) : "r" (bit));
126 do_cpuid(u_int ax, u_int *p)
128 __asm __volatile("cpuid"
129 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
134 cpu_disable_intr(void)
136 __asm __volatile("cli" : : : "memory");
140 cpu_enable_intr(void)
142 __asm __volatile("sti");
146 * Cpu and compiler memory ordering fence. mfence ensures strong read and
149 * A serializing or fence instruction is required here. A locked bus
150 * cycle on data for which we already own cache mastership is the most
157 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
159 __asm __volatile("" : : : "memory");
164 * cpu_lfence() ensures strong read ordering for reads issued prior
165 * to the instruction verses reads issued afterwords.
167 * A serializing or fence instruction is required here. A locked bus
168 * cycle on data for which we already own cache mastership is the most
175 __asm __volatile("lock; addl $0,(%%esp)" : : : "memory");
177 __asm __volatile("" : : : "memory");
182 * cpu_lfence() ensures strong write ordering for writes issued prior
183 * to the instruction verses writes issued afterwords. Writes are
184 * ordered on intel cpus so we do not actually have to do anything.
189 __asm __volatile("" : : : "memory");
193 * cpu_ccfence() prevents the compiler from reordering instructions, in
194 * particular stores, relative to the current cpu. Use cpu_sfence() if
195 * you need to guarentee ordering by both the compiler and by the cpu.
197 * This also prevents the compiler from caching memory loads into local
198 * variables across the routine.
203 __asm __volatile("" : : : "memory");
208 #define HAVE_INLINE_FFS
214 * Note that gcc-2's builtin ffs would be used if we didn't declare
215 * this inline or turn off the builtin. The builtin is faster but
216 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
219 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
222 #define HAVE_INLINE_FLS
227 return (mask == 0 ? mask : (int) bsrl((u_int)mask) + 1);
233 * The following complications are to get around gcc not having a
234 * constraint letter for the range 0..255. We still put "d" in the
235 * constraint because "i" isn't a valid constraint when the port
236 * isn't constant. This only matters for -O0 because otherwise
237 * the non-working version gets optimized away.
239 * Use an expression-statement instead of a conditional expression
240 * because gcc-2.6.0 would promote the operands of the conditional
241 * and produce poor code for "if ((inb(var) & const1) == const2)".
243 * The unnecessary test `(port) < 0x10000' is to generate a warning if
244 * the `port' has type u_short or smaller. Such types are pessimal.
245 * This actually only works for signed types. The range check is
246 * careful to avoid generating warnings.
248 #define inb(port) __extension__ ({ \
250 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
251 && (port) < 0x10000) \
252 _data = inbc(port); \
254 _data = inbv(port); \
257 #define outb(port, data) ( \
258 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
259 && (port) < 0x10000 \
260 ? outbc(port, data) : outbv(port, data))
262 static __inline u_char
267 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
272 outbc(u_int port, u_char data)
274 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
277 static __inline u_char
282 * We use %%dx and not %1 here because i/o is done at %dx and not at
283 * %edx, while gcc generates inferior code (movw instead of movl)
284 * if we tell it to load (u_short) port.
286 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
290 static __inline u_int
295 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
300 insb(u_int port, void *addr, size_t cnt)
302 __asm __volatile("cld; rep; insb"
303 : "=D" (addr), "=c" (cnt)
304 : "0" (addr), "1" (cnt), "d" (port)
309 insw(u_int port, void *addr, size_t cnt)
311 __asm __volatile("cld; rep; insw"
312 : "=D" (addr), "=c" (cnt)
313 : "0" (addr), "1" (cnt), "d" (port)
318 insl(u_int port, void *addr, size_t cnt)
320 __asm __volatile("cld; rep; insl"
321 : "=D" (addr), "=c" (cnt)
322 : "0" (addr), "1" (cnt), "d" (port)
329 __asm __volatile("invd");
335 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
336 * will cause the invl*() functions to be equivalent to the cpu_invl*()
340 void smp_invltlb(void);
342 #define smp_invltlb()
346 * Invalidate a patricular VA on this cpu only
349 cpu_invlpg(void *addr)
351 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
355 * Invalidate the TLB on this cpu only
362 * This should be implemented as load_cr3(rcr3()) when load_cr3()
365 __asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
367 #if defined(SWTCH_OPTIM_STATS)
374 static __inline u_short
379 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
383 static __inline u_int
384 loadandclear(volatile u_int *addr)
388 __asm __volatile("xorl %0,%0; xchgl %1,%0"
389 : "=&r" (result) : "m" (*addr));
394 outbv(u_int port, u_char data)
398 * Use an unnecessary assignment to help gcc's register allocator.
399 * This make a large difference for gcc-1.40 and a tiny difference
400 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
401 * best results. gcc-2.6.0 can't handle this.
404 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
408 outl(u_int port, u_int data)
411 * outl() and outw() aren't used much so we haven't looked at
412 * possible micro-optimizations such as the unnecessary
413 * assignment for them.
415 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
419 outsb(u_int port, const void *addr, size_t cnt)
421 __asm __volatile("cld; rep; outsb"
422 : "=S" (addr), "=c" (cnt)
423 : "0" (addr), "1" (cnt), "d" (port));
427 outsw(u_int port, const void *addr, size_t cnt)
429 __asm __volatile("cld; rep; outsw"
430 : "=S" (addr), "=c" (cnt)
431 : "0" (addr), "1" (cnt), "d" (port));
435 outsl(u_int port, const void *addr, size_t cnt)
437 __asm __volatile("cld; rep; outsl"
438 : "=S" (addr), "=c" (cnt)
439 : "0" (addr), "1" (cnt), "d" (port));
443 outw(u_int port, u_short data)
445 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
448 static __inline u_int
453 __asm __volatile("movl %%cr2,%0" : "=r" (data));
457 static __inline u_int
462 __asm __volatile("pushfl; popl %0" : "=r" (ef));
466 static __inline u_int64_t
471 __asm __volatile(".byte 0x0f, 0x32" : "=A" (rv) : "c" (msr));
475 static __inline u_int64_t
480 __asm __volatile(".byte 0x0f, 0x33" : "=A" (rv) : "c" (pmc));
484 static __inline u_int64_t
489 __asm __volatile(".byte 0x0f, 0x31" : "=A" (rv));
496 __asm __volatile("wbinvd");
500 write_eflags(u_int ef)
502 __asm __volatile("pushl %0; popfl" : : "r" (ef));
506 wrmsr(u_int msr, u_int64_t newval)
508 __asm __volatile(".byte 0x0f, 0x30" : : "A" (newval), "c" (msr));
511 static __inline u_int
515 __asm __volatile("movl %%fs,%0" : "=rm" (sel));
519 static __inline u_int
523 __asm __volatile("movl %%gs,%0" : "=rm" (sel));
530 __asm __volatile("movl %0,%%fs" : : "rm" (sel));
536 __asm __volatile("movl %0,%%gs" : : "rm" (sel));
539 static __inline u_int
543 __asm __volatile("movl %%dr0,%0" : "=r" (data));
550 __asm __volatile("movl %0,%%dr0" : : "r" (sel));
553 static __inline u_int
557 __asm __volatile("movl %%dr1,%0" : "=r" (data));
564 __asm __volatile("movl %0,%%dr1" : : "r" (sel));
567 static __inline u_int
571 __asm __volatile("movl %%dr2,%0" : "=r" (data));
578 __asm __volatile("movl %0,%%dr2" : : "r" (sel));
581 static __inline u_int
585 __asm __volatile("movl %%dr3,%0" : "=r" (data));
592 __asm __volatile("movl %0,%%dr3" : : "r" (sel));
595 static __inline u_int
599 __asm __volatile("movl %%dr4,%0" : "=r" (data));
606 __asm __volatile("movl %0,%%dr4" : : "r" (sel));
609 static __inline u_int
613 __asm __volatile("movl %%dr5,%0" : "=r" (data));
620 __asm __volatile("movl %0,%%dr5" : : "r" (sel));
623 static __inline u_int
627 __asm __volatile("movl %%dr6,%0" : "=r" (data));
634 __asm __volatile("movl %0,%%dr6" : : "r" (sel));
637 static __inline u_int
641 __asm __volatile("movl %%dr7,%0" : "=r" (data));
648 __asm __volatile("movl %0,%%dr7" : : "r" (sel));
651 #else /* !__GNUC__ */
653 int breakpoint (void);
654 u_int bsfl (u_int mask);
655 u_int bsrl (u_int mask);
656 void cpu_disable_intr (void);
657 void do_cpuid (u_int ax, u_int *p);
658 void cpu_enable_intr (void);
659 u_char inb (u_int port);
660 u_int inl (u_int port);
661 void insb (u_int port, void *addr, size_t cnt);
662 void insl (u_int port, void *addr, size_t cnt);
663 void insw (u_int port, void *addr, size_t cnt);
665 u_short inw (u_int port);
666 u_int loadandclear (u_int *addr);
667 void outb (u_int port, u_char data);
668 void outl (u_int port, u_int data);
669 void outsb (u_int port, void *addr, size_t cnt);
670 void outsl (u_int port, void *addr, size_t cnt);
671 void outsw (u_int port, void *addr, size_t cnt);
672 void outw (u_int port, u_short data);
674 u_int64_t rdmsr (u_int msr);
675 u_int64_t rdpmc (u_int pmc);
676 u_int64_t rdtsc (void);
677 u_int read_eflags (void);
679 void write_eflags (u_int ef);
680 void wrmsr (u_int msr, u_int64_t newval);
683 void load_fs (u_int sel);
684 void load_gs (u_int sel);
686 #endif /* __GNUC__ */
688 void load_cr0 (u_int cr0);
689 void load_cr3 (u_int cr3);
690 void load_cr4 (u_int cr4);
691 void ltr (u_short sel);
695 void reset_dbregs (void);
698 #endif /* !_MACHINE_CPUFUNC_H_ */