2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $
33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.16 2005/02/21 18:40:37 joerg Exp $
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/sockio.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/socket.h>
45 #include <net/ifq_var.h>
46 #include <net/if_arp.h>
47 #include <net/ethernet.h>
48 #include <net/if_dl.h>
49 #include <net/if_media.h>
50 #include <net/vlan/if_vlan_var.h>
54 #include <vm/vm.h> /* for vtophys */
55 #include <vm/pmap.h> /* for vtophys */
56 #include <machine/clock.h> /* for DELAY */
57 #include <machine/bus_memio.h>
58 #include <machine/bus_pio.h>
59 #include <machine/bus.h>
60 #include <machine/resource.h>
64 #include "../mii_layer/mii.h"
65 #include "../mii_layer/miivar.h"
67 #include <bus/pci/pcireg.h>
68 #include <bus/pci/pcivar.h>
70 /* "controller miibus0" required. See GENERIC if you get errors here. */
71 #include "miibus_if.h"
73 #define STE_USEIOSPACE
75 #include "if_stereg.h"
78 * Various supported device vendors/types and their names.
80 static struct ste_type ste_devs[] = {
81 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" },
82 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" },
86 static int ste_probe (device_t);
87 static int ste_attach (device_t);
88 static int ste_detach (device_t);
89 static void ste_init (void *);
90 static void ste_intr (void *);
91 static void ste_rxeof (struct ste_softc *);
92 static void ste_txeoc (struct ste_softc *);
93 static void ste_txeof (struct ste_softc *);
94 static void ste_stats_update (void *);
95 static void ste_stop (struct ste_softc *);
96 static void ste_reset (struct ste_softc *);
97 static int ste_ioctl (struct ifnet *, u_long, caddr_t,
99 static int ste_encap (struct ste_softc *, struct ste_chain *,
101 static void ste_start (struct ifnet *);
102 static void ste_watchdog (struct ifnet *);
103 static void ste_shutdown (device_t);
104 static int ste_newbuf (struct ste_softc *,
105 struct ste_chain_onefrag *,
107 static int ste_ifmedia_upd (struct ifnet *);
108 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *);
110 static void ste_mii_sync (struct ste_softc *);
111 static void ste_mii_send (struct ste_softc *, u_int32_t, int);
112 static int ste_mii_readreg (struct ste_softc *,
113 struct ste_mii_frame *);
114 static int ste_mii_writereg (struct ste_softc *,
115 struct ste_mii_frame *);
116 static int ste_miibus_readreg (device_t, int, int);
117 static int ste_miibus_writereg (device_t, int, int, int);
118 static void ste_miibus_statchg (device_t);
120 static int ste_eeprom_wait (struct ste_softc *);
121 static int ste_read_eeprom (struct ste_softc *, caddr_t, int,
123 static void ste_wait (struct ste_softc *);
124 static u_int8_t ste_calchash (caddr_t);
125 static void ste_setmulti (struct ste_softc *);
126 static int ste_init_rx_list (struct ste_softc *);
127 static void ste_init_tx_list (struct ste_softc *);
129 #ifdef STE_USEIOSPACE
130 #define STE_RES SYS_RES_IOPORT
131 #define STE_RID STE_PCI_LOIO
133 #define STE_RES SYS_RES_MEMORY
134 #define STE_RID STE_PCI_LOMEM
137 static device_method_t ste_methods[] = {
138 /* Device interface */
139 DEVMETHOD(device_probe, ste_probe),
140 DEVMETHOD(device_attach, ste_attach),
141 DEVMETHOD(device_detach, ste_detach),
142 DEVMETHOD(device_shutdown, ste_shutdown),
145 DEVMETHOD(bus_print_child, bus_generic_print_child),
146 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
149 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
150 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
151 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
156 static driver_t ste_driver = {
159 sizeof(struct ste_softc)
162 static devclass_t ste_devclass;
164 DECLARE_DUMMY_MODULE(if_ste);
165 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0);
166 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
168 #define STE_SETBIT4(sc, reg, x) \
169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
171 #define STE_CLRBIT4(sc, reg, x) \
172 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
174 #define STE_SETBIT2(sc, reg, x) \
175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
177 #define STE_CLRBIT2(sc, reg, x) \
178 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
180 #define STE_SETBIT1(sc, reg, x) \
181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
183 #define STE_CLRBIT1(sc, reg, x) \
184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
187 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
188 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
191 * Sync the PHYs by setting data bit and strobing the clock 32 times.
193 static void ste_mii_sync(sc)
194 struct ste_softc *sc;
198 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
200 for (i = 0; i < 32; i++) {
201 MII_SET(STE_PHYCTL_MCLK);
203 MII_CLR(STE_PHYCTL_MCLK);
211 * Clock a series of bits through the MII.
213 static void ste_mii_send(sc, bits, cnt)
214 struct ste_softc *sc;
220 MII_CLR(STE_PHYCTL_MCLK);
222 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
224 MII_SET(STE_PHYCTL_MDATA);
226 MII_CLR(STE_PHYCTL_MDATA);
229 MII_CLR(STE_PHYCTL_MCLK);
231 MII_SET(STE_PHYCTL_MCLK);
236 * Read an PHY register through the MII.
238 static int ste_mii_readreg(sc, frame)
239 struct ste_softc *sc;
240 struct ste_mii_frame *frame;
248 * Set up frame for RX.
250 frame->mii_stdelim = STE_MII_STARTDELIM;
251 frame->mii_opcode = STE_MII_READOP;
252 frame->mii_turnaround = 0;
255 CSR_WRITE_2(sc, STE_PHYCTL, 0);
259 MII_SET(STE_PHYCTL_MDIR);
264 * Send command/address info.
266 ste_mii_send(sc, frame->mii_stdelim, 2);
267 ste_mii_send(sc, frame->mii_opcode, 2);
268 ste_mii_send(sc, frame->mii_phyaddr, 5);
269 ste_mii_send(sc, frame->mii_regaddr, 5);
272 MII_CLR(STE_PHYCTL_MDIR);
275 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
277 MII_SET(STE_PHYCTL_MCLK);
281 MII_CLR(STE_PHYCTL_MCLK);
283 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
284 MII_SET(STE_PHYCTL_MCLK);
288 * Now try reading data bits. If the ack failed, we still
289 * need to clock through 16 cycles to keep the PHY(s) in sync.
292 for(i = 0; i < 16; i++) {
293 MII_CLR(STE_PHYCTL_MCLK);
295 MII_SET(STE_PHYCTL_MCLK);
301 for (i = 0x8000; i; i >>= 1) {
302 MII_CLR(STE_PHYCTL_MCLK);
305 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
306 frame->mii_data |= i;
309 MII_SET(STE_PHYCTL_MCLK);
315 MII_CLR(STE_PHYCTL_MCLK);
317 MII_SET(STE_PHYCTL_MCLK);
328 * Write to a PHY register through the MII.
330 static int ste_mii_writereg(sc, frame)
331 struct ste_softc *sc;
332 struct ste_mii_frame *frame;
339 * Set up frame for TX.
342 frame->mii_stdelim = STE_MII_STARTDELIM;
343 frame->mii_opcode = STE_MII_WRITEOP;
344 frame->mii_turnaround = STE_MII_TURNAROUND;
347 * Turn on data output.
349 MII_SET(STE_PHYCTL_MDIR);
353 ste_mii_send(sc, frame->mii_stdelim, 2);
354 ste_mii_send(sc, frame->mii_opcode, 2);
355 ste_mii_send(sc, frame->mii_phyaddr, 5);
356 ste_mii_send(sc, frame->mii_regaddr, 5);
357 ste_mii_send(sc, frame->mii_turnaround, 2);
358 ste_mii_send(sc, frame->mii_data, 16);
361 MII_SET(STE_PHYCTL_MCLK);
363 MII_CLR(STE_PHYCTL_MCLK);
369 MII_CLR(STE_PHYCTL_MDIR);
376 static int ste_miibus_readreg(dev, phy, reg)
380 struct ste_softc *sc;
381 struct ste_mii_frame frame;
383 sc = device_get_softc(dev);
385 if ( sc->ste_one_phy && phy != 0 )
388 bzero((char *)&frame, sizeof(frame));
390 frame.mii_phyaddr = phy;
391 frame.mii_regaddr = reg;
392 ste_mii_readreg(sc, &frame);
394 return(frame.mii_data);
397 static int ste_miibus_writereg(dev, phy, reg, data)
401 struct ste_softc *sc;
402 struct ste_mii_frame frame;
404 sc = device_get_softc(dev);
405 bzero((char *)&frame, sizeof(frame));
407 frame.mii_phyaddr = phy;
408 frame.mii_regaddr = reg;
409 frame.mii_data = data;
411 ste_mii_writereg(sc, &frame);
416 static void ste_miibus_statchg(dev)
419 struct ste_softc *sc;
420 struct mii_data *mii;
423 sc = device_get_softc(dev);
424 mii = device_get_softc(sc->ste_miibus);
426 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
427 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
429 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
432 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET |
433 STE_ASICCTL_TX_RESET);
434 for (i = 0; i < STE_TIMEOUT; i++) {
435 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
438 if (i == STE_TIMEOUT)
439 printf("ste%d: rx reset never completed\n", sc->ste_unit);
444 static int ste_ifmedia_upd(ifp)
447 struct ste_softc *sc;
448 struct mii_data *mii;
451 mii = device_get_softc(sc->ste_miibus);
453 if (mii->mii_instance) {
454 struct mii_softc *miisc;
455 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
456 miisc = LIST_NEXT(miisc, mii_list))
457 mii_phy_reset(miisc);
464 static void ste_ifmedia_sts(ifp, ifmr)
466 struct ifmediareq *ifmr;
468 struct ste_softc *sc;
469 struct mii_data *mii;
472 mii = device_get_softc(sc->ste_miibus);
475 ifmr->ifm_active = mii->mii_media_active;
476 ifmr->ifm_status = mii->mii_media_status;
481 static void ste_wait(sc)
482 struct ste_softc *sc;
486 for (i = 0; i < STE_TIMEOUT; i++) {
487 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
491 if (i == STE_TIMEOUT)
492 printf("ste%d: command never completed!\n", sc->ste_unit);
498 * The EEPROM is slow: give it time to come ready after issuing
501 static int ste_eeprom_wait(sc)
502 struct ste_softc *sc;
508 for (i = 0; i < 100; i++) {
509 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
516 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit);
524 * Read a sequence of words from the EEPROM. Note that ethernet address
525 * data is stored in the EEPROM in network byte order.
527 static int ste_read_eeprom(sc, dest, off, cnt, swap)
528 struct ste_softc *sc;
535 u_int16_t word = 0, *ptr;
537 if (ste_eeprom_wait(sc))
540 for (i = 0; i < cnt; i++) {
541 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
542 err = ste_eeprom_wait(sc);
545 word = CSR_READ_2(sc, STE_EEPROM_DATA);
546 ptr = (u_int16_t *)(dest + (i * 2));
556 static u_int8_t ste_calchash(addr)
560 u_int32_t crc, carry;
564 /* Compute CRC for the address value. */
565 crc = 0xFFFFFFFF; /* initial value */
567 for (i = 0; i < 6; i++) {
569 for (j = 0; j < 8; j++) {
570 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
574 crc = (crc ^ 0x04c11db6) | carry;
578 /* return the filter bit position */
579 return(crc & 0x0000003F);
582 static void ste_setmulti(sc)
583 struct ste_softc *sc;
587 u_int32_t hashes[2] = { 0, 0 };
588 struct ifmultiaddr *ifma;
590 ifp = &sc->arpcom.ac_if;
591 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
592 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
593 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
597 /* first, zot all the existing hash bits */
598 CSR_WRITE_2(sc, STE_MAR0, 0);
599 CSR_WRITE_2(sc, STE_MAR1, 0);
600 CSR_WRITE_2(sc, STE_MAR2, 0);
601 CSR_WRITE_2(sc, STE_MAR3, 0);
603 /* now program new ones */
604 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
605 ifma = ifma->ifma_link.le_next) {
606 if (ifma->ifma_addr->sa_family != AF_LINK)
608 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
610 hashes[0] |= (1 << h);
612 hashes[1] |= (1 << (h - 32));
615 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
616 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
617 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
618 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
619 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
620 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
625 static void ste_intr(xsc)
628 struct ste_softc *sc;
633 ifp = &sc->arpcom.ac_if;
635 /* See if this is really our interrupt. */
636 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH))
640 status = CSR_READ_2(sc, STE_ISR_ACK);
642 if (!(status & STE_INTRS))
645 if (status & STE_ISR_RX_DMADONE)
648 if (status & STE_ISR_TX_DMADONE)
651 if (status & STE_ISR_TX_DONE)
654 if (status & STE_ISR_STATS_OFLOW) {
655 callout_stop(&sc->ste_stat_timer);
656 ste_stats_update(sc);
659 if (status & STE_ISR_LINKEVENT)
660 mii_pollstat(device_get_softc(sc->ste_miibus));
662 if (status & STE_ISR_HOSTERR) {
668 /* Re-enable interrupts */
669 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
671 if (!ifq_is_empty(&ifp->if_snd))
678 * A frame has been uploaded: pass the resulting mbuf chain up to
679 * the higher level protocols.
681 static void ste_rxeof(sc)
682 struct ste_softc *sc;
686 struct ste_chain_onefrag *cur_rx;
687 int total_len = 0, count=0;
690 ifp = &sc->arpcom.ac_if;
692 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)
693 & STE_RXSTAT_DMADONE) {
694 if ((STE_RX_LIST_CNT - count) < 3) {
698 cur_rx = sc->ste_cdata.ste_rx_head;
699 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
702 * If an error occurs, update stats, clear the
703 * status word and leave the mbuf cluster in place:
704 * it should simply get re-used next time this descriptor
705 * comes up in the ring.
707 if (rxstat & STE_RXSTAT_FRAME_ERR) {
709 cur_rx->ste_ptr->ste_status = 0;
714 * If there error bit was not set, the upload complete
715 * bit should be set which means we have a valid packet.
716 * If not, something truly strange has happened.
718 if (!(rxstat & STE_RXSTAT_DMADONE)) {
719 printf("ste%d: bad receive status -- packet dropped",
722 cur_rx->ste_ptr->ste_status = 0;
726 /* No errors; receive the packet. */
727 m = cur_rx->ste_mbuf;
728 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
731 * Try to conjure up a new mbuf cluster. If that
732 * fails, it means we have an out of memory condition and
733 * should leave the buffer in place and continue. This will
734 * result in a lost packet, but there's little else we
735 * can do in this situation.
737 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
739 cur_rx->ste_ptr->ste_status = 0;
744 m->m_pkthdr.rcvif = ifp;
745 m->m_pkthdr.len = m->m_len = total_len;
747 (*ifp->if_input)(ifp, m);
749 cur_rx->ste_ptr->ste_status = 0;
756 static void ste_txeoc(sc)
757 struct ste_softc *sc;
762 ifp = &sc->arpcom.ac_if;
764 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
765 STE_TXSTATUS_TXDONE) {
766 if (txstat & STE_TXSTATUS_UNDERRUN ||
767 txstat & STE_TXSTATUS_EXCESSCOLLS ||
768 txstat & STE_TXSTATUS_RECLAIMERR) {
770 printf("ste%d: transmission error: %x\n",
771 sc->ste_unit, txstat);
776 if (txstat & STE_TXSTATUS_UNDERRUN &&
777 sc->ste_tx_thresh < STE_PACKET_SIZE) {
778 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
779 printf("ste%d: tx underrun, increasing tx"
780 " start threshold to %d bytes\n",
781 sc->ste_unit, sc->ste_tx_thresh);
783 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
784 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
785 (STE_PACKET_SIZE >> 4));
788 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
794 static void ste_txeof(sc)
795 struct ste_softc *sc;
797 struct ste_chain *cur_tx = NULL;
801 ifp = &sc->arpcom.ac_if;
803 idx = sc->ste_cdata.ste_tx_cons;
804 while(idx != sc->ste_cdata.ste_tx_prod) {
805 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
807 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
810 if (cur_tx->ste_mbuf != NULL) {
811 m_freem(cur_tx->ste_mbuf);
812 cur_tx->ste_mbuf = NULL;
817 sc->ste_cdata.ste_tx_cnt--;
818 STE_INC(idx, STE_TX_LIST_CNT);
822 sc->ste_cdata.ste_tx_cons = idx;
825 ifp->if_flags &= ~IFF_OACTIVE;
830 static void ste_stats_update(xsc)
833 struct ste_softc *sc;
835 struct mii_data *mii;
841 ifp = &sc->arpcom.ac_if;
842 mii = device_get_softc(sc->ste_miibus);
844 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
845 + CSR_READ_1(sc, STE_MULTI_COLLS)
846 + CSR_READ_1(sc, STE_SINGLE_COLLS);
850 if (mii->mii_media_status & IFM_ACTIVE &&
851 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
854 * we don't get a call-back on re-init so do it
855 * otherwise we get stuck in the wrong link state
857 ste_miibus_statchg(sc->ste_dev);
858 if (!ifq_is_empty(&ifp->if_snd))
863 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc);
871 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
872 * IDs against our list and return a device name if we find a match.
874 static int ste_probe(dev)
881 while(t->ste_name != NULL) {
882 if ((pci_get_vendor(dev) == t->ste_vid) &&
883 (pci_get_device(dev) == t->ste_did)) {
884 device_set_desc(dev, t->ste_name);
894 * Attach the interface. Allocate softc structures, do ifmedia
895 * setup and ethernet/BPF attach.
897 static int ste_attach(dev)
902 struct ste_softc *sc;
904 int unit, error = 0, rid;
908 sc = device_get_softc(dev);
909 unit = device_get_unit(dev);
910 bzero(sc, sizeof(struct ste_softc));
914 * Only use one PHY since this chip reports multiple
915 * Note on the DFE-550 the PHY is at 1 on the DFE-580
916 * it is at 0 & 1. It is rev 0x12.
918 if (pci_get_vendor(dev) == DL_VENDORID &&
919 pci_get_device(dev) == DL_DEVICEID_550TX &&
920 pci_get_revid(dev) == 0x12 )
924 * Handle power management nonsense.
926 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF;
927 if (command == 0x01) {
929 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4);
930 if (command & STE_PSTATE_MASK) {
931 u_int32_t iobase, membase, irq;
933 /* Save important PCI config data. */
934 iobase = pci_read_config(dev, STE_PCI_LOIO, 4);
935 membase = pci_read_config(dev, STE_PCI_LOMEM, 4);
936 irq = pci_read_config(dev, STE_PCI_INTLINE, 4);
938 /* Reset the power state. */
939 printf("ste%d: chip is in D%d power mode "
940 "-- setting to D0\n", unit, command & STE_PSTATE_MASK);
941 command &= 0xFFFFFFFC;
942 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4);
944 /* Restore PCI config data. */
945 pci_write_config(dev, STE_PCI_LOIO, iobase, 4);
946 pci_write_config(dev, STE_PCI_LOMEM, membase, 4);
947 pci_write_config(dev, STE_PCI_INTLINE, irq, 4);
952 * Map control/status registers.
954 command = pci_read_config(dev, PCIR_COMMAND, 4);
955 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
956 pci_write_config(dev, PCIR_COMMAND, command, 4);
957 command = pci_read_config(dev, PCIR_COMMAND, 4);
959 #ifdef STE_USEIOSPACE
960 if (!(command & PCIM_CMD_PORTEN)) {
961 printf("ste%d: failed to enable I/O ports!\n", unit);
966 if (!(command & PCIM_CMD_MEMEN)) {
967 printf("ste%d: failed to enable memory mapping!\n", unit);
974 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid,
975 0, ~0, 1, RF_ACTIVE);
977 if (sc->ste_res == NULL) {
978 printf ("ste%d: couldn't map ports/memory\n", unit);
983 sc->ste_btag = rman_get_bustag(sc->ste_res);
984 sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
987 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
988 RF_SHAREABLE | RF_ACTIVE);
990 if (sc->ste_irq == NULL) {
991 printf("ste%d: couldn't map interrupt\n", unit);
992 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
997 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET,
998 ste_intr, sc, &sc->ste_intrhand);
1001 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1002 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1003 printf("ste%d: couldn't set up irq\n", unit);
1007 callout_init(&sc->ste_stat_timer);
1009 /* Reset the adapter. */
1013 * Get station address from the EEPROM.
1015 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1016 STE_EEADDR_NODE0, 3, 0)) {
1017 printf("ste%d: failed to read station address\n", unit);
1018 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1019 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1020 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1025 sc->ste_unit = unit;
1027 /* Allocate the descriptor queues. */
1028 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
1029 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1031 if (sc->ste_ldata == NULL) {
1032 printf("ste%d: no memory for list buffers!\n", unit);
1033 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1034 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1035 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1040 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1043 if (mii_phy_probe(dev, &sc->ste_miibus,
1044 ste_ifmedia_upd, ste_ifmedia_sts)) {
1045 printf("ste%d: MII without any phy!\n", sc->ste_unit);
1046 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1047 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1048 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1049 contigfree(sc->ste_ldata,
1050 sizeof(struct ste_list_data), M_DEVBUF);
1055 ifp = &sc->arpcom.ac_if;
1057 if_initname(ifp, "ste", unit);
1058 ifp->if_mtu = ETHERMTU;
1059 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1060 ifp->if_ioctl = ste_ioctl;
1061 ifp->if_start = ste_start;
1062 ifp->if_watchdog = ste_watchdog;
1063 ifp->if_init = ste_init;
1064 ifp->if_baudrate = 10000000;
1065 ifq_set_maxlen(&ifp->if_snd, STE_TX_LIST_CNT - 1);
1066 ifq_set_ready(&ifp->if_snd);
1068 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1071 * Call MI attach routine.
1073 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1076 * Tell the upper layer(s) we support long frames.
1078 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1085 static int ste_detach(dev)
1088 struct ste_softc *sc;
1094 sc = device_get_softc(dev);
1095 ifp = &sc->arpcom.ac_if;
1098 ether_ifdetach(ifp);
1100 bus_generic_detach(dev);
1101 device_delete_child(dev, sc->ste_miibus);
1103 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1104 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1105 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1107 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF);
1114 static int ste_newbuf(sc, c, m)
1115 struct ste_softc *sc;
1116 struct ste_chain_onefrag *c;
1119 struct mbuf *m_new = NULL;
1122 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1125 MCLGET(m_new, MB_DONTWAIT);
1126 if (!(m_new->m_flags & M_EXT)) {
1130 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1133 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1134 m_new->m_data = m_new->m_ext.ext_buf;
1137 m_adj(m_new, ETHER_ALIGN);
1139 c->ste_mbuf = m_new;
1140 c->ste_ptr->ste_status = 0;
1141 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
1142 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST;
1147 static int ste_init_rx_list(sc)
1148 struct ste_softc *sc;
1150 struct ste_chain_data *cd;
1151 struct ste_list_data *ld;
1154 cd = &sc->ste_cdata;
1157 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1158 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1159 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
1161 if (i == (STE_RX_LIST_CNT - 1)) {
1162 cd->ste_rx_chain[i].ste_next =
1163 &cd->ste_rx_chain[0];
1164 ld->ste_rx_list[i].ste_next =
1165 vtophys(&ld->ste_rx_list[0]);
1167 cd->ste_rx_chain[i].ste_next =
1168 &cd->ste_rx_chain[i + 1];
1169 ld->ste_rx_list[i].ste_next =
1170 vtophys(&ld->ste_rx_list[i + 1]);
1172 ld->ste_rx_list[i].ste_status = 0;
1175 cd->ste_rx_head = &cd->ste_rx_chain[0];
1180 static void ste_init_tx_list(sc)
1181 struct ste_softc *sc;
1183 struct ste_chain_data *cd;
1184 struct ste_list_data *ld;
1187 cd = &sc->ste_cdata;
1189 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1190 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1191 cd->ste_tx_chain[i].ste_ptr->ste_next = 0;
1192 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0;
1193 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
1194 if (i == (STE_TX_LIST_CNT - 1))
1195 cd->ste_tx_chain[i].ste_next =
1196 &cd->ste_tx_chain[0];
1198 cd->ste_tx_chain[i].ste_next =
1199 &cd->ste_tx_chain[i + 1];
1201 cd->ste_tx_chain[i].ste_prev =
1202 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1];
1204 cd->ste_tx_chain[i].ste_prev =
1205 &cd->ste_tx_chain[i - 1];
1208 cd->ste_tx_prod = 0;
1209 cd->ste_tx_cons = 0;
1215 static void ste_init(xsc)
1218 struct ste_softc *sc;
1221 struct mii_data *mii;
1226 ifp = &sc->arpcom.ac_if;
1227 mii = device_get_softc(sc->ste_miibus);
1231 /* Init our MAC address */
1232 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1233 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1237 if (ste_init_rx_list(sc) == ENOBUFS) {
1238 printf("ste%d: initialization failed: no "
1239 "memory for RX buffers\n", sc->ste_unit);
1245 /* Set RX polling interval */
1246 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1);
1248 /* Init TX descriptors */
1249 ste_init_tx_list(sc);
1251 /* Set the TX freethresh value */
1252 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1254 /* Set the TX start threshold for best performance. */
1255 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1257 /* Set the TX reclaim threshold. */
1258 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1260 /* Set up the RX filter. */
1261 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
1263 /* If we want promiscuous mode, set the allframes bit. */
1264 if (ifp->if_flags & IFF_PROMISC) {
1265 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1267 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1270 /* Set capture broadcast bit to accept broadcast frames. */
1271 if (ifp->if_flags & IFF_BROADCAST) {
1272 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1274 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1279 /* Load the address of the RX list. */
1280 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1282 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1283 vtophys(&sc->ste_ldata->ste_rx_list[0]));
1284 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1285 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1287 /* Set TX polling interval (defer until we TX first packet */
1288 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1290 /* Load address of the TX list */
1291 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1293 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1294 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1295 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1297 sc->ste_tx_prev_idx=-1;
1299 /* Enable receiver and transmitter */
1300 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1301 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1302 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1303 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1305 /* Enable stats counters. */
1306 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1308 /* Enable interrupts. */
1309 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1310 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1312 /* Accept VLAN length packets */
1313 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN);
1315 ste_ifmedia_upd(ifp);
1317 ifp->if_flags |= IFF_RUNNING;
1318 ifp->if_flags &= ~IFF_OACTIVE;
1322 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc);
1327 static void ste_stop(sc)
1328 struct ste_softc *sc;
1333 ifp = &sc->arpcom.ac_if;
1335 callout_stop(&sc->ste_stat_timer);
1337 CSR_WRITE_2(sc, STE_IMR, 0);
1338 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
1339 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
1340 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
1341 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1342 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1345 * Try really hard to stop the RX engine or under heavy RX
1346 * data chip will write into de-allocated memory.
1352 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1353 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
1354 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
1355 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
1359 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1360 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
1361 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
1362 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
1366 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1368 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1373 static void ste_reset(sc)
1374 struct ste_softc *sc;
1378 STE_SETBIT4(sc, STE_ASICCTL,
1379 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
1380 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
1381 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
1382 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
1383 STE_ASICCTL_EXTRESET_RESET);
1387 for (i = 0; i < STE_TIMEOUT; i++) {
1388 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1392 if (i == STE_TIMEOUT)
1393 printf("ste%d: global reset never completed\n", sc->ste_unit);
1398 static int ste_ioctl(ifp, command, data, cr)
1404 struct ste_softc *sc;
1406 struct mii_data *mii;
1412 ifr = (struct ifreq *)data;
1418 error = ether_ioctl(ifp, command, data);
1421 if (ifp->if_flags & IFF_UP) {
1422 if (ifp->if_flags & IFF_RUNNING &&
1423 ifp->if_flags & IFF_PROMISC &&
1424 !(sc->ste_if_flags & IFF_PROMISC)) {
1425 STE_SETBIT1(sc, STE_RX_MODE,
1426 STE_RXMODE_PROMISC);
1427 } else if (ifp->if_flags & IFF_RUNNING &&
1428 !(ifp->if_flags & IFF_PROMISC) &&
1429 sc->ste_if_flags & IFF_PROMISC) {
1430 STE_CLRBIT1(sc, STE_RX_MODE,
1431 STE_RXMODE_PROMISC);
1433 if (!(ifp->if_flags & IFF_RUNNING)) {
1434 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1438 if (ifp->if_flags & IFF_RUNNING)
1441 sc->ste_if_flags = ifp->if_flags;
1451 mii = device_get_softc(sc->ste_miibus);
1452 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1464 static int ste_encap(sc, c, m_head)
1465 struct ste_softc *sc;
1466 struct ste_chain *c;
1467 struct mbuf *m_head;
1470 struct ste_frag *f = NULL;
1479 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1480 if (m->m_len != 0) {
1481 if (frag == STE_MAXFRAGS)
1483 total_len += m->m_len;
1484 f = &d->ste_frags[frag];
1485 f->ste_addr = vtophys(mtod(m, vm_offset_t));
1486 f->ste_len = m->m_len;
1495 * We ran out of segments. We have to recopy this
1496 * mbuf chain first. Bail out if we can't get the
1497 * new buffers. Code borrowed from if_fxp.c.
1499 MGETHDR(mn, MB_DONTWAIT, MT_DATA);
1504 if (m_head->m_pkthdr.len > MHLEN) {
1505 MCLGET(mn, MB_DONTWAIT);
1506 if ((mn->m_flags & M_EXT) == 0) {
1512 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1514 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len;
1520 c->ste_mbuf = m_head;
1521 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
1527 static void ste_start(ifp)
1530 struct ste_softc *sc;
1531 struct mbuf *m_head = NULL;
1532 struct ste_chain *cur_tx = NULL;
1540 if (ifp->if_flags & IFF_OACTIVE)
1543 idx = sc->ste_cdata.ste_tx_prod;
1545 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
1547 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) {
1548 ifp->if_flags |= IFF_OACTIVE;
1552 m_head = ifq_dequeue(&ifp->if_snd);
1556 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
1558 if (ste_encap(sc, cur_tx, m_head) != 0)
1561 cur_tx->ste_ptr->ste_next = 0;
1563 if(sc->ste_tx_prev_idx < 0){
1564 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1565 /* Load address of the TX list */
1566 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1569 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1570 vtophys(&sc->ste_ldata->ste_tx_list[0]));
1572 /* Set TX polling interval to start TX engine */
1573 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1575 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1578 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1579 sc->ste_cdata.ste_tx_chain[
1580 sc->ste_tx_prev_idx].ste_ptr->ste_next
1584 sc->ste_tx_prev_idx=idx;
1586 BPF_MTAP(ifp, cur_tx->ste_mbuf);
1588 STE_INC(idx, STE_TX_LIST_CNT);
1589 sc->ste_cdata.ste_tx_cnt++;
1591 sc->ste_cdata.ste_tx_prod = idx;
1597 static void ste_watchdog(ifp)
1600 struct ste_softc *sc;
1605 printf("ste%d: watchdog timeout\n", sc->ste_unit);
1613 if (!ifq_is_empty(&ifp->if_snd))
1619 static void ste_shutdown(dev)
1622 struct ste_softc *sc;
1624 sc = device_get_softc(dev);