2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar9285_reset.c 203930 2010-02-15 17:49:49Z rpaulo $
22 * This is almost the same as ar5416_reset.c but uses the v4k EEPROM and
23 * supports only 2Ghz operation.
29 #include "ah_internal.h"
32 #include "ah_eeprom_v14.h"
33 #include "ah_eeprom_v4k.h"
35 #include "ar5416/ar9285.h"
36 #include "ar5416/ar5416.h"
37 #include "ar5416/ar5416reg.h"
38 #include "ar5416/ar5416phy.h"
40 /* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */
41 #define EEP_MINOR(_ah) \
42 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
43 #define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2)
44 #define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3)
46 /* Additional Time delay to wait after activiting the Base band */
47 #define BASE_ACTIVATE_DELAY 100 /* 100 usec */
48 #define PLL_SETTLE_DELAY 300 /* 300 usec */
49 #define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */
51 static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah,
52 struct ar5416eeprom_4k *pEepData,
53 const struct ieee80211_channel *chan, int16_t *ratesArray,
54 uint16_t cfgCtl, uint16_t AntennaReduction,
55 uint16_t twiceMaxRegulatoryPower,
57 static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah,
58 struct ar5416eeprom_4k *pEepData,
59 const struct ieee80211_channel *chan,
60 int16_t *pTxPowerIndexOffset);
61 static int16_t interpolate(uint16_t target, uint16_t srcLeft,
62 uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
63 static HAL_BOOL ar9285FillVpdTable(uint8_t, uint8_t, uint8_t *, uint8_t *,
65 static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah,
66 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet,
67 uint8_t * bChans, uint16_t availPiers,
68 uint16_t tPdGainOverlap, int16_t *pMinCalPower,
69 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues,
70 uint16_t numXpdGains);
71 static HAL_BOOL getLowerUpperIndex(uint8_t target, uint8_t *pList,
72 uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
73 static uint16_t ar9285GetMaxEdgePower(uint16_t, CAL_CTL_EDGES *);
75 /* XXX gag, this is sick */
76 typedef enum Ar5416_Rates {
77 rate6mb, rate9mb, rate12mb, rate18mb,
78 rate24mb, rate36mb, rate48mb, rate54mb,
79 rate1l, rate2l, rate2s, rate5_5l,
80 rate5_5s, rate11l, rate11s, rateXr,
81 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
82 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
83 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
84 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
85 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
90 ar9285SetTransmitPower(struct ath_hal *ah,
91 const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
93 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
94 #define N(a) (sizeof (a) / sizeof (a[0]))
96 MODAL_EEP4K_HEADER *pModal;
97 struct ath_hal_5212 *ahp = AH5212(ah);
98 int16_t ratesArray[Ar5416RateSize];
99 int16_t txPowerIndexOffset = 0;
100 uint8_t ht40PowerIncForPdadc = 2;
105 uint16_t twiceAntennaReduction;
106 uint16_t twiceMaxRegulatoryPower;
108 HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
109 struct ar5416eeprom_4k *pEepData = &ee->ee_base;
111 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
113 /* Setup info for the actual eeprom */
114 OS_MEMZERO(ratesArray, sizeof(ratesArray));
115 cfgCtl = ath_hal_getctl(ah, chan);
116 powerLimit = chan->ic_maxregpower * 2;
117 twiceAntennaReduction = chan->ic_maxantgain;
118 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
119 pModal = &pEepData->modalHeader;
120 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
121 __func__,chan->ic_freq, cfgCtl );
123 if (IS_EEP_MINOR_V2(ah)) {
124 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
127 if (!ar9285SetPowerPerRateTable(ah, pEepData, chan,
128 &ratesArray[0],cfgCtl,
129 twiceAntennaReduction,
130 twiceMaxRegulatoryPower, powerLimit)) {
131 HALDEBUG(ah, HAL_DEBUG_ANY,
132 "%s: unable to set tx power per rate table\n", __func__);
136 if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) {
137 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
142 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]);
143 maxPower = AH_MAX(maxPower, ratesArray[rate1l]);
145 if (IEEE80211_IS_CHAN_HT40(chan)) {
146 maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]);
149 ahp->ah_tx6PowerInHalfDbm = maxPower;
150 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;
151 ahp->ah_txPowerIndexOffset = txPowerIndexOffset;
154 * txPowerIndexOffset is set by the SetPowerTable() call -
155 * adjust the rate table (0 offset if rates EEPROM not loaded)
157 for (i = 0; i < N(ratesArray); i++) {
158 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
159 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
160 ratesArray[i] = AR5416_MAX_RATE_POWER;
161 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
164 #ifdef AH_EEPROM_DUMP
165 ar5416PrintPowerPerRate(ah, ratesArray);
168 /* Write the OFDM power per rate set */
169 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
170 POW_SM(ratesArray[rate18mb], 24)
171 | POW_SM(ratesArray[rate12mb], 16)
172 | POW_SM(ratesArray[rate9mb], 8)
173 | POW_SM(ratesArray[rate6mb], 0)
175 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
176 POW_SM(ratesArray[rate54mb], 24)
177 | POW_SM(ratesArray[rate48mb], 16)
178 | POW_SM(ratesArray[rate36mb], 8)
179 | POW_SM(ratesArray[rate24mb], 0)
182 /* Write the CCK power per rate set */
183 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
184 POW_SM(ratesArray[rate2s], 24)
185 | POW_SM(ratesArray[rate2l], 16)
186 | POW_SM(ratesArray[rateXr], 8) /* XR target power */
187 | POW_SM(ratesArray[rate1l], 0)
189 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
190 POW_SM(ratesArray[rate11s], 24)
191 | POW_SM(ratesArray[rate11l], 16)
192 | POW_SM(ratesArray[rate5_5s], 8)
193 | POW_SM(ratesArray[rate5_5l], 0)
195 HALDEBUG(ah, HAL_DEBUG_RESET,
196 "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n",
197 __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3),
198 OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4));
200 /* Write the HT20 power per rate set */
201 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
202 POW_SM(ratesArray[rateHt20_3], 24)
203 | POW_SM(ratesArray[rateHt20_2], 16)
204 | POW_SM(ratesArray[rateHt20_1], 8)
205 | POW_SM(ratesArray[rateHt20_0], 0)
207 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
208 POW_SM(ratesArray[rateHt20_7], 24)
209 | POW_SM(ratesArray[rateHt20_6], 16)
210 | POW_SM(ratesArray[rateHt20_5], 8)
211 | POW_SM(ratesArray[rateHt20_4], 0)
214 if (IEEE80211_IS_CHAN_HT40(chan)) {
215 /* Write the HT40 power per rate set */
216 /* Correct PAR difference between HT40 and HT20/LEGACY */
217 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
218 POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24)
219 | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16)
220 | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8)
221 | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0)
223 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
224 POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24)
225 | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16)
226 | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8)
227 | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0)
229 /* Write the Dup/Ext 40 power per rate set */
230 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
231 POW_SM(ratesArray[rateExtOfdm], 24)
232 | POW_SM(ratesArray[rateExtCck], 16)
233 | POW_SM(ratesArray[rateDupOfdm], 8)
234 | POW_SM(ratesArray[rateDupCck], 0)
244 ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
246 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
247 const struct ar5416eeprom_4k *eep = &ee->ee_base;
248 const MODAL_EEP4K_HEADER *pModal;
249 uint8_t txRxAttenLocal = 23;
251 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
252 pModal = &eep->modalHeader;
254 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
255 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, pModal->antCtrlChain[0]);
256 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4,
257 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) &
258 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
259 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
260 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
262 if (IS_EEP_MINOR_V3(ah)) {
263 if (IEEE80211_IS_CHAN_HT40(chan)) {
264 /* Overwrite switch settling with HT40 value */
265 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
266 pModal->swSettleHt40);
268 txRxAttenLocal = pModal->txRxAttenCh[0];
270 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
271 pModal->bswMargin[0]);
272 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
273 pModal->bswAtten[0]);
274 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
275 pModal->xatten2Margin[0]);
276 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
277 pModal->xatten2Db[0]);
279 /* block 1 has the same values as block 0 */
280 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
281 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
282 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
283 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
284 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
285 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, pModal->xatten2Margin[0]);
286 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
287 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
290 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
291 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
292 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
293 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
295 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
296 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
297 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
298 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
300 if (AR_SREV_KITE_11(ah))
301 OS_REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
307 * Helper functions common for AP/CB/XB
311 ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData,
312 const struct ieee80211_channel *chan,
313 int16_t *ratesArray, uint16_t cfgCtl,
314 uint16_t AntennaReduction,
315 uint16_t twiceMaxRegulatoryPower,
318 #define N(a) (sizeof(a)/sizeof(a[0]))
319 /* Local defines to distinguish between extension and control CTL's */
320 #define EXT_ADDITIVE (0x8000)
321 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
322 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
324 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
326 int16_t twiceLargestAntenna;
327 CAL_CTL_DATA_4K *rep;
328 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}};
329 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}};
330 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}};
331 int16_t scaledPower, minCtlPower;
333 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
334 static const uint16_t ctlModesFor11g[] = {
335 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
337 const uint16_t *pCtlMode;
338 uint16_t numCtlModes, ctlMode, freq;
339 CHAN_CENTERS centers;
341 ar5416GetChannelCenters(ah, chan, ¢ers);
343 /* Compute TxPower reduction due to Antenna Gain */
345 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
346 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0);
348 /* XXX setup for 5212 use (really used?) */
349 ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna);
352 * scaledPower is the minimum of the user input power level and
353 * the regulatory allowed power level
355 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna);
357 /* Get target powers from EEPROM - our baseline for TX Power */
358 /* Setup for CTL modes */
359 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */
360 pCtlMode = ctlModesFor11g;
362 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
363 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE);
364 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
365 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
366 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20,
367 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
369 if (IEEE80211_IS_CHAN_HT40(chan)) {
370 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */
372 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40,
373 AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE);
374 /* Get target powers for extension channels */
375 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
376 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE);
377 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
378 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE);
382 * For MIMO, need to apply regulatory caps individually across dynamically
383 * running modes: CCK, OFDM, HT20, HT40
385 * The outer loop walks through each possible applicable runtime mode.
386 * The inner loop walks through each ctlIndex entry in EEPROM.
387 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
390 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
391 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
392 (pCtlMode[ctlMode] == CTL_2GHT40);
394 freq = centers.ctl_center;
395 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) {
396 freq = centers.ext_center;
398 freq = centers.ctl_center;
401 /* walk through each CTL index stored in EEPROM */
402 for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
403 uint16_t twiceMinEdgePower;
405 /* compare test group from regulatory channel list with test mode from pCtlMode list */
406 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) ||
407 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) ==
408 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
409 rep = &(pEepData->ctlData[i]);
410 twiceMinEdgePower = ar9285GetMaxEdgePower(freq,
412 owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1]);
413 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
414 /* Find the minimum of all CTL edge powers that apply to this channel */
415 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
418 twiceMaxEdgePower = twiceMinEdgePower;
423 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower);
424 /* Apply ctl mode to correct target power set */
425 switch(pCtlMode[ctlMode]) {
427 for (i = 0; i < N(targetPowerCck.tPow2x); i++) {
428 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower);
433 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) {
434 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower);
439 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) {
440 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower);
444 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower);
447 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower);
451 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) {
452 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower);
459 } /* end ctl mode checking */
461 /* Set rates Array from collected data */
462 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
463 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
464 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
465 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
466 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
468 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) {
469 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
472 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
473 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
474 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
475 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
476 if (IEEE80211_IS_CHAN_HT40(chan)) {
477 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) {
478 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
480 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
481 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
482 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
483 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
484 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
491 #undef SUB_NUM_CTL_MODES_AT_2G_40
495 /**************************************************************************
498 * Get channel value from binary representation held in eeprom
499 * RETURNS: the frequency in MHz
502 fbin2freq(uint8_t fbin)
505 * Reserved value 0xFF provides an empty definition both as
506 * an fbin and as a frequency - do not convert
508 if (fbin == AR5416_BCHAN_UNUSED) {
512 return (uint16_t)(2300 + fbin);
516 * XXX almost the same as ar5416GetMaxEdgePower.
519 ar9285GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower)
521 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
524 /* Get the edge power */
525 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) {
527 * If there's an exact channel match or an inband flag set
528 * on the lower channel use the given rdEdgePower
530 if (freq == fbin2freq(pRdEdgesPower[i].bChannel)) {
531 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER);
533 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel))) {
534 if (fbin2freq(pRdEdgesPower[i - 1].bChannel) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) {
535 twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER);
537 /* Leave loop - no more affecting edges possible in this monotonic increasing list */
541 HALASSERT(twiceMaxEdgePower > 0);
542 return twiceMaxEdgePower;
548 ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData,
549 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
551 CAL_DATA_PER_FREQ_4K *pRawDataset;
552 uint8_t *pCalBChans = AH_NULL;
553 uint16_t pdGainOverlap_t2;
554 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
555 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
556 uint16_t numPiers, i, j;
557 int16_t tMinCalPower;
558 uint16_t numXpdGain, xpdMask;
559 uint16_t xpdGainValues[AR5416_4K_NUM_PD_GAINS];
560 uint32_t reg32, regOffset, regChainOffset;
562 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues));
564 xpdMask = pEepData->modalHeader.xpdGain;
566 if (IS_EEP_MINOR_V2(ah)) {
567 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
569 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
572 pCalBChans = pEepData->calFreqPier2G;
573 numPiers = AR5416_4K_NUM_2G_CAL_PIERS;
575 /* Calculate the value of xpdgains from the xpdGain Mask */
576 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
577 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
578 if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) {
582 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i);
587 /* Write the detector gain biases and their number */
588 OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) &
589 ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) |
590 SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) |
591 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(0, AR_PHY_TPCRG1_PD_GAIN_3));
593 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
595 if (AR_SREV_OWL_20_OR_LATER(ah) &&
596 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) {
597 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with
598 * only chains 0 and 2 populated
600 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
602 regChainOffset = i * 0x1000;
605 if (pEepData->baseEepHeader.txMask & (1 << i)) {
606 pRawDataset = pEepData->calPierData2G[i];
608 ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,
609 pCalBChans, numPiers,
611 &tMinCalPower, gainBoundaries,
612 pdadcValues, numXpdGain);
614 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
616 * Note the pdadc table may not start at 0 dBm power, could be
617 * negative or greater than 0. Need to offset the power
618 * values by the amount of minPower for griffin
621 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
622 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
623 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
624 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
625 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
626 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
629 /* Write the power values into the baseband power table */
630 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
632 for (j = 0; j < 32; j++) {
633 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) |
634 ((pdadcValues[4*j + 1] & 0xFF) << 8) |
635 ((pdadcValues[4*j + 2] & 0xFF) << 16) |
636 ((pdadcValues[4*j + 3] & 0xFF) << 24) ;
637 OS_REG_WRITE(ah, regOffset, reg32);
640 ath_hal_printf(ah, "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n",
642 4*j, pdadcValues[4*j],
643 4*j+1, pdadcValues[4*j + 1],
644 4*j+2, pdadcValues[4*j + 2],
645 4*j+3, pdadcValues[4*j + 3]);
651 *pTxPowerIndexOffset = 0;
657 ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah,
658 const struct ieee80211_channel *chan,
659 CAL_DATA_PER_FREQ_4K *pRawDataSet,
660 uint8_t * bChans, uint16_t availPiers,
661 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries,
662 uint8_t * pPDADCValues, uint16_t numXpdGains)
666 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */
667 uint16_t idxL, idxR, numPiers; /* Pier indexes */
669 /* filled out Vpd table for all pdGains (chanL) */
670 static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
672 /* filled out Vpd table for all pdGains (chanR) */
673 static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
675 /* filled out Vpd table for all pdGains (interpolated) */
676 static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
678 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR;
679 uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS];
680 uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS];
683 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex;
685 int16_t minDelta = 0;
686 CHAN_CENTERS centers;
688 ar5416GetChannelCenters(ah, chan, ¢ers);
690 /* Trim numPiers for the number of populated channel Piers */
691 for (numPiers = 0; numPiers < availPiers; numPiers++) {
692 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) {
697 /* Find pier indexes around the current channel */
698 match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
699 bChans, numPiers, &idxL, &idxR);
702 /* Directly fill both vpd tables from the matching index */
703 for (i = 0; i < numXpdGains; i++) {
704 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
705 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
706 ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i],
707 pRawDataSet[idxL].pwrPdg[i],
708 pRawDataSet[idxL].vpdPdg[i],
709 AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
712 for (i = 0; i < numXpdGains; i++) {
713 pVpdL = pRawDataSet[idxL].vpdPdg[i];
714 pPwrL = pRawDataSet[idxL].pwrPdg[i];
715 pVpdR = pRawDataSet[idxR].vpdPdg[i];
716 pPwrR = pRawDataSet[idxR].pwrPdg[i];
718 /* Start Vpd interpolation from the max of the minimum powers */
719 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]);
721 /* End Vpd interpolation from the min of the max powers */
722 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
723 HALASSERT(maxPwrT4[i] > minPwrT4[i]);
726 ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL,
727 AR5416_PD_GAIN_ICEPTS, vpdTableL[i]);
728 ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR,
729 AR5416_PD_GAIN_ICEPTS, vpdTableR[i]);
731 /* Interpolate the final vpd */
732 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
733 vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
734 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j]));
738 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
740 k = 0; /* index for the final table */
741 for (i = 0; i < numXpdGains; i++) {
742 if (i == (numXpdGains - 1)) {
743 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2);
745 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
748 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
750 /* NB: only applies to owl 1.0 */
751 if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) {
753 * fix the gain delta, but get a delta that can be applied to min to
754 * keep the upper power values accurate, don't think max needs to
755 * be adjusted because should not be at that area of the table?
757 minDelta = pPdGainBoundaries[0] - 23;
758 pPdGainBoundaries[0] = 23;
764 /* Find starting index for this pdGain */
766 ss = 0; /* for the first pdGain, start from index 0 */
768 /* need overlap entries extrapolated below. */
769 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta);
771 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
772 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
774 *-ve ss indicates need to extrapolate data below for this pdGain
776 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
777 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
778 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal);
782 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1);
783 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2));
784 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
786 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
787 pPDADCValues[k++] = vpdTableI[i][ss++];
790 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]);
791 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
793 * for last gain, pdGainBoundary == Pmax_t2, so will
794 * have to extrapolate
796 if (tgtIndex >= maxIndex) { /* need to extrapolate above */
797 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
798 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
799 (ss - maxIndex +1) * vpdStep));
800 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal);
803 } /* extrapolated above */
804 } /* for all pdGainUsed */
806 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */
807 while (i < AR5416_PD_GAINS_IN_MASK) {
808 pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
812 while (k < AR5416_NUM_PDADC_VALUES) {
813 pPDADCValues[k] = pPDADCValues[k-1];
819 * XXX same as ar5416FillVpdTable
822 ar9285FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList,
823 uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList)
826 uint8_t currPwr = pwrMin;
829 HALASSERT(pwrMax > pwrMin);
830 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
831 getLowerUpperIndex(currPwr, pPwrList, numIntercepts,
834 idxR = 1; /* extrapolate below */
835 if (idxL == numIntercepts - 1)
836 idxL = (uint16_t)(numIntercepts - 2); /* extrapolate above */
837 if (pPwrList[idxL] == pPwrList[idxR])
840 k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
841 (pPwrList[idxR] - pPwrList[idxL]) );
843 pRetVpdList[i] = (uint8_t)k;
844 currPwr += 2; /* half dB steps */
850 interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
851 int16_t targetLeft, int16_t targetRight)
855 if (srcRight == srcLeft) {
858 rv = (int16_t)( ((target - srcLeft) * targetRight +
859 (srcRight - target) * targetLeft) / (srcRight - srcLeft) );
865 getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize,
866 uint16_t *indexL, uint16_t *indexR)
871 * Check first and last elements for beyond ordered array cases.
873 if (target <= pList[0]) {
874 *indexL = *indexR = 0;
877 if (target >= pList[listSize-1]) {
878 *indexL = *indexR = (uint16_t)(listSize - 1);
882 /* look for value being near or between 2 values in list */
883 for (i = 0; i < listSize - 1; i++) {
885 * If value is close to the current value of the list
886 * then target is not between values, it is one of the values
888 if (pList[i] == target) {
889 *indexL = *indexR = i;
893 * Look for value being between current value and next value
894 * if so return these 2 values
896 if (target < pList[i + 1]) {
898 *indexR = (uint16_t)(i + 1);
903 *indexL = *indexR = 0;