2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <drm/i915_drm.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_rect.h>
39 #include <drm/drm_atomic.h>
42 * _wait_for - magic (register) wait macro
44 * Does the right thing for modeset paths when run under kdgb or similar atomic
45 * contexts. Note that it's important that we check the condition again after
46 * having timed out, since the timeout could be due to preemption or similar and
47 * we've never had a chance to check the condition before the timeout.
49 * TODO: When modesetting has fully transitioned to atomic, the below
50 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
53 #define _wait_for(COND, US, W) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
57 if (time_after(jiffies, timeout__)) { \
62 if ((W) && drm_can_sleep()) { \
63 usleep_range((W), (W)*2); \
71 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
73 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
74 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
75 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
77 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
80 #define _wait_for_atomic(COND, US, ATOMIC) \
82 int cpu, ret, timeout = (US) * 1000; \
84 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
85 BUILD_BUG_ON((US) > 50000); \
88 cpu = smp_processor_id(); \
90 base = local_clock(); \
92 u64 now = local_clock(); \
99 if (now - base >= timeout) { \
106 if (unlikely(cpu != smp_processor_id())) { \
107 timeout -= now - base; \
108 cpu = smp_processor_id(); \
109 base = local_clock(); \
116 #define wait_for_us(COND, US) \
119 BUILD_BUG_ON(!__builtin_constant_p(US)); \
121 ret__ = _wait_for((COND), (US), 10); \
123 ret__ = _wait_for_atomic((COND), (US), 0); \
127 #define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1)
128 #define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1)
130 #define KHz(x) (1000 * (x))
131 #define MHz(x) KHz(1000 * (x))
134 * Display related stuff
137 /* store information about an Ixxx DVO */
138 /* The i830->i865 use multiple DVOs with multiple i2cs */
139 /* the i915, i945 have a single sDVO i2c bus - which is different */
140 #define MAX_OUTPUTS 6
141 /* maximum connectors per crtcs in the mode set */
143 /* Maximum cursor sizes */
144 #define GEN2_CURSOR_WIDTH 64
145 #define GEN2_CURSOR_HEIGHT 64
146 #define MAX_CURSOR_WIDTH 256
147 #define MAX_CURSOR_HEIGHT 256
149 #define INTEL_I2C_BUS_DVO 1
150 #define INTEL_I2C_BUS_SDVO 2
152 /* these are outputs from the chip - integrated only
153 external chips are via DVO or SDVO output */
154 enum intel_output_type {
155 INTEL_OUTPUT_UNUSED = 0,
156 INTEL_OUTPUT_ANALOG = 1,
157 INTEL_OUTPUT_DVO = 2,
158 INTEL_OUTPUT_SDVO = 3,
159 INTEL_OUTPUT_LVDS = 4,
160 INTEL_OUTPUT_TVOUT = 5,
161 INTEL_OUTPUT_HDMI = 6,
163 INTEL_OUTPUT_EDP = 8,
164 INTEL_OUTPUT_DSI = 9,
165 INTEL_OUTPUT_UNKNOWN = 10,
166 INTEL_OUTPUT_DP_MST = 11,
169 #define INTEL_DVO_CHIP_NONE 0
170 #define INTEL_DVO_CHIP_LVDS 1
171 #define INTEL_DVO_CHIP_TMDS 2
172 #define INTEL_DVO_CHIP_TVOUT 4
174 #define INTEL_DSI_VIDEO_MODE 0
175 #define INTEL_DSI_COMMAND_MODE 1
177 struct intel_framebuffer {
178 struct drm_framebuffer base;
179 struct drm_i915_gem_object *obj;
180 struct intel_rotation_info rot_info;
184 struct drm_fb_helper helper;
185 struct intel_framebuffer *fb;
186 async_cookie_t cookie;
190 struct intel_encoder {
191 struct drm_encoder base;
193 enum intel_output_type type;
194 unsigned int cloneable;
195 void (*hot_plug)(struct intel_encoder *);
196 bool (*compute_config)(struct intel_encoder *,
197 struct intel_crtc_state *);
198 void (*pre_pll_enable)(struct intel_encoder *);
199 void (*pre_enable)(struct intel_encoder *);
200 void (*enable)(struct intel_encoder *);
201 void (*mode_set)(struct intel_encoder *intel_encoder);
202 void (*disable)(struct intel_encoder *);
203 void (*post_disable)(struct intel_encoder *);
204 void (*post_pll_disable)(struct intel_encoder *);
205 /* Read out the current hw state of this connector, returning true if
206 * the encoder is active. If the encoder is enabled it also set the pipe
207 * it is connected to in the pipe parameter. */
208 bool (*get_hw_state)(struct intel_encoder *, enum i915_pipe *pipe);
209 /* Reconstructs the equivalent mode flags for the current hardware
210 * state. This must be called _after_ display->get_pipe_config has
211 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
212 * be set correctly before calling this function. */
213 void (*get_config)(struct intel_encoder *,
214 struct intel_crtc_state *pipe_config);
216 * Called during system suspend after all pending requests for the
217 * encoder are flushed (for example for DP AUX transactions) and
218 * device interrupts are disabled.
220 void (*suspend)(struct intel_encoder *);
222 enum hpd_pin hpd_pin;
226 struct drm_display_mode *fixed_mode;
227 struct drm_display_mode *downclock_mode;
237 bool combination_mode; /* gen 2/4 only */
239 bool alternate_pwm_increment; /* lpt+ */
242 bool util_pin_active_low; /* bxt+ */
243 u8 controller; /* bxt+ only */
244 struct pwm_device *pwm;
246 struct backlight_device *device;
248 /* Connector and platform specific backlight functions */
249 int (*setup)(struct intel_connector *connector, enum i915_pipe pipe);
250 uint32_t (*get)(struct intel_connector *connector);
251 void (*set)(struct intel_connector *connector, uint32_t level);
252 void (*disable)(struct intel_connector *connector);
253 void (*enable)(struct intel_connector *connector);
254 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
256 void (*power)(struct intel_connector *, bool enable);
260 struct intel_connector {
261 struct drm_connector base;
263 * The fixed encoder this connector is connected to.
265 struct intel_encoder *encoder;
267 /* Reads out the current hw, returning true if the connector is enabled
268 * and active (i.e. dpms ON state). */
269 bool (*get_hw_state)(struct intel_connector *);
271 /* Panel info for eDP and LVDS */
272 struct intel_panel panel;
274 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
276 struct edid *detect_edid;
278 /* since POLL and HPD connectors may use the same HPD line keep the native
279 state of connector->polled in case hotplug storm detection changes it */
282 void *port; /* store this opaque as its illegal to dereference it */
284 struct intel_dp *mst_port;
299 struct intel_atomic_state {
300 struct drm_atomic_state base;
305 * Calculated device cdclk, can be different from cdclk
306 * only when all crtc's are DPMS off.
308 unsigned int dev_cdclk;
310 bool dpll_set, modeset;
313 * Does this transaction change the pipes that are active? This mask
314 * tracks which CRTC's have changed their active state at the end of
315 * the transaction (not counting the temporary disable during modesets).
316 * This mask should only be non-zero when intel_state->modeset is true,
317 * but the converse is not necessarily true; simply changing a mode may
318 * not flip the final active status of any CRTC's
320 unsigned int active_pipe_changes;
322 unsigned int active_crtcs;
323 unsigned int min_pixclk[I915_MAX_PIPES];
326 unsigned int cdclk_pll_vco;
328 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
331 * Current watermarks can't be trusted during hardware readout, so
332 * don't bother calculating intermediate watermarks.
334 bool skip_intermediate_wm;
337 struct skl_wm_values wm_results;
340 struct intel_plane_state {
341 struct drm_plane_state base;
344 struct drm_rect clip;
349 * = -1 : not using a scaler
350 * >= 0 : using a scalers
352 * plane requiring a scaler:
353 * - During check_plane, its bit is set in
354 * crtc_state->scaler_state.scaler_users by calling helper function
355 * update_scaler_plane.
356 * - scaler_id indicates the scaler it got assigned.
358 * plane doesn't require a scaler:
359 * - this can happen when scaling is no more required or plane simply
361 * - During check_plane, corresponding bit is reset in
362 * crtc_state->scaler_state.scaler_users by calling helper function
363 * update_scaler_plane.
367 struct drm_intel_sprite_colorkey ckey;
369 /* async flip related structures */
370 struct drm_i915_gem_request *wait_req;
373 struct intel_initial_plane_config {
374 struct intel_framebuffer *fb;
380 #define SKL_MIN_SRC_W 8
381 #define SKL_MAX_SRC_W 4096
382 #define SKL_MIN_SRC_H 8
383 #define SKL_MAX_SRC_H 4096
384 #define SKL_MIN_DST_W 8
385 #define SKL_MAX_DST_W 4096
386 #define SKL_MIN_DST_H 8
387 #define SKL_MAX_DST_H 4096
389 struct intel_scaler {
394 struct intel_crtc_scaler_state {
395 #define SKL_NUM_SCALERS 2
396 struct intel_scaler scalers[SKL_NUM_SCALERS];
399 * scaler_users: keeps track of users requesting scalers on this crtc.
401 * If a bit is set, a user is using a scaler.
402 * Here user can be a plane or crtc as defined below:
403 * bits 0-30 - plane (bit position is index from drm_plane_index)
406 * Instead of creating a new index to cover planes and crtc, using
407 * existing drm_plane_index for planes which is well less than 31
408 * planes and bit 31 for crtc. This should be fine to cover all
411 * intel_atomic_setup_scalers will setup available scalers to users
412 * requesting scalers. It will gracefully fail if request exceeds
415 #define SKL_CRTC_INDEX 31
416 unsigned scaler_users;
418 /* scaler used by crtc for panel fitting purpose */
422 /* drm_mode->private_flags */
423 #define I915_MODE_FLAG_INHERITED 1
425 struct intel_pipe_wm {
426 struct intel_wm_level wm[5];
427 struct intel_wm_level raw_wm[5];
431 bool sprites_enabled;
436 struct skl_wm_level wm[8];
437 struct skl_wm_level trans_wm;
441 struct intel_crtc_wm_state {
445 * Intermediate watermarks; these can be
446 * programmed immediately since they satisfy
447 * both the current configuration we're
448 * switching away from and the new
449 * configuration we're switching to.
451 struct intel_pipe_wm intermediate;
454 * Optimal watermarks, programmed post-vblank
455 * when this state is committed.
457 struct intel_pipe_wm optimal;
461 /* gen9+ only needs 1-step wm programming */
462 struct skl_pipe_wm optimal;
464 /* cached plane data rate */
465 unsigned plane_data_rate[I915_MAX_PLANES];
466 unsigned plane_y_data_rate[I915_MAX_PLANES];
468 /* minimum block allocation */
469 uint16_t minimum_blocks[I915_MAX_PLANES];
470 uint16_t minimum_y_blocks[I915_MAX_PLANES];
475 * Platforms with two-step watermark programming will need to
476 * update watermark programming post-vblank to switch from the
477 * safe intermediate watermarks to the optimal final
480 bool need_postvbl_update;
483 struct intel_crtc_state {
484 struct drm_crtc_state base;
487 * quirks - bitfield with hw state readout quirks
489 * For various reasons the hw state readout code might not be able to
490 * completely faithfully read out the current state. These cases are
491 * tracked with quirk flags so that fastboot and state checker can act
494 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
495 unsigned long quirks;
497 unsigned fb_bits; /* framebuffers to flip */
498 bool update_pipe; /* can a fast modeset be performed? */
500 bool update_wm_pre, update_wm_post; /* watermarks are updated */
501 bool fb_changed; /* fb on any of the planes is changed */
503 /* Pipe source size (ie. panel fitter input size)
504 * All planes will be positioned inside this space,
505 * and get clipped at the edges. */
506 int pipe_src_w, pipe_src_h;
508 /* Whether to set up the PCH/FDI. Note that we never allow sharing
509 * between pch encoders and cpu encoders. */
510 bool has_pch_encoder;
512 /* Are we sending infoframes on the attached port */
515 /* CPU Transcoder for the pipe. Currently this can only differ from the
516 * pipe on Haswell and later (where we have a special eDP transcoder)
517 * and Broxton (where we have special DSI transcoders). */
518 enum transcoder cpu_transcoder;
521 * Use reduced/limited/broadcast rbg range, compressing from the full
522 * range fed into the crtcs.
524 bool limited_color_range;
526 /* Bitmask of encoder types (enum intel_output_type)
527 * driven by the pipe.
529 unsigned int output_types;
531 /* Whether we should send NULL infoframes. Required for audio. */
534 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
535 * has_dp_encoder is set. */
539 * Enable dithering, used when the selected pipe bpp doesn't match the
544 /* Controls for the clock computation, to override various stages. */
547 /* SDVO TV has a bunch of special case. To make multifunction encoders
548 * work correctly, we need to track this at runtime.*/
552 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
553 * required. This is set in the 2nd loop of calling encoder's
554 * ->compute_config if the first pick doesn't work out.
558 /* Settings for the intel dpll used on pretty much everything but
562 /* Selected dpll when shared or NULL. */
563 struct intel_shared_dpll *shared_dpll;
566 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
567 * - enum skl_dpll on SKL
569 uint32_t ddi_pll_sel;
571 /* Actual register state of the dpll, for shared dpll cross-checking. */
572 struct intel_dpll_hw_state dpll_hw_state;
574 /* DSI PLL registers */
580 struct intel_link_m_n dp_m_n;
582 /* m2_n2 for eDP downclock */
583 struct intel_link_m_n dp_m2_n2;
587 * Frequence the dpll for the port should run at. Differs from the
588 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
589 * already multiplied by pixel_multiplier.
593 /* Used by SDVO (and if we ever fix it, HDMI). */
594 unsigned pixel_multiplier;
599 * Used by platforms having DP/HDMI PHY with programmable lane
600 * latency optimization.
602 uint8_t lane_lat_optim_mask;
604 /* Panel fitter controls for gen2-gen4 + VLV */
608 u32 lvds_border_bits;
611 /* Panel fitter placement and size for Ironlake+ */
619 /* FDI configuration, only valid if has_pch_encoder is set. */
621 struct intel_link_m_n fdi_m_n;
629 bool dp_encoder_is_mst;
632 struct intel_crtc_scaler_state scaler_state;
634 /* w/a for waiting 2 vblanks during crtc enable */
635 enum i915_pipe hsw_workaround_pipe;
637 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
640 struct intel_crtc_wm_state wm;
642 /* Gamma mode programmed on the pipe */
646 struct vlv_wm_state {
647 struct vlv_pipe_wm wm[3];
648 struct vlv_sr_wm sr[3];
649 uint8_t num_active_planes;
656 struct drm_crtc base;
659 u8 lut_r[256], lut_g[256], lut_b[256];
661 * Whether the crtc and the connected output pipeline is active. Implies
662 * that crtc->enabled is set, i.e. the current mode configuration has
663 * some outputs connected to this crtc.
666 unsigned long enabled_power_domains;
668 struct intel_overlay *overlay;
669 struct intel_flip_work *flip_work;
671 atomic_t unpin_work_count;
673 /* Display surface base address adjustement for pageflips. Note that on
674 * gen4+ this only adjusts up to a tile, offsets within a tile are
675 * handled in the hw itself (with the TILEOFF register). */
680 uint32_t cursor_addr;
681 uint32_t cursor_cntl;
682 uint32_t cursor_size;
683 uint32_t cursor_base;
685 struct intel_crtc_state *config;
687 /* reset counter value when the last flip was submitted */
688 unsigned int reset_counter;
690 /* Access to these should be protected by dev_priv->irq_lock. */
691 bool cpu_fifo_underrun_disabled;
692 bool pch_fifo_underrun_disabled;
694 /* per-pipe watermark state */
696 /* watermarks currently being used */
698 struct intel_pipe_wm ilk;
699 struct skl_pipe_wm skl;
702 /* allow CxSR on this pipe */
709 unsigned start_vbl_count;
710 ktime_t start_vbl_time;
711 int min_vbl, max_vbl;
715 /* scalers available on this crtc */
718 struct vlv_wm_state wm_state;
721 struct intel_plane_wm_parameters {
722 uint32_t horiz_pixels;
723 uint32_t vert_pixels;
725 * For packed pixel formats:
726 * bytes_per_pixel - holds bytes per pixel
727 * For planar pixel formats:
728 * bytes_per_pixel - holds bytes per pixel for uv-plane
729 * y_bytes_per_pixel - holds bytes per pixel for y-plane
731 uint8_t bytes_per_pixel;
732 uint8_t y_bytes_per_pixel;
736 unsigned int rotation;
741 struct drm_plane base;
746 uint32_t frontbuffer_bit;
748 /* Since we need to change the watermarks before/after
749 * enabling/disabling the planes, we need to store the parameters here
750 * as the other pieces of the struct may not reflect the values we want
751 * for the watermark calculations. Currently only Haswell uses this.
753 struct intel_plane_wm_parameters wm;
756 * NOTE: Do not place new plane state fields here (e.g., when adding
757 * new plane properties). New runtime state should now be placed in
758 * the intel_plane_state structure and accessed via plane_state.
761 void (*update_plane)(struct drm_plane *plane,
762 const struct intel_crtc_state *crtc_state,
763 const struct intel_plane_state *plane_state);
764 void (*disable_plane)(struct drm_plane *plane,
765 struct drm_crtc *crtc);
766 int (*check_plane)(struct drm_plane *plane,
767 struct intel_crtc_state *crtc_state,
768 struct intel_plane_state *state);
771 struct intel_watermark_params {
772 unsigned long fifo_size;
773 unsigned long max_wm;
774 unsigned long default_wm;
775 unsigned long guard_size;
776 unsigned long cacheline_size;
779 struct cxsr_latency {
782 unsigned long fsb_freq;
783 unsigned long mem_freq;
784 unsigned long display_sr;
785 unsigned long display_hpll_disable;
786 unsigned long cursor_sr;
787 unsigned long cursor_hpll_disable;
790 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
791 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
792 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
793 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
794 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
795 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
796 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
797 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
798 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
804 enum drm_dp_dual_mode_type type;
807 bool limited_color_range;
808 bool color_range_auto;
811 enum hdmi_force_audio force_audio;
812 bool rgb_quant_range_selectable;
813 enum hdmi_picture_aspect aspect_ratio;
814 struct intel_connector *attached_connector;
815 void (*write_infoframe)(struct drm_encoder *encoder,
816 enum hdmi_infoframe_type type,
817 const void *frame, ssize_t len);
818 void (*set_infoframes)(struct drm_encoder *encoder,
820 const struct drm_display_mode *adjusted_mode);
821 bool (*infoframe_enabled)(struct drm_encoder *encoder,
822 const struct intel_crtc_state *pipe_config);
825 struct intel_dp_mst_encoder;
826 #define DP_MAX_DOWNSTREAM_PORTS 0x10
830 * When platform provides two set of M_N registers for dp, we can
831 * program them and switch between them incase of DRRS.
832 * But When only one such register is provided, we have to program the
833 * required divider value on that registers itself based on the DRRS state.
835 * M1_N1 : Program dp_m_n on M1_N1 registers
836 * dp_m2_n2 on M2_N2 registers (If supported)
838 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
839 * M2_N2 registers are not supported
843 /* Sets the m1_n1 and m2_n2 */
849 i915_reg_t output_reg;
850 i915_reg_t aux_ch_ctl_reg;
851 i915_reg_t aux_ch_data_reg[5];
858 enum hdmi_force_audio force_audio;
859 bool limited_color_range;
860 bool color_range_auto;
861 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
862 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
863 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
864 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
865 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
866 uint8_t num_sink_rates;
867 int sink_rates[DP_MAX_SUPPORTED_RATES];
868 struct drm_dp_aux aux;
869 uint8_t train_set[4];
870 int panel_power_up_delay;
871 int panel_power_down_delay;
872 int panel_power_cycle_delay;
873 int backlight_on_delay;
874 int backlight_off_delay;
875 struct delayed_work panel_vdd_work;
877 unsigned long last_power_on;
878 unsigned long last_backlight_off;
879 ktime_t panel_power_off_time;
881 struct notifier_block edp_notifier;
884 * Pipe whose power sequencer is currently locked into
885 * this port. Only relevant on VLV/CHV.
887 enum i915_pipe pps_pipe;
889 * Set if the sequencer may be reset due to a power transition,
890 * requiring a reinitialization. Only relevant on BXT.
893 struct edp_power_seq pps_delays;
895 bool can_mst; /* this port supports mst */
897 int active_mst_links;
898 /* connector directly attached - won't be use for modeset in mst world */
899 struct intel_connector *attached_connector;
901 /* mst connector list */
902 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
903 struct drm_dp_mst_topology_mgr mst_mgr;
905 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
907 * This function returns the value we have to program the AUX_CTL
908 * register with to kick off an AUX transaction.
910 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
913 uint32_t aux_clock_divider);
915 /* This is called before a link training is starterd */
916 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
918 /* Displayport compliance testing */
919 unsigned long compliance_test_type;
920 unsigned long compliance_test_data;
921 bool compliance_test_active;
924 struct intel_digital_port {
925 struct intel_encoder base;
929 struct intel_hdmi hdmi;
930 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
931 bool release_cl2_override;
933 /* for communication with audio component; protected by av_mutex */
934 const struct drm_connector *audio_connector;
937 struct intel_dp_mst_encoder {
938 struct intel_encoder base;
940 struct intel_digital_port *primary;
941 struct intel_connector *connector;
944 static inline enum dpio_channel
945 vlv_dport_to_channel(struct intel_digital_port *dport)
947 switch (dport->port) {
958 static inline enum dpio_phy
959 vlv_dport_to_phy(struct intel_digital_port *dport)
961 switch (dport->port) {
972 static inline enum dpio_channel
973 vlv_pipe_to_channel(enum i915_pipe pipe)
986 static inline struct drm_crtc *
987 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
989 struct drm_i915_private *dev_priv = to_i915(dev);
990 return dev_priv->pipe_to_crtc_mapping[pipe];
993 static inline struct drm_crtc *
994 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
996 struct drm_i915_private *dev_priv = to_i915(dev);
997 return dev_priv->plane_to_crtc_mapping[plane];
1000 struct intel_flip_work {
1001 struct work_struct unpin_work;
1002 struct work_struct mmio_work;
1004 struct drm_crtc *crtc;
1005 struct drm_framebuffer *old_fb;
1006 struct drm_i915_gem_object *pending_flip_obj;
1007 struct drm_pending_vblank_event *event;
1011 struct drm_i915_gem_request *flip_queued_req;
1012 u32 flip_queued_vblank;
1013 u32 flip_ready_vblank;
1014 unsigned int rotation;
1017 struct intel_load_detect_pipe {
1018 struct drm_atomic_state *restore_state;
1021 static inline struct intel_encoder *
1022 intel_attached_encoder(struct drm_connector *connector)
1024 return to_intel_connector(connector)->encoder;
1027 static inline struct intel_digital_port *
1028 enc_to_dig_port(struct drm_encoder *encoder)
1030 return container_of(encoder, struct intel_digital_port, base.base);
1033 static inline struct intel_dp_mst_encoder *
1034 enc_to_mst(struct drm_encoder *encoder)
1036 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1039 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1041 return &enc_to_dig_port(encoder)->dp;
1044 static inline struct intel_digital_port *
1045 dp_to_dig_port(struct intel_dp *intel_dp)
1047 return container_of(intel_dp, struct intel_digital_port, dp);
1050 static inline struct intel_digital_port *
1051 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1053 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1057 * Returns the number of planes for this pipe, ie the number of sprites + 1
1058 * (primary plane). This doesn't count the cursor plane then.
1060 static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1062 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1065 /* intel_fifo_underrun.c */
1066 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1067 enum i915_pipe pipe, bool enable);
1068 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1069 enum transcoder pch_transcoder,
1071 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1072 enum i915_pipe pipe);
1073 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1074 enum transcoder pch_transcoder);
1075 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1076 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1079 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1080 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1081 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1082 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1083 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1084 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1085 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1086 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1087 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1088 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1089 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1092 * We only use drm_irq_uninstall() at unload and VT switch, so
1093 * this is the only thing we need to check.
1095 return dev_priv->pm.irqs_enabled;
1098 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1099 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1100 unsigned int pipe_mask);
1101 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1102 unsigned int pipe_mask);
1105 void intel_crt_init(struct drm_device *dev);
1106 void intel_crt_reset(struct drm_encoder *encoder);
1109 void intel_ddi_clk_select(struct intel_encoder *encoder,
1110 const struct intel_crtc_state *pipe_config);
1111 void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1112 void hsw_fdi_link_train(struct drm_crtc *crtc);
1113 void intel_ddi_init(struct drm_device *dev, enum port port);
1114 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1115 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum i915_pipe *pipe);
1116 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1117 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1118 enum transcoder cpu_transcoder);
1119 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1120 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1121 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1122 struct intel_crtc_state *crtc_state);
1123 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1124 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1125 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1126 void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1127 void intel_ddi_get_config(struct intel_encoder *encoder,
1128 struct intel_crtc_state *pipe_config);
1129 struct intel_encoder *
1130 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1132 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1133 void intel_ddi_clock_get(struct intel_encoder *encoder,
1134 struct intel_crtc_state *pipe_config);
1135 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1136 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1138 /* intel_frontbuffer.c */
1139 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1140 enum fb_op_origin origin);
1141 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
1142 unsigned frontbuffer_bits);
1143 void intel_frontbuffer_flip_complete(struct drm_device *dev,
1144 unsigned frontbuffer_bits);
1145 void intel_frontbuffer_flip(struct drm_device *dev,
1146 unsigned frontbuffer_bits);
1147 unsigned int intel_fb_align_height(struct drm_device *dev,
1148 unsigned int height,
1149 uint32_t pixel_format,
1150 uint64_t fb_format_modifier);
1151 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
1152 enum fb_op_origin origin);
1153 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1154 uint64_t fb_modifier, uint32_t pixel_format);
1157 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1158 void intel_audio_codec_enable(struct intel_encoder *encoder);
1159 void intel_audio_codec_disable(struct intel_encoder *encoder);
1160 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1161 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1163 /* intel_display.c */
1164 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1165 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1166 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1167 const char *name, u32 reg, int ref_freq);
1168 extern const struct drm_plane_funcs intel_plane_funcs;
1169 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1170 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1171 bool intel_has_pending_fb_unpin(struct drm_device *dev);
1172 void intel_mark_busy(struct drm_i915_private *dev_priv);
1173 void intel_mark_idle(struct drm_i915_private *dev_priv);
1174 void intel_crtc_restore_mode(struct drm_crtc *crtc);
1175 int intel_display_suspend(struct drm_device *dev);
1176 void intel_encoder_destroy(struct drm_encoder *encoder);
1177 int intel_connector_init(struct intel_connector *);
1178 struct intel_connector *intel_connector_alloc(void);
1179 bool intel_connector_get_hw_state(struct intel_connector *connector);
1180 void intel_connector_attach_encoder(struct intel_connector *connector,
1181 struct intel_encoder *encoder);
1182 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1183 struct drm_crtc *crtc);
1184 enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1185 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1186 struct drm_file *file_priv);
1187 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1188 enum i915_pipe pipe);
1190 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1191 enum intel_output_type type)
1193 return crtc_state->output_types & (1 << type);
1196 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1198 return crtc_state->output_types &
1199 ((1 << INTEL_OUTPUT_DP) |
1200 (1 << INTEL_OUTPUT_DP_MST) |
1201 (1 << INTEL_OUTPUT_EDP));
1204 intel_wait_for_vblank(struct drm_device *dev, int pipe)
1206 drm_wait_one_vblank(dev, pipe);
1209 intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1211 const struct intel_crtc *crtc =
1212 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1215 intel_wait_for_vblank(dev, pipe);
1218 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1220 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1221 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1222 struct intel_digital_port *dport,
1223 unsigned int expected_mask);
1224 bool intel_get_load_detect_pipe(struct drm_connector *connector,
1225 struct drm_display_mode *mode,
1226 struct intel_load_detect_pipe *old,
1227 struct drm_modeset_acquire_ctx *ctx);
1228 void intel_release_load_detect_pipe(struct drm_connector *connector,
1229 struct intel_load_detect_pipe *old,
1230 struct drm_modeset_acquire_ctx *ctx);
1231 int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1232 unsigned int rotation);
1233 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1234 struct drm_framebuffer *
1235 __intel_framebuffer_create(struct drm_device *dev,
1236 struct drm_mode_fb_cmd2 *mode_cmd,
1237 struct drm_i915_gem_object *obj);
1238 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1239 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1240 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1241 int intel_prepare_plane_fb(struct drm_plane *plane,
1242 struct drm_plane_state *new_state);
1243 void intel_cleanup_plane_fb(struct drm_plane *plane,
1244 struct drm_plane_state *old_state);
1245 int intel_plane_atomic_get_property(struct drm_plane *plane,
1246 const struct drm_plane_state *state,
1247 struct drm_property *property,
1249 int intel_plane_atomic_set_property(struct drm_plane *plane,
1250 struct drm_plane_state *state,
1251 struct drm_property *property,
1253 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1254 struct drm_plane_state *plane_state);
1256 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1257 uint64_t fb_modifier, unsigned int cpp);
1260 intel_rotation_90_or_270(unsigned int rotation)
1262 return rotation & (DRM_ROTATE_90 | DRM_ROTATE_270);
1265 void intel_create_rotation_property(struct drm_device *dev,
1266 struct intel_plane *plane);
1268 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1269 enum i915_pipe pipe);
1271 int vlv_force_pll_on(struct drm_device *dev, enum i915_pipe pipe,
1272 const struct dpll *dpll);
1273 void vlv_force_pll_off(struct drm_device *dev, enum i915_pipe pipe);
1274 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1276 /* modesetting asserts */
1277 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1278 enum i915_pipe pipe);
1279 void assert_pll(struct drm_i915_private *dev_priv,
1280 enum i915_pipe pipe, bool state);
1281 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1282 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1283 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1284 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1285 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1286 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1287 enum i915_pipe pipe, bool state);
1288 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1289 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1290 void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, bool state);
1291 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1292 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1293 u32 intel_compute_tile_offset(int *x, int *y,
1294 const struct drm_framebuffer *fb, int plane,
1296 unsigned int rotation);
1297 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1298 void intel_finish_reset(struct drm_i915_private *dev_priv);
1299 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1300 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1301 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1302 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1303 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1304 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1305 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1307 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1309 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1310 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1311 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1312 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1313 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1314 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1315 unsigned int skl_cdclk_get_vco(unsigned int freq);
1316 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1317 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1318 void intel_dp_get_m_n(struct intel_crtc *crtc,
1319 struct intel_crtc_state *pipe_config);
1320 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1321 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1322 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1323 struct dpll *best_clock);
1324 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1326 bool intel_crtc_active(struct drm_crtc *crtc);
1327 void hsw_enable_ips(struct intel_crtc *crtc);
1328 void hsw_disable_ips(struct intel_crtc *crtc);
1329 enum intel_display_power_domain
1330 intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1331 enum intel_display_power_domain
1332 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1333 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1334 struct intel_crtc_state *pipe_config);
1336 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1337 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1339 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
1340 struct drm_i915_gem_object *obj,
1341 unsigned int plane);
1343 u32 skl_plane_ctl_format(uint32_t pixel_format);
1344 u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1345 u32 skl_plane_ctl_rotation(unsigned int rotation);
1348 void intel_csr_ucode_init(struct drm_i915_private *);
1349 void intel_csr_load_program(struct drm_i915_private *);
1350 void intel_csr_ucode_fini(struct drm_i915_private *);
1351 void intel_csr_ucode_suspend(struct drm_i915_private *);
1352 void intel_csr_ucode_resume(struct drm_i915_private *);
1355 bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1356 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1357 struct intel_connector *intel_connector);
1358 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1359 const struct intel_crtc_state *pipe_config);
1360 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1361 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1362 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1363 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1364 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1365 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1366 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1367 bool intel_dp_compute_config(struct intel_encoder *encoder,
1368 struct intel_crtc_state *pipe_config);
1369 bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1370 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1372 void intel_edp_backlight_on(struct intel_dp *intel_dp);
1373 void intel_edp_backlight_off(struct intel_dp *intel_dp);
1374 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1375 void intel_edp_panel_on(struct intel_dp *intel_dp);
1376 void intel_edp_panel_off(struct intel_dp *intel_dp);
1377 void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1378 void intel_dp_mst_suspend(struct drm_device *dev);
1379 void intel_dp_mst_resume(struct drm_device *dev);
1380 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1381 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1382 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1383 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1384 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1385 void intel_plane_destroy(struct drm_plane *plane);
1386 void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1387 void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1388 void intel_edp_drrs_invalidate(struct drm_device *dev,
1389 unsigned frontbuffer_bits);
1390 void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1393 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1394 uint8_t dp_train_pat);
1396 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1397 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1399 intel_dp_voltage_max(struct intel_dp *intel_dp);
1401 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1402 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1403 uint8_t *link_bw, uint8_t *rate_select);
1404 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1406 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1408 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1410 return ~((1 << lane_count) - 1) & 0xf;
1413 /* intel_dp_aux_backlight.c */
1414 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1416 /* intel_dp_mst.c */
1417 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1418 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1420 void intel_dsi_init(struct drm_device *dev);
1422 /* intel_dsi_dcs_backlight.c */
1423 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1426 void intel_dvo_init(struct drm_device *dev);
1427 /* intel_hotplug.c */
1428 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1431 /* legacy fbdev emulation in intel_fbdev.c */
1432 #ifdef CONFIG_DRM_FBDEV_EMULATION
1433 extern int intel_fbdev_init(struct drm_device *dev);
1434 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1435 extern void intel_fbdev_fini(struct drm_device *dev);
1436 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1437 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1438 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1440 static inline int intel_fbdev_init(struct drm_device *dev)
1445 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1449 static inline void intel_fbdev_fini(struct drm_device *dev)
1453 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1457 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1463 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1464 struct drm_atomic_state *state);
1465 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1466 void intel_fbc_pre_update(struct intel_crtc *crtc,
1467 struct intel_crtc_state *crtc_state,
1468 struct intel_plane_state *plane_state);
1469 void intel_fbc_post_update(struct intel_crtc *crtc);
1470 void intel_fbc_init(struct drm_i915_private *dev_priv);
1471 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1472 void intel_fbc_enable(struct intel_crtc *crtc,
1473 struct intel_crtc_state *crtc_state,
1474 struct intel_plane_state *plane_state);
1475 void intel_fbc_disable(struct intel_crtc *crtc);
1476 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1477 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1478 unsigned int frontbuffer_bits,
1479 enum fb_op_origin origin);
1480 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1481 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1482 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1485 void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1486 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1487 struct intel_connector *intel_connector);
1488 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1489 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1490 struct intel_crtc_state *pipe_config);
1491 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1495 void intel_lvds_init(struct drm_device *dev);
1496 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1497 bool intel_is_dual_link_lvds(struct drm_device *dev);
1501 int intel_connector_update_modes(struct drm_connector *connector,
1503 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1504 void intel_attach_force_audio_property(struct drm_connector *connector);
1505 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1506 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1509 /* intel_overlay.c */
1510 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1511 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1512 int intel_overlay_switch_off(struct intel_overlay *overlay);
1513 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1514 struct drm_file *file_priv);
1515 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1516 struct drm_file *file_priv);
1517 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1521 int intel_panel_init(struct intel_panel *panel,
1522 struct drm_display_mode *fixed_mode,
1523 struct drm_display_mode *downclock_mode);
1524 void intel_panel_fini(struct intel_panel *panel);
1525 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1526 struct drm_display_mode *adjusted_mode);
1527 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1528 struct intel_crtc_state *pipe_config,
1530 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1531 struct intel_crtc_state *pipe_config,
1533 void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1534 u32 level, u32 max);
1535 int intel_panel_setup_backlight(struct drm_connector *connector,
1536 enum i915_pipe pipe);
1537 void intel_panel_enable_backlight(struct intel_connector *connector);
1538 void intel_panel_disable_backlight(struct intel_connector *connector);
1539 void intel_panel_destroy_backlight(struct drm_connector *connector);
1540 enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1541 extern struct drm_display_mode *intel_find_panel_downclock(
1542 struct drm_device *dev,
1543 struct drm_display_mode *fixed_mode,
1544 struct drm_connector *connector);
1546 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1547 int intel_backlight_device_register(struct intel_connector *connector);
1548 void intel_backlight_device_unregister(struct intel_connector *connector);
1549 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1550 static int intel_backlight_device_register(struct intel_connector *connector)
1554 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1557 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1561 void intel_psr_enable(struct intel_dp *intel_dp);
1562 void intel_psr_disable(struct intel_dp *intel_dp);
1563 void intel_psr_invalidate(struct drm_device *dev,
1564 unsigned frontbuffer_bits);
1565 void intel_psr_flush(struct drm_device *dev,
1566 unsigned frontbuffer_bits,
1567 enum fb_op_origin origin);
1568 void intel_psr_init(struct drm_device *dev);
1569 void intel_psr_single_frame_update(struct drm_device *dev,
1570 unsigned frontbuffer_bits);
1572 /* intel_runtime_pm.c */
1573 int intel_power_domains_init(struct drm_i915_private *);
1574 void intel_power_domains_fini(struct drm_i915_private *);
1575 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1576 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1577 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1578 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1579 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1581 intel_display_power_domain_str(enum intel_display_power_domain domain);
1583 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1584 enum intel_display_power_domain domain);
1585 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1586 enum intel_display_power_domain domain);
1587 void intel_display_power_get(struct drm_i915_private *dev_priv,
1588 enum intel_display_power_domain domain);
1589 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1590 enum intel_display_power_domain domain);
1591 void intel_display_power_put(struct drm_i915_private *dev_priv,
1592 enum intel_display_power_domain domain);
1595 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1597 WARN_ONCE(dev_priv->pm.suspended,
1598 "Device suspended during HW access\n");
1602 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1604 assert_rpm_device_not_suspended(dev_priv);
1605 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1606 * too much noise. */
1607 if (!atomic_read(&dev_priv->pm.wakeref_count))
1608 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1612 assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1614 int seq = atomic_read(&dev_priv->pm.atomic_seq);
1616 assert_rpm_wakelock_held(dev_priv);
1622 assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1624 WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1625 "HW access outside of RPM atomic section\n");
1629 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1630 * @dev_priv: i915 device instance
1632 * This function disable asserts that check if we hold an RPM wakelock
1633 * reference, while keeping the device-not-suspended checks still enabled.
1634 * It's meant to be used only in special circumstances where our rule about
1635 * the wakelock refcount wrt. the device power state doesn't hold. According
1636 * to this rule at any point where we access the HW or want to keep the HW in
1637 * an active state we must hold an RPM wakelock reference acquired via one of
1638 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1639 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1640 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1641 * users should avoid using this function.
1643 * Any calls to this function must have a symmetric call to
1644 * enable_rpm_wakeref_asserts().
1647 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1649 atomic_inc(&dev_priv->pm.wakeref_count);
1653 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1654 * @dev_priv: i915 device instance
1656 * This function re-enables the RPM assert checks after disabling them with
1657 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1658 * circumstances otherwise its use should be avoided.
1660 * Any calls to this function must have a symmetric call to
1661 * disable_rpm_wakeref_asserts().
1664 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1666 atomic_dec(&dev_priv->pm.wakeref_count);
1669 /* TODO: convert users of these to rely instead on proper RPM refcounting */
1670 #define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1671 disable_rpm_wakeref_asserts(dev_priv)
1673 #define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv) \
1674 enable_rpm_wakeref_asserts(dev_priv)
1676 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1677 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1678 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1679 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1681 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1683 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1684 bool override, unsigned int mask);
1685 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1686 enum dpio_channel ch, bool override);
1690 void intel_init_clock_gating(struct drm_device *dev);
1691 void intel_suspend_hw(struct drm_device *dev);
1692 int ilk_wm_max_level(const struct drm_device *dev);
1693 void intel_update_watermarks(struct drm_crtc *crtc);
1694 void intel_init_pm(struct drm_device *dev);
1695 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1696 void intel_pm_setup(struct drm_device *dev);
1697 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1698 void intel_gpu_ips_teardown(void);
1699 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1700 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1701 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1702 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1703 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1704 void intel_reset_gt_powersave(struct drm_i915_private *dev_priv);
1705 void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
1706 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1707 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1708 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1709 void gen6_rps_boost(struct drm_i915_private *dev_priv,
1710 struct intel_rps_client *rps,
1711 unsigned long submitted);
1712 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1713 void vlv_wm_get_hw_state(struct drm_device *dev);
1714 void ilk_wm_get_hw_state(struct drm_device *dev);
1715 void skl_wm_get_hw_state(struct drm_device *dev);
1716 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1717 struct skl_ddb_allocation *ddb /* out */);
1718 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1719 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1720 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1721 bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
1722 const struct skl_ddb_allocation *new,
1723 enum i915_pipe pipe);
1724 bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
1725 const struct skl_ddb_allocation *old,
1726 const struct skl_ddb_allocation *new,
1727 enum i915_pipe pipe);
1728 void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
1729 const struct skl_wm_values *wm);
1730 void skl_write_plane_wm(struct intel_crtc *intel_crtc,
1731 const struct skl_wm_values *wm,
1733 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1734 bool ilk_disable_lp_wm(struct drm_device *dev);
1735 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1736 static inline int intel_enable_rc6(void)
1738 return i915.enable_rc6;
1742 bool intel_sdvo_init(struct drm_device *dev,
1743 i915_reg_t reg, enum port port);
1746 /* intel_sprite.c */
1747 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1749 int intel_plane_init(struct drm_device *dev, enum i915_pipe pipe, int plane);
1750 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1751 struct drm_file *file_priv);
1752 void intel_pipe_update_start(struct intel_crtc *crtc);
1753 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
1756 void intel_tv_init(struct drm_device *dev);
1758 /* intel_atomic.c */
1759 int intel_connector_atomic_get_property(struct drm_connector *connector,
1760 const struct drm_connector_state *state,
1761 struct drm_property *property,
1763 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1764 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1765 struct drm_crtc_state *state);
1766 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1767 void intel_atomic_state_clear(struct drm_atomic_state *);
1768 struct intel_shared_dpll_config *
1769 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1771 static inline struct intel_crtc_state *
1772 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1773 struct intel_crtc *crtc)
1775 struct drm_crtc_state *crtc_state;
1776 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1777 if (IS_ERR(crtc_state))
1778 return ERR_CAST(crtc_state);
1780 return to_intel_crtc_state(crtc_state);
1783 static inline struct intel_plane_state *
1784 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1785 struct intel_plane *plane)
1787 struct drm_plane_state *plane_state;
1789 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1791 return to_intel_plane_state(plane_state);
1794 int intel_atomic_setup_scalers(struct drm_device *dev,
1795 struct intel_crtc *intel_crtc,
1796 struct intel_crtc_state *crtc_state);
1798 /* intel_atomic_plane.c */
1799 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1800 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1801 void intel_plane_destroy_state(struct drm_plane *plane,
1802 struct drm_plane_state *state);
1803 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1806 void intel_color_init(struct drm_crtc *crtc);
1807 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1808 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1809 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1811 #endif /* __INTEL_DRV_H__ */