2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $
33 * $DragonFly: src/sys/dev/netif/ste/if_ste.c,v 1.22 2005/06/09 19:10:04 joerg Exp $
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/sockio.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/socket.h>
43 #include <sys/thread2.h>
46 #include <net/ifq_var.h>
47 #include <net/if_arp.h>
48 #include <net/ethernet.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
51 #include <net/vlan/if_vlan_var.h>
55 #include <vm/vm.h> /* for vtophys */
56 #include <vm/pmap.h> /* for vtophys */
57 #include <machine/bus_memio.h>
58 #include <machine/bus_pio.h>
59 #include <machine/bus.h>
60 #include <machine/resource.h>
64 #include "../mii_layer/mii.h"
65 #include "../mii_layer/miivar.h"
67 #include <bus/pci/pcireg.h>
68 #include <bus/pci/pcivar.h>
70 /* "controller miibus0" required. See GENERIC if you get errors here. */
71 #include "miibus_if.h"
73 #define STE_USEIOSPACE
75 #include "if_stereg.h"
78 * Various supported device vendors/types and their names.
80 static struct ste_type ste_devs[] = {
81 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" },
82 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" },
86 static int ste_probe (device_t);
87 static int ste_attach (device_t);
88 static int ste_detach (device_t);
89 static void ste_init (void *);
90 static void ste_intr (void *);
91 static void ste_rxeof (struct ste_softc *);
92 static void ste_txeoc (struct ste_softc *);
93 static void ste_txeof (struct ste_softc *);
94 static void ste_stats_update (void *);
95 static void ste_stop (struct ste_softc *);
96 static void ste_reset (struct ste_softc *);
97 static int ste_ioctl (struct ifnet *, u_long, caddr_t,
99 static int ste_encap (struct ste_softc *, struct ste_chain *,
101 static void ste_start (struct ifnet *);
102 static void ste_watchdog (struct ifnet *);
103 static void ste_shutdown (device_t);
104 static int ste_newbuf (struct ste_softc *,
105 struct ste_chain_onefrag *,
107 static int ste_ifmedia_upd (struct ifnet *);
108 static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *);
110 static void ste_mii_sync (struct ste_softc *);
111 static void ste_mii_send (struct ste_softc *, u_int32_t, int);
112 static int ste_mii_readreg (struct ste_softc *,
113 struct ste_mii_frame *);
114 static int ste_mii_writereg (struct ste_softc *,
115 struct ste_mii_frame *);
116 static int ste_miibus_readreg (device_t, int, int);
117 static int ste_miibus_writereg (device_t, int, int, int);
118 static void ste_miibus_statchg (device_t);
120 static int ste_eeprom_wait (struct ste_softc *);
121 static int ste_read_eeprom (struct ste_softc *, caddr_t, int,
123 static void ste_wait (struct ste_softc *);
124 static u_int8_t ste_calchash (caddr_t);
125 static void ste_setmulti (struct ste_softc *);
126 static int ste_init_rx_list (struct ste_softc *);
127 static void ste_init_tx_list (struct ste_softc *);
129 #ifdef STE_USEIOSPACE
130 #define STE_RES SYS_RES_IOPORT
131 #define STE_RID STE_PCI_LOIO
133 #define STE_RES SYS_RES_MEMORY
134 #define STE_RID STE_PCI_LOMEM
137 static device_method_t ste_methods[] = {
138 /* Device interface */
139 DEVMETHOD(device_probe, ste_probe),
140 DEVMETHOD(device_attach, ste_attach),
141 DEVMETHOD(device_detach, ste_detach),
142 DEVMETHOD(device_shutdown, ste_shutdown),
145 DEVMETHOD(bus_print_child, bus_generic_print_child),
146 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
149 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
150 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
151 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
156 static driver_t ste_driver = {
159 sizeof(struct ste_softc)
162 static devclass_t ste_devclass;
164 DECLARE_DUMMY_MODULE(if_ste);
165 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0);
166 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
168 #define STE_SETBIT4(sc, reg, x) \
169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
171 #define STE_CLRBIT4(sc, reg, x) \
172 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
174 #define STE_SETBIT2(sc, reg, x) \
175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
177 #define STE_CLRBIT2(sc, reg, x) \
178 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
180 #define STE_SETBIT1(sc, reg, x) \
181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
183 #define STE_CLRBIT1(sc, reg, x) \
184 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
187 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
188 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
191 * Sync the PHYs by setting data bit and strobing the clock 32 times.
193 static void ste_mii_sync(sc)
194 struct ste_softc *sc;
198 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
200 for (i = 0; i < 32; i++) {
201 MII_SET(STE_PHYCTL_MCLK);
203 MII_CLR(STE_PHYCTL_MCLK);
211 * Clock a series of bits through the MII.
213 static void ste_mii_send(sc, bits, cnt)
214 struct ste_softc *sc;
220 MII_CLR(STE_PHYCTL_MCLK);
222 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
224 MII_SET(STE_PHYCTL_MDATA);
226 MII_CLR(STE_PHYCTL_MDATA);
229 MII_CLR(STE_PHYCTL_MCLK);
231 MII_SET(STE_PHYCTL_MCLK);
236 * Read an PHY register through the MII.
238 static int ste_mii_readreg(sc, frame)
239 struct ste_softc *sc;
240 struct ste_mii_frame *frame;
248 * Set up frame for RX.
250 frame->mii_stdelim = STE_MII_STARTDELIM;
251 frame->mii_opcode = STE_MII_READOP;
252 frame->mii_turnaround = 0;
255 CSR_WRITE_2(sc, STE_PHYCTL, 0);
259 MII_SET(STE_PHYCTL_MDIR);
264 * Send command/address info.
266 ste_mii_send(sc, frame->mii_stdelim, 2);
267 ste_mii_send(sc, frame->mii_opcode, 2);
268 ste_mii_send(sc, frame->mii_phyaddr, 5);
269 ste_mii_send(sc, frame->mii_regaddr, 5);
272 MII_CLR(STE_PHYCTL_MDIR);
275 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
277 MII_SET(STE_PHYCTL_MCLK);
281 MII_CLR(STE_PHYCTL_MCLK);
283 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
284 MII_SET(STE_PHYCTL_MCLK);
288 * Now try reading data bits. If the ack failed, we still
289 * need to clock through 16 cycles to keep the PHY(s) in sync.
292 for(i = 0; i < 16; i++) {
293 MII_CLR(STE_PHYCTL_MCLK);
295 MII_SET(STE_PHYCTL_MCLK);
301 for (i = 0x8000; i; i >>= 1) {
302 MII_CLR(STE_PHYCTL_MCLK);
305 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
306 frame->mii_data |= i;
309 MII_SET(STE_PHYCTL_MCLK);
315 MII_CLR(STE_PHYCTL_MCLK);
317 MII_SET(STE_PHYCTL_MCLK);
328 * Write to a PHY register through the MII.
330 static int ste_mii_writereg(sc, frame)
331 struct ste_softc *sc;
332 struct ste_mii_frame *frame;
338 * Set up frame for TX.
341 frame->mii_stdelim = STE_MII_STARTDELIM;
342 frame->mii_opcode = STE_MII_WRITEOP;
343 frame->mii_turnaround = STE_MII_TURNAROUND;
346 * Turn on data output.
348 MII_SET(STE_PHYCTL_MDIR);
352 ste_mii_send(sc, frame->mii_stdelim, 2);
353 ste_mii_send(sc, frame->mii_opcode, 2);
354 ste_mii_send(sc, frame->mii_phyaddr, 5);
355 ste_mii_send(sc, frame->mii_regaddr, 5);
356 ste_mii_send(sc, frame->mii_turnaround, 2);
357 ste_mii_send(sc, frame->mii_data, 16);
360 MII_SET(STE_PHYCTL_MCLK);
362 MII_CLR(STE_PHYCTL_MCLK);
368 MII_CLR(STE_PHYCTL_MDIR);
375 static int ste_miibus_readreg(dev, phy, reg)
379 struct ste_softc *sc;
380 struct ste_mii_frame frame;
382 sc = device_get_softc(dev);
384 if ( sc->ste_one_phy && phy != 0 )
387 bzero((char *)&frame, sizeof(frame));
389 frame.mii_phyaddr = phy;
390 frame.mii_regaddr = reg;
391 ste_mii_readreg(sc, &frame);
393 return(frame.mii_data);
396 static int ste_miibus_writereg(dev, phy, reg, data)
400 struct ste_softc *sc;
401 struct ste_mii_frame frame;
403 sc = device_get_softc(dev);
404 bzero((char *)&frame, sizeof(frame));
406 frame.mii_phyaddr = phy;
407 frame.mii_regaddr = reg;
408 frame.mii_data = data;
410 ste_mii_writereg(sc, &frame);
415 static void ste_miibus_statchg(dev)
418 struct ste_softc *sc;
419 struct mii_data *mii;
422 sc = device_get_softc(dev);
423 mii = device_get_softc(sc->ste_miibus);
425 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
426 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
428 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
431 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET |
432 STE_ASICCTL_TX_RESET);
433 for (i = 0; i < STE_TIMEOUT; i++) {
434 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
437 if (i == STE_TIMEOUT)
438 if_printf(&sc->arpcom.ac_if, "rx reset never completed\n");
443 static int ste_ifmedia_upd(ifp)
446 struct ste_softc *sc;
447 struct mii_data *mii;
450 mii = device_get_softc(sc->ste_miibus);
452 if (mii->mii_instance) {
453 struct mii_softc *miisc;
454 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
455 miisc = LIST_NEXT(miisc, mii_list))
456 mii_phy_reset(miisc);
463 static void ste_ifmedia_sts(ifp, ifmr)
465 struct ifmediareq *ifmr;
467 struct ste_softc *sc;
468 struct mii_data *mii;
471 mii = device_get_softc(sc->ste_miibus);
474 ifmr->ifm_active = mii->mii_media_active;
475 ifmr->ifm_status = mii->mii_media_status;
480 static void ste_wait(sc)
481 struct ste_softc *sc;
485 for (i = 0; i < STE_TIMEOUT; i++) {
486 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
490 if (i == STE_TIMEOUT)
491 if_printf(&sc->arpcom.ac_if, "command never completed!\n");
497 * The EEPROM is slow: give it time to come ready after issuing
500 static int ste_eeprom_wait(sc)
501 struct ste_softc *sc;
507 for (i = 0; i < 100; i++) {
508 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
515 if_printf(&sc->arpcom.ac_if, "eeprom failed to come ready\n");
523 * Read a sequence of words from the EEPROM. Note that ethernet address
524 * data is stored in the EEPROM in network byte order.
526 static int ste_read_eeprom(sc, dest, off, cnt, swap)
527 struct ste_softc *sc;
534 u_int16_t word = 0, *ptr;
536 if (ste_eeprom_wait(sc))
539 for (i = 0; i < cnt; i++) {
540 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
541 err = ste_eeprom_wait(sc);
544 word = CSR_READ_2(sc, STE_EEPROM_DATA);
545 ptr = (u_int16_t *)(dest + (i * 2));
555 static u_int8_t ste_calchash(addr)
559 u_int32_t crc, carry;
563 /* Compute CRC for the address value. */
564 crc = 0xFFFFFFFF; /* initial value */
566 for (i = 0; i < 6; i++) {
568 for (j = 0; j < 8; j++) {
569 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
573 crc = (crc ^ 0x04c11db6) | carry;
577 /* return the filter bit position */
578 return(crc & 0x0000003F);
581 static void ste_setmulti(sc)
582 struct ste_softc *sc;
586 u_int32_t hashes[2] = { 0, 0 };
587 struct ifmultiaddr *ifma;
589 ifp = &sc->arpcom.ac_if;
590 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
591 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
592 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
596 /* first, zot all the existing hash bits */
597 CSR_WRITE_2(sc, STE_MAR0, 0);
598 CSR_WRITE_2(sc, STE_MAR1, 0);
599 CSR_WRITE_2(sc, STE_MAR2, 0);
600 CSR_WRITE_2(sc, STE_MAR3, 0);
602 /* now program new ones */
603 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
604 ifma = ifma->ifma_link.le_next) {
605 if (ifma->ifma_addr->sa_family != AF_LINK)
607 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
609 hashes[0] |= (1 << h);
611 hashes[1] |= (1 << (h - 32));
614 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
615 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
616 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
617 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
618 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
619 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
624 static void ste_intr(xsc)
627 struct ste_softc *sc;
632 ifp = &sc->arpcom.ac_if;
634 /* See if this is really our interrupt. */
635 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH))
639 status = CSR_READ_2(sc, STE_ISR_ACK);
641 if (!(status & STE_INTRS))
644 if (status & STE_ISR_RX_DMADONE)
647 if (status & STE_ISR_TX_DMADONE)
650 if (status & STE_ISR_TX_DONE)
653 if (status & STE_ISR_STATS_OFLOW) {
654 callout_stop(&sc->ste_stat_timer);
655 ste_stats_update(sc);
658 if (status & STE_ISR_LINKEVENT)
659 mii_pollstat(device_get_softc(sc->ste_miibus));
661 if (status & STE_ISR_HOSTERR) {
667 /* Re-enable interrupts */
668 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
670 if (!ifq_is_empty(&ifp->if_snd))
677 * A frame has been uploaded: pass the resulting mbuf chain up to
678 * the higher level protocols.
680 static void ste_rxeof(sc)
681 struct ste_softc *sc;
685 struct ste_chain_onefrag *cur_rx;
686 int total_len = 0, count=0;
689 ifp = &sc->arpcom.ac_if;
691 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)
692 & STE_RXSTAT_DMADONE) {
693 if ((STE_RX_LIST_CNT - count) < 3) {
697 cur_rx = sc->ste_cdata.ste_rx_head;
698 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
701 * If an error occurs, update stats, clear the
702 * status word and leave the mbuf cluster in place:
703 * it should simply get re-used next time this descriptor
704 * comes up in the ring.
706 if (rxstat & STE_RXSTAT_FRAME_ERR) {
708 cur_rx->ste_ptr->ste_status = 0;
713 * If there error bit was not set, the upload complete
714 * bit should be set which means we have a valid packet.
715 * If not, something truly strange has happened.
717 if (!(rxstat & STE_RXSTAT_DMADONE)) {
718 if_printf(ifp, "bad receive status -- packet dropped");
720 cur_rx->ste_ptr->ste_status = 0;
724 /* No errors; receive the packet. */
725 m = cur_rx->ste_mbuf;
726 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
729 * Try to conjure up a new mbuf cluster. If that
730 * fails, it means we have an out of memory condition and
731 * should leave the buffer in place and continue. This will
732 * result in a lost packet, but there's little else we
733 * can do in this situation.
735 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
737 cur_rx->ste_ptr->ste_status = 0;
742 m->m_pkthdr.rcvif = ifp;
743 m->m_pkthdr.len = m->m_len = total_len;
745 (*ifp->if_input)(ifp, m);
747 cur_rx->ste_ptr->ste_status = 0;
754 static void ste_txeoc(sc)
755 struct ste_softc *sc;
760 ifp = &sc->arpcom.ac_if;
762 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
763 STE_TXSTATUS_TXDONE) {
764 if (txstat & STE_TXSTATUS_UNDERRUN ||
765 txstat & STE_TXSTATUS_EXCESSCOLLS ||
766 txstat & STE_TXSTATUS_RECLAIMERR) {
768 if_printf(ifp, "transmission error: %x\n", txstat);
773 if (txstat & STE_TXSTATUS_UNDERRUN &&
774 sc->ste_tx_thresh < STE_PACKET_SIZE) {
775 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
776 if_printf(ifp, "tx underrun, increasing tx"
777 " start threshold to %d bytes\n",
780 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
781 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
782 (STE_PACKET_SIZE >> 4));
785 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
791 static void ste_txeof(sc)
792 struct ste_softc *sc;
794 struct ste_chain *cur_tx = NULL;
798 ifp = &sc->arpcom.ac_if;
800 idx = sc->ste_cdata.ste_tx_cons;
801 while(idx != sc->ste_cdata.ste_tx_prod) {
802 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
804 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
807 if (cur_tx->ste_mbuf != NULL) {
808 m_freem(cur_tx->ste_mbuf);
809 cur_tx->ste_mbuf = NULL;
814 sc->ste_cdata.ste_tx_cnt--;
815 STE_INC(idx, STE_TX_LIST_CNT);
819 sc->ste_cdata.ste_tx_cons = idx;
822 ifp->if_flags &= ~IFF_OACTIVE;
827 static void ste_stats_update(xsc)
830 struct ste_softc *sc;
832 struct mii_data *mii;
837 ifp = &sc->arpcom.ac_if;
838 mii = device_get_softc(sc->ste_miibus);
840 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
841 + CSR_READ_1(sc, STE_MULTI_COLLS)
842 + CSR_READ_1(sc, STE_SINGLE_COLLS);
846 if (mii->mii_media_status & IFM_ACTIVE &&
847 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
850 * we don't get a call-back on re-init so do it
851 * otherwise we get stuck in the wrong link state
853 ste_miibus_statchg(sc->ste_dev);
854 if (!ifq_is_empty(&ifp->if_snd))
859 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc);
867 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
868 * IDs against our list and return a device name if we find a match.
870 static int ste_probe(dev)
877 while(t->ste_name != NULL) {
878 if ((pci_get_vendor(dev) == t->ste_vid) &&
879 (pci_get_device(dev) == t->ste_did)) {
880 device_set_desc(dev, t->ste_name);
890 * Attach the interface. Allocate softc structures, do ifmedia
891 * setup and ethernet/BPF attach.
893 static int ste_attach(dev)
897 struct ste_softc *sc;
903 sc = device_get_softc(dev);
904 bzero(sc, sizeof(struct ste_softc));
908 * Only use one PHY since this chip reports multiple
909 * Note on the DFE-550 the PHY is at 1 on the DFE-580
910 * it is at 0 & 1. It is rev 0x12.
912 if (pci_get_vendor(dev) == DL_VENDORID &&
913 pci_get_device(dev) == DL_DEVICEID_550TX &&
914 pci_get_revid(dev) == 0x12 )
918 * Handle power management nonsense.
920 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
921 u_int32_t iobase, membase, irq;
923 /* Save important PCI config data. */
924 iobase = pci_read_config(dev, STE_PCI_LOIO, 4);
925 membase = pci_read_config(dev, STE_PCI_LOMEM, 4);
926 irq = pci_read_config(dev, STE_PCI_INTLINE, 4);
928 /* Reset the power state. */
929 device_printf(dev, "chip is in D%d power mode "
930 "-- setting to D0\n", pci_get_powerstate(dev));
931 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
933 /* Restore PCI config data. */
934 pci_write_config(dev, STE_PCI_LOIO, iobase, 4);
935 pci_write_config(dev, STE_PCI_LOMEM, membase, 4);
936 pci_write_config(dev, STE_PCI_INTLINE, irq, 4);
940 * Map control/status registers.
942 pci_enable_busmaster(dev);
943 pci_enable_io(dev, SYS_RES_IOPORT);
944 pci_enable_io(dev, SYS_RES_MEMORY);
945 command = pci_read_config(dev, PCIR_COMMAND, 4);
947 #ifdef STE_USEIOSPACE
948 if (!(command & PCIM_CMD_PORTEN)) {
949 device_printf(dev, "failed to enable I/O ports!\n");
954 if (!(command & PCIM_CMD_MEMEN)) {
955 device_printf(dev, "failed to enable memory mapping!\n");
962 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE);
964 if (sc->ste_res == NULL) {
965 device_printf(dev, "couldn't map ports/memory\n");
970 sc->ste_btag = rman_get_bustag(sc->ste_res);
971 sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
974 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
975 RF_SHAREABLE | RF_ACTIVE);
977 if (sc->ste_irq == NULL) {
978 device_printf(dev, "couldn't map interrupt\n");
979 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
984 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET,
985 ste_intr, sc, &sc->ste_intrhand, NULL);
988 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
989 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
990 device_printf(dev, "couldn't set up irq\n");
994 callout_init(&sc->ste_stat_timer);
996 ifp = &sc->arpcom.ac_if;
997 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
999 /* Reset the adapter. */
1003 * Get station address from the EEPROM.
1005 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1006 STE_EEADDR_NODE0, 3, 0)) {
1007 device_printf(dev, "failed to read station address\n");
1008 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1009 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1010 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1015 /* Allocate the descriptor queues. */
1016 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
1017 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1019 if (sc->ste_ldata == NULL) {
1020 device_printf(dev, "no memory for list buffers!\n");
1021 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1022 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1023 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1028 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1031 if (mii_phy_probe(dev, &sc->ste_miibus,
1032 ste_ifmedia_upd, ste_ifmedia_sts)) {
1033 device_printf(dev, "MII without any phy!\n");
1034 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1035 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1036 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1037 contigfree(sc->ste_ldata,
1038 sizeof(struct ste_list_data), M_DEVBUF);
1044 ifp->if_mtu = ETHERMTU;
1045 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1046 ifp->if_ioctl = ste_ioctl;
1047 ifp->if_start = ste_start;
1048 ifp->if_watchdog = ste_watchdog;
1049 ifp->if_init = ste_init;
1050 ifp->if_baudrate = 10000000;
1051 ifq_set_maxlen(&ifp->if_snd, STE_TX_LIST_CNT - 1);
1052 ifq_set_ready(&ifp->if_snd);
1054 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1057 * Call MI attach routine.
1059 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1062 * Tell the upper layer(s) we support long frames.
1064 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1071 static int ste_detach(dev)
1074 struct ste_softc *sc;
1079 sc = device_get_softc(dev);
1080 ifp = &sc->arpcom.ac_if;
1083 ether_ifdetach(ifp);
1085 bus_generic_detach(dev);
1086 device_delete_child(dev, sc->ste_miibus);
1088 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1089 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1090 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1092 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF);
1099 static int ste_newbuf(sc, c, m)
1100 struct ste_softc *sc;
1101 struct ste_chain_onefrag *c;
1104 struct mbuf *m_new = NULL;
1107 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1110 MCLGET(m_new, MB_DONTWAIT);
1111 if (!(m_new->m_flags & M_EXT)) {
1115 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1118 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1119 m_new->m_data = m_new->m_ext.ext_buf;
1122 m_adj(m_new, ETHER_ALIGN);
1124 c->ste_mbuf = m_new;
1125 c->ste_ptr->ste_status = 0;
1126 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
1127 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST;
1132 static int ste_init_rx_list(sc)
1133 struct ste_softc *sc;
1135 struct ste_chain_data *cd;
1136 struct ste_list_data *ld;
1139 cd = &sc->ste_cdata;
1142 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1143 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1144 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
1146 if (i == (STE_RX_LIST_CNT - 1)) {
1147 cd->ste_rx_chain[i].ste_next =
1148 &cd->ste_rx_chain[0];
1149 ld->ste_rx_list[i].ste_next =
1150 vtophys(&ld->ste_rx_list[0]);
1152 cd->ste_rx_chain[i].ste_next =
1153 &cd->ste_rx_chain[i + 1];
1154 ld->ste_rx_list[i].ste_next =
1155 vtophys(&ld->ste_rx_list[i + 1]);
1157 ld->ste_rx_list[i].ste_status = 0;
1160 cd->ste_rx_head = &cd->ste_rx_chain[0];
1165 static void ste_init_tx_list(sc)
1166 struct ste_softc *sc;
1168 struct ste_chain_data *cd;
1169 struct ste_list_data *ld;
1172 cd = &sc->ste_cdata;
1174 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1175 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1176 cd->ste_tx_chain[i].ste_ptr->ste_next = 0;
1177 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0;
1178 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
1179 if (i == (STE_TX_LIST_CNT - 1))
1180 cd->ste_tx_chain[i].ste_next =
1181 &cd->ste_tx_chain[0];
1183 cd->ste_tx_chain[i].ste_next =
1184 &cd->ste_tx_chain[i + 1];
1186 cd->ste_tx_chain[i].ste_prev =
1187 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1];
1189 cd->ste_tx_chain[i].ste_prev =
1190 &cd->ste_tx_chain[i - 1];
1193 cd->ste_tx_prod = 0;
1194 cd->ste_tx_cons = 0;
1200 static void ste_init(xsc)
1203 struct ste_softc *sc;
1206 struct mii_data *mii;
1211 ifp = &sc->arpcom.ac_if;
1212 mii = device_get_softc(sc->ste_miibus);
1216 /* Init our MAC address */
1217 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1218 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1222 if (ste_init_rx_list(sc) == ENOBUFS) {
1223 if_printf(ifp, "initialization failed: no "
1224 "memory for RX buffers\n");
1230 /* Set RX polling interval */
1231 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1);
1233 /* Init TX descriptors */
1234 ste_init_tx_list(sc);
1236 /* Set the TX freethresh value */
1237 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1239 /* Set the TX start threshold for best performance. */
1240 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1242 /* Set the TX reclaim threshold. */
1243 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1245 /* Set up the RX filter. */
1246 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
1248 /* If we want promiscuous mode, set the allframes bit. */
1249 if (ifp->if_flags & IFF_PROMISC) {
1250 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1252 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1255 /* Set capture broadcast bit to accept broadcast frames. */
1256 if (ifp->if_flags & IFF_BROADCAST) {
1257 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1259 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1264 /* Load the address of the RX list. */
1265 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1267 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1268 vtophys(&sc->ste_ldata->ste_rx_list[0]));
1269 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1270 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1272 /* Set TX polling interval (defer until we TX first packet */
1273 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1275 /* Load address of the TX list */
1276 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1278 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1279 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1280 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1282 sc->ste_tx_prev_idx=-1;
1284 /* Enable receiver and transmitter */
1285 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1286 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1287 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1288 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1290 /* Enable stats counters. */
1291 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1293 /* Enable interrupts. */
1294 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1295 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1297 /* Accept VLAN length packets */
1298 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN);
1300 ste_ifmedia_upd(ifp);
1302 ifp->if_flags |= IFF_RUNNING;
1303 ifp->if_flags &= ~IFF_OACTIVE;
1307 callout_reset(&sc->ste_stat_timer, hz, ste_stats_update, sc);
1312 static void ste_stop(sc)
1313 struct ste_softc *sc;
1318 ifp = &sc->arpcom.ac_if;
1320 callout_stop(&sc->ste_stat_timer);
1322 CSR_WRITE_2(sc, STE_IMR, 0);
1323 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
1324 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
1325 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
1326 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1327 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1330 * Try really hard to stop the RX engine or under heavy RX
1331 * data chip will write into de-allocated memory.
1337 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1338 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
1339 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
1340 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
1344 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1345 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
1346 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
1347 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
1351 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1353 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1358 static void ste_reset(sc)
1359 struct ste_softc *sc;
1363 STE_SETBIT4(sc, STE_ASICCTL,
1364 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
1365 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
1366 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
1367 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
1368 STE_ASICCTL_EXTRESET_RESET);
1372 for (i = 0; i < STE_TIMEOUT; i++) {
1373 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1377 if (i == STE_TIMEOUT)
1378 if_printf(&sc->arpcom.ac_if, "global reset never completed\n");
1383 static int ste_ioctl(ifp, command, data, cr)
1389 struct ste_softc *sc;
1391 struct mii_data *mii;
1397 ifr = (struct ifreq *)data;
1401 if (ifp->if_flags & IFF_UP) {
1402 if (ifp->if_flags & IFF_RUNNING &&
1403 ifp->if_flags & IFF_PROMISC &&
1404 !(sc->ste_if_flags & IFF_PROMISC)) {
1405 STE_SETBIT1(sc, STE_RX_MODE,
1406 STE_RXMODE_PROMISC);
1407 } else if (ifp->if_flags & IFF_RUNNING &&
1408 !(ifp->if_flags & IFF_PROMISC) &&
1409 sc->ste_if_flags & IFF_PROMISC) {
1410 STE_CLRBIT1(sc, STE_RX_MODE,
1411 STE_RXMODE_PROMISC);
1413 if (!(ifp->if_flags & IFF_RUNNING)) {
1414 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1418 if (ifp->if_flags & IFF_RUNNING)
1421 sc->ste_if_flags = ifp->if_flags;
1431 mii = device_get_softc(sc->ste_miibus);
1432 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1435 error = ether_ioctl(ifp, command, data);
1444 static int ste_encap(sc, c, m_head)
1445 struct ste_softc *sc;
1446 struct ste_chain *c;
1447 struct mbuf *m_head;
1450 struct ste_frag *f = NULL;
1459 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1460 if (m->m_len != 0) {
1461 if (frag == STE_MAXFRAGS)
1463 total_len += m->m_len;
1464 f = &d->ste_frags[frag];
1465 f->ste_addr = vtophys(mtod(m, vm_offset_t));
1466 f->ste_len = m->m_len;
1475 * We ran out of segments. We have to recopy this
1476 * mbuf chain first. Bail out if we can't get the
1477 * new buffers. Code borrowed from if_fxp.c.
1479 MGETHDR(mn, MB_DONTWAIT, MT_DATA);
1484 if (m_head->m_pkthdr.len > MHLEN) {
1485 MCLGET(mn, MB_DONTWAIT);
1486 if ((mn->m_flags & M_EXT) == 0) {
1492 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1494 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len;
1500 c->ste_mbuf = m_head;
1501 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
1507 static void ste_start(ifp)
1510 struct ste_softc *sc;
1511 struct mbuf *m_head = NULL;
1512 struct ste_chain *cur_tx = NULL;
1520 if (ifp->if_flags & IFF_OACTIVE)
1523 idx = sc->ste_cdata.ste_tx_prod;
1525 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
1527 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) {
1528 ifp->if_flags |= IFF_OACTIVE;
1532 m_head = ifq_dequeue(&ifp->if_snd);
1536 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
1538 if (ste_encap(sc, cur_tx, m_head) != 0)
1541 cur_tx->ste_ptr->ste_next = 0;
1543 if(sc->ste_tx_prev_idx < 0){
1544 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1545 /* Load address of the TX list */
1546 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1549 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1550 vtophys(&sc->ste_ldata->ste_tx_list[0]));
1552 /* Set TX polling interval to start TX engine */
1553 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1555 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1558 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1559 sc->ste_cdata.ste_tx_chain[
1560 sc->ste_tx_prev_idx].ste_ptr->ste_next
1564 sc->ste_tx_prev_idx=idx;
1566 BPF_MTAP(ifp, cur_tx->ste_mbuf);
1568 STE_INC(idx, STE_TX_LIST_CNT);
1569 sc->ste_cdata.ste_tx_cnt++;
1571 sc->ste_cdata.ste_tx_prod = idx;
1577 static void ste_watchdog(ifp)
1580 struct ste_softc *sc;
1585 if_printf(ifp, "watchdog timeout\n");
1593 if (!ifq_is_empty(&ifp->if_snd))
1599 static void ste_shutdown(dev)
1602 struct ste_softc *sc;
1604 sc = device_get_softc(dev);