2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/if_ringmap.h>
95 #include <net/toeplitz.h>
96 #include <net/toeplitz2.h>
97 #include <net/vlan/if_vlan_var.h>
98 #include <net/vlan/if_vlan_ether.h>
99 #include <net/if_poll.h>
101 #include <netinet/in_systm.h>
102 #include <netinet/in.h>
103 #include <netinet/ip.h>
104 #include <netinet/tcp.h>
105 #include <netinet/udp.h>
107 #include <bus/pci/pcivar.h>
108 #include <bus/pci/pcireg.h>
110 #include <dev/netif/ig_hal/e1000_api.h>
111 #include <dev/netif/ig_hal/e1000_82571.h>
112 #include <dev/netif/ig_hal/e1000_dragonfly.h>
113 #include <dev/netif/emx/if_emx.h>
118 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
120 if (sc->rss_debug >= lvl) \
121 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
123 #else /* !EMX_RSS_DEBUG */
124 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
125 #endif /* EMX_RSS_DEBUG */
127 #define EMX_NAME "Intel(R) PRO/1000 "
129 #define EMX_DEVICE(id) \
130 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
131 #define EMX_DEVICE_NULL { 0, 0, NULL }
133 static const struct emx_device {
138 EMX_DEVICE(82571EB_COPPER),
139 EMX_DEVICE(82571EB_FIBER),
140 EMX_DEVICE(82571EB_SERDES),
141 EMX_DEVICE(82571EB_SERDES_DUAL),
142 EMX_DEVICE(82571EB_SERDES_QUAD),
143 EMX_DEVICE(82571EB_QUAD_COPPER),
144 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
145 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
146 EMX_DEVICE(82571EB_QUAD_FIBER),
147 EMX_DEVICE(82571PT_QUAD_COPPER),
149 EMX_DEVICE(82572EI_COPPER),
150 EMX_DEVICE(82572EI_FIBER),
151 EMX_DEVICE(82572EI_SERDES),
155 EMX_DEVICE(82573E_IAMT),
158 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
159 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
160 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
161 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
166 EMX_DEVICE(PCH_LPT_I217_LM),
167 EMX_DEVICE(PCH_LPT_I217_V),
168 EMX_DEVICE(PCH_LPTLP_I218_LM),
169 EMX_DEVICE(PCH_LPTLP_I218_V),
170 EMX_DEVICE(PCH_I218_LM2),
171 EMX_DEVICE(PCH_I218_V2),
172 EMX_DEVICE(PCH_I218_LM3),
173 EMX_DEVICE(PCH_I218_V3),
174 EMX_DEVICE(PCH_SPT_I219_LM),
175 EMX_DEVICE(PCH_SPT_I219_V),
176 EMX_DEVICE(PCH_SPT_I219_LM2),
177 EMX_DEVICE(PCH_SPT_I219_V2),
179 /* required last entry */
183 static int emx_probe(device_t);
184 static int emx_attach(device_t);
185 static int emx_detach(device_t);
186 static int emx_shutdown(device_t);
187 static int emx_suspend(device_t);
188 static int emx_resume(device_t);
190 static void emx_init(void *);
191 static void emx_stop(struct emx_softc *);
192 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
193 static void emx_start(struct ifnet *, struct ifaltq_subque *);
195 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
196 static void emx_npoll_status(struct ifnet *);
197 static void emx_npoll_tx(struct ifnet *, void *, int);
198 static void emx_npoll_rx(struct ifnet *, void *, int);
200 static void emx_watchdog(struct ifaltq_subque *);
201 static void emx_media_status(struct ifnet *, struct ifmediareq *);
202 static int emx_media_change(struct ifnet *);
203 static void emx_timer(void *);
204 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
205 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
206 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
208 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
212 static void emx_intr(void *);
213 static void emx_intr_mask(void *);
214 static void emx_intr_body(struct emx_softc *, boolean_t);
215 static void emx_rxeof(struct emx_rxdata *, int);
216 static void emx_txeof(struct emx_txdata *);
217 static void emx_tx_collect(struct emx_txdata *);
218 static void emx_tx_purge(struct emx_softc *);
219 static void emx_enable_intr(struct emx_softc *);
220 static void emx_disable_intr(struct emx_softc *);
222 static int emx_dma_alloc(struct emx_softc *);
223 static void emx_dma_free(struct emx_softc *);
224 static void emx_init_tx_ring(struct emx_txdata *);
225 static int emx_init_rx_ring(struct emx_rxdata *);
226 static void emx_free_tx_ring(struct emx_txdata *);
227 static void emx_free_rx_ring(struct emx_rxdata *);
228 static int emx_create_tx_ring(struct emx_txdata *);
229 static int emx_create_rx_ring(struct emx_rxdata *);
230 static void emx_destroy_tx_ring(struct emx_txdata *, int);
231 static void emx_destroy_rx_ring(struct emx_rxdata *, int);
232 static int emx_newbuf(struct emx_rxdata *, int, int);
233 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *);
234 static int emx_txcsum(struct emx_txdata *, struct mbuf *,
235 uint32_t *, uint32_t *);
236 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **);
237 static int emx_tso_setup(struct emx_txdata *, struct mbuf *,
238 uint32_t *, uint32_t *);
239 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t);
241 static int emx_is_valid_eaddr(const uint8_t *);
242 static int emx_reset(struct emx_softc *);
243 static void emx_setup_ifp(struct emx_softc *);
244 static void emx_init_tx_unit(struct emx_softc *);
245 static void emx_init_rx_unit(struct emx_softc *);
246 static void emx_update_stats(struct emx_softc *);
247 static void emx_set_promisc(struct emx_softc *);
248 static void emx_disable_promisc(struct emx_softc *);
249 static void emx_set_multi(struct emx_softc *);
250 static void emx_update_link_status(struct emx_softc *);
251 static void emx_smartspeed(struct emx_softc *);
252 static void emx_set_itr(struct emx_softc *, uint32_t);
253 static void emx_disable_aspm(struct emx_softc *);
255 static void emx_print_debug_info(struct emx_softc *);
256 static void emx_print_nvm_info(struct emx_softc *);
257 static void emx_print_hw_stats(struct emx_softc *);
259 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
260 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
261 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
262 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
263 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
264 static void emx_add_sysctl(struct emx_softc *);
266 static void emx_serialize_skipmain(struct emx_softc *);
267 static void emx_deserialize_skipmain(struct emx_softc *);
269 /* Management and WOL Support */
270 static void emx_get_mgmt(struct emx_softc *);
271 static void emx_rel_mgmt(struct emx_softc *);
272 static void emx_get_hw_control(struct emx_softc *);
273 static void emx_rel_hw_control(struct emx_softc *);
274 static void emx_enable_wol(device_t);
276 static device_method_t emx_methods[] = {
277 /* Device interface */
278 DEVMETHOD(device_probe, emx_probe),
279 DEVMETHOD(device_attach, emx_attach),
280 DEVMETHOD(device_detach, emx_detach),
281 DEVMETHOD(device_shutdown, emx_shutdown),
282 DEVMETHOD(device_suspend, emx_suspend),
283 DEVMETHOD(device_resume, emx_resume),
287 static driver_t emx_driver = {
290 sizeof(struct emx_softc),
293 static devclass_t emx_devclass;
295 DECLARE_DUMMY_MODULE(if_emx);
296 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
297 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
302 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
303 static int emx_rxd = EMX_DEFAULT_RXD;
304 static int emx_txd = EMX_DEFAULT_TXD;
305 static int emx_smart_pwr_down = 0;
306 static int emx_rxr = 0;
307 static int emx_txr = 1;
309 /* Controls whether promiscuous also shows bad packets */
310 static int emx_debug_sbp = 0;
312 static int emx_82573_workaround = 1;
313 static int emx_msi_enable = 1;
315 static char emx_flowctrl[IFM_ETH_FC_STRLEN] = IFM_ETH_FC_RXPAUSE;
317 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
318 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
319 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
320 TUNABLE_INT("hw.emx.txd", &emx_txd);
321 TUNABLE_INT("hw.emx.txr", &emx_txr);
322 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
323 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
324 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
325 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
326 TUNABLE_STR("hw.emx.flow_ctrl", emx_flowctrl, sizeof(emx_flowctrl));
328 /* Global used in WOL setup with multiport cards */
329 static int emx_global_quad_port_a = 0;
331 /* Set this to one to display debug statistics */
332 static int emx_display_debug_stats = 0;
334 #if !defined(KTR_IF_EMX)
335 #define KTR_IF_EMX KTR_ALL
337 KTR_INFO_MASTER(if_emx);
338 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
339 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
340 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
341 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
342 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
343 #define logif(name) KTR_LOG(if_emx_ ## name)
346 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
348 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
349 /* DD bit must be cleared */
350 rxd->rxd_staterr = 0;
354 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
356 /* Ignore Checksum bit is set */
357 if (staterr & E1000_RXD_STAT_IXSM)
360 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
362 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
364 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
365 E1000_RXD_STAT_TCPCS) {
366 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
368 CSUM_FRAG_NOT_CHECKED;
369 mp->m_pkthdr.csum_data = htons(0xffff);
373 static __inline struct pktinfo *
374 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
375 uint32_t mrq, uint32_t hash, uint32_t staterr)
377 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
378 case EMX_RXDMRQ_IPV4_TCP:
379 pi->pi_netisr = NETISR_IP;
381 pi->pi_l3proto = IPPROTO_TCP;
384 case EMX_RXDMRQ_IPV6_TCP:
385 pi->pi_netisr = NETISR_IPV6;
387 pi->pi_l3proto = IPPROTO_TCP;
390 case EMX_RXDMRQ_IPV4:
391 if (staterr & E1000_RXD_STAT_IXSM)
395 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
396 E1000_RXD_STAT_TCPCS) {
397 pi->pi_netisr = NETISR_IP;
399 pi->pi_l3proto = IPPROTO_UDP;
407 m_sethash(m, toeplitz_hash(hash));
412 emx_probe(device_t dev)
414 const struct emx_device *d;
417 vid = pci_get_vendor(dev);
418 did = pci_get_device(dev);
420 for (d = emx_devices; d->desc != NULL; ++d) {
421 if (vid == d->vid && did == d->did) {
422 device_set_desc(dev, d->desc);
423 device_set_async_attach(dev, TRUE);
431 emx_attach(device_t dev)
433 struct emx_softc *sc = device_get_softc(dev);
434 int error = 0, i, throttle, msi_enable;
435 int tx_ring_max, ring_cnt;
437 uint16_t eeprom_data, device_id, apme_mask;
438 driver_intr_t *intr_func;
439 char flowctrl[IFM_ETH_FC_STRLEN];
444 for (i = 0; i < EMX_NRX_RING; ++i) {
445 sc->rx_data[i].sc = sc;
446 sc->rx_data[i].idx = i;
452 for (i = 0; i < EMX_NTX_RING; ++i) {
453 sc->tx_data[i].sc = sc;
454 sc->tx_data[i].idx = i;
458 * Initialize serializers
460 lwkt_serialize_init(&sc->main_serialize);
461 for (i = 0; i < EMX_NTX_RING; ++i)
462 lwkt_serialize_init(&sc->tx_data[i].tx_serialize);
463 for (i = 0; i < EMX_NRX_RING; ++i)
464 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
467 * Initialize serializer array
471 KKASSERT(i < EMX_NSERIALIZE);
472 sc->serializes[i++] = &sc->main_serialize;
474 KKASSERT(i < EMX_NSERIALIZE);
475 sc->serializes[i++] = &sc->tx_data[0].tx_serialize;
476 KKASSERT(i < EMX_NSERIALIZE);
477 sc->serializes[i++] = &sc->tx_data[1].tx_serialize;
479 KKASSERT(i < EMX_NSERIALIZE);
480 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
481 KKASSERT(i < EMX_NSERIALIZE);
482 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
484 KKASSERT(i == EMX_NSERIALIZE);
486 ifmedia_init(&sc->media, IFM_IMASK | IFM_ETH_FCMASK,
487 emx_media_change, emx_media_status);
488 callout_init_mp(&sc->timer);
490 sc->dev = sc->osdep.dev = dev;
493 * Determine hardware and mac type
495 sc->hw.vendor_id = pci_get_vendor(dev);
496 sc->hw.device_id = pci_get_device(dev);
497 sc->hw.revision_id = pci_get_revid(dev);
498 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
499 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
501 if (e1000_set_mac_type(&sc->hw))
504 /* Enable bus mastering */
505 pci_enable_busmaster(dev);
510 sc->memory_rid = EMX_BAR_MEM;
511 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
512 &sc->memory_rid, RF_ACTIVE);
513 if (sc->memory == NULL) {
514 device_printf(dev, "Unable to allocate bus resource: memory\n");
518 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
519 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
521 /* XXX This is quite goofy, it is not actually used */
522 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
525 * Don't enable MSI-X on 82574, see:
526 * 82574 specification update errata #15
528 * Don't enable MSI on 82571/82572, see:
529 * 82571/82572 specification update errata #63
531 msi_enable = emx_msi_enable;
533 (sc->hw.mac.type == e1000_82571 ||
534 sc->hw.mac.type == e1000_82572))
540 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
541 &sc->intr_rid, &intr_flags);
543 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
546 unshared = device_getenv_int(dev, "irq.unshared", 0);
548 sc->flags |= EMX_FLAG_SHARED_INTR;
550 device_printf(dev, "IRQ shared\n");
552 intr_flags &= ~RF_SHAREABLE;
554 device_printf(dev, "IRQ unshared\n");
558 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
560 if (sc->intr_res == NULL) {
561 device_printf(dev, "Unable to allocate bus resource: %s\n",
562 sc->intr_type == PCI_INTR_TYPE_MSI ? "MSI" : "legacy intr");
564 /* Retry with MSI. */
566 sc->flags &= ~EMX_FLAG_SHARED_INTR;
573 /* Save PCI command register for Shared Code */
574 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
575 sc->hw.back = &sc->osdep;
578 * For I217/I218, we need to map the flash memory and this
579 * must happen after the MAC is identified.
581 if (sc->hw.mac.type == e1000_pch_lpt) {
582 sc->flash_rid = EMX_BAR_FLASH;
584 sc->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
585 &sc->flash_rid, RF_ACTIVE);
586 if (sc->flash == NULL) {
587 device_printf(dev, "Mapping of Flash failed\n");
591 sc->osdep.flash_bus_space_tag = rman_get_bustag(sc->flash);
592 sc->osdep.flash_bus_space_handle =
593 rman_get_bushandle(sc->flash);
596 * This is used in the shared code
597 * XXX this goof is actually not used.
599 sc->hw.flash_address = (uint8_t *)sc->flash;
602 /* Do Shared Code initialization */
603 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
604 device_printf(dev, "Setup of Shared code failed\n");
608 e1000_get_bus_info(&sc->hw);
610 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
611 sc->hw.phy.autoneg_wait_to_complete = FALSE;
612 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
615 * Interrupt throttle rate
617 throttle = device_getenv_int(dev, "int_throttle_ceil",
618 emx_int_throttle_ceil);
620 sc->int_throttle_ceil = 0;
623 throttle = EMX_DEFAULT_ITR;
625 /* Recalculate the tunable value to get the exact frequency. */
626 throttle = 1000000000 / 256 / throttle;
628 /* Upper 16bits of ITR is reserved and should be zero */
629 if (throttle & 0xffff0000)
630 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
632 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
635 e1000_init_script_state_82541(&sc->hw, TRUE);
636 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
639 if (sc->hw.phy.media_type == e1000_media_type_copper) {
640 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
641 sc->hw.phy.disable_polarity_correction = FALSE;
642 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
645 /* Set the frame limits assuming standard ethernet sized frames. */
646 sc->hw.mac.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
648 /* This controls when hardware reports transmit completion status. */
649 sc->hw.mac.report_tx_early = 1;
652 * Calculate # of RX/TX rings
654 ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
655 sc->rx_rmap = if_ringmap_alloc(dev, ring_cnt, EMX_NRX_RING);
658 if (sc->hw.mac.type == e1000_82571 ||
659 sc->hw.mac.type == e1000_82572 ||
660 sc->hw.mac.type == e1000_80003es2lan ||
661 sc->hw.mac.type == e1000_pch_lpt ||
662 sc->hw.mac.type == e1000_pch_spt ||
663 sc->hw.mac.type == e1000_82574)
664 tx_ring_max = EMX_NTX_RING;
665 ring_cnt = device_getenv_int(dev, "txr", emx_txr);
666 sc->tx_rmap = if_ringmap_alloc(dev, ring_cnt, tx_ring_max);
668 if_ringmap_match(dev, sc->rx_rmap, sc->tx_rmap);
669 sc->rx_ring_cnt = if_ringmap_count(sc->rx_rmap);
670 sc->tx_ring_cnt = if_ringmap_count(sc->tx_rmap);
672 /* Allocate RX/TX rings' busdma(9) stuffs */
673 error = emx_dma_alloc(sc);
677 /* Allocate multicast array memory. */
678 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
681 /* Indicate SOL/IDER usage */
682 if (e1000_check_reset_block(&sc->hw)) {
684 "PHY reset is blocked due to SOL/IDER session.\n");
687 /* Disable EEE on I217/I218 */
688 sc->hw.dev_spec.ich8lan.eee_disable = 1;
691 * Start from a known state, this is important in reading the
692 * nvm and mac from that.
694 e1000_reset_hw(&sc->hw);
696 /* Make sure we have a good EEPROM before we read from it */
697 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
699 * Some PCI-E parts fail the first check due to
700 * the link being in sleep state, call it again,
701 * if it fails a second time its a real issue.
703 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
705 "The EEPROM Checksum Is Not Valid\n");
711 /* Copy the permanent MAC address out of the EEPROM */
712 if (e1000_read_mac_addr(&sc->hw) < 0) {
713 device_printf(dev, "EEPROM read error while reading MAC"
718 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
719 device_printf(dev, "Invalid MAC address\n");
724 /* Disable ULP support */
725 e1000_disable_ulp_lpt_lp(&sc->hw, TRUE);
727 /* Determine if we have to control management hardware */
728 if (e1000_enable_mng_pass_thru(&sc->hw))
729 sc->flags |= EMX_FLAG_HAS_MGMT;
734 apme_mask = EMX_EEPROM_APME;
736 switch (sc->hw.mac.type) {
738 sc->flags |= EMX_FLAG_HAS_AMT;
743 case e1000_80003es2lan:
744 if (sc->hw.bus.func == 1) {
745 e1000_read_nvm(&sc->hw,
746 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
748 e1000_read_nvm(&sc->hw,
749 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
754 e1000_read_nvm(&sc->hw,
755 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
758 if (eeprom_data & apme_mask)
759 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
762 * We have the eeprom settings, now apply the special cases
763 * where the eeprom may be wrong or the board won't support
764 * wake on lan on a particular port
766 device_id = pci_get_device(dev);
768 case E1000_DEV_ID_82571EB_FIBER:
770 * Wake events only supported on port A for dual fiber
771 * regardless of eeprom setting
773 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
778 case E1000_DEV_ID_82571EB_QUAD_COPPER:
779 case E1000_DEV_ID_82571EB_QUAD_FIBER:
780 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
781 /* if quad port sc, disable WoL on all but port A */
782 if (emx_global_quad_port_a != 0)
784 /* Reset for multiple quad port adapters */
785 if (++emx_global_quad_port_a == 4)
786 emx_global_quad_port_a = 0;
790 /* XXX disable wol */
793 /* Initialized #of TX rings to use. */
794 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE);
796 /* Setup flow control. */
797 device_getenv_string(dev, "flow_ctrl", flowctrl, sizeof(flowctrl),
799 sc->ifm_flowctrl = ifmedia_str2ethfc(flowctrl);
801 /* Setup OS specific network interface */
804 /* Add sysctl tree, must after em_setup_ifp() */
807 /* Reset the hardware */
808 error = emx_reset(sc);
811 * Some 82573 parts fail the first reset, call it again,
812 * if it fails a second time its a real issue.
814 error = emx_reset(sc);
816 device_printf(dev, "Unable to reset the hardware\n");
817 ether_ifdetach(&sc->arpcom.ac_if);
822 /* Initialize statistics */
823 emx_update_stats(sc);
825 sc->hw.mac.get_link_status = 1;
826 emx_update_link_status(sc);
828 /* Non-AMT based hardware can now take control from firmware */
829 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
831 emx_get_hw_control(sc);
834 * Missing Interrupt Following ICR read:
836 * 82571/82572 specification update errata #76
837 * 82573 specification update errata #31
838 * 82574 specification update errata #12
840 intr_func = emx_intr;
841 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
842 (sc->hw.mac.type == e1000_82571 ||
843 sc->hw.mac.type == e1000_82572 ||
844 sc->hw.mac.type == e1000_82573 ||
845 sc->hw.mac.type == e1000_82574))
846 intr_func = emx_intr_mask;
848 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
849 &sc->intr_tag, &sc->main_serialize);
851 device_printf(dev, "Failed to register interrupt handler");
852 ether_ifdetach(&sc->arpcom.ac_if);
862 emx_detach(device_t dev)
864 struct emx_softc *sc = device_get_softc(dev);
866 if (device_is_attached(dev)) {
867 struct ifnet *ifp = &sc->arpcom.ac_if;
869 ifnet_serialize_all(ifp);
873 e1000_phy_hw_reset(&sc->hw);
876 emx_rel_hw_control(sc);
879 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
880 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
884 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
886 ifnet_deserialize_all(ifp);
889 } else if (sc->memory != NULL) {
890 emx_rel_hw_control(sc);
893 ifmedia_removeall(&sc->media);
894 bus_generic_detach(dev);
896 if (sc->intr_res != NULL) {
897 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
901 if (sc->intr_type == PCI_INTR_TYPE_MSI)
902 pci_release_msi(dev);
904 if (sc->memory != NULL) {
905 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
909 if (sc->flash != NULL) {
910 bus_release_resource(dev, SYS_RES_MEMORY, sc->flash_rid,
917 kfree(sc->mta, M_DEVBUF);
919 if (sc->rx_rmap != NULL)
920 if_ringmap_free(sc->rx_rmap);
921 if (sc->tx_rmap != NULL)
922 if_ringmap_free(sc->tx_rmap);
928 emx_shutdown(device_t dev)
930 return emx_suspend(dev);
934 emx_suspend(device_t dev)
936 struct emx_softc *sc = device_get_softc(dev);
937 struct ifnet *ifp = &sc->arpcom.ac_if;
939 ifnet_serialize_all(ifp);
944 emx_rel_hw_control(sc);
947 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
948 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
952 ifnet_deserialize_all(ifp);
954 return bus_generic_suspend(dev);
958 emx_resume(device_t dev)
960 struct emx_softc *sc = device_get_softc(dev);
961 struct ifnet *ifp = &sc->arpcom.ac_if;
964 ifnet_serialize_all(ifp);
968 for (i = 0; i < sc->tx_ring_inuse; ++i)
969 ifsq_devstart_sched(sc->tx_data[i].ifsq);
971 ifnet_deserialize_all(ifp);
973 return bus_generic_resume(dev);
977 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
979 struct emx_softc *sc = ifp->if_softc;
980 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
982 int idx = -1, nsegs = 0;
984 KKASSERT(tdata->ifsq == ifsq);
985 ASSERT_SERIALIZED(&tdata->tx_serialize);
987 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
990 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) {
995 while (!ifsq_is_empty(ifsq)) {
996 /* Now do we at least have a minimal? */
997 if (EMX_IS_OACTIVE(tdata)) {
998 emx_tx_collect(tdata);
999 if (EMX_IS_OACTIVE(tdata)) {
1000 ifsq_set_oactive(ifsq);
1006 m_head = ifsq_dequeue(ifsq);
1010 if (emx_encap(tdata, &m_head, &nsegs, &idx)) {
1011 IFNET_STAT_INC(ifp, oerrors, 1);
1012 emx_tx_collect(tdata);
1017 * TX interrupt are aggressively aggregated, so increasing
1018 * opackets at TX interrupt time will make the opackets
1019 * statistics vastly inaccurate; we do the opackets increment
1022 IFNET_STAT_INC(ifp, opackets, 1);
1024 if (nsegs >= tdata->tx_wreg_nsegs) {
1025 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1030 /* Send a copy of the frame to the BPF listener */
1031 ETHER_BPF_MTAP(ifp, m_head);
1033 /* Set timeout in case hardware has problems transmitting. */
1034 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1037 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1041 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1043 struct emx_softc *sc = ifp->if_softc;
1044 struct ifreq *ifr = (struct ifreq *)data;
1045 uint16_t eeprom_data = 0;
1046 int max_frame_size, mask, reinit;
1049 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1053 switch (sc->hw.mac.type) {
1056 * 82573 only supports jumbo frames
1057 * if ASPM is disabled.
1059 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
1061 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1062 max_frame_size = ETHER_MAX_LEN;
1067 /* Limit Jumbo Frame size */
1073 case e1000_80003es2lan:
1074 max_frame_size = 9234;
1078 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1081 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1087 ifp->if_mtu = ifr->ifr_mtu;
1088 sc->hw.mac.max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1091 if (ifp->if_flags & IFF_RUNNING)
1096 if (ifp->if_flags & IFF_UP) {
1097 if ((ifp->if_flags & IFF_RUNNING)) {
1098 if ((ifp->if_flags ^ sc->if_flags) &
1099 (IFF_PROMISC | IFF_ALLMULTI)) {
1100 emx_disable_promisc(sc);
1101 emx_set_promisc(sc);
1106 } else if (ifp->if_flags & IFF_RUNNING) {
1109 sc->if_flags = ifp->if_flags;
1114 if (ifp->if_flags & IFF_RUNNING) {
1115 emx_disable_intr(sc);
1117 #ifdef IFPOLL_ENABLE
1118 if (!(ifp->if_flags & IFF_NPOLLING))
1120 emx_enable_intr(sc);
1125 /* Check SOL/IDER usage */
1126 if (e1000_check_reset_block(&sc->hw)) {
1127 device_printf(sc->dev, "Media change is"
1128 " blocked due to SOL/IDER session.\n");
1134 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1139 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1140 if (mask & IFCAP_RXCSUM) {
1141 ifp->if_capenable ^= IFCAP_RXCSUM;
1144 if (mask & IFCAP_VLAN_HWTAGGING) {
1145 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1148 if (mask & IFCAP_TXCSUM) {
1149 ifp->if_capenable ^= IFCAP_TXCSUM;
1150 if (ifp->if_capenable & IFCAP_TXCSUM)
1151 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1153 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1155 if (mask & IFCAP_TSO) {
1156 ifp->if_capenable ^= IFCAP_TSO;
1157 if (ifp->if_capenable & IFCAP_TSO)
1158 ifp->if_hwassist |= CSUM_TSO;
1160 ifp->if_hwassist &= ~CSUM_TSO;
1162 if (mask & IFCAP_RSS)
1163 ifp->if_capenable ^= IFCAP_RSS;
1164 if (reinit && (ifp->if_flags & IFF_RUNNING))
1169 error = ether_ioctl(ifp, command, data);
1176 emx_watchdog(struct ifaltq_subque *ifsq)
1178 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1179 struct ifnet *ifp = ifsq_get_ifp(ifsq);
1180 struct emx_softc *sc = ifp->if_softc;
1183 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1186 * The timer is set to 5 every time start queues a packet.
1187 * Then txeof keeps resetting it as long as it cleans at
1188 * least one descriptor.
1189 * Finally, anytime all descriptors are clean the timer is
1193 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) ==
1194 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) {
1196 * If we reach here, all TX jobs are completed and
1197 * the TX engine should have been idled for some time.
1198 * We don't need to call ifsq_devstart_sched() here.
1200 ifsq_clr_oactive(ifsq);
1201 tdata->tx_watchdog.wd_timer = 0;
1206 * If we are in this routine because of pause frames, then
1207 * don't reset the hardware.
1209 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1210 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1214 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx);
1216 IFNET_STAT_INC(ifp, oerrors, 1);
1219 for (i = 0; i < sc->tx_ring_inuse; ++i)
1220 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1226 struct emx_softc *sc = xsc;
1227 struct ifnet *ifp = &sc->arpcom.ac_if;
1228 device_t dev = sc->dev;
1232 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1236 /* Get the latest mac address, User can use a LAA */
1237 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1239 /* Put the address into the Receive Address Array */
1240 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1243 * With the 82571 sc, RAR[0] may be overwritten
1244 * when the other port is reset, we make a duplicate
1245 * in RAR[14] for that eventuality, this assures
1246 * the interface continues to function.
1248 if (sc->hw.mac.type == e1000_82571) {
1249 e1000_set_laa_state_82571(&sc->hw, TRUE);
1250 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1251 E1000_RAR_ENTRIES - 1);
1254 /* Initialize the hardware */
1255 if (emx_reset(sc)) {
1256 device_printf(dev, "Unable to reset the hardware\n");
1257 /* XXX emx_stop()? */
1260 emx_update_link_status(sc);
1262 /* Setup VLAN support, basic and offload if available */
1263 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1265 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1268 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1269 ctrl |= E1000_CTRL_VME;
1270 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1273 /* Configure for OS presence */
1277 #ifdef IFPOLL_ENABLE
1278 if (ifp->if_flags & IFF_NPOLLING)
1281 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling);
1282 ifq_set_subq_divisor(&ifp->if_snd, sc->tx_ring_inuse);
1284 /* Prepare transmit descriptors and buffers */
1285 for (i = 0; i < sc->tx_ring_inuse; ++i)
1286 emx_init_tx_ring(&sc->tx_data[i]);
1287 emx_init_tx_unit(sc);
1289 /* Setup Multicast table */
1292 /* Prepare receive descriptors and buffers */
1293 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1294 if (emx_init_rx_ring(&sc->rx_data[i])) {
1296 "Could not setup receive structures\n");
1301 emx_init_rx_unit(sc);
1303 /* Don't lose promiscuous settings */
1304 emx_set_promisc(sc);
1306 ifp->if_flags |= IFF_RUNNING;
1307 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1308 ifsq_clr_oactive(sc->tx_data[i].ifsq);
1309 ifsq_watchdog_start(&sc->tx_data[i].tx_watchdog);
1312 callout_reset(&sc->timer, hz, emx_timer, sc);
1313 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1315 /* MSI/X configuration for 82574 */
1316 if (sc->hw.mac.type == e1000_82574) {
1319 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1320 tmp |= E1000_CTRL_EXT_PBA_CLR;
1321 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1324 * Set the IVAR - interrupt vector routing.
1325 * Each nibble represents a vector, high bit
1326 * is enable, other 3 bits are the MSIX table
1327 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1328 * Link (other) to 2, hence the magic number.
1330 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1334 * Only enable interrupts if we are not polling, make sure
1335 * they are off otherwise.
1338 emx_disable_intr(sc);
1340 emx_enable_intr(sc);
1342 /* AMT based hardware can now take control from firmware */
1343 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1344 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1345 emx_get_hw_control(sc);
1351 emx_intr_body(xsc, TRUE);
1355 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1357 struct ifnet *ifp = &sc->arpcom.ac_if;
1361 ASSERT_SERIALIZED(&sc->main_serialize);
1363 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1365 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1371 * XXX: some laptops trigger several spurious interrupts
1372 * on emx(4) when in the resume cycle. The ICR register
1373 * reports all-ones value in this case. Processing such
1374 * interrupts would lead to a freeze. I don't know why.
1376 if (reg_icr == 0xffffffff) {
1381 if (ifp->if_flags & IFF_RUNNING) {
1383 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1386 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1387 lwkt_serialize_enter(
1388 &sc->rx_data[i].rx_serialize);
1389 emx_rxeof(&sc->rx_data[i], -1);
1390 lwkt_serialize_exit(
1391 &sc->rx_data[i].rx_serialize);
1394 if (reg_icr & E1000_ICR_TXDW) {
1395 struct emx_txdata *tdata = &sc->tx_data[0];
1397 lwkt_serialize_enter(&tdata->tx_serialize);
1399 if (!ifsq_is_empty(tdata->ifsq))
1400 ifsq_devstart(tdata->ifsq);
1401 lwkt_serialize_exit(&tdata->tx_serialize);
1405 /* Link status change */
1406 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1407 emx_serialize_skipmain(sc);
1409 callout_stop(&sc->timer);
1410 sc->hw.mac.get_link_status = 1;
1411 emx_update_link_status(sc);
1413 /* Deal with TX cruft when link lost */
1416 callout_reset(&sc->timer, hz, emx_timer, sc);
1418 emx_deserialize_skipmain(sc);
1421 if (reg_icr & E1000_ICR_RXO)
1428 emx_intr_mask(void *xsc)
1430 struct emx_softc *sc = xsc;
1432 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1435 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1436 * so don't check it.
1438 emx_intr_body(sc, FALSE);
1439 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1443 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1445 struct emx_softc *sc = ifp->if_softc;
1447 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1449 emx_update_link_status(sc);
1451 ifmr->ifm_status = IFM_AVALID;
1452 ifmr->ifm_active = IFM_ETHER;
1454 if (!sc->link_active) {
1455 if (sc->hw.mac.autoneg)
1456 ifmr->ifm_active |= IFM_NONE;
1458 ifmr->ifm_active |= sc->media.ifm_media;
1462 ifmr->ifm_status |= IFM_ACTIVE;
1463 if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE)
1464 ifmr->ifm_active |= sc->ifm_flowctrl;
1466 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1467 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1468 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1470 switch (sc->link_speed) {
1472 ifmr->ifm_active |= IFM_10_T;
1475 ifmr->ifm_active |= IFM_100_TX;
1479 ifmr->ifm_active |= IFM_1000_T;
1482 if (sc->link_duplex == FULL_DUPLEX)
1483 ifmr->ifm_active |= IFM_FDX;
1485 ifmr->ifm_active |= IFM_HDX;
1487 if (ifmr->ifm_active & IFM_FDX)
1488 ifmr->ifm_active |= e1000_fc2ifmedia(sc->hw.fc.current_mode);
1492 emx_media_change(struct ifnet *ifp)
1494 struct emx_softc *sc = ifp->if_softc;
1495 struct ifmedia *ifm = &sc->media;
1497 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1499 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1502 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1504 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1505 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1510 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1511 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1515 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
1516 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1518 if (IFM_OPTIONS(ifm->ifm_media) &
1519 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1521 if_printf(ifp, "Flow control is not "
1522 "allowed for half-duplex\n");
1526 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1528 sc->hw.mac.autoneg = FALSE;
1529 sc->hw.phy.autoneg_advertised = 0;
1533 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
1534 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1536 if (IFM_OPTIONS(ifm->ifm_media) &
1537 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1539 if_printf(ifp, "Flow control is not "
1540 "allowed for half-duplex\n");
1544 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1546 sc->hw.mac.autoneg = FALSE;
1547 sc->hw.phy.autoneg_advertised = 0;
1552 if_printf(ifp, "Unsupported media type %d\n",
1553 IFM_SUBTYPE(ifm->ifm_media));
1557 sc->ifm_flowctrl = ifm->ifm_media & IFM_ETH_FCMASK;
1559 if (ifp->if_flags & IFF_RUNNING)
1566 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp,
1567 int *segs_used, int *idx)
1569 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1571 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1572 struct e1000_tx_desc *ctxd = NULL;
1573 struct mbuf *m_head = *m_headp;
1574 uint32_t txd_upper, txd_lower, cmd = 0;
1575 int maxsegs, nsegs, i, j, first, last = 0, error;
1577 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1578 error = emx_tso_pullup(tdata, m_headp);
1584 txd_upper = txd_lower = 0;
1587 * Capture the first descriptor index, this descriptor
1588 * will have the index of the EOP which is the only one
1589 * that now gets a DONE bit writeback.
1591 first = tdata->next_avail_tx_desc;
1592 tx_buffer = &tdata->tx_buf[first];
1593 tx_buffer_mapped = tx_buffer;
1594 map = tx_buffer->map;
1596 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED;
1597 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc"));
1598 if (maxsegs > EMX_MAX_SCATTER)
1599 maxsegs = EMX_MAX_SCATTER;
1601 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp,
1602 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1608 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE);
1611 tdata->tx_nsegs += nsegs;
1612 *segs_used += nsegs;
1614 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1615 /* TSO will consume one TX desc */
1616 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower);
1617 tdata->tx_nsegs += i;
1619 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1620 /* TX csum offloading will consume one TX desc */
1621 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower);
1622 tdata->tx_nsegs += i;
1626 /* Handle VLAN tag */
1627 if (m_head->m_flags & M_VLANTAG) {
1628 /* Set the vlan id. */
1629 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16);
1630 /* Tell hardware to add tag */
1631 txd_lower |= htole32(E1000_TXD_CMD_VLE);
1634 i = tdata->next_avail_tx_desc;
1636 /* Set up our transmit descriptors */
1637 for (j = 0; j < nsegs; j++) {
1638 tx_buffer = &tdata->tx_buf[i];
1639 ctxd = &tdata->tx_desc_base[i];
1641 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1642 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1643 txd_lower | segs[j].ds_len);
1644 ctxd->upper.data = htole32(txd_upper);
1647 if (++i == tdata->num_tx_desc)
1651 tdata->next_avail_tx_desc = i;
1653 KKASSERT(tdata->num_tx_desc_avail > nsegs);
1654 tdata->num_tx_desc_avail -= nsegs;
1656 tx_buffer->m_head = m_head;
1657 tx_buffer_mapped->map = tx_buffer->map;
1658 tx_buffer->map = map;
1660 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) {
1661 tdata->tx_nsegs = 0;
1664 * Report Status (RS) is turned on
1665 * every tx_intr_nsegs descriptors.
1667 cmd = E1000_TXD_CMD_RS;
1670 * Keep track of the descriptor, which will
1671 * be written back by hardware.
1673 tdata->tx_dd[tdata->tx_dd_tail] = last;
1674 EMX_INC_TXDD_IDX(tdata->tx_dd_tail);
1675 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head);
1679 * Last Descriptor of Packet needs End Of Packet (EOP)
1681 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1684 * Defer TDT updating, until enough descriptors are setup
1688 #ifdef EMX_TSS_DEBUG
1696 emx_set_promisc(struct emx_softc *sc)
1698 struct ifnet *ifp = &sc->arpcom.ac_if;
1701 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1703 if (ifp->if_flags & IFF_PROMISC) {
1704 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1705 /* Turn this on if you want to see bad packets */
1707 reg_rctl |= E1000_RCTL_SBP;
1708 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1709 } else if (ifp->if_flags & IFF_ALLMULTI) {
1710 reg_rctl |= E1000_RCTL_MPE;
1711 reg_rctl &= ~E1000_RCTL_UPE;
1712 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1717 emx_disable_promisc(struct emx_softc *sc)
1721 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1723 reg_rctl &= ~E1000_RCTL_UPE;
1724 reg_rctl &= ~E1000_RCTL_MPE;
1725 reg_rctl &= ~E1000_RCTL_SBP;
1726 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1730 emx_set_multi(struct emx_softc *sc)
1732 struct ifnet *ifp = &sc->arpcom.ac_if;
1733 struct ifmultiaddr *ifma;
1734 uint32_t reg_rctl = 0;
1739 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1741 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1742 if (ifma->ifma_addr->sa_family != AF_LINK)
1745 if (mcnt == EMX_MCAST_ADDR_MAX)
1748 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1749 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1753 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1754 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1755 reg_rctl |= E1000_RCTL_MPE;
1756 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1758 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1763 * This routine checks for link status and updates statistics.
1766 emx_timer(void *xsc)
1768 struct emx_softc *sc = xsc;
1769 struct ifnet *ifp = &sc->arpcom.ac_if;
1771 lwkt_serialize_enter(&sc->main_serialize);
1773 emx_update_link_status(sc);
1774 emx_update_stats(sc);
1776 /* Reset LAA into RAR[0] on 82571 */
1777 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1778 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1780 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1781 emx_print_hw_stats(sc);
1785 callout_reset(&sc->timer, hz, emx_timer, sc);
1787 lwkt_serialize_exit(&sc->main_serialize);
1791 emx_update_link_status(struct emx_softc *sc)
1793 struct e1000_hw *hw = &sc->hw;
1794 struct ifnet *ifp = &sc->arpcom.ac_if;
1795 device_t dev = sc->dev;
1796 uint32_t link_check = 0;
1798 /* Get the cached link value or read phy for real */
1799 switch (hw->phy.media_type) {
1800 case e1000_media_type_copper:
1801 if (hw->mac.get_link_status) {
1802 /* Do the work to read phy */
1803 e1000_check_for_link(hw);
1804 link_check = !hw->mac.get_link_status;
1805 if (link_check) /* ESB2 fix */
1806 e1000_cfg_on_link_up(hw);
1812 case e1000_media_type_fiber:
1813 e1000_check_for_link(hw);
1814 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1817 case e1000_media_type_internal_serdes:
1818 e1000_check_for_link(hw);
1819 link_check = sc->hw.mac.serdes_has_link;
1822 case e1000_media_type_unknown:
1827 /* Now check for a transition */
1828 if (link_check && sc->link_active == 0) {
1829 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1833 * Check if we should enable/disable SPEED_MODE bit on
1836 if (sc->link_speed != SPEED_1000 &&
1837 (hw->mac.type == e1000_82571 ||
1838 hw->mac.type == e1000_82572)) {
1841 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1842 tarc0 &= ~EMX_TARC_SPEED_MODE;
1843 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1846 char flowctrl[IFM_ETH_FC_STRLEN];
1848 e1000_fc2str(hw->fc.current_mode, flowctrl,
1850 device_printf(dev, "Link is up %d Mbps %s, "
1851 "Flow control: %s\n",
1853 (sc->link_duplex == FULL_DUPLEX) ?
1854 "Full Duplex" : "Half Duplex",
1857 if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE)
1858 e1000_force_flowctrl(hw, sc->ifm_flowctrl);
1859 sc->link_active = 1;
1861 ifp->if_baudrate = sc->link_speed * 1000000;
1862 ifp->if_link_state = LINK_STATE_UP;
1863 if_link_state_change(ifp);
1864 } else if (!link_check && sc->link_active == 1) {
1865 ifp->if_baudrate = sc->link_speed = 0;
1866 sc->link_duplex = 0;
1868 device_printf(dev, "Link is Down\n");
1869 sc->link_active = 0;
1870 ifp->if_link_state = LINK_STATE_DOWN;
1871 if_link_state_change(ifp);
1876 emx_stop(struct emx_softc *sc)
1878 struct ifnet *ifp = &sc->arpcom.ac_if;
1881 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1883 emx_disable_intr(sc);
1885 callout_stop(&sc->timer);
1887 ifp->if_flags &= ~IFF_RUNNING;
1888 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1889 struct emx_txdata *tdata = &sc->tx_data[i];
1891 ifsq_clr_oactive(tdata->ifsq);
1892 ifsq_watchdog_stop(&tdata->tx_watchdog);
1893 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED;
1897 * Disable multiple receive queues.
1900 * We should disable multiple receive queues before
1901 * resetting the hardware.
1903 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1905 e1000_reset_hw(&sc->hw);
1906 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1908 for (i = 0; i < sc->tx_ring_cnt; ++i)
1909 emx_free_tx_ring(&sc->tx_data[i]);
1910 for (i = 0; i < sc->rx_ring_cnt; ++i)
1911 emx_free_rx_ring(&sc->rx_data[i]);
1915 emx_reset(struct emx_softc *sc)
1917 device_t dev = sc->dev;
1918 uint16_t rx_buffer_size;
1921 /* Set up smart power down as default off on newer adapters. */
1922 if (!emx_smart_pwr_down &&
1923 (sc->hw.mac.type == e1000_82571 ||
1924 sc->hw.mac.type == e1000_82572)) {
1925 uint16_t phy_tmp = 0;
1927 /* Speed up time to link by disabling smart power down. */
1928 e1000_read_phy_reg(&sc->hw,
1929 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1930 phy_tmp &= ~IGP02E1000_PM_SPD;
1931 e1000_write_phy_reg(&sc->hw,
1932 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1936 * Packet Buffer Allocation (PBA)
1937 * Writing PBA sets the receive portion of the buffer
1938 * the remainder is used for the transmit buffer.
1940 switch (sc->hw.mac.type) {
1941 /* Total Packet Buffer on these is 48K */
1944 case e1000_80003es2lan:
1945 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1948 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1949 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1953 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1958 pba = E1000_PBA_26K;
1962 /* Devices before 82547 had a Packet Buffer of 64K. */
1963 if (sc->hw.mac.max_frame_size > 8192)
1964 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1966 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1968 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1971 * These parameters control the automatic generation (Tx) and
1972 * response (Rx) to Ethernet PAUSE frames.
1973 * - High water mark should allow for at least two frames to be
1974 * received after sending an XOFF.
1975 * - Low water mark works best when it is very near the high water mark.
1976 * This allows the receiver to restart by sending XON when it has
1977 * drained a bit. Here we use an arbitary value of 1500 which will
1978 * restart after one full frame is pulled from the buffer. There
1979 * could be several smaller frames in the buffer and if so they will
1980 * not trigger the XON until their total number reduces the buffer
1982 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1984 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1986 sc->hw.fc.high_water = rx_buffer_size -
1987 roundup2(sc->hw.mac.max_frame_size, 1024);
1988 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1990 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1991 sc->hw.fc.send_xon = TRUE;
1992 sc->hw.fc.requested_mode = e1000_ifmedia2fc(sc->ifm_flowctrl);
1995 * Device specific overrides/settings
1997 if (sc->hw.mac.type == e1000_pch_lpt ||
1998 sc->hw.mac.type == e1000_pch_spt) {
1999 sc->hw.fc.high_water = 0x5C20;
2000 sc->hw.fc.low_water = 0x5048;
2001 sc->hw.fc.pause_time = 0x0650;
2002 sc->hw.fc.refresh_time = 0x0400;
2003 /* Jumbos need adjusted PBA */
2004 if (sc->arpcom.ac_if.if_mtu > ETHERMTU)
2005 E1000_WRITE_REG(&sc->hw, E1000_PBA, 12);
2007 E1000_WRITE_REG(&sc->hw, E1000_PBA, 26);
2008 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2009 sc->hw.fc.pause_time = 0xFFFF;
2012 /* Issue a global reset */
2013 e1000_reset_hw(&sc->hw);
2014 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
2015 emx_disable_aspm(sc);
2017 if (e1000_init_hw(&sc->hw) < 0) {
2018 device_printf(dev, "Hardware Initialization Failed\n");
2022 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
2023 e1000_get_phy_info(&sc->hw);
2024 e1000_check_for_link(&sc->hw);
2030 emx_setup_ifp(struct emx_softc *sc)
2032 struct ifnet *ifp = &sc->arpcom.ac_if;
2035 if_initname(ifp, device_get_name(sc->dev),
2036 device_get_unit(sc->dev));
2038 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2039 ifp->if_init = emx_init;
2040 ifp->if_ioctl = emx_ioctl;
2041 ifp->if_start = emx_start;
2042 #ifdef IFPOLL_ENABLE
2043 ifp->if_npoll = emx_npoll;
2045 ifp->if_serialize = emx_serialize;
2046 ifp->if_deserialize = emx_deserialize;
2047 ifp->if_tryserialize = emx_tryserialize;
2049 ifp->if_serialize_assert = emx_serialize_assert;
2052 ifp->if_nmbclusters = sc->rx_ring_cnt * sc->rx_data[0].num_rx_desc;
2054 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1);
2055 ifq_set_ready(&ifp->if_snd);
2056 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
2058 ifp->if_mapsubq = ifq_mapsubq_modulo;
2059 ifq_set_subq_divisor(&ifp->if_snd, 1);
2061 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
2063 ifp->if_capabilities = IFCAP_HWCSUM |
2064 IFCAP_VLAN_HWTAGGING |
2067 if (sc->rx_ring_cnt > 1)
2068 ifp->if_capabilities |= IFCAP_RSS;
2069 ifp->if_capenable = ifp->if_capabilities;
2070 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
2073 * Tell the upper layer(s) we support long frames.
2075 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2077 for (i = 0; i < sc->tx_ring_cnt; ++i) {
2078 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2079 struct emx_txdata *tdata = &sc->tx_data[i];
2081 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res));
2082 ifsq_set_priv(ifsq, tdata);
2083 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize);
2086 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog);
2090 * Specify the media types supported by this sc and register
2091 * callbacks to update media and link information
2093 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2094 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
2095 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2098 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
2099 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2101 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2102 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2104 if (sc->hw.phy.type != e1000_phy_ife) {
2105 ifmedia_add(&sc->media,
2106 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2109 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2110 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO | sc->ifm_flowctrl);
2114 * Workaround for SmartSpeed on 82541 and 82547 controllers
2117 emx_smartspeed(struct emx_softc *sc)
2121 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
2122 sc->hw.mac.autoneg == 0 ||
2123 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2126 if (sc->smartspeed == 0) {
2128 * If Master/Slave config fault is asserted twice,
2129 * we assume back-to-back
2131 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2132 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2134 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2135 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2136 e1000_read_phy_reg(&sc->hw,
2137 PHY_1000T_CTRL, &phy_tmp);
2138 if (phy_tmp & CR_1000T_MS_ENABLE) {
2139 phy_tmp &= ~CR_1000T_MS_ENABLE;
2140 e1000_write_phy_reg(&sc->hw,
2141 PHY_1000T_CTRL, phy_tmp);
2143 if (sc->hw.mac.autoneg &&
2144 !e1000_phy_setup_autoneg(&sc->hw) &&
2145 !e1000_read_phy_reg(&sc->hw,
2146 PHY_CONTROL, &phy_tmp)) {
2147 phy_tmp |= MII_CR_AUTO_NEG_EN |
2148 MII_CR_RESTART_AUTO_NEG;
2149 e1000_write_phy_reg(&sc->hw,
2150 PHY_CONTROL, phy_tmp);
2155 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2156 /* If still no link, perhaps using 2/3 pair cable */
2157 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2158 phy_tmp |= CR_1000T_MS_ENABLE;
2159 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2160 if (sc->hw.mac.autoneg &&
2161 !e1000_phy_setup_autoneg(&sc->hw) &&
2162 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2163 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2164 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2168 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2169 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2174 emx_create_tx_ring(struct emx_txdata *tdata)
2176 device_t dev = tdata->sc->dev;
2177 struct emx_txbuf *tx_buffer;
2178 int error, i, tsize, ntxd;
2181 * Validate number of transmit descriptors. It must not exceed
2182 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2184 ntxd = device_getenv_int(dev, "txd", emx_txd);
2185 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2186 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2187 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2188 EMX_DEFAULT_TXD, ntxd);
2189 tdata->num_tx_desc = EMX_DEFAULT_TXD;
2191 tdata->num_tx_desc = ntxd;
2195 * Allocate Transmit Descriptor ring
2197 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc),
2199 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag,
2200 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2201 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap,
2202 &tdata->tx_desc_paddr);
2203 if (tdata->tx_desc_base == NULL) {
2204 device_printf(dev, "Unable to allocate tx_desc memory\n");
2208 tsize = __VM_CACHELINE_ALIGN(
2209 sizeof(struct emx_txbuf) * tdata->num_tx_desc);
2210 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
2213 * Create DMA tags for tx buffers
2215 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */
2216 1, 0, /* alignment, bounds */
2217 BUS_SPACE_MAXADDR, /* lowaddr */
2218 BUS_SPACE_MAXADDR, /* highaddr */
2219 NULL, NULL, /* filter, filterarg */
2220 EMX_TSO_SIZE, /* maxsize */
2221 EMX_MAX_SCATTER, /* nsegments */
2222 EMX_MAX_SEGSIZE, /* maxsegsize */
2223 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2224 BUS_DMA_ONEBPAGE, /* flags */
2227 device_printf(dev, "Unable to allocate TX DMA tag\n");
2228 kfree(tdata->tx_buf, M_DEVBUF);
2229 tdata->tx_buf = NULL;
2234 * Create DMA maps for tx buffers
2236 for (i = 0; i < tdata->num_tx_desc; i++) {
2237 tx_buffer = &tdata->tx_buf[i];
2239 error = bus_dmamap_create(tdata->txtag,
2240 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2243 device_printf(dev, "Unable to create TX DMA map\n");
2244 emx_destroy_tx_ring(tdata, i);
2250 * Setup TX parameters
2252 tdata->spare_tx_desc = EMX_TX_SPARE;
2253 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG;
2256 * Keep following relationship between spare_tx_desc, oact_tx_desc
2257 * and tx_intr_nsegs:
2258 * (spare_tx_desc + EMX_TX_RESERVED) <=
2259 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs
2261 tdata->oact_tx_desc = tdata->num_tx_desc / 8;
2262 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX)
2263 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX;
2264 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED)
2265 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED;
2267 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16;
2268 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc)
2269 tdata->tx_intr_nsegs = tdata->oact_tx_desc;
2272 * Pullup extra 4bytes into the first data segment for TSO, see:
2273 * 82571/82572 specification update errata #7
2275 * Same applies to I217 (and maybe I218 and I219).
2278 * 4bytes instead of 2bytes, which are mentioned in the errata,
2279 * are pulled; mainly to keep rest of the data properly aligned.
2281 if (tdata->sc->hw.mac.type == e1000_82571 ||
2282 tdata->sc->hw.mac.type == e1000_82572 ||
2283 tdata->sc->hw.mac.type == e1000_pch_lpt ||
2284 tdata->sc->hw.mac.type == e1000_pch_spt)
2285 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX;
2291 emx_init_tx_ring(struct emx_txdata *tdata)
2293 /* Clear the old ring contents */
2294 bzero(tdata->tx_desc_base,
2295 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc);
2298 tdata->next_avail_tx_desc = 0;
2299 tdata->next_tx_to_clean = 0;
2300 tdata->num_tx_desc_avail = tdata->num_tx_desc;
2302 tdata->tx_flags |= EMX_TXFLAG_ENABLED;
2303 if (tdata->sc->tx_ring_inuse > 1) {
2304 tdata->tx_flags |= EMX_TXFLAG_FORCECTX;
2306 if_printf(&tdata->sc->arpcom.ac_if,
2307 "TX %d force ctx setup\n", tdata->idx);
2313 emx_init_tx_unit(struct emx_softc *sc)
2315 uint32_t tctl, tarc, tipg = 0, txdctl;
2318 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2319 struct emx_txdata *tdata = &sc->tx_data[i];
2322 /* Setup the Base and Length of the Tx Descriptor Ring */
2323 bus_addr = tdata->tx_desc_paddr;
2324 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i),
2325 tdata->num_tx_desc * sizeof(struct e1000_tx_desc));
2326 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i),
2327 (uint32_t)(bus_addr >> 32));
2328 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i),
2329 (uint32_t)bus_addr);
2330 /* Setup the HW Tx Head and Tail descriptor pointers */
2331 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0);
2332 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0);
2335 /* Set the default values for the Tx Inter Packet Gap timer */
2336 switch (sc->hw.mac.type) {
2337 case e1000_80003es2lan:
2338 tipg = DEFAULT_82543_TIPG_IPGR1;
2339 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2340 E1000_TIPG_IPGR2_SHIFT;
2344 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2345 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2346 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2348 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2349 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2350 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2354 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2356 /* NOTE: 0 is not allowed for TIDV */
2357 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2358 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2361 * Errata workaround (obtained from Linux). This is necessary
2362 * to make multiple TX queues work on 82574.
2363 * XXX can't find it in any published errata though.
2365 txdctl = E1000_READ_REG(&sc->hw, E1000_TXDCTL(0));
2366 E1000_WRITE_REG(&sc->hw, E1000_TXDCTL(1), txdctl);
2368 if (sc->hw.mac.type == e1000_82571 ||
2369 sc->hw.mac.type == e1000_82572) {
2370 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2371 tarc |= EMX_TARC_SPEED_MODE;
2372 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2373 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2374 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2376 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2377 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2379 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2382 /* Program the Transmit Control Register */
2383 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2384 tctl &= ~E1000_TCTL_CT;
2385 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2386 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2387 tctl |= E1000_TCTL_MULR;
2389 /* This write will effectively turn on the transmit unit. */
2390 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2392 if (sc->hw.mac.type == e1000_82571 ||
2393 sc->hw.mac.type == e1000_82572 ||
2394 sc->hw.mac.type == e1000_80003es2lan) {
2395 /* Bit 28 of TARC1 must be cleared when MULR is enabled */
2396 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2398 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2401 if (sc->tx_ring_inuse > 1) {
2402 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2403 tarc &= ~EMX_TARC_COUNT_MASK;
2405 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2407 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2408 tarc &= ~EMX_TARC_COUNT_MASK;
2410 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2415 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc)
2417 struct emx_txbuf *tx_buffer;
2420 /* Free Transmit Descriptor ring */
2421 if (tdata->tx_desc_base) {
2422 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap);
2423 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base,
2424 tdata->tx_desc_dmap);
2425 bus_dma_tag_destroy(tdata->tx_desc_dtag);
2427 tdata->tx_desc_base = NULL;
2430 if (tdata->tx_buf == NULL)
2433 for (i = 0; i < ndesc; i++) {
2434 tx_buffer = &tdata->tx_buf[i];
2436 KKASSERT(tx_buffer->m_head == NULL);
2437 bus_dmamap_destroy(tdata->txtag, tx_buffer->map);
2439 bus_dma_tag_destroy(tdata->txtag);
2441 kfree(tdata->tx_buf, M_DEVBUF);
2442 tdata->tx_buf = NULL;
2446 * The offload context needs to be set when we transfer the first
2447 * packet of a particular protocol (TCP/UDP). This routine has been
2448 * enhanced to deal with inserted VLAN headers.
2450 * If the new packet's ether header length, ip header length and
2451 * csum offloading type are same as the previous packet, we should
2452 * avoid allocating a new csum context descriptor; mainly to take
2453 * advantage of the pipeline effect of the TX data read request.
2455 * This function returns number of TX descrptors allocated for
2459 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp,
2460 uint32_t *txd_upper, uint32_t *txd_lower)
2462 struct e1000_context_desc *TXD;
2463 int curr_txd, ehdrlen, csum_flags;
2464 uint32_t cmd, hdr_len, ip_hlen;
2466 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2467 ip_hlen = mp->m_pkthdr.csum_iphlen;
2468 ehdrlen = mp->m_pkthdr.csum_lhlen;
2470 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
2471 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen &&
2472 tdata->csum_flags == csum_flags) {
2474 * Same csum offload context as the previous packets;
2477 *txd_upper = tdata->csum_txd_upper;
2478 *txd_lower = tdata->csum_txd_lower;
2483 * Setup a new csum offload context.
2486 curr_txd = tdata->next_avail_tx_desc;
2487 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
2491 /* Setup of IP header checksum. */
2492 if (csum_flags & CSUM_IP) {
2494 * Start offset for header checksum calculation.
2495 * End offset for header checksum calculation.
2496 * Offset of place to put the checksum.
2498 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2499 TXD->lower_setup.ip_fields.ipcse =
2500 htole16(ehdrlen + ip_hlen - 1);
2501 TXD->lower_setup.ip_fields.ipcso =
2502 ehdrlen + offsetof(struct ip, ip_sum);
2503 cmd |= E1000_TXD_CMD_IP;
2504 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2506 hdr_len = ehdrlen + ip_hlen;
2508 if (csum_flags & CSUM_TCP) {
2510 * Start offset for payload checksum calculation.
2511 * End offset for payload checksum calculation.
2512 * Offset of place to put the checksum.
2514 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2515 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2516 TXD->upper_setup.tcp_fields.tucso =
2517 hdr_len + offsetof(struct tcphdr, th_sum);
2518 cmd |= E1000_TXD_CMD_TCP;
2519 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2520 } else if (csum_flags & CSUM_UDP) {
2522 * Start offset for header checksum calculation.
2523 * End offset for header checksum calculation.
2524 * Offset of place to put the checksum.
2526 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2527 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2528 TXD->upper_setup.tcp_fields.tucso =
2529 hdr_len + offsetof(struct udphdr, uh_sum);
2530 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2533 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2534 E1000_TXD_DTYP_D; /* Data descr */
2536 /* Save the information for this csum offloading context */
2537 tdata->csum_lhlen = ehdrlen;
2538 tdata->csum_iphlen = ip_hlen;
2539 tdata->csum_flags = csum_flags;
2540 tdata->csum_txd_upper = *txd_upper;
2541 tdata->csum_txd_lower = *txd_lower;
2543 TXD->tcp_seg_setup.data = htole32(0);
2544 TXD->cmd_and_length =
2545 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2547 if (++curr_txd == tdata->num_tx_desc)
2550 KKASSERT(tdata->num_tx_desc_avail > 0);
2551 tdata->num_tx_desc_avail--;
2553 tdata->next_avail_tx_desc = curr_txd;
2558 emx_txeof(struct emx_txdata *tdata)
2560 struct emx_txbuf *tx_buffer;
2561 int first, num_avail;
2563 if (tdata->tx_dd_head == tdata->tx_dd_tail)
2566 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2569 num_avail = tdata->num_tx_desc_avail;
2570 first = tdata->next_tx_to_clean;
2572 while (tdata->tx_dd_head != tdata->tx_dd_tail) {
2573 int dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2574 struct e1000_tx_desc *tx_desc;
2576 tx_desc = &tdata->tx_desc_base[dd_idx];
2577 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2578 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2580 if (++dd_idx == tdata->num_tx_desc)
2583 while (first != dd_idx) {
2588 tx_buffer = &tdata->tx_buf[first];
2589 if (tx_buffer->m_head) {
2590 bus_dmamap_unload(tdata->txtag,
2592 m_freem(tx_buffer->m_head);
2593 tx_buffer->m_head = NULL;
2596 if (++first == tdata->num_tx_desc)
2603 tdata->next_tx_to_clean = first;
2604 tdata->num_tx_desc_avail = num_avail;
2606 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2607 tdata->tx_dd_head = 0;
2608 tdata->tx_dd_tail = 0;
2611 if (!EMX_IS_OACTIVE(tdata)) {
2612 ifsq_clr_oactive(tdata->ifsq);
2614 /* All clean, turn off the timer */
2615 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2616 tdata->tx_watchdog.wd_timer = 0;
2621 emx_tx_collect(struct emx_txdata *tdata)
2623 struct emx_txbuf *tx_buffer;
2624 int tdh, first, num_avail, dd_idx = -1;
2626 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2629 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx));
2630 if (tdh == tdata->next_tx_to_clean)
2633 if (tdata->tx_dd_head != tdata->tx_dd_tail)
2634 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2636 num_avail = tdata->num_tx_desc_avail;
2637 first = tdata->next_tx_to_clean;
2639 while (first != tdh) {
2644 tx_buffer = &tdata->tx_buf[first];
2645 if (tx_buffer->m_head) {
2646 bus_dmamap_unload(tdata->txtag,
2648 m_freem(tx_buffer->m_head);
2649 tx_buffer->m_head = NULL;
2652 if (first == dd_idx) {
2653 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2654 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2655 tdata->tx_dd_head = 0;
2656 tdata->tx_dd_tail = 0;
2659 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2663 if (++first == tdata->num_tx_desc)
2666 tdata->next_tx_to_clean = first;
2667 tdata->num_tx_desc_avail = num_avail;
2669 if (!EMX_IS_OACTIVE(tdata)) {
2670 ifsq_clr_oactive(tdata->ifsq);
2672 /* All clean, turn off the timer */
2673 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2674 tdata->tx_watchdog.wd_timer = 0;
2679 * When Link is lost sometimes there is work still in the TX ring
2680 * which will result in a watchdog, rather than allow that do an
2681 * attempted cleanup and then reinit here. Note that this has been
2682 * seens mostly with fiber adapters.
2685 emx_tx_purge(struct emx_softc *sc)
2689 if (sc->link_active)
2692 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2693 struct emx_txdata *tdata = &sc->tx_data[i];
2695 if (tdata->tx_watchdog.wd_timer) {
2696 emx_tx_collect(tdata);
2697 if (tdata->tx_watchdog.wd_timer) {
2698 if_printf(&sc->arpcom.ac_if,
2699 "Link lost, TX pending, reinit\n");
2708 emx_newbuf(struct emx_rxdata *rdata, int i, int init)
2711 bus_dma_segment_t seg;
2713 struct emx_rxbuf *rx_buffer;
2716 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
2719 if_printf(&rdata->sc->arpcom.ac_if,
2720 "Unable to allocate RX mbuf\n");
2724 m->m_len = m->m_pkthdr.len = MCLBYTES;
2726 if (rdata->sc->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN)
2727 m_adj(m, ETHER_ALIGN);
2729 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2730 rdata->rx_sparemap, m,
2731 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2735 if_printf(&rdata->sc->arpcom.ac_if,
2736 "Unable to load RX mbuf\n");
2741 rx_buffer = &rdata->rx_buf[i];
2742 if (rx_buffer->m_head != NULL)
2743 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2745 map = rx_buffer->map;
2746 rx_buffer->map = rdata->rx_sparemap;
2747 rdata->rx_sparemap = map;
2749 rx_buffer->m_head = m;
2750 rx_buffer->paddr = seg.ds_addr;
2752 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2757 emx_create_rx_ring(struct emx_rxdata *rdata)
2759 device_t dev = rdata->sc->dev;
2760 struct emx_rxbuf *rx_buffer;
2761 int i, error, rsize, nrxd;
2764 * Validate number of receive descriptors. It must not exceed
2765 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2767 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2768 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2769 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2770 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2771 EMX_DEFAULT_RXD, nrxd);
2772 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2774 rdata->num_rx_desc = nrxd;
2778 * Allocate Receive Descriptor ring
2780 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2782 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag,
2783 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2784 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2785 &rdata->rx_desc_paddr);
2786 if (rdata->rx_desc == NULL) {
2787 device_printf(dev, "Unable to allocate rx_desc memory\n");
2791 rsize = __VM_CACHELINE_ALIGN(
2792 sizeof(struct emx_rxbuf) * rdata->num_rx_desc);
2793 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2796 * Create DMA tag for rx buffers
2798 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */
2799 1, 0, /* alignment, bounds */
2800 BUS_SPACE_MAXADDR, /* lowaddr */
2801 BUS_SPACE_MAXADDR, /* highaddr */
2802 NULL, NULL, /* filter, filterarg */
2803 MCLBYTES, /* maxsize */
2805 MCLBYTES, /* maxsegsize */
2806 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2809 device_printf(dev, "Unable to allocate RX DMA tag\n");
2810 kfree(rdata->rx_buf, M_DEVBUF);
2811 rdata->rx_buf = NULL;
2816 * Create spare DMA map for rx buffers
2818 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2819 &rdata->rx_sparemap);
2821 device_printf(dev, "Unable to create spare RX DMA map\n");
2822 bus_dma_tag_destroy(rdata->rxtag);
2823 kfree(rdata->rx_buf, M_DEVBUF);
2824 rdata->rx_buf = NULL;
2829 * Create DMA maps for rx buffers
2831 for (i = 0; i < rdata->num_rx_desc; i++) {
2832 rx_buffer = &rdata->rx_buf[i];
2834 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2837 device_printf(dev, "Unable to create RX DMA map\n");
2838 emx_destroy_rx_ring(rdata, i);
2846 emx_free_rx_ring(struct emx_rxdata *rdata)
2850 for (i = 0; i < rdata->num_rx_desc; i++) {
2851 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2853 if (rx_buffer->m_head != NULL) {
2854 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2855 m_freem(rx_buffer->m_head);
2856 rx_buffer->m_head = NULL;
2860 if (rdata->fmp != NULL)
2861 m_freem(rdata->fmp);
2867 emx_free_tx_ring(struct emx_txdata *tdata)
2871 for (i = 0; i < tdata->num_tx_desc; i++) {
2872 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i];
2874 if (tx_buffer->m_head != NULL) {
2875 bus_dmamap_unload(tdata->txtag, tx_buffer->map);
2876 m_freem(tx_buffer->m_head);
2877 tx_buffer->m_head = NULL;
2881 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX;
2883 tdata->csum_flags = 0;
2884 tdata->csum_lhlen = 0;
2885 tdata->csum_iphlen = 0;
2886 tdata->csum_thlen = 0;
2887 tdata->csum_mss = 0;
2888 tdata->csum_pktlen = 0;
2890 tdata->tx_dd_head = 0;
2891 tdata->tx_dd_tail = 0;
2892 tdata->tx_nsegs = 0;
2896 emx_init_rx_ring(struct emx_rxdata *rdata)
2900 /* Reset descriptor ring */
2901 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2903 /* Allocate new ones. */
2904 for (i = 0; i < rdata->num_rx_desc; i++) {
2905 error = emx_newbuf(rdata, i, 1);
2910 /* Setup our descriptor pointers */
2911 rdata->next_rx_desc_to_check = 0;
2917 emx_init_rx_unit(struct emx_softc *sc)
2919 struct ifnet *ifp = &sc->arpcom.ac_if;
2921 uint32_t rctl, itr, rfctl;
2925 * Make sure receives are disabled while setting
2926 * up the descriptor ring
2928 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2929 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2932 * Set the interrupt throttling rate. Value is calculated
2933 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2935 if (sc->int_throttle_ceil)
2936 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2939 emx_set_itr(sc, itr);
2941 /* Use extended RX descriptor */
2942 rfctl = E1000_RFCTL_EXTEN;
2944 /* Disable accelerated ackknowledge */
2945 if (sc->hw.mac.type == e1000_82574)
2946 rfctl |= E1000_RFCTL_ACK_DIS;
2948 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2951 * Receive Checksum Offload for TCP and UDP
2953 * Checksum offloading is also enabled if multiple receive
2954 * queue is to be supported, since we need it to figure out
2957 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2958 sc->rx_ring_cnt > 1) {
2961 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2965 * PCSD must be enabled to enable multiple
2968 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2970 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2974 * Configure multiple receive queue (RSS)
2976 if (sc->rx_ring_cnt > 1) {
2977 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2980 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2981 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
2985 * When we reach here, RSS has already been disabled
2986 * in emx_stop(), so we could safely configure RSS key
2987 * and redirect table.
2993 toeplitz_get_key(key, sizeof(key));
2994 for (i = 0; i < EMX_NRSSRK; ++i) {
2997 rssrk = EMX_RSSRK_VAL(key, i);
2998 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
3000 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
3004 * Configure RSS redirect table.
3006 if_ringmap_rdrtable(sc->rx_rmap, sc->rdr_table,
3010 for (j = 0; j < EMX_NRETA; ++j) {
3013 for (i = 0; i < EMX_RETA_SIZE; ++i) {
3016 q = sc->rdr_table[r] << EMX_RETA_RINGIDX_SHIFT;
3017 reta |= q << (8 * i);
3020 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
3021 E1000_WRITE_REG(&sc->hw, E1000_RETA(j), reta);
3025 * Enable multiple receive queues.
3026 * Enable IPv4 RSS standard hash functions.
3027 * Disable RSS interrupt.
3029 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
3030 E1000_MRQC_ENABLE_RSS_2Q |
3031 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3032 E1000_MRQC_RSS_FIELD_IPV4);
3036 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3037 * long latencies are observed, like Lenovo X60. This
3038 * change eliminates the problem, but since having positive
3039 * values in RDTR is a known source of problems on other
3040 * platforms another solution is being sought.
3042 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
3043 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
3044 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
3047 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3048 struct emx_rxdata *rdata = &sc->rx_data[i];
3051 * Setup the Base and Length of the Rx Descriptor Ring
3053 bus_addr = rdata->rx_desc_paddr;
3054 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
3055 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
3056 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
3057 (uint32_t)(bus_addr >> 32));
3058 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
3059 (uint32_t)bus_addr);
3062 * Setup the HW Rx Head and Tail Descriptor Pointers
3064 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
3065 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
3066 sc->rx_data[i].num_rx_desc - 1);
3069 if (sc->hw.mac.type >= e1000_pch2lan) {
3070 if (ifp->if_mtu > ETHERMTU)
3071 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, TRUE);
3073 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, FALSE);
3076 /* Setup the Receive Control Register */
3077 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3078 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3079 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
3080 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3082 /* Make sure VLAN Filters are off */
3083 rctl &= ~E1000_RCTL_VFE;
3085 /* Don't store bad paket */
3086 rctl &= ~E1000_RCTL_SBP;
3089 rctl |= E1000_RCTL_SZ_2048;
3091 if (ifp->if_mtu > ETHERMTU)
3092 rctl |= E1000_RCTL_LPE;
3094 rctl &= ~E1000_RCTL_LPE;
3096 /* Enable Receives */
3097 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
3101 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc)
3103 struct emx_rxbuf *rx_buffer;
3106 /* Free Receive Descriptor ring */
3107 if (rdata->rx_desc) {
3108 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
3109 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
3110 rdata->rx_desc_dmap);
3111 bus_dma_tag_destroy(rdata->rx_desc_dtag);
3113 rdata->rx_desc = NULL;
3116 if (rdata->rx_buf == NULL)
3119 for (i = 0; i < ndesc; i++) {
3120 rx_buffer = &rdata->rx_buf[i];
3122 KKASSERT(rx_buffer->m_head == NULL);
3123 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
3125 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
3126 bus_dma_tag_destroy(rdata->rxtag);
3128 kfree(rdata->rx_buf, M_DEVBUF);
3129 rdata->rx_buf = NULL;
3133 emx_rxeof(struct emx_rxdata *rdata, int count)
3135 struct ifnet *ifp = &rdata->sc->arpcom.ac_if;
3137 emx_rxdesc_t *current_desc;
3139 int i, cpuid = mycpuid;
3141 i = rdata->next_rx_desc_to_check;
3142 current_desc = &rdata->rx_desc[i];
3143 staterr = le32toh(current_desc->rxd_staterr);
3145 if (!(staterr & E1000_RXD_STAT_DD))
3148 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
3149 struct pktinfo *pi = NULL, pi0;
3150 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
3151 struct mbuf *m = NULL;
3156 mp = rx_buf->m_head;
3159 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3160 * needs to access the last received byte in the mbuf.
3162 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
3163 BUS_DMASYNC_POSTREAD);
3165 len = le16toh(current_desc->rxd_length);
3166 if (staterr & E1000_RXD_STAT_EOP) {
3173 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3175 uint32_t mrq, rss_hash;
3178 * Save several necessary information,
3179 * before emx_newbuf() destroy it.
3181 if ((staterr & E1000_RXD_STAT_VP) && eop)
3182 vlan = le16toh(current_desc->rxd_vlan);
3184 mrq = le32toh(current_desc->rxd_mrq);
3185 rss_hash = le32toh(current_desc->rxd_rss);
3187 EMX_RSS_DPRINTF(rdata->sc, 10,
3188 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
3189 rdata->idx, mrq, rss_hash);
3191 if (emx_newbuf(rdata, i, 0) != 0) {
3192 IFNET_STAT_INC(ifp, iqdrops, 1);
3196 /* Assign correct length to the current fragment */
3199 if (rdata->fmp == NULL) {
3200 mp->m_pkthdr.len = len;
3201 rdata->fmp = mp; /* Store the first mbuf */
3205 * Chain mbuf's together
3207 rdata->lmp->m_next = mp;
3208 rdata->lmp = rdata->lmp->m_next;
3209 rdata->fmp->m_pkthdr.len += len;
3213 rdata->fmp->m_pkthdr.rcvif = ifp;
3214 IFNET_STAT_INC(ifp, ipackets, 1);
3216 if (ifp->if_capenable & IFCAP_RXCSUM)
3217 emx_rxcsum(staterr, rdata->fmp);
3219 if (staterr & E1000_RXD_STAT_VP) {
3220 rdata->fmp->m_pkthdr.ether_vlantag =
3222 rdata->fmp->m_flags |= M_VLANTAG;
3228 if (ifp->if_capenable & IFCAP_RSS) {
3229 pi = emx_rssinfo(m, &pi0, mrq,
3232 #ifdef EMX_RSS_DEBUG
3237 IFNET_STAT_INC(ifp, ierrors, 1);
3239 emx_setup_rxdesc(current_desc, rx_buf);
3240 if (rdata->fmp != NULL) {
3241 m_freem(rdata->fmp);
3249 ifp->if_input(ifp, m, pi, cpuid);
3251 /* Advance our pointers to the next descriptor. */
3252 if (++i == rdata->num_rx_desc)
3255 current_desc = &rdata->rx_desc[i];
3256 staterr = le32toh(current_desc->rxd_staterr);
3258 rdata->next_rx_desc_to_check = i;
3260 /* Advance the E1000's Receive Queue "Tail Pointer". */
3262 i = rdata->num_rx_desc - 1;
3263 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i);
3267 emx_enable_intr(struct emx_softc *sc)
3269 uint32_t ims_mask = IMS_ENABLE_MASK;
3271 lwkt_serialize_handler_enable(&sc->main_serialize);
3274 if (sc->hw.mac.type == e1000_82574) {
3275 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3276 ims_mask |= EM_MSIX_MASK;
3279 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3283 emx_disable_intr(struct emx_softc *sc)
3285 if (sc->hw.mac.type == e1000_82574)
3286 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3287 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3289 lwkt_serialize_handler_disable(&sc->main_serialize);
3293 * Bit of a misnomer, what this really means is
3294 * to enable OS management of the system... aka
3295 * to disable special hardware management features
3298 emx_get_mgmt(struct emx_softc *sc)
3300 /* A shared code workaround */
3301 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3302 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3303 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3305 /* disable hardware interception of ARP */
3306 manc &= ~(E1000_MANC_ARP_EN);
3308 /* enable receiving management packets to the host */
3309 manc |= E1000_MANC_EN_MNG2HOST;
3310 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3311 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3312 manc2h |= E1000_MNG2HOST_PORT_623;
3313 manc2h |= E1000_MNG2HOST_PORT_664;
3314 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3316 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3321 * Give control back to hardware management
3322 * controller if there is one.
3325 emx_rel_mgmt(struct emx_softc *sc)
3327 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3328 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3330 /* re-enable hardware interception of ARP */
3331 manc |= E1000_MANC_ARP_EN;
3332 manc &= ~E1000_MANC_EN_MNG2HOST;
3334 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3339 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3340 * For ASF and Pass Through versions of f/w this means that
3341 * the driver is loaded. For AMT version (only with 82573)
3342 * of the f/w this means that the network i/f is open.
3345 emx_get_hw_control(struct emx_softc *sc)
3347 /* Let firmware know the driver has taken over */
3348 if (sc->hw.mac.type == e1000_82573) {
3351 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3352 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3353 swsm | E1000_SWSM_DRV_LOAD);
3357 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3358 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3359 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3361 sc->flags |= EMX_FLAG_HW_CTRL;
3365 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3366 * For ASF and Pass Through versions of f/w this means that the
3367 * driver is no longer loaded. For AMT version (only with 82573)
3368 * of the f/w this means that the network i/f is closed.
3371 emx_rel_hw_control(struct emx_softc *sc)
3373 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3375 sc->flags &= ~EMX_FLAG_HW_CTRL;
3377 /* Let firmware taken over control of h/w */
3378 if (sc->hw.mac.type == e1000_82573) {
3381 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3382 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3383 swsm & ~E1000_SWSM_DRV_LOAD);
3387 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3388 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3389 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3394 emx_is_valid_eaddr(const uint8_t *addr)
3396 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3398 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3405 * Enable PCI Wake On Lan capability
3408 emx_enable_wol(device_t dev)
3410 uint16_t cap, status;
3413 /* First find the capabilities pointer*/
3414 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3416 /* Read the PM Capabilities */
3417 id = pci_read_config(dev, cap, 1);
3418 if (id != PCIY_PMG) /* Something wrong */
3422 * OK, we have the power capabilities,
3423 * so now get the status register
3425 cap += PCIR_POWER_STATUS;
3426 status = pci_read_config(dev, cap, 2);
3427 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3428 pci_write_config(dev, cap, status, 2);
3432 emx_update_stats(struct emx_softc *sc)
3434 struct ifnet *ifp = &sc->arpcom.ac_if;
3436 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3437 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3438 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3439 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3441 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3442 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3443 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3444 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3446 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3447 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3448 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3449 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3450 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3451 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3452 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3453 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3454 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3455 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3456 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3457 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3458 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3459 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3460 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3461 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3462 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3463 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3464 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3465 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3467 /* For the 64-bit byte counters the low dword must be read first. */
3468 /* Both registers clear on the read of the high dword */
3470 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3471 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3473 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3474 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3475 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3476 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3477 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3479 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3480 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3482 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3483 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3484 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3485 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3486 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3487 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3488 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3489 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3490 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3491 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3493 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3494 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3495 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3496 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3497 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3498 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3500 IFNET_STAT_SET(ifp, collisions, sc->stats.colc);
3503 IFNET_STAT_SET(ifp, ierrors,
3504 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc +
3505 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr);
3508 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol);
3512 emx_print_debug_info(struct emx_softc *sc)
3514 device_t dev = sc->dev;
3515 uint8_t *hw_addr = sc->hw.hw_addr;
3518 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3519 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3520 E1000_READ_REG(&sc->hw, E1000_CTRL),
3521 E1000_READ_REG(&sc->hw, E1000_RCTL));
3522 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3523 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3524 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3525 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3526 sc->hw.fc.high_water, sc->hw.fc.low_water);
3527 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3528 E1000_READ_REG(&sc->hw, E1000_TIDV),
3529 E1000_READ_REG(&sc->hw, E1000_TADV));
3530 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3531 E1000_READ_REG(&sc->hw, E1000_RDTR),
3532 E1000_READ_REG(&sc->hw, E1000_RADV));
3534 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3535 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i,
3536 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
3537 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
3539 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3540 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i,
3541 E1000_READ_REG(&sc->hw, E1000_RDH(i)),
3542 E1000_READ_REG(&sc->hw, E1000_RDT(i)));
3545 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3546 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i,
3547 sc->tx_data[i].num_tx_desc_avail);
3548 device_printf(dev, "TX %d TSO segments = %lu\n", i,
3549 sc->tx_data[i].tso_segments);
3550 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i,
3551 sc->tx_data[i].tso_ctx_reused);
3556 emx_print_hw_stats(struct emx_softc *sc)
3558 device_t dev = sc->dev;
3560 device_printf(dev, "Excessive collisions = %lld\n",
3561 (long long)sc->stats.ecol);
3562 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3563 device_printf(dev, "Symbol errors = %lld\n",
3564 (long long)sc->stats.symerrs);
3566 device_printf(dev, "Sequence errors = %lld\n",
3567 (long long)sc->stats.sec);
3568 device_printf(dev, "Defer count = %lld\n",
3569 (long long)sc->stats.dc);
3570 device_printf(dev, "Missed Packets = %lld\n",
3571 (long long)sc->stats.mpc);
3572 device_printf(dev, "Receive No Buffers = %lld\n",
3573 (long long)sc->stats.rnbc);
3574 /* RLEC is inaccurate on some hardware, calculate our own. */
3575 device_printf(dev, "Receive Length Errors = %lld\n",
3576 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3577 device_printf(dev, "Receive errors = %lld\n",
3578 (long long)sc->stats.rxerrc);
3579 device_printf(dev, "Crc errors = %lld\n",
3580 (long long)sc->stats.crcerrs);
3581 device_printf(dev, "Alignment errors = %lld\n",
3582 (long long)sc->stats.algnerrc);
3583 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3584 (long long)sc->stats.cexterr);
3585 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3586 device_printf(dev, "XON Rcvd = %lld\n",
3587 (long long)sc->stats.xonrxc);
3588 device_printf(dev, "XON Xmtd = %lld\n",
3589 (long long)sc->stats.xontxc);
3590 device_printf(dev, "XOFF Rcvd = %lld\n",
3591 (long long)sc->stats.xoffrxc);
3592 device_printf(dev, "XOFF Xmtd = %lld\n",
3593 (long long)sc->stats.xofftxc);
3594 device_printf(dev, "Good Packets Rcvd = %lld\n",
3595 (long long)sc->stats.gprc);
3596 device_printf(dev, "Good Packets Xmtd = %lld\n",
3597 (long long)sc->stats.gptc);
3601 emx_print_nvm_info(struct emx_softc *sc)
3603 uint16_t eeprom_data;
3606 /* Its a bit crude, but it gets the job done */
3607 kprintf("\nInterface EEPROM Dump:\n");
3608 kprintf("Offset\n0x0000 ");
3609 for (i = 0, j = 0; i < 32; i++, j++) {
3610 if (j == 8) { /* Make the offset block */
3612 kprintf("\n0x00%x0 ",row);
3614 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3615 kprintf("%04x ", eeprom_data);
3621 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3623 struct emx_softc *sc;
3628 error = sysctl_handle_int(oidp, &result, 0, req);
3629 if (error || !req->newptr)
3632 sc = (struct emx_softc *)arg1;
3633 ifp = &sc->arpcom.ac_if;
3635 ifnet_serialize_all(ifp);
3638 emx_print_debug_info(sc);
3641 * This value will cause a hex dump of the
3642 * first 32 16-bit words of the EEPROM to
3646 emx_print_nvm_info(sc);
3648 ifnet_deserialize_all(ifp);
3654 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3659 error = sysctl_handle_int(oidp, &result, 0, req);
3660 if (error || !req->newptr)
3664 struct emx_softc *sc = (struct emx_softc *)arg1;
3665 struct ifnet *ifp = &sc->arpcom.ac_if;
3667 ifnet_serialize_all(ifp);
3668 emx_print_hw_stats(sc);
3669 ifnet_deserialize_all(ifp);
3675 emx_add_sysctl(struct emx_softc *sc)
3677 struct sysctl_ctx_list *ctx;
3678 struct sysctl_oid *tree;
3679 #if defined(EMX_RSS_DEBUG) || defined(EMX_TSS_DEBUG)
3684 ctx = device_get_sysctl_ctx(sc->dev);
3685 tree = device_get_sysctl_tree(sc->dev);
3686 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3687 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3688 emx_sysctl_debug_info, "I", "Debug Information");
3690 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3691 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3692 emx_sysctl_stats, "I", "Statistics");
3694 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3695 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0,
3697 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3698 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0,
3701 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3702 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3703 emx_sysctl_int_throttle, "I", "interrupt throttling rate");
3704 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3705 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3706 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt");
3707 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3708 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3709 emx_sysctl_tx_wreg_nsegs, "I",
3710 "# segments sent before write to hardware register");
3712 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3713 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0,
3715 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3716 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0,
3718 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3719 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
3720 "# of TX rings used");
3722 #ifdef IFPOLL_ENABLE
3723 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3724 OID_AUTO, "tx_poll_cpumap", CTLTYPE_OPAQUE | CTLFLAG_RD,
3725 sc->tx_rmap, 0, if_ringmap_cpumap_sysctl, "I",
3726 "TX polling CPU map");
3727 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3728 OID_AUTO, "rx_poll_cpumap", CTLTYPE_OPAQUE | CTLFLAG_RD,
3729 sc->rx_rmap, 0, if_ringmap_cpumap_sysctl, "I",
3730 "RX polling CPU map");
3733 #ifdef EMX_RSS_DEBUG
3734 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3735 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3736 0, "RSS debug level");
3737 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3738 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i);
3739 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3740 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts,
3744 #ifdef EMX_TSS_DEBUG
3745 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3746 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i);
3747 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3748 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts,
3755 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3757 struct emx_softc *sc = (void *)arg1;
3758 struct ifnet *ifp = &sc->arpcom.ac_if;
3759 int error, throttle;
3761 throttle = sc->int_throttle_ceil;
3762 error = sysctl_handle_int(oidp, &throttle, 0, req);
3763 if (error || req->newptr == NULL)
3765 if (throttle < 0 || throttle > 1000000000 / 256)
3770 * Set the interrupt throttling rate in 256ns increments,
3771 * recalculate sysctl value assignment to get exact frequency.
3773 throttle = 1000000000 / 256 / throttle;
3775 /* Upper 16bits of ITR is reserved and should be zero */
3776 if (throttle & 0xffff0000)
3780 ifnet_serialize_all(ifp);
3783 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3785 sc->int_throttle_ceil = 0;
3787 if (ifp->if_flags & IFF_RUNNING)
3788 emx_set_itr(sc, throttle);
3790 ifnet_deserialize_all(ifp);
3793 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3794 sc->int_throttle_ceil);
3800 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3802 struct emx_softc *sc = (void *)arg1;
3803 struct ifnet *ifp = &sc->arpcom.ac_if;
3804 struct emx_txdata *tdata = &sc->tx_data[0];
3807 segs = tdata->tx_intr_nsegs;
3808 error = sysctl_handle_int(oidp, &segs, 0, req);
3809 if (error || req->newptr == NULL)
3814 ifnet_serialize_all(ifp);
3817 * Don't allow tx_intr_nsegs to become:
3818 * o Less the oact_tx_desc
3819 * o Too large that no TX desc will cause TX interrupt to
3820 * be generated (OACTIVE will never recover)
3821 * o Too small that will cause tx_dd[] overflow
3823 if (segs < tdata->oact_tx_desc ||
3824 segs >= tdata->num_tx_desc - tdata->oact_tx_desc ||
3825 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) {
3831 for (i = 0; i < sc->tx_ring_cnt; ++i)
3832 sc->tx_data[i].tx_intr_nsegs = segs;
3835 ifnet_deserialize_all(ifp);
3841 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3843 struct emx_softc *sc = (void *)arg1;
3844 struct ifnet *ifp = &sc->arpcom.ac_if;
3845 int error, nsegs, i;
3847 nsegs = sc->tx_data[0].tx_wreg_nsegs;
3848 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3849 if (error || req->newptr == NULL)
3852 ifnet_serialize_all(ifp);
3853 for (i = 0; i < sc->tx_ring_cnt; ++i)
3854 sc->tx_data[i].tx_wreg_nsegs =nsegs;
3855 ifnet_deserialize_all(ifp);
3861 emx_dma_alloc(struct emx_softc *sc)
3866 * Create top level busdma tag
3868 error = bus_dma_tag_create(NULL, 1, 0,
3869 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3871 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3872 0, &sc->parent_dtag);
3874 device_printf(sc->dev, "could not create top level DMA tag\n");
3879 * Allocate transmit descriptors ring and buffers
3881 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3882 error = emx_create_tx_ring(&sc->tx_data[i]);
3884 device_printf(sc->dev,
3885 "Could not setup transmit structures\n");
3891 * Allocate receive descriptors ring and buffers
3893 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3894 error = emx_create_rx_ring(&sc->rx_data[i]);
3896 device_printf(sc->dev,
3897 "Could not setup receive structures\n");
3905 emx_dma_free(struct emx_softc *sc)
3909 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3910 emx_destroy_tx_ring(&sc->tx_data[i],
3911 sc->tx_data[i].num_tx_desc);
3914 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3915 emx_destroy_rx_ring(&sc->rx_data[i],
3916 sc->rx_data[i].num_rx_desc);
3919 /* Free top level busdma tag */
3920 if (sc->parent_dtag != NULL)
3921 bus_dma_tag_destroy(sc->parent_dtag);
3925 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3927 struct emx_softc *sc = ifp->if_softc;
3929 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, slz);
3933 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3935 struct emx_softc *sc = ifp->if_softc;
3937 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, slz);
3941 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3943 struct emx_softc *sc = ifp->if_softc;
3945 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, slz);
3949 emx_serialize_skipmain(struct emx_softc *sc)
3951 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3955 emx_deserialize_skipmain(struct emx_softc *sc)
3957 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3963 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3964 boolean_t serialized)
3966 struct emx_softc *sc = ifp->if_softc;
3968 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3972 #endif /* INVARIANTS */
3974 #ifdef IFPOLL_ENABLE
3977 emx_npoll_status(struct ifnet *ifp)
3979 struct emx_softc *sc = ifp->if_softc;
3982 ASSERT_SERIALIZED(&sc->main_serialize);
3984 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3985 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3986 callout_stop(&sc->timer);
3987 sc->hw.mac.get_link_status = 1;
3988 emx_update_link_status(sc);
3989 callout_reset(&sc->timer, hz, emx_timer, sc);
3994 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3996 struct emx_txdata *tdata = arg;
3998 ASSERT_SERIALIZED(&tdata->tx_serialize);
4001 if (!ifsq_is_empty(tdata->ifsq))
4002 ifsq_devstart(tdata->ifsq);
4006 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
4008 struct emx_rxdata *rdata = arg;
4010 ASSERT_SERIALIZED(&rdata->rx_serialize);
4012 emx_rxeof(rdata, cycle);
4016 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
4018 struct emx_softc *sc = ifp->if_softc;
4021 ASSERT_IFNET_SERIALIZED_ALL(ifp);
4026 info->ifpi_status.status_func = emx_npoll_status;
4027 info->ifpi_status.serializer = &sc->main_serialize;
4029 txr_cnt = emx_get_txring_inuse(sc, TRUE);
4030 for (i = 0; i < txr_cnt; ++i) {
4031 struct emx_txdata *tdata = &sc->tx_data[i];
4033 cpu = if_ringmap_cpumap(sc->tx_rmap, i);
4034 KKASSERT(cpu < netisr_ncpus);
4035 info->ifpi_tx[cpu].poll_func = emx_npoll_tx;
4036 info->ifpi_tx[cpu].arg = tdata;
4037 info->ifpi_tx[cpu].serializer = &tdata->tx_serialize;
4038 ifsq_set_cpuid(tdata->ifsq, cpu);
4041 for (i = 0; i < sc->rx_ring_cnt; ++i) {
4042 struct emx_rxdata *rdata = &sc->rx_data[i];
4044 cpu = if_ringmap_cpumap(sc->rx_rmap, i);
4045 KKASSERT(cpu < netisr_ncpus);
4046 info->ifpi_rx[cpu].poll_func = emx_npoll_rx;
4047 info->ifpi_rx[cpu].arg = rdata;
4048 info->ifpi_rx[cpu].serializer = &rdata->rx_serialize;
4051 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4052 struct emx_txdata *tdata = &sc->tx_data[i];
4054 ifsq_set_cpuid(tdata->ifsq,
4055 rman_get_cpuid(sc->intr_res));
4058 if (ifp->if_flags & IFF_RUNNING)
4062 #endif /* IFPOLL_ENABLE */
4065 emx_set_itr(struct emx_softc *sc, uint32_t itr)
4067 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
4068 if (sc->hw.mac.type == e1000_82574) {
4072 * When using MSIX interrupts we need to
4073 * throttle using the EITR register
4075 for (i = 0; i < 4; ++i)
4076 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
4081 * Disable the L0s, 82574L Errata #20
4084 emx_disable_aspm(struct emx_softc *sc)
4086 uint16_t link_cap, link_ctrl, disable;
4087 uint8_t pcie_ptr, reg;
4088 device_t dev = sc->dev;
4090 switch (sc->hw.mac.type) {
4095 * 82573 specification update
4096 * errata #8 disable L0s
4097 * errata #41 disable L1
4099 * 82571/82572 specification update
4100 # errata #13 disable L1
4101 * errata #68 disable L0s
4103 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4108 * 82574 specification update errata #20
4110 * There is no need to disable L1
4112 disable = PCIEM_LNKCTL_ASPM_L0S;
4119 pcie_ptr = pci_get_pciecap_ptr(dev);
4123 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4124 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4128 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
4130 reg = pcie_ptr + PCIER_LINKCTRL;
4131 link_ctrl = pci_read_config(dev, reg, 2);
4132 link_ctrl &= ~disable;
4133 pci_write_config(dev, reg, link_ctrl, 2);
4137 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp)
4139 int iphlen, hoff, thoff, ex = 0;
4144 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4146 iphlen = m->m_pkthdr.csum_iphlen;
4147 thoff = m->m_pkthdr.csum_thlen;
4148 hoff = m->m_pkthdr.csum_lhlen;
4150 KASSERT(iphlen > 0, ("invalid ip hlen"));
4151 KASSERT(thoff > 0, ("invalid tcp hlen"));
4152 KASSERT(hoff > 0, ("invalid ether hlen"));
4154 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX)
4157 if (m->m_len < hoff + iphlen + thoff + ex) {
4158 m = m_pullup(m, hoff + iphlen + thoff + ex);
4165 ip = mtodoff(m, struct ip *, hoff);
4172 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp,
4173 uint32_t *txd_upper, uint32_t *txd_lower)
4175 struct e1000_context_desc *TXD;
4176 int hoff, iphlen, thoff, hlen;
4177 int mss, pktlen, curr_txd;
4179 #ifdef EMX_TSO_DEBUG
4180 tdata->tso_segments++;
4183 iphlen = mp->m_pkthdr.csum_iphlen;
4184 thoff = mp->m_pkthdr.csum_thlen;
4185 hoff = mp->m_pkthdr.csum_lhlen;
4186 mss = mp->m_pkthdr.tso_segsz;
4187 pktlen = mp->m_pkthdr.len;
4189 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
4190 tdata->csum_flags == CSUM_TSO &&
4191 tdata->csum_iphlen == iphlen &&
4192 tdata->csum_lhlen == hoff &&
4193 tdata->csum_thlen == thoff &&
4194 tdata->csum_mss == mss &&
4195 tdata->csum_pktlen == pktlen) {
4196 *txd_upper = tdata->csum_txd_upper;
4197 *txd_lower = tdata->csum_txd_lower;
4198 #ifdef EMX_TSO_DEBUG
4199 tdata->tso_ctx_reused++;
4203 hlen = hoff + iphlen + thoff;
4206 * Setup a new TSO context.
4209 curr_txd = tdata->next_avail_tx_desc;
4210 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
4212 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4213 E1000_TXD_DTYP_D | /* Data descr type */
4214 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4216 /* IP and/or TCP header checksum calculation and insertion. */
4217 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4220 * Start offset for header checksum calculation.
4221 * End offset for header checksum calculation.
4222 * Offset of place put the checksum.
4224 TXD->lower_setup.ip_fields.ipcss = hoff;
4225 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4226 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4229 * Start offset for payload checksum calculation.
4230 * End offset for payload checksum calculation.
4231 * Offset of place to put the checksum.
4233 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4234 TXD->upper_setup.tcp_fields.tucse = 0;
4235 TXD->upper_setup.tcp_fields.tucso =
4236 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4239 * Payload size per packet w/o any headers.
4240 * Length of all headers up to payload.
4242 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4243 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4244 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4245 E1000_TXD_CMD_DEXT | /* Extended descr */
4246 E1000_TXD_CMD_TSE | /* TSE context */
4247 E1000_TXD_CMD_IP | /* Do IP csum */
4248 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4249 (pktlen - hlen)); /* Total len */
4251 /* Save the information for this TSO context */
4252 tdata->csum_flags = CSUM_TSO;
4253 tdata->csum_lhlen = hoff;
4254 tdata->csum_iphlen = iphlen;
4255 tdata->csum_thlen = thoff;
4256 tdata->csum_mss = mss;
4257 tdata->csum_pktlen = pktlen;
4258 tdata->csum_txd_upper = *txd_upper;
4259 tdata->csum_txd_lower = *txd_lower;
4261 if (++curr_txd == tdata->num_tx_desc)
4264 KKASSERT(tdata->num_tx_desc_avail > 0);
4265 tdata->num_tx_desc_avail--;
4267 tdata->next_avail_tx_desc = curr_txd;
4272 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling)
4275 return sc->tx_ring_cnt;