3a9d1d8b56921fa82b74446ecc370de857660cae
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
1 /*
2  * Copyright (c) 2001-2011, Intel Corporation 
3  * All rights reserved.
4  * 
5  * Redistribution and use in source and binary forms, with or without 
6  * modification, are permitted provided that the following conditions are met:
7  * 
8  *  1. Redistributions of source code must retain the above copyright notice, 
9  *     this list of conditions and the following disclaimer.
10  * 
11  *  2. Redistributions in binary form must reproduce the above copyright 
12  *     notice, this list of conditions and the following disclaimer in the 
13  *     documentation and/or other materials provided with the distribution.
14  * 
15  *  3. Neither the name of the Intel Corporation nor the names of its 
16  *     contributors may be used to endorse or promote products derived from 
17  *     this software without specific prior written permission.
18  * 
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31
32 #include "opt_polling.h"
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/interrupt.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/mbuf.h>
41 #include <sys/proc.h>
42 #include <sys/rman.h>
43 #include <sys/serialize.h>
44 #include <sys/serialize2.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
48 #include <sys/systm.h>
49
50 #include <net/bpf.h>
51 #include <net/ethernet.h>
52 #include <net/if.h>
53 #include <net/if_arp.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
56 #include <net/ifq_var.h>
57 #include <net/toeplitz.h>
58 #include <net/toeplitz2.h>
59 #include <net/vlan/if_vlan_var.h>
60 #include <net/vlan/if_vlan_ether.h>
61 #include <net/if_poll.h>
62
63 #include <netinet/in_systm.h>
64 #include <netinet/in.h>
65 #include <netinet/ip.h>
66 #include <netinet/tcp.h>
67 #include <netinet/udp.h>
68
69 #include <bus/pci/pcivar.h>
70 #include <bus/pci/pcireg.h>
71
72 #include <dev/netif/ig_hal/e1000_api.h>
73 #include <dev/netif/ig_hal/e1000_82575.h>
74 #include <dev/netif/igb/if_igb.h>
75
76 #define IGB_NAME        "Intel(R) PRO/1000 "
77 #define IGB_DEVICE(id)  \
78         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
79 #define IGB_DEVICE_NULL { 0, 0, NULL }
80
81 static struct igb_device {
82         uint16_t        vid;
83         uint16_t        did;
84         const char      *desc;
85 } igb_devices[] = {
86         IGB_DEVICE(82575EB_COPPER),
87         IGB_DEVICE(82575EB_FIBER_SERDES),
88         IGB_DEVICE(82575GB_QUAD_COPPER),
89         IGB_DEVICE(82576),
90         IGB_DEVICE(82576_NS),
91         IGB_DEVICE(82576_NS_SERDES),
92         IGB_DEVICE(82576_FIBER),
93         IGB_DEVICE(82576_SERDES),
94         IGB_DEVICE(82576_SERDES_QUAD),
95         IGB_DEVICE(82576_QUAD_COPPER),
96         IGB_DEVICE(82576_QUAD_COPPER_ET2),
97         IGB_DEVICE(82576_VF),
98         IGB_DEVICE(82580_COPPER),
99         IGB_DEVICE(82580_FIBER),
100         IGB_DEVICE(82580_SERDES),
101         IGB_DEVICE(82580_SGMII),
102         IGB_DEVICE(82580_COPPER_DUAL),
103         IGB_DEVICE(82580_QUAD_FIBER),
104         IGB_DEVICE(DH89XXCC_SERDES),
105         IGB_DEVICE(DH89XXCC_SGMII),
106         IGB_DEVICE(DH89XXCC_SFP),
107         IGB_DEVICE(DH89XXCC_BACKPLANE),
108         IGB_DEVICE(I350_COPPER),
109         IGB_DEVICE(I350_FIBER),
110         IGB_DEVICE(I350_SERDES),
111         IGB_DEVICE(I350_SGMII),
112         IGB_DEVICE(I350_VF),
113
114         /* required last entry */
115         IGB_DEVICE_NULL
116 };
117
118 static int      igb_probe(device_t);
119 static int      igb_attach(device_t);
120 static int      igb_detach(device_t);
121 static int      igb_shutdown(device_t);
122 static int      igb_suspend(device_t);
123 static int      igb_resume(device_t);
124
125 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
126 static void     igb_setup_ifp(struct igb_softc *);
127 static int      igb_txctx_pullup(struct igb_tx_ring *, struct mbuf **);
128 static boolean_t igb_txctx(struct igb_tx_ring *, struct mbuf *);
129 static void     igb_add_sysctl(struct igb_softc *);
130 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
131
132 static void     igb_vf_init_stats(struct igb_softc *);
133 static void     igb_reset(struct igb_softc *);
134 static void     igb_update_stats_counters(struct igb_softc *);
135 static void     igb_update_vf_stats_counters(struct igb_softc *);
136 static void     igb_update_link_status(struct igb_softc *);
137 static void     igb_init_tx_unit(struct igb_softc *);
138 static void     igb_init_rx_unit(struct igb_softc *);
139
140 static void     igb_set_vlan(struct igb_softc *);
141 static void     igb_set_multi(struct igb_softc *);
142 static void     igb_set_promisc(struct igb_softc *);
143 static void     igb_disable_promisc(struct igb_softc *);
144
145 static int      igb_dma_alloc(struct igb_softc *);
146 static void     igb_dma_free(struct igb_softc *);
147 static int      igb_create_tx_ring(struct igb_tx_ring *);
148 static int      igb_create_rx_ring(struct igb_rx_ring *);
149 static void     igb_free_tx_ring(struct igb_tx_ring *);
150 static void     igb_free_rx_ring(struct igb_rx_ring *);
151 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
152 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
153 static void     igb_init_tx_ring(struct igb_tx_ring *);
154 static int      igb_init_rx_ring(struct igb_rx_ring *);
155 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
156 static int      igb_encap(struct igb_tx_ring *, struct mbuf **);
157
158 static void     igb_stop(struct igb_softc *);
159 static void     igb_init(void *);
160 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
161 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
162 static int      igb_media_change(struct ifnet *);
163 static void     igb_timer(void *);
164 static void     igb_watchdog(struct ifnet *);
165 static void     igb_start(struct ifnet *);
166 #ifdef DEVICE_POLLING
167 static void     igb_poll(struct ifnet *, enum poll_cmd, int);
168 #endif
169
170 static void     igb_intr(void *);
171 static void     igb_rxeof(struct igb_rx_ring *, int);
172 static void     igb_txeof(struct igb_tx_ring *);
173 static void     igb_set_itr(struct igb_softc *);
174 static void     igb_enable_intr(struct igb_softc *);
175 static void     igb_disable_intr(struct igb_softc *);
176
177 /* Management and WOL Support */
178 static void     igb_get_mgmt(struct igb_softc *);
179 static void     igb_rel_mgmt(struct igb_softc *);
180 static void     igb_get_hw_control(struct igb_softc *);
181 static void     igb_rel_hw_control(struct igb_softc *);
182 static void     igb_enable_wol(device_t);
183
184 static device_method_t igb_methods[] = {
185         /* Device interface */
186         DEVMETHOD(device_probe,         igb_probe),
187         DEVMETHOD(device_attach,        igb_attach),
188         DEVMETHOD(device_detach,        igb_detach),
189         DEVMETHOD(device_shutdown,      igb_shutdown),
190         DEVMETHOD(device_suspend,       igb_suspend),
191         DEVMETHOD(device_resume,        igb_resume),
192         { 0, 0 }
193 };
194
195 static driver_t igb_driver = {
196         "igb",
197         igb_methods,
198         sizeof(struct igb_softc),
199 };
200
201 static devclass_t igb_devclass;
202
203 DECLARE_DUMMY_MODULE(if_igb);
204 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
205 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
206
207 static int      igb_rxd = IGB_DEFAULT_RXD;
208 static int      igb_txd = IGB_DEFAULT_TXD;
209 static int      igb_msi_enable = 1;
210 static int      igb_msix_enable = 1;
211 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
212 static int      igb_fc_setting = e1000_fc_full;
213
214 /*
215  * DMA Coalescing, only for i350 - default to off,
216  * this feature is for power savings
217  */
218 static int      igb_dma_coalesce = 0;
219
220 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
221 TUNABLE_INT("hw.igb.txd", &igb_txd);
222 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
223 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
224 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
225
226 /* i350 specific */
227 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
228 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
229
230 static __inline void
231 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
232 {
233         /* Ignore Checksum bit is set */
234         if (staterr & E1000_RXD_STAT_IXSM)
235                 return;
236
237         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
238             E1000_RXD_STAT_IPCS)
239                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
240
241         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
242                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
243                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
244                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
245                         mp->m_pkthdr.csum_data = htons(0xffff);
246                 }
247         }
248 }
249
250 static int
251 igb_probe(device_t dev)
252 {
253         const struct igb_device *d;
254         uint16_t vid, did;
255
256         vid = pci_get_vendor(dev);
257         did = pci_get_device(dev);
258
259         for (d = igb_devices; d->desc != NULL; ++d) {
260                 if (vid == d->vid && did == d->did) {
261                         device_set_desc(dev, d->desc);
262                         return 0;
263                 }
264         }
265         return ENXIO;
266 }
267
268 static int
269 igb_attach(device_t dev)
270 {
271         struct igb_softc *sc = device_get_softc(dev);
272         struct ifnet *ifp = &sc->arpcom.ac_if;
273         uint16_t eeprom_data;
274         u_int intr_flags;
275         int error = 0;
276
277 #ifdef notyet
278         /* SYSCTL stuff */
279         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
280             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
281             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
282             igb_sysctl_nvm_info, "I", "NVM Information");
283
284         SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
285             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
286             OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
287             &igb_enable_aim, 1, "Interrupt Moderation");
288
289         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
290             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
291             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
292             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
293 #endif
294
295         callout_init_mp(&sc->timer);
296
297         sc->dev = sc->osdep.dev = dev;
298
299         /*
300          * Determine hardware and mac type
301          */
302         sc->hw.vendor_id = pci_get_vendor(dev);
303         sc->hw.device_id = pci_get_device(dev);
304         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
305         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
306         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
307
308         if (e1000_set_mac_type(&sc->hw))
309                 return ENXIO;
310
311         /* Are we a VF device? */
312         if (sc->hw.mac.type == e1000_vfadapt ||
313             sc->hw.mac.type == e1000_vfadapt_i350)
314                 sc->vf_ifp = 1;
315         else
316                 sc->vf_ifp = 0;
317
318         /* Enable bus mastering */
319         pci_enable_busmaster(dev);
320
321         /*
322          * Allocate IO memory
323          */
324         sc->mem_rid = PCIR_BAR(0);
325         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
326             RF_ACTIVE);
327         if (sc->mem_res == NULL) {
328                 device_printf(dev, "Unable to allocate bus resource: memory\n");
329                 error = ENXIO;
330                 goto failed;
331         }
332         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
333         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
334
335         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
336
337         /*
338          * Allocate interrupt
339          */
340         sc->intr_type = pci_alloc_1intr(dev, igb_msi_enable,
341             &sc->intr_rid, &intr_flags);
342
343         sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
344             intr_flags);
345         if (sc->intr_res == NULL) {
346                 device_printf(dev, "Unable to allocate bus resource: "
347                     "interrupt\n");
348                 error = ENXIO;
349                 goto failed;
350         }
351
352         /* Save PCI command register for Shared Code */
353         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
354         sc->hw.back = &sc->osdep;
355
356         sc->num_queues = 1; /* Defaults for Legacy or MSI */
357         sc->intr_rate = IGB_INTR_RATE;
358
359         /* Do Shared Code initialization */
360         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
361                 device_printf(dev, "Setup of Shared code failed\n");
362                 error = ENXIO;
363                 goto failed;
364         }
365
366         e1000_get_bus_info(&sc->hw);
367
368         sc->hw.mac.autoneg = DO_AUTO_NEG;
369         sc->hw.phy.autoneg_wait_to_complete = FALSE;
370         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
371
372         /* Copper options */
373         if (sc->hw.phy.media_type == e1000_media_type_copper) {
374                 sc->hw.phy.mdix = AUTO_ALL_MODES;
375                 sc->hw.phy.disable_polarity_correction = FALSE;
376                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
377         }
378
379         /* Set the frame limits assuming  standard ethernet sized frames. */
380         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
381         sc->min_frame_size = ETHER_MIN_LEN;
382
383         /* Allocate RX/TX rings' busdma(9) stuffs */
384         error = igb_dma_alloc(sc);
385         if (error)
386                 goto failed;
387
388         /* Allocate the appropriate stats memory */
389         if (sc->vf_ifp) {
390                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
391                     M_WAITOK | M_ZERO);
392                 igb_vf_init_stats(sc);
393         } else {
394                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
395                     M_WAITOK | M_ZERO);
396         }
397
398         /* Allocate multicast array memory. */
399         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
400             M_DEVBUF, M_WAITOK);
401
402         /* Some adapter-specific advanced features */
403         if (sc->hw.mac.type >= e1000_i350) {
404 #ifdef notyet
405                 igb_set_sysctl_value(adapter, "dma_coalesce",
406                     "configure dma coalesce",
407                     &adapter->dma_coalesce, igb_dma_coalesce);
408                 igb_set_sysctl_value(adapter, "eee_disabled",
409                     "enable Energy Efficient Ethernet",
410                     &adapter->hw.dev_spec._82575.eee_disable,
411                     igb_eee_disabled);
412 #else
413                 sc->dma_coalesce = igb_dma_coalesce;
414                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
415 #endif
416                 e1000_set_eee_i350(&sc->hw);
417         }
418
419         /*
420          * Start from a known state, this is important in reading the nvm and
421          * mac from that.
422          */
423         e1000_reset_hw(&sc->hw);
424
425         /* Make sure we have a good EEPROM before we read from it */
426         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
427                 /*
428                  * Some PCI-E parts fail the first check due to
429                  * the link being in sleep state, call it again,
430                  * if it fails a second time its a real issue.
431                  */
432                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
433                         device_printf(dev,
434                             "The EEPROM Checksum Is Not Valid\n");
435                         error = EIO;
436                         goto failed;
437                 }
438         }
439
440         /* Copy the permanent MAC address out of the EEPROM */
441         if (e1000_read_mac_addr(&sc->hw) < 0) {
442                 device_printf(dev, "EEPROM read error while reading MAC"
443                     " address\n");
444                 error = EIO;
445                 goto failed;
446         }
447         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
448                 device_printf(dev, "Invalid MAC address\n");
449                 error = EIO;
450                 goto failed;
451         }
452
453 #ifdef notyet
454         /* 
455         ** Configure Interrupts
456         */
457         if ((adapter->msix > 1) && (igb_enable_msix))
458                 error = igb_allocate_msix(adapter);
459         else /* MSI or Legacy */
460                 error = igb_allocate_legacy(adapter);
461         if (error)
462                 goto err_late;
463 #endif
464
465         /* Setup OS specific network interface */
466         igb_setup_ifp(sc);
467
468         /* Add sysctl tree, must after igb_setup_ifp() */
469         igb_add_sysctl(sc);
470
471         /* Now get a good starting state */
472         igb_reset(sc);
473
474         /* Initialize statistics */
475         igb_update_stats_counters(sc);
476
477         sc->hw.mac.get_link_status = 1;
478         igb_update_link_status(sc);
479
480         /* Indicate SOL/IDER usage */
481         if (e1000_check_reset_block(&sc->hw)) {
482                 device_printf(dev,
483                     "PHY reset is blocked due to SOL/IDER session.\n");
484         }
485
486         /* Determine if we have to control management hardware */
487         sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
488
489         /*
490          * Setup Wake-on-Lan
491          */
492         /* APME bit in EEPROM is mapped to WUC.APME */
493         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
494         if (eeprom_data)
495                 sc->wol = E1000_WUFC_MAG;
496         /* XXX disable WOL */
497         sc->wol = 0; 
498
499 #ifdef notyet
500         /* Register for VLAN events */
501         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
502              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
503         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
504              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
505 #endif
506
507 #ifdef notyet
508         igb_add_hw_stats(adapter);
509 #endif
510
511         error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, igb_intr, sc,
512             &sc->intr_tag, ifp->if_serializer);
513         if (error) {
514                 device_printf(dev, "Failed to register interrupt handler");
515                 ether_ifdetach(&sc->arpcom.ac_if);
516                 goto failed;
517         }
518
519         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
520         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
521
522         return 0;
523
524 failed:
525         igb_detach(dev);
526         return error;
527 }
528
529 static int
530 igb_detach(device_t dev)
531 {
532         struct igb_softc *sc = device_get_softc(dev);
533
534         if (device_is_attached(dev)) {
535                 struct ifnet *ifp = &sc->arpcom.ac_if;
536
537                 ifnet_serialize_all(ifp);
538
539                 igb_stop(sc);
540
541                 e1000_phy_hw_reset(&sc->hw);
542
543                 /* Give control back to firmware */
544                 igb_rel_mgmt(sc);
545                 igb_rel_hw_control(sc);
546
547                 if (sc->wol) {
548                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
549                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
550                         igb_enable_wol(dev);
551                 }
552
553                 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
554
555                 ifnet_deserialize_all(ifp);
556
557                 ether_ifdetach(ifp);
558         } else if (sc->mem_res != NULL) {
559                 igb_rel_hw_control(sc);
560         }
561         bus_generic_detach(dev);
562
563         if (sc->intr_res != NULL) {
564                 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
565                     sc->intr_res);
566         }
567         if (sc->intr_type == PCI_INTR_TYPE_MSI)
568                 pci_release_msi(dev);
569
570         if (sc->mem_res != NULL) {
571                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
572                     sc->mem_res);
573         }
574
575         igb_dma_free(sc);
576
577         if (sc->mta != NULL)
578                 kfree(sc->mta, M_DEVBUF);
579         if (sc->stats != NULL)
580                 kfree(sc->stats, M_DEVBUF);
581
582         if (sc->sysctl_tree != NULL)
583                 sysctl_ctx_free(&sc->sysctl_ctx);
584
585         return 0;
586 }
587
588 static int
589 igb_shutdown(device_t dev)
590 {
591         return igb_suspend(dev);
592 }
593
594 static int
595 igb_suspend(device_t dev)
596 {
597         struct igb_softc *sc = device_get_softc(dev);
598         struct ifnet *ifp = &sc->arpcom.ac_if;
599
600         ifnet_serialize_all(ifp);
601
602         igb_stop(sc);
603
604         igb_rel_mgmt(sc);
605         igb_rel_hw_control(sc);
606
607         if (sc->wol) {
608                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
609                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
610                 igb_enable_wol(dev);
611         }
612
613         ifnet_deserialize_all(ifp);
614
615         return bus_generic_suspend(dev);
616 }
617
618 static int
619 igb_resume(device_t dev)
620 {
621         struct igb_softc *sc = device_get_softc(dev);
622         struct ifnet *ifp = &sc->arpcom.ac_if;
623
624         ifnet_serialize_all(ifp);
625
626         igb_init(sc);
627         igb_get_mgmt(sc);
628
629         if_devstart(ifp);
630
631         ifnet_deserialize_all(ifp);
632
633         return bus_generic_resume(dev);
634 }
635
636 static int
637 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
638 {
639         struct igb_softc *sc = ifp->if_softc;
640         struct ifreq *ifr = (struct ifreq *)data;
641         int max_frame_size, mask, reinit;
642         int error = 0;
643
644         ASSERT_IFNET_SERIALIZED_ALL(ifp);
645
646         switch (command) {
647         case SIOCSIFMTU:
648                 max_frame_size = 9234;
649                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
650                     ETHER_CRC_LEN) {
651                         error = EINVAL;
652                         break;
653                 }
654
655                 ifp->if_mtu = ifr->ifr_mtu;
656                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
657                     ETHER_CRC_LEN;
658
659                 if (ifp->if_flags & IFF_RUNNING)
660                         igb_init(sc);
661                 break;
662
663         case SIOCSIFFLAGS:
664                 if (ifp->if_flags & IFF_UP) {
665                         if (ifp->if_flags & IFF_RUNNING) {
666                                 if ((ifp->if_flags ^ sc->if_flags) &
667                                     (IFF_PROMISC | IFF_ALLMULTI)) {
668                                         igb_disable_promisc(sc);
669                                         igb_set_promisc(sc);
670                                 }
671                         } else {
672                                 igb_init(sc);
673                         }
674                 } else if (ifp->if_flags & IFF_RUNNING) {
675                         igb_stop(sc);
676                 }
677                 sc->if_flags = ifp->if_flags;
678                 break;
679
680         case SIOCADDMULTI:
681         case SIOCDELMULTI:
682                 if (ifp->if_flags & IFF_RUNNING) {
683                         igb_disable_intr(sc);
684                         igb_set_multi(sc);
685 #ifdef DEVICE_POLLING
686                         if (!(ifp->if_flags & IFF_POLLING))
687 #endif
688                                 igb_enable_intr(sc);
689                 }
690                 break;
691
692         case SIOCSIFMEDIA:
693                 /*
694                  * As the speed/duplex settings are being
695                  * changed, we need toreset the PHY.
696                  */
697                 sc->hw.phy.reset_disable = FALSE;
698
699                 /* Check SOL/IDER usage */
700                 if (e1000_check_reset_block(&sc->hw)) {
701                         if_printf(ifp, "Media change is "
702                             "blocked due to SOL/IDER session.\n");
703                         break;
704                 }
705                 /* FALL THROUGH */
706
707         case SIOCGIFMEDIA:
708                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
709                 break;
710
711         case SIOCSIFCAP:
712                 reinit = 0;
713                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
714                 if (mask & IFCAP_HWCSUM) {
715                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
716                         reinit = 1;
717                 }
718                 if (mask & IFCAP_VLAN_HWTAGGING) {
719                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
720                         reinit = 1;
721                 }
722                 if (reinit && (ifp->if_flags & IFF_RUNNING))
723                         igb_init(sc);
724                 break;
725
726         default:
727                 error = ether_ioctl(ifp, command, data);
728                 break;
729         }
730         return error;
731 }
732
733 static void
734 igb_init(void *xsc)
735 {
736         struct igb_softc *sc = xsc;
737         struct ifnet *ifp = &sc->arpcom.ac_if;
738         int i;
739
740         ASSERT_IFNET_SERIALIZED_ALL(ifp);
741
742         igb_stop(sc);
743
744         /* Get the latest mac address, User can use a LAA */
745         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
746
747         /* Put the address into the Receive Address Array */
748         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
749
750         igb_reset(sc);
751         igb_update_link_status(sc);
752
753         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
754
755         /* Set hardware offload abilities */
756         if (ifp->if_capenable & IFCAP_TXCSUM)
757                 ifp->if_hwassist = IGB_CSUM_FEATURES;
758         else
759                 ifp->if_hwassist = 0;
760
761         /* Configure for OS presence */
762         igb_get_mgmt(sc);
763
764         /* Prepare transmit descriptors and buffers */
765         for (i = 0; i < sc->num_queues; ++i)
766                 igb_init_tx_ring(&sc->tx_rings[i]);
767         igb_init_tx_unit(sc);
768
769         /* Setup Multicast table */
770         igb_set_multi(sc);
771
772 #if 0
773         /*
774          * Figure out the desired mbuf pool
775          * for doing jumbo/packetsplit
776          */
777         if (adapter->max_frame_size <= 2048)
778                 adapter->rx_mbuf_sz = MCLBYTES;
779         else if (adapter->max_frame_size <= 4096)
780                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
781         else
782                 adapter->rx_mbuf_sz = MJUM9BYTES;
783 #else
784         sc->rx_mbuf_sz = MCLBYTES;
785 #endif
786
787         /* Prepare receive descriptors and buffers */
788         for (i = 0; i < sc->num_queues; ++i) {
789                 int error;
790
791                 error = igb_init_rx_ring(&sc->rx_rings[i]);
792                 if (error) {
793                         if_printf(ifp, "Could not setup receive structures\n");
794                         igb_stop(sc);
795                         return;
796                 }
797         }
798         igb_init_rx_unit(sc);
799
800         /* Enable VLAN support */
801         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
802                 igb_set_vlan(sc);
803
804         /* Don't lose promiscuous settings */
805         igb_set_promisc(sc);
806
807         /* Configure interrupt moderation */
808         igb_set_itr(sc);
809
810         ifp->if_flags |= IFF_RUNNING;
811         ifp->if_flags &= ~IFF_OACTIVE;
812
813         callout_reset(&sc->timer, hz, igb_timer, sc);
814         e1000_clear_hw_cntrs_base_generic(&sc->hw);
815
816 #if 0
817         if (adapter->msix > 1) /* Set up queue routing */
818                 igb_configure_queues(adapter);
819 #endif
820
821         /* this clears any pending interrupts */
822         E1000_READ_REG(&sc->hw, E1000_ICR);
823 #ifdef DEVICE_POLLING
824         /*
825          * Only enable interrupts if we are not polling, make sure
826          * they are off otherwise.
827          */
828         if (ifp->if_flags & IFF_POLLING)
829                 igb_disable_intr(sc);
830         else
831 #endif /* DEVICE_POLLING */
832         {
833                 igb_enable_intr(sc);
834                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
835         }
836
837         /* Set Energy Efficient Ethernet */
838         e1000_set_eee_i350(&sc->hw);
839
840         /* Don't reset the phy next time init gets called */
841         sc->hw.phy.reset_disable = TRUE;
842 }
843
844 static void
845 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
846 {
847         struct igb_softc *sc = ifp->if_softc;
848         u_char fiber_type = IFM_1000_SX;
849
850         ASSERT_IFNET_SERIALIZED_ALL(ifp);
851
852         igb_update_link_status(sc);
853
854         ifmr->ifm_status = IFM_AVALID;
855         ifmr->ifm_active = IFM_ETHER;
856
857         if (!sc->link_active)
858                 return;
859
860         ifmr->ifm_status |= IFM_ACTIVE;
861
862         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
863             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
864                 ifmr->ifm_active |= fiber_type | IFM_FDX;
865         } else {
866                 switch (sc->link_speed) {
867                 case 10:
868                         ifmr->ifm_active |= IFM_10_T;
869                         break;
870
871                 case 100:
872                         ifmr->ifm_active |= IFM_100_TX;
873                         break;
874
875                 case 1000:
876                         ifmr->ifm_active |= IFM_1000_T;
877                         break;
878                 }
879                 if (sc->link_duplex == FULL_DUPLEX)
880                         ifmr->ifm_active |= IFM_FDX;
881                 else
882                         ifmr->ifm_active |= IFM_HDX;
883         }
884 }
885
886 static int
887 igb_media_change(struct ifnet *ifp)
888 {
889         struct igb_softc *sc = ifp->if_softc;
890         struct ifmedia *ifm = &sc->media;
891
892         ASSERT_IFNET_SERIALIZED_ALL(ifp);
893
894         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
895                 return EINVAL;
896
897         switch (IFM_SUBTYPE(ifm->ifm_media)) {
898         case IFM_AUTO:
899                 sc->hw.mac.autoneg = DO_AUTO_NEG;
900                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
901                 break;
902
903         case IFM_1000_LX:
904         case IFM_1000_SX:
905         case IFM_1000_T:
906                 sc->hw.mac.autoneg = DO_AUTO_NEG;
907                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
908                 break;
909
910         case IFM_100_TX:
911                 sc->hw.mac.autoneg = FALSE;
912                 sc->hw.phy.autoneg_advertised = 0;
913                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
914                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
915                 else
916                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
917                 break;
918
919         case IFM_10_T:
920                 sc->hw.mac.autoneg = FALSE;
921                 sc->hw.phy.autoneg_advertised = 0;
922                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
923                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
924                 else
925                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
926                 break;
927
928         default:
929                 if_printf(ifp, "Unsupported media type\n");
930                 break;
931         }
932
933         igb_init(sc);
934
935         return 0;
936 }
937
938 static void
939 igb_set_promisc(struct igb_softc *sc)
940 {
941         struct ifnet *ifp = &sc->arpcom.ac_if;
942         struct e1000_hw *hw = &sc->hw;
943         uint32_t reg;
944
945         if (sc->vf_ifp) {
946                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
947                 return;
948         }
949
950         reg = E1000_READ_REG(hw, E1000_RCTL);
951         if (ifp->if_flags & IFF_PROMISC) {
952                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
953                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
954         } else if (ifp->if_flags & IFF_ALLMULTI) {
955                 reg |= E1000_RCTL_MPE;
956                 reg &= ~E1000_RCTL_UPE;
957                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
958         }
959 }
960
961 static void
962 igb_disable_promisc(struct igb_softc *sc)
963 {
964         struct e1000_hw *hw = &sc->hw;
965         uint32_t reg;
966
967         if (sc->vf_ifp) {
968                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
969                 return;
970         }
971         reg = E1000_READ_REG(hw, E1000_RCTL);
972         reg &= ~E1000_RCTL_UPE;
973         reg &= ~E1000_RCTL_MPE;
974         E1000_WRITE_REG(hw, E1000_RCTL, reg);
975 }
976
977 static void
978 igb_set_multi(struct igb_softc *sc)
979 {
980         struct ifnet *ifp = &sc->arpcom.ac_if;
981         struct ifmultiaddr *ifma;
982         uint32_t reg_rctl = 0;
983         uint8_t *mta;
984         int mcnt = 0;
985
986         mta = sc->mta;
987         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
988
989         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
990                 if (ifma->ifma_addr->sa_family != AF_LINK)
991                         continue;
992
993                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
994                         break;
995
996                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
997                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
998                 mcnt++;
999         }
1000
1001         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1002                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1003                 reg_rctl |= E1000_RCTL_MPE;
1004                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1005         } else {
1006                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1007         }
1008 }
1009
1010 static void
1011 igb_timer(void *xsc)
1012 {
1013         struct igb_softc *sc = xsc;
1014         struct ifnet *ifp = &sc->arpcom.ac_if;
1015
1016         ifnet_serialize_all(ifp);
1017
1018         igb_update_link_status(sc);
1019         igb_update_stats_counters(sc);
1020
1021         callout_reset(&sc->timer, hz, igb_timer, sc);
1022
1023         ifnet_deserialize_all(ifp);
1024 }
1025
1026 static void
1027 igb_update_link_status(struct igb_softc *sc)
1028 {
1029         struct ifnet *ifp = &sc->arpcom.ac_if;
1030         struct e1000_hw *hw = &sc->hw;
1031         uint32_t link_check, thstat, ctrl;
1032
1033         link_check = thstat = ctrl = 0;
1034
1035         /* Get the cached link value or read for real */
1036         switch (hw->phy.media_type) {
1037         case e1000_media_type_copper:
1038                 if (hw->mac.get_link_status) {
1039                         /* Do the work to read phy */
1040                         e1000_check_for_link(hw);
1041                         link_check = !hw->mac.get_link_status;
1042                 } else {
1043                         link_check = TRUE;
1044                 }
1045                 break;
1046
1047         case e1000_media_type_fiber:
1048                 e1000_check_for_link(hw);
1049                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1050                 break;
1051
1052         case e1000_media_type_internal_serdes:
1053                 e1000_check_for_link(hw);
1054                 link_check = hw->mac.serdes_has_link;
1055                 break;
1056
1057         /* VF device is type_unknown */
1058         case e1000_media_type_unknown:
1059                 e1000_check_for_link(hw);
1060                 link_check = !hw->mac.get_link_status;
1061                 /* Fall thru */
1062         default:
1063                 break;
1064         }
1065
1066         /* Check for thermal downshift or shutdown */
1067         if (hw->mac.type == e1000_i350) {
1068                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1069                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1070         }
1071
1072         /* Now we check if a transition has happened */
1073         if (link_check && sc->link_active == 0) {
1074                 e1000_get_speed_and_duplex(hw, 
1075                     &sc->link_speed, &sc->link_duplex);
1076                 if (bootverbose) {
1077                         if_printf(ifp, "Link is up %d Mbps %s\n",
1078                             sc->link_speed,
1079                             sc->link_duplex == FULL_DUPLEX ?
1080                             "Full Duplex" : "Half Duplex");
1081                 }
1082                 sc->link_active = 1;
1083
1084                 ifp->if_baudrate = sc->link_speed * 1000000;
1085                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1086                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1087                         if_printf(ifp, "Link: thermal downshift\n");
1088                 /* This can sleep */
1089                 ifp->if_link_state = LINK_STATE_UP;
1090                 if_link_state_change(ifp);
1091         } else if (!link_check && sc->link_active == 1) {
1092                 ifp->if_baudrate = sc->link_speed = 0;
1093                 sc->link_duplex = 0;
1094                 if (bootverbose)
1095                         if_printf(ifp, "Link is Down\n");
1096                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1097                     (thstat & E1000_THSTAT_PWR_DOWN))
1098                         if_printf(ifp, "Link: thermal shutdown\n");
1099                 sc->link_active = 0;
1100                 /* This can sleep */
1101                 ifp->if_link_state = LINK_STATE_DOWN;
1102                 if_link_state_change(ifp);
1103         }
1104 }
1105
1106 static void
1107 igb_stop(struct igb_softc *sc)
1108 {
1109         struct ifnet *ifp = &sc->arpcom.ac_if;
1110         int i;
1111
1112         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1113
1114         igb_disable_intr(sc);
1115
1116         callout_stop(&sc->timer);
1117
1118         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1119         ifp->if_timer = 0;
1120
1121         e1000_reset_hw(&sc->hw);
1122         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1123
1124         e1000_led_off(&sc->hw);
1125         e1000_cleanup_led(&sc->hw);
1126
1127         for (i = 0; i < sc->num_queues; ++i)
1128                 igb_free_tx_ring(&sc->tx_rings[i]);
1129         for (i = 0; i < sc->num_queues; ++i)
1130                 igb_free_rx_ring(&sc->rx_rings[i]);
1131 }
1132
1133 static void
1134 igb_reset(struct igb_softc *sc)
1135 {
1136         struct ifnet *ifp = &sc->arpcom.ac_if;
1137         struct e1000_hw *hw = &sc->hw;
1138         struct e1000_fc_info *fc = &hw->fc;
1139         uint32_t pba = 0;
1140         uint16_t hwm;
1141
1142         /* Let the firmware know the OS is in control */
1143         igb_get_hw_control(sc);
1144
1145         /*
1146          * Packet Buffer Allocation (PBA)
1147          * Writing PBA sets the receive portion of the buffer
1148          * the remainder is used for the transmit buffer.
1149          */
1150         switch (hw->mac.type) {
1151         case e1000_82575:
1152                 pba = E1000_PBA_32K;
1153                 break;
1154
1155         case e1000_82576:
1156         case e1000_vfadapt:
1157                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1158                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1159                 break;
1160
1161         case e1000_82580:
1162         case e1000_i350:
1163         case e1000_vfadapt_i350:
1164                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1165                 pba = e1000_rxpbs_adjust_82580(pba);
1166                 break;
1167                 /* XXX pba = E1000_PBA_35K; */
1168
1169         default:
1170                 break;
1171         }
1172
1173         /* Special needs in case of Jumbo frames */
1174         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1175                 uint32_t tx_space, min_tx, min_rx;
1176
1177                 pba = E1000_READ_REG(hw, E1000_PBA);
1178                 tx_space = pba >> 16;
1179                 pba &= 0xffff;
1180
1181                 min_tx = (sc->max_frame_size +
1182                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1183                 min_tx = roundup2(min_tx, 1024);
1184                 min_tx >>= 10;
1185                 min_rx = sc->max_frame_size;
1186                 min_rx = roundup2(min_rx, 1024);
1187                 min_rx >>= 10;
1188                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1189                         pba = pba - (min_tx - tx_space);
1190                         /*
1191                          * if short on rx space, rx wins
1192                          * and must trump tx adjustment
1193                          */
1194                         if (pba < min_rx)
1195                                 pba = min_rx;
1196                 }
1197                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1198         }
1199
1200         /*
1201          * These parameters control the automatic generation (Tx) and
1202          * response (Rx) to Ethernet PAUSE frames.
1203          * - High water mark should allow for at least two frames to be
1204          *   received after sending an XOFF.
1205          * - Low water mark works best when it is very near the high water mark.
1206          *   This allows the receiver to restart by sending XON when it has
1207          *   drained a bit.
1208          */
1209         hwm = min(((pba << 10) * 9 / 10),
1210             ((pba << 10) - 2 * sc->max_frame_size));
1211
1212         if (hw->mac.type < e1000_82576) {
1213                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1214                 fc->low_water = fc->high_water - 8;
1215         } else {
1216                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1217                 fc->low_water = fc->high_water - 16;
1218         }
1219         fc->pause_time = IGB_FC_PAUSE_TIME;
1220         fc->send_xon = TRUE;
1221
1222         /* Issue a global reset */
1223         e1000_reset_hw(hw);
1224         E1000_WRITE_REG(hw, E1000_WUC, 0);
1225
1226         if (e1000_init_hw(hw) < 0)
1227                 if_printf(ifp, "Hardware Initialization Failed\n");
1228
1229         /* Setup DMA Coalescing */
1230         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1231                 uint32_t reg;
1232
1233                 hwm = (pba - 4) << 10;
1234                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1235                     & E1000_DMACR_DMACTHR_MASK;
1236
1237                 /* transition to L0x or L1 if available..*/
1238                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1239
1240                 /* timer = +-1000 usec in 32usec intervals */
1241                 reg |= (1000 >> 5);
1242                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1243
1244                 /* No lower threshold */
1245                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1246
1247                 /* set hwm to PBA -  2 * max frame size */
1248                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1249
1250                 /* Set the interval before transition */
1251                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1252                 reg |= 0x800000FF; /* 255 usec */
1253                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1254
1255                 /* free space in tx packet buffer to wake from DMA coal */
1256                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1257                     (20480 - (2 * sc->max_frame_size)) >> 6);
1258
1259                 /* make low power state decision controlled by DMA coal */
1260                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1261                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1262                     reg | E1000_PCIEMISC_LX_DECISION);
1263                 if_printf(ifp, "DMA Coalescing enabled\n");
1264         }
1265
1266         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1267         e1000_get_phy_info(hw);
1268         e1000_check_for_link(hw);
1269 }
1270
1271 static void
1272 igb_setup_ifp(struct igb_softc *sc)
1273 {
1274         struct ifnet *ifp = &sc->arpcom.ac_if;
1275
1276         if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1277         ifp->if_softc = sc;
1278         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1279         ifp->if_init =  igb_init;
1280         ifp->if_ioctl = igb_ioctl;
1281         ifp->if_start = igb_start;
1282 #ifdef DEVICE_POLLING
1283         ifp->if_poll = igb_poll;
1284 #endif
1285         ifp->if_watchdog = igb_watchdog;
1286
1287         ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1288         ifq_set_ready(&ifp->if_snd);
1289
1290         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1291
1292         ifp->if_capabilities =
1293             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1294         ifp->if_capenable = ifp->if_capabilities;
1295         ifp->if_hwassist = IGB_CSUM_FEATURES;
1296
1297         /*
1298          * Tell the upper layer(s) we support long frames
1299          */
1300         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1301
1302         /*
1303          * Specify the media types supported by this adapter and register
1304          * callbacks to update media and link information
1305          */
1306         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1307         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1308             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1309                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1310                     0, NULL);
1311                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1312         } else {
1313                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1314                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1315                     0, NULL);
1316                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1317                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1318                     0, NULL);
1319                 if (sc->hw.phy.type != e1000_phy_ife) {
1320                         ifmedia_add(&sc->media,
1321                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1322                         ifmedia_add(&sc->media,
1323                             IFM_ETHER | IFM_1000_T, 0, NULL);
1324                 }
1325         }
1326         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1327         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1328 }
1329
1330 static void
1331 igb_add_sysctl(struct igb_softc *sc)
1332 {
1333         sysctl_ctx_init(&sc->sysctl_ctx);
1334         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1335             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1336             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1337         if (sc->sysctl_tree == NULL) {
1338                 device_printf(sc->dev, "can't add sysctl node\n");
1339                 return;
1340         }
1341
1342         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1343             OID_AUTO, "rxd", CTLFLAG_RD, &sc->num_rx_desc, 0, NULL);
1344         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1345             OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
1346
1347         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1348             OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1349             sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1350 }
1351
1352 static int
1353 igb_dma_alloc(struct igb_softc *sc)
1354 {
1355         int error, i;
1356
1357         /* First allocate the top level queue structs */
1358         sc->queues = kmalloc(sizeof(struct igb_queue) * sc->num_queues,
1359             M_DEVBUF, M_WAITOK | M_ZERO);
1360
1361         /*
1362          * Create top level busdma tag
1363          */
1364         error = bus_dma_tag_create(NULL, 1, 0,
1365             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1366             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1367             &sc->parent_tag);
1368         if (error) {
1369                 device_printf(sc->dev, "could not create top level DMA tag\n");
1370                 return error;
1371         }
1372
1373         /*
1374          * Allocate TX descriptor rings and buffers
1375          */
1376         sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->num_queues,
1377             M_DEVBUF, M_WAITOK | M_ZERO);
1378         for (i = 0; i < sc->num_queues; ++i) {
1379                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1380
1381                 /* Set up some basics */
1382                 txr->sc = sc;
1383                 txr->me = i;
1384
1385                 error = igb_create_tx_ring(txr);
1386                 if (error)
1387                         return error;
1388         }
1389
1390         /*
1391          * Allocate RX descriptor rings and buffers
1392          */ 
1393         sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->num_queues,
1394             M_DEVBUF, M_WAITOK | M_ZERO);
1395         for (i = 0; i < sc->num_queues; ++i) {
1396                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1397
1398                 /* Set up some basics */
1399                 rxr->sc = sc;
1400                 rxr->me = i;
1401
1402                 error = igb_create_rx_ring(rxr);
1403                 if (error)
1404                         return error;
1405         }
1406
1407         /*
1408          * Finally set up the queue holding structs
1409          */
1410         for (i = 0; i < sc->num_queues; i++) {
1411                 struct igb_queue *que = &sc->queues[i];
1412
1413                 que->sc = sc;
1414                 que->txr = &sc->tx_rings[i];
1415                 que->rxr = &sc->rx_rings[i];
1416         }
1417         return 0;
1418 }
1419
1420 static void
1421 igb_dma_free(struct igb_softc *sc)
1422 {
1423         int i;
1424
1425         if (sc->queues != NULL)
1426                 kfree(sc->queues, M_DEVBUF);
1427
1428         if (sc->tx_rings != NULL) {
1429                 for (i = 0; i < sc->num_queues; ++i)
1430                         igb_destroy_tx_ring(&sc->tx_rings[i], sc->num_tx_desc);
1431                 kfree(sc->tx_rings, M_DEVBUF);
1432         }
1433
1434         if (sc->rx_rings != NULL) {
1435                 for (i = 0; i < sc->num_queues; ++i)
1436                         igb_destroy_rx_ring(&sc->rx_rings[i], sc->num_rx_desc);
1437                 kfree(sc->rx_rings, M_DEVBUF);
1438         }
1439 }
1440
1441 static int
1442 igb_create_tx_ring(struct igb_tx_ring *txr)
1443 {
1444         int tsize, error, i;
1445
1446         /*
1447          * Validate number of transmit descriptors. It must not exceed
1448          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1449          */
1450         if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1451             (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1452                 device_printf(txr->sc->dev,
1453                     "Using %d TX descriptors instead of %d!\n",
1454                     IGB_DEFAULT_TXD, igb_txd);
1455                 txr->sc->num_tx_desc = IGB_DEFAULT_TXD;
1456         } else {
1457                 txr->sc->num_tx_desc = igb_txd;
1458         }
1459
1460         /*
1461          * Allocate TX descriptor ring
1462          */
1463         tsize = roundup2(txr->sc->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1464             IGB_DBA_ALIGN);
1465         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1466             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1467             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1468         if (txr->txdma.dma_vaddr == NULL) {
1469                 device_printf(txr->sc->dev,
1470                     "Unable to allocate TX Descriptor memory\n");
1471                 return ENOMEM;
1472         }
1473         txr->tx_base = txr->txdma.dma_vaddr;
1474         bzero(txr->tx_base, tsize);
1475
1476         txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->sc->num_tx_desc,
1477             M_DEVBUF, M_WAITOK | M_ZERO);
1478
1479         /*
1480          * Create DMA tag for TX buffers
1481          */
1482         error = bus_dma_tag_create(txr->sc->parent_tag,
1483             1, 0,               /* alignment, bounds */
1484             BUS_SPACE_MAXADDR,  /* lowaddr */
1485             BUS_SPACE_MAXADDR,  /* highaddr */
1486             NULL, NULL,         /* filter, filterarg */
1487             IGB_TSO_SIZE,       /* maxsize */
1488             IGB_MAX_SCATTER,    /* nsegments */
1489             PAGE_SIZE,          /* maxsegsize */
1490             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1491             BUS_DMA_ONEBPAGE,   /* flags */
1492             &txr->tx_tag);
1493         if (error) {
1494                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1495                 kfree(txr->tx_buf, M_DEVBUF);
1496                 txr->tx_buf = NULL;
1497                 return error;
1498         }
1499
1500         /*
1501          * Create DMA maps for TX buffers
1502          */
1503         for (i = 0; i < txr->sc->num_tx_desc; ++i) {
1504                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1505
1506                 error = bus_dmamap_create(txr->tx_tag,
1507                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1508                 if (error) {
1509                         device_printf(txr->sc->dev,
1510                             "Unable to create TX DMA map\n");
1511                         igb_destroy_tx_ring(txr, i);
1512                         return error;
1513                 }
1514         }
1515         return 0;
1516 }
1517
1518 static void
1519 igb_free_tx_ring(struct igb_tx_ring *txr)
1520 {
1521         int i;
1522
1523         for (i = 0; i < txr->sc->num_tx_desc; ++i) {
1524                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1525
1526                 if (txbuf->m_head != NULL) {
1527                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1528                         m_freem(txbuf->m_head);
1529                         txbuf->m_head = NULL;
1530                 }
1531         }
1532 }
1533
1534 static void
1535 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1536 {
1537         int i;
1538
1539         if (txr->txdma.dma_vaddr != NULL) {
1540                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1541                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1542                     txr->txdma.dma_map);
1543                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1544                 txr->txdma.dma_vaddr = NULL;
1545         }
1546
1547         if (txr->tx_buf == NULL)
1548                 return;
1549
1550         for (i = 0; i < ndesc; ++i) {
1551                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1552
1553                 KKASSERT(txbuf->m_head == NULL);
1554                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1555         }
1556         bus_dma_tag_destroy(txr->tx_tag);
1557
1558         kfree(txr->tx_buf, M_DEVBUF);
1559         txr->tx_buf = NULL;
1560 }
1561
1562 static void
1563 igb_init_tx_ring(struct igb_tx_ring *txr)
1564 {
1565         int i;
1566
1567         /* Clear the old descriptor contents */
1568         bzero(txr->tx_base,
1569             sizeof(union e1000_adv_tx_desc) * txr->sc->num_tx_desc);
1570
1571         /* Reset indices */
1572         txr->next_avail_desc = 0;
1573         txr->next_to_clean = 0;
1574
1575         /* Clear the watch index */
1576         for (i = 0; i < txr->sc->num_tx_desc; ++i)
1577                 txr->tx_buf[i].next_eop = -1;
1578
1579         /* Set number of descriptors available */
1580         txr->tx_avail = txr->sc->num_tx_desc;
1581 }
1582
1583 static void
1584 igb_init_tx_unit(struct igb_softc *sc)
1585 {
1586         struct e1000_hw *hw = &sc->hw;
1587         uint32_t tctl;
1588         int i;
1589
1590         /* Setup the Tx Descriptor Rings */
1591         for (i = 0; i < sc->num_queues; ++i) {
1592                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1593                 uint64_t bus_addr = txr->txdma.dma_paddr;
1594                 uint32_t txdctl = 0;
1595
1596                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1597                     sc->num_tx_desc * sizeof(struct e1000_tx_desc));
1598                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1599                     (uint32_t)(bus_addr >> 32));
1600                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1601                     (uint32_t)bus_addr);
1602
1603                 /* Setup the HW Tx Head and Tail descriptor pointers */
1604                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1605                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1606
1607                 txdctl |= IGB_TX_PTHRESH;
1608                 txdctl |= IGB_TX_HTHRESH << 8;
1609                 txdctl |= IGB_TX_WTHRESH << 16;
1610                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1611                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1612         }
1613
1614         if (sc->vf_ifp)
1615                 return;
1616
1617         e1000_config_collision_dist(hw);
1618
1619         /* Program the Transmit Control Register */
1620         tctl = E1000_READ_REG(hw, E1000_TCTL);
1621         tctl &= ~E1000_TCTL_CT;
1622         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1623             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1624
1625         /* This write will effectively turn on the transmit unit. */
1626         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1627 }
1628
1629 static boolean_t
1630 igb_txctx(struct igb_tx_ring *txr, struct mbuf *mp)
1631 {
1632         struct e1000_adv_tx_context_desc *TXD;
1633         struct igb_tx_buf *txbuf;
1634         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1635         struct ether_vlan_header *eh;
1636         struct ip *ip = NULL;
1637         int ehdrlen, ctxd, ip_hlen = 0;
1638         uint16_t etype, vlantag = 0;
1639         boolean_t offload = TRUE;
1640
1641         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1642                 offload = FALSE;
1643
1644         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1645         ctxd = txr->next_avail_desc;
1646         txbuf = &txr->tx_buf[ctxd];
1647         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1648
1649         /*
1650          * In advanced descriptors the vlan tag must 
1651          * be placed into the context descriptor, thus
1652          * we need to be here just for that setup.
1653          */
1654         if (mp->m_flags & M_VLANTAG) {
1655                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1656                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1657         } else if (!offload) {
1658                 return FALSE;
1659         }
1660
1661         /*
1662          * Determine where frame payload starts.
1663          * Jump over vlan headers if already present,
1664          * helpful for QinQ too.
1665          */
1666         KASSERT(mp->m_len >= ETHER_HDR_LEN,
1667             ("igb_txctx_pullup is not called (eh)?\n"));
1668         eh = mtod(mp, struct ether_vlan_header *);
1669         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1670                 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
1671                     ("igb_txctx_pullup is not called (evh)?\n"));
1672                 etype = ntohs(eh->evl_proto);
1673                 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
1674         } else {
1675                 etype = ntohs(eh->evl_encap_proto);
1676                 ehdrlen = ETHER_HDR_LEN;
1677         }
1678
1679         /* Set the ether header length */
1680         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1681
1682         switch (etype) {
1683         case ETHERTYPE_IP:
1684                 KASSERT(mp->m_len >= ehdrlen + IGB_IPVHL_SIZE,
1685                     ("igb_txctx_pullup is not called (eh+ip_vhl)?\n"));
1686
1687                 /* NOTE: We could only safely access ip.ip_vhl part */
1688                 ip = (struct ip *)(mp->m_data + ehdrlen);
1689                 ip_hlen = ip->ip_hl << 2;
1690
1691                 if (mp->m_pkthdr.csum_flags & CSUM_IP)
1692                         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1693                 break;
1694
1695 #ifdef notyet
1696         case ETHERTYPE_IPV6:
1697                 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1698                 ip_hlen = sizeof(struct ip6_hdr);
1699                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
1700                 break;
1701 #endif
1702
1703         default:
1704                 offload = FALSE;
1705                 break;
1706         }
1707
1708         vlan_macip_lens |= ip_hlen;
1709         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1710
1711         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1712                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1713         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1714                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1715
1716         /* 82575 needs the queue index added */
1717         if (txr->sc->hw.mac.type == e1000_82575)
1718                 mss_l4len_idx = txr->me << 4;
1719
1720         /* Now copy bits into descriptor */
1721         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1722         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1723         TXD->seqnum_seed = htole32(0);
1724         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1725
1726         txbuf->m_head = NULL;
1727         txbuf->next_eop = -1;
1728
1729         /* We've consumed the first desc, adjust counters */
1730         if (++ctxd == txr->sc->num_tx_desc)
1731                 ctxd = 0;
1732         txr->next_avail_desc = ctxd;
1733         --txr->tx_avail;
1734
1735         return offload;
1736 }
1737
1738 static void
1739 igb_txeof(struct igb_tx_ring *txr)
1740 {
1741         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1742         int first, last, done;
1743         struct igb_tx_buf *txbuf;
1744         struct e1000_tx_desc *tx_desc, *eop_desc;
1745
1746         if (txr->tx_avail == txr->sc->num_tx_desc)
1747                 return;
1748
1749         first = txr->next_to_clean;
1750         tx_desc = &txr->tx_base[first];
1751         txbuf = &txr->tx_buf[first];
1752         last = txbuf->next_eop;
1753         eop_desc = &txr->tx_base[last];
1754
1755         /*
1756          * What this does is get the index of the
1757          * first descriptor AFTER the EOP of the 
1758          * first packet, that way we can do the
1759          * simple comparison on the inner while loop.
1760          */
1761         if (++last == txr->sc->num_tx_desc)
1762                 last = 0;
1763         done = last;
1764
1765         while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) {
1766                 /* We clean the range of the packet */
1767                 while (first != done) {
1768                         tx_desc->upper.data = 0;
1769                         tx_desc->lower.data = 0;
1770                         tx_desc->buffer_addr = 0;
1771                         ++txr->tx_avail;
1772
1773                         if (txbuf->m_head) {
1774                                 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1775                                 m_freem(txbuf->m_head);
1776                                 txbuf->m_head = NULL;
1777                         }
1778                         txbuf->next_eop = -1;
1779
1780                         if (++first == txr->sc->num_tx_desc)
1781                                 first = 0;
1782
1783                         txbuf = &txr->tx_buf[first];
1784                         tx_desc = &txr->tx_base[first];
1785                 }
1786                 ++ifp->if_opackets;
1787
1788                 /* See if we can continue to the next packet */
1789                 last = txbuf->next_eop;
1790                 if (last != -1) {
1791                         eop_desc = &txr->tx_base[last];
1792
1793                         /* Get new done point */
1794                         if (++last == txr->sc->num_tx_desc)
1795                                 last = 0;
1796                         done = last;
1797                 } else {
1798                         break;
1799                 }
1800         }
1801         txr->next_to_clean = first;
1802
1803         /*
1804          * If we have a minimum free, clear IFF_OACTIVE
1805          * to tell the stack that it is OK to send packets.
1806          */
1807         if (txr->tx_avail > IGB_TX_CLEANUP_THRESHOLD(txr->sc)) {
1808                 ifp->if_flags &= ~IFF_OACTIVE;
1809
1810 #ifdef foo
1811                 /* All clean, turn off the watchdog */
1812                 if (txr->tx_avail == txr->sc->num_tx_desc)
1813                         ifp->if_timer = 0;
1814 #else
1815                 /*
1816                  * We have enough TX descriptors, turn off
1817                  * the watchdog.  On some 82575EB chips,
1818                  * tiny amount of done TX descriptors will
1819                  * not trigger TX descriptor write-back.
1820                  */
1821                 ifp->if_timer = 0;
1822 #endif
1823         }
1824 }
1825
1826 static int
1827 igb_create_rx_ring(struct igb_rx_ring *rxr)
1828 {
1829         int rsize, i, error;
1830
1831         /*
1832          * Validate number of receive descriptors. It must not exceed
1833          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1834          */
1835         if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1836             (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1837                 device_printf(rxr->sc->dev,
1838                     "Using %d RX descriptors instead of %d!\n",
1839                     IGB_DEFAULT_RXD, igb_rxd);
1840                 rxr->sc->num_rx_desc = IGB_DEFAULT_RXD;
1841         } else {
1842                 rxr->sc->num_rx_desc = igb_rxd;
1843         }
1844
1845         /*
1846          * Allocate RX descriptor ring
1847          */
1848         rsize = roundup2(rxr->sc->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1849             IGB_DBA_ALIGN);
1850         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1851             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1852             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1853             &rxr->rxdma.dma_paddr);
1854         if (rxr->rxdma.dma_vaddr == NULL) {
1855                 device_printf(rxr->sc->dev,
1856                     "Unable to allocate RxDescriptor memory\n");
1857                 return ENOMEM;
1858         }
1859         rxr->rx_base = rxr->rxdma.dma_vaddr;
1860         bzero(rxr->rx_base, rsize);
1861
1862         rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->sc->num_rx_desc,
1863             M_DEVBUF, M_WAITOK | M_ZERO);
1864
1865         /*
1866          * Create DMA tag for RX buffers
1867          */
1868         error = bus_dma_tag_create(rxr->sc->parent_tag,
1869             1, 0,               /* alignment, bounds */
1870             BUS_SPACE_MAXADDR,  /* lowaddr */
1871             BUS_SPACE_MAXADDR,  /* highaddr */
1872             NULL, NULL,         /* filter, filterarg */
1873             MCLBYTES,           /* maxsize */
1874             1,                  /* nsegments */
1875             MCLBYTES,           /* maxsegsize */
1876             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
1877             &rxr->rx_tag);
1878         if (error) {
1879                 device_printf(rxr->sc->dev,
1880                     "Unable to create RX payload DMA tag\n");
1881                 kfree(rxr->rx_buf, M_DEVBUF);
1882                 rxr->rx_buf = NULL;
1883                 return error;
1884         }
1885
1886         /*
1887          * Create spare DMA map for RX buffers
1888          */
1889         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
1890             &rxr->rx_sparemap);
1891         if (error) {
1892                 device_printf(rxr->sc->dev,
1893                     "Unable to create spare RX DMA maps\n");
1894                 bus_dma_tag_destroy(rxr->rx_tag);
1895                 kfree(rxr->rx_buf, M_DEVBUF);
1896                 rxr->rx_buf = NULL;
1897                 return error;
1898         }
1899
1900         /*
1901          * Create DMA maps for RX buffers
1902          */
1903         for (i = 0; i < rxr->sc->num_rx_desc; i++) {
1904                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1905
1906                 error = bus_dmamap_create(rxr->rx_tag,
1907                     BUS_DMA_WAITOK, &rxbuf->map);
1908                 if (error) {
1909                         device_printf(rxr->sc->dev,
1910                             "Unable to create RX DMA maps\n");
1911                         igb_destroy_rx_ring(rxr, i);
1912                         return error;
1913                 }
1914         }
1915         return 0;
1916 }
1917
1918 static void
1919 igb_free_rx_ring(struct igb_rx_ring *rxr)
1920 {
1921         int i;
1922
1923         for (i = 0; i < rxr->sc->num_rx_desc; ++i) {
1924                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1925
1926                 if (rxbuf->m_head != NULL) {
1927                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
1928                         m_freem(rxbuf->m_head);
1929                         rxbuf->m_head = NULL;
1930                 }
1931         }
1932
1933         if (rxr->fmp != NULL)
1934                 m_freem(rxr->fmp);
1935         rxr->fmp = NULL;
1936         rxr->lmp = NULL;
1937 }
1938
1939 static void
1940 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
1941 {
1942         int i;
1943
1944         if (rxr->rxdma.dma_vaddr != NULL) {
1945                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
1946                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
1947                     rxr->rxdma.dma_map);
1948                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
1949                 rxr->rxdma.dma_vaddr = NULL;
1950         }
1951
1952         if (rxr->rx_buf == NULL)
1953                 return;
1954
1955         for (i = 0; i < ndesc; ++i) {
1956                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1957
1958                 KKASSERT(rxbuf->m_head == NULL);
1959                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
1960         }
1961         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
1962         bus_dma_tag_destroy(rxr->rx_tag);
1963
1964         kfree(rxr->rx_buf, M_DEVBUF);
1965         rxr->rx_buf = NULL;
1966 }
1967
1968 static void
1969 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
1970 {
1971         rxd->read.pkt_addr = htole64(rxbuf->paddr);
1972         rxd->wb.upper.status_error = 0;
1973 }
1974
1975 static int
1976 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
1977 {
1978         struct mbuf *m;
1979         bus_dma_segment_t seg;
1980         bus_dmamap_t map;
1981         struct igb_rx_buf *rxbuf;
1982         int error, nseg;
1983
1984         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1985         if (m == NULL) {
1986                 if (wait) {
1987                         if_printf(&rxr->sc->arpcom.ac_if,
1988                             "Unable to allocate RX mbuf\n");
1989                 }
1990                 return ENOBUFS;
1991         }
1992         m->m_len = m->m_pkthdr.len = MCLBYTES;
1993
1994         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
1995                 m_adj(m, ETHER_ALIGN);
1996
1997         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
1998             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
1999         if (error) {
2000                 m_freem(m);
2001                 if (wait) {
2002                         if_printf(&rxr->sc->arpcom.ac_if,
2003                             "Unable to load RX mbuf\n");
2004                 }
2005                 return error;
2006         }
2007
2008         rxbuf = &rxr->rx_buf[i];
2009         if (rxbuf->m_head != NULL)
2010                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2011
2012         map = rxbuf->map;
2013         rxbuf->map = rxr->rx_sparemap;
2014         rxr->rx_sparemap = map;
2015
2016         rxbuf->m_head = m;
2017         rxbuf->paddr = seg.ds_addr;
2018
2019         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2020         return 0;
2021 }
2022
2023 static int
2024 igb_init_rx_ring(struct igb_rx_ring *rxr)
2025 {
2026         int i;
2027
2028         /* Clear the ring contents */
2029         bzero(rxr->rx_base,
2030             rxr->sc->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2031
2032         /* Now replenish the ring mbufs */
2033         for (i = 0; i < rxr->sc->num_rx_desc; ++i) {
2034                 int error;
2035
2036                 error = igb_newbuf(rxr, i, TRUE);
2037                 if (error)
2038                         return error;
2039         }
2040
2041         /* Setup our descriptor indices */
2042         rxr->next_to_check = 0;
2043
2044         rxr->fmp = NULL;
2045         rxr->lmp = NULL;
2046         rxr->discard = FALSE;
2047
2048         return 0;
2049 }
2050
2051 static void
2052 igb_init_rx_unit(struct igb_softc *sc)
2053 {
2054         struct ifnet *ifp = &sc->arpcom.ac_if;
2055         struct e1000_hw *hw = &sc->hw;
2056         uint32_t rctl, rxcsum, srrctl = 0;
2057         int i;
2058
2059         /*
2060          * Make sure receives are disabled while setting
2061          * up the descriptor ring
2062          */
2063         rctl = E1000_READ_REG(hw, E1000_RCTL);
2064         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2065
2066 #if 0
2067         /*
2068         ** Set up for header split
2069         */
2070         if (igb_header_split) {
2071                 /* Use a standard mbuf for the header */
2072                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2073                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2074         } else
2075 #endif
2076                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2077
2078         /*
2079         ** Set up for jumbo frames
2080         */
2081         if (ifp->if_mtu > ETHERMTU) {
2082                 rctl |= E1000_RCTL_LPE;
2083 #if 0
2084                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2085                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2086                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2087                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2088                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2089                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2090                 }
2091                 /* Set maximum packet len */
2092                 psize = adapter->max_frame_size;
2093                 /* are we on a vlan? */
2094                 if (adapter->ifp->if_vlantrunk != NULL)
2095                         psize += VLAN_TAG_SIZE;
2096                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2097 #else
2098                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2099                 rctl |= E1000_RCTL_SZ_2048;
2100 #endif
2101         } else {
2102                 rctl &= ~E1000_RCTL_LPE;
2103                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2104                 rctl |= E1000_RCTL_SZ_2048;
2105         }
2106
2107         /* Setup the Base and Length of the Rx Descriptor Rings */
2108         for (i = 0; i < sc->num_queues; ++i) {
2109                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2110                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2111                 uint32_t rxdctl;
2112
2113                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2114                     sc->num_rx_desc * sizeof(struct e1000_rx_desc));
2115                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2116                     (uint32_t)(bus_addr >> 32));
2117                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2118                     (uint32_t)bus_addr);
2119                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2120                 /* Enable this Queue */
2121                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2122                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2123                 rxdctl &= 0xFFF00000;
2124                 rxdctl |= IGB_RX_PTHRESH;
2125                 rxdctl |= IGB_RX_HTHRESH << 8;
2126                 rxdctl |= IGB_RX_WTHRESH << 16;
2127                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2128         }
2129
2130         /*
2131          * Setup for RX MultiQueue
2132          */
2133         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2134 #if 0
2135         if (adapter->num_queues >1) {
2136                 u32 random[10], mrqc, shift = 0;
2137                 union igb_reta {
2138                         u32 dword;
2139                         u8  bytes[4];
2140                 } reta;
2141
2142                 arc4rand(&random, sizeof(random), 0);
2143                 if (adapter->hw.mac.type == e1000_82575)
2144                         shift = 6;
2145                 /* Warning FM follows */
2146                 for (int i = 0; i < 128; i++) {
2147                         reta.bytes[i & 3] =
2148                             (i % adapter->num_queues) << shift;
2149                         if ((i & 3) == 3)
2150                                 E1000_WRITE_REG(hw,
2151                                     E1000_RETA(i >> 2), reta.dword);
2152                 }
2153                 /* Now fill in hash table */
2154                 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2155                 for (int i = 0; i < 10; i++)
2156                         E1000_WRITE_REG_ARRAY(hw,
2157                             E1000_RSSRK(0), i, random[i]);
2158
2159                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2160                     E1000_MRQC_RSS_FIELD_IPV4_TCP);
2161                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2162                     E1000_MRQC_RSS_FIELD_IPV6_TCP);
2163                 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2164                     E1000_MRQC_RSS_FIELD_IPV6_UDP);
2165                 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2166                     E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2167
2168                 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2169
2170                 /*
2171                 ** NOTE: Receive Full-Packet Checksum Offload 
2172                 ** is mutually exclusive with Multiqueue. However
2173                 ** this is not the same as TCP/IP checksums which
2174                 ** still work.
2175                 */
2176                 rxcsum |= E1000_RXCSUM_PCSD;
2177         } else
2178 #endif
2179         {
2180                 /* Non RSS setup */
2181                 if (ifp->if_capenable & IFCAP_RXCSUM)
2182                         rxcsum |= E1000_RXCSUM_IPPCSE;
2183                 else
2184                         rxcsum &= ~E1000_RXCSUM_TUOFL;
2185         }
2186         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2187
2188         /* Setup the Receive Control Register */
2189         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2190         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2191             E1000_RCTL_RDMTS_HALF |
2192             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2193         /* Strip CRC bytes. */
2194         rctl |= E1000_RCTL_SECRC;
2195         /* Make sure VLAN Filters are off */
2196         rctl &= ~E1000_RCTL_VFE;
2197         /* Don't store bad packets */
2198         rctl &= ~E1000_RCTL_SBP;
2199
2200         /* Enable Receives */
2201         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2202
2203         /*
2204          * Setup the HW Rx Head and Tail Descriptor Pointers
2205          *   - needs to be after enable
2206          */
2207         for (i = 0; i < sc->num_queues; ++i) {
2208                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2209
2210                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2211                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->sc->num_rx_desc - 1);
2212         }
2213 }
2214
2215 static void
2216 igb_rxeof(struct igb_rx_ring *rxr, int count)
2217 {
2218         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2219         union e1000_adv_rx_desc *cur;
2220         uint32_t staterr;
2221         int i;
2222
2223         i = rxr->next_to_check;
2224         cur = &rxr->rx_base[i];
2225         staterr = le32toh(cur->wb.upper.status_error);
2226
2227         if ((staterr & E1000_RXD_STAT_DD) == 0)
2228                 return;
2229
2230         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2231                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2232                 struct mbuf *m = NULL;
2233                 boolean_t eop;
2234
2235                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2236                 if (eop)
2237                         --count;
2238
2239                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2240                     !rxr->discard) {
2241                         struct mbuf *mp = rxbuf->m_head;
2242                         uint16_t vlan;
2243                         int len;
2244
2245                         len = le16toh(cur->wb.upper.length);
2246                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2247                             (staterr & E1000_RXDEXT_STATERR_LB))
2248                                 vlan = be16toh(cur->wb.upper.vlan);
2249                         else
2250                                 vlan = le16toh(cur->wb.upper.vlan);
2251
2252                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2253                             BUS_DMASYNC_POSTREAD);
2254
2255                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2256                                 ifp->if_iqdrops++;
2257                                 goto discard;
2258                         }
2259
2260                         mp->m_len = len;
2261                         if (rxr->fmp == NULL) {
2262                                 mp->m_pkthdr.len = len;
2263                                 rxr->fmp = mp;
2264                                 rxr->lmp = mp;
2265                         } else {
2266                                 rxr->lmp->m_next = mp;
2267                                 rxr->lmp = rxr->lmp->m_next;
2268                                 rxr->fmp->m_pkthdr.len += len;
2269                         }
2270
2271                         if (eop) {
2272                                 m = rxr->fmp;
2273                                 rxr->fmp = NULL;
2274                                 rxr->lmp = NULL;
2275
2276                                 m->m_pkthdr.rcvif = ifp;
2277                                 ifp->if_ipackets++;
2278
2279                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2280                                         igb_rxcsum(staterr, m);
2281
2282                                 if (staterr & E1000_RXD_STAT_VP) {
2283                                         m->m_pkthdr.ether_vlantag = vlan;
2284                                         m->m_flags |= M_VLANTAG;
2285                                 }
2286
2287 #if 0
2288                                 if (ifp->if_capenable & IFCAP_RSS) {
2289                                         pi = emx_rssinfo(m, &pi0, mrq,
2290                                                          rss_hash, staterr);
2291                                 }
2292 #endif
2293                         }
2294                 } else {
2295                         ifp->if_ierrors++;
2296 discard:
2297                         igb_setup_rxdesc(cur, rxbuf);
2298                         if (!eop)
2299                                 rxr->discard = TRUE;
2300                         else
2301                                 rxr->discard = FALSE;
2302                         if (rxr->fmp != NULL) {
2303                                 m_freem(rxr->fmp);
2304                                 rxr->fmp = NULL;
2305                                 rxr->lmp = NULL;
2306                         }
2307                         m = NULL;
2308                 }
2309
2310                 if (m != NULL)
2311                         ether_input_pkt(ifp, m, NULL);
2312
2313                 /* Advance our pointers to the next descriptor. */
2314                 if (++i == rxr->sc->num_rx_desc)
2315                         i = 0;
2316
2317                 cur = &rxr->rx_base[i];
2318                 staterr = le32toh(cur->wb.upper.status_error);
2319         }
2320         rxr->next_to_check = i;
2321
2322         if (--i < 0)
2323                 i = rxr->sc->num_rx_desc - 1;
2324         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2325 }
2326
2327
2328 static void
2329 igb_set_vlan(struct igb_softc *sc)
2330 {
2331         struct e1000_hw *hw = &sc->hw;
2332         uint32_t reg;
2333 #if 0
2334         struct ifnet *ifp = sc->arpcom.ac_if;
2335 #endif
2336
2337         if (sc->vf_ifp) {
2338                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2339                 return;
2340         }
2341
2342         reg = E1000_READ_REG(hw, E1000_CTRL);
2343         reg |= E1000_CTRL_VME;
2344         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2345
2346 #if 0
2347         /* Enable the Filter Table */
2348         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2349                 reg = E1000_READ_REG(hw, E1000_RCTL);
2350                 reg &= ~E1000_RCTL_CFIEN;
2351                 reg |= E1000_RCTL_VFE;
2352                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2353         }
2354 #endif
2355
2356         /* Update the frame size */
2357         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2358             sc->max_frame_size + VLAN_TAG_SIZE);
2359
2360 #if 0
2361         /* Don't bother with table if no vlans */
2362         if ((adapter->num_vlans == 0) ||
2363             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2364                 return;
2365         /*
2366         ** A soft reset zero's out the VFTA, so
2367         ** we need to repopulate it now.
2368         */
2369         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2370                 if (adapter->shadow_vfta[i] != 0) {
2371                         if (adapter->vf_ifp)
2372                                 e1000_vfta_set_vf(hw,
2373                                     adapter->shadow_vfta[i], TRUE);
2374                         else
2375                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2376                                  i, adapter->shadow_vfta[i]);
2377                 }
2378 #endif
2379 }
2380
2381 static void
2382 igb_enable_intr(struct igb_softc *sc)
2383 {
2384         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
2385
2386         /* With RSS set up what to auto clear */
2387         if (sc->msix_mem) {
2388                 uint32_t mask = (sc->que_mask | sc->link_mask);
2389
2390                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, mask);
2391                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, mask);
2392                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, mask);
2393                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2394         } else {
2395                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2396         }
2397         E1000_WRITE_FLUSH(&sc->hw);
2398 }
2399
2400 static void
2401 igb_disable_intr(struct igb_softc *sc)
2402 {
2403         if (sc->msix_mem != NULL) {
2404                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2405                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2406         } 
2407         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2408         E1000_WRITE_FLUSH(&sc->hw);
2409
2410         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
2411 }
2412
2413 /*
2414  * Bit of a misnomer, what this really means is
2415  * to enable OS management of the system... aka
2416  * to disable special hardware management features 
2417  */
2418 static void
2419 igb_get_mgmt(struct igb_softc *sc)
2420 {
2421         if (sc->has_manage) {
2422                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2423                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2424
2425                 /* disable hardware interception of ARP */
2426                 manc &= ~E1000_MANC_ARP_EN;
2427
2428                 /* enable receiving management packets to the host */
2429                 manc |= E1000_MANC_EN_MNG2HOST;
2430                 manc2h |= 1 << 5; /* Mng Port 623 */
2431                 manc2h |= 1 << 6; /* Mng Port 664 */
2432                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2433                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2434         }
2435 }
2436
2437 /*
2438  * Give control back to hardware management controller
2439  * if there is one.
2440  */
2441 static void
2442 igb_rel_mgmt(struct igb_softc *sc)
2443 {
2444         if (sc->has_manage) {
2445                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2446
2447                 /* Re-enable hardware interception of ARP */
2448                 manc |= E1000_MANC_ARP_EN;
2449                 manc &= ~E1000_MANC_EN_MNG2HOST;
2450
2451                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2452         }
2453 }
2454
2455 /*
2456  * Sets CTRL_EXT:DRV_LOAD bit.
2457  *
2458  * For ASF and Pass Through versions of f/w this means that
2459  * the driver is loaded. 
2460  */
2461 static void
2462 igb_get_hw_control(struct igb_softc *sc)
2463 {
2464         uint32_t ctrl_ext;
2465
2466         if (sc->vf_ifp)
2467                 return;
2468
2469         /* Let firmware know the driver has taken over */
2470         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2471         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2472             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2473 }
2474
2475 /*
2476  * Resets CTRL_EXT:DRV_LOAD bit.
2477  *
2478  * For ASF and Pass Through versions of f/w this means that the
2479  * driver is no longer loaded.
2480  */
2481 static void
2482 igb_rel_hw_control(struct igb_softc *sc)
2483 {
2484         uint32_t ctrl_ext;
2485
2486         if (sc->vf_ifp)
2487                 return;
2488
2489         /* Let firmware taken over control of h/w */
2490         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2491         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2492             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2493 }
2494
2495 static int
2496 igb_is_valid_ether_addr(const uint8_t *addr)
2497 {
2498         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2499
2500         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2501                 return FALSE;
2502         return TRUE;
2503 }
2504
2505 /*
2506  * Enable PCI Wake On Lan capability
2507  */
2508 static void
2509 igb_enable_wol(device_t dev)
2510 {
2511         uint16_t cap, status;
2512         uint8_t id;
2513
2514         /* First find the capabilities pointer*/
2515         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2516
2517         /* Read the PM Capabilities */
2518         id = pci_read_config(dev, cap, 1);
2519         if (id != PCIY_PMG)     /* Something wrong */
2520                 return;
2521
2522         /*
2523          * OK, we have the power capabilities,
2524          * so now get the status register
2525          */
2526         cap += PCIR_POWER_STATUS;
2527         status = pci_read_config(dev, cap, 2);
2528         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2529         pci_write_config(dev, cap, status, 2);
2530 }
2531
2532 static void
2533 igb_update_stats_counters(struct igb_softc *sc)
2534 {
2535         struct e1000_hw *hw = &sc->hw;
2536         struct e1000_hw_stats *stats;
2537         struct ifnet *ifp = &sc->arpcom.ac_if;
2538
2539         /* 
2540          * The virtual function adapter has only a
2541          * small controlled set of stats, do only 
2542          * those and return.
2543          */
2544         if (sc->vf_ifp) {
2545                 igb_update_vf_stats_counters(sc);
2546                 return;
2547         }
2548         stats = sc->stats;
2549
2550         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2551             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2552                 stats->symerrs +=
2553                     E1000_READ_REG(hw,E1000_SYMERRS);
2554                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2555         }
2556
2557         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2558         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2559         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2560         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2561
2562         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2563         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2564         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2565         stats->dc += E1000_READ_REG(hw, E1000_DC);
2566         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2567         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2568         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2569
2570         /*
2571          * For watchdog management we need to know if we have been
2572          * paused during the last interval, so capture that here.
2573          */ 
2574         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2575         stats->xoffrxc += sc->pause_frames;
2576         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2577         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2578         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2579         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2580         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2581         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2582         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2583         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2584         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2585         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2586         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2587         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2588
2589         /* For the 64-bit byte counters the low dword must be read first. */
2590         /* Both registers clear on the read of the high dword */
2591
2592         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2593             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2594         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2595             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2596
2597         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2598         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2599         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2600         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2601         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2602
2603         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2604         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2605
2606         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2607         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2608         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2609         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2610         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2611         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2612         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2613         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2614         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2615         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2616
2617         /* Interrupt Counts */
2618
2619         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2620         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2621         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2622         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2623         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2624         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2625         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2626         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2627         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2628
2629         /* Host to Card Statistics */
2630
2631         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2632         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2633         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2634         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2635         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2636         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2637         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2638         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2639             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2640         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2641             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2642         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2643         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2644         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2645
2646         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2647         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2648         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2649         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2650         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2651         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2652
2653         ifp->if_collisions = stats->colc;
2654
2655         /* Rx Errors */
2656         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2657             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2658
2659         /* Tx Errors */
2660         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2661
2662         /* Driver specific counters */
2663         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2664         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2665         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2666         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2667         sc->packet_buf_alloc_tx =
2668             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2669         sc->packet_buf_alloc_rx =
2670             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2671 }
2672
2673 static void
2674 igb_vf_init_stats(struct igb_softc *sc)
2675 {
2676         struct e1000_hw *hw = &sc->hw;
2677         struct e1000_vf_stats *stats;
2678
2679         stats = sc->stats;
2680         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2681         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2682         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2683         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2684         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2685 }
2686  
2687 static void
2688 igb_update_vf_stats_counters(struct igb_softc *sc)
2689 {
2690         struct e1000_hw *hw = &sc->hw;
2691         struct e1000_vf_stats *stats;
2692
2693         if (sc->link_speed == 0)
2694                 return;
2695
2696         stats = sc->stats;
2697         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2698         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2699         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2700         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2701         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2702 }
2703
2704 #ifdef DEVICE_POLLING
2705
2706 static void
2707 igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2708 {
2709         struct igb_softc *sc = ifp->if_softc;
2710         uint32_t reg_icr;
2711
2712         ASSERT_SERIALIZED(ifp->if_serializer);
2713
2714         switch (cmd) {
2715         case POLL_REGISTER:
2716                 igb_disable_intr(sc);
2717                 break;
2718
2719         case POLL_DEREGISTER:
2720                 igb_enable_intr(sc);
2721                 break;
2722
2723         case POLL_AND_CHECK_STATUS:
2724                 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2725                 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2726                         sc->hw.mac.get_link_status = 1;
2727                         igb_update_link_status(sc);
2728                 }
2729                 /* FALL THROUGH */
2730         case POLL_ONLY:
2731                 if (ifp->if_flags & IFF_RUNNING) {
2732                         igb_rxeof(sc->queues[0].rxr, count);
2733
2734                         igb_txeof(sc->queues[0].txr);
2735                         if (!ifq_is_empty(&ifp->if_snd))
2736                                 if_devstart(ifp);
2737                 }
2738                 break;
2739         }
2740 }
2741
2742 #endif /* DEVICE_POLLING */
2743
2744 static void
2745 igb_intr(void *xsc)
2746 {
2747         struct igb_softc *sc = xsc;
2748         struct ifnet *ifp = &sc->arpcom.ac_if;
2749         uint32_t reg_icr;
2750
2751         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2752
2753         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2754
2755         /* Hot eject?  */
2756         if (reg_icr == 0xffffffff)
2757                 return;
2758
2759         /* Definitely not our interrupt.  */
2760         if (reg_icr == 0x0)
2761                 return;
2762
2763         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
2764                 return;
2765
2766         if (ifp->if_flags & IFF_RUNNING) {
2767                 igb_rxeof(sc->queues[0].rxr, -1);
2768
2769                 igb_txeof(sc->queues[0].txr);
2770                 if (!ifq_is_empty(&ifp->if_snd))
2771                         if_devstart(ifp);
2772         }
2773
2774         /* Link status change */
2775         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2776                 sc->hw.mac.get_link_status = 1;
2777                 igb_update_link_status(sc);
2778         }
2779
2780         if (reg_icr & E1000_ICR_RXO)
2781                 sc->rx_overruns++;
2782 }
2783
2784 static int
2785 igb_txctx_pullup(struct igb_tx_ring *txr, struct mbuf **m0)
2786 {
2787         struct mbuf *m = *m0;
2788         struct ether_header *eh;
2789         int len;
2790
2791         txr->ctx_try_pullup++;
2792
2793         len = ETHER_HDR_LEN + IGB_IPVHL_SIZE;
2794
2795         if (__predict_false(!M_WRITABLE(m))) {
2796                 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2797                         txr->ctx_drop1++;
2798                         m_freem(m);
2799                         *m0 = NULL;
2800                         return ENOBUFS;
2801                 }
2802                 eh = mtod(m, struct ether_header *);
2803
2804                 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2805                         len += EVL_ENCAPLEN;
2806
2807                 if (m->m_len < len) {
2808                         txr->ctx_drop2++;
2809                         m_freem(m);
2810                         *m0 = NULL;
2811                         return ENOBUFS;
2812                 }
2813                 return 0;
2814         }
2815
2816         if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2817                 txr->ctx_pullup1++;
2818                 m = m_pullup(m, ETHER_HDR_LEN);
2819                 if (m == NULL) {
2820                         txr->ctx_pullup1_failed++;
2821                         *m0 = NULL;
2822                         return ENOBUFS;
2823                 }
2824                 *m0 = m;
2825         }
2826         eh = mtod(m, struct ether_header *);
2827
2828         if (eh->ether_type == htons(ETHERTYPE_VLAN))
2829                 len += EVL_ENCAPLEN;
2830
2831         if (m->m_len < len) {
2832                 txr->ctx_pullup2++;
2833                 m = m_pullup(m, len);
2834                 if (m == NULL) {
2835                         txr->ctx_pullup2_failed++;
2836                         *m0 = NULL;
2837                         return ENOBUFS;
2838                 }
2839                 *m0 = m;
2840         }
2841         return 0;
2842 }
2843
2844 static int
2845 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
2846 {
2847         bus_dma_segment_t segs[IGB_MAX_SCATTER];
2848         bus_dmamap_t map;
2849         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
2850         union e1000_adv_tx_desc *txd = NULL;
2851         struct mbuf *m_head = *m_headp;
2852         uint32_t olinfo_status = 0, cmd_type_len = 0;
2853         int maxsegs, nsegs, i, j, error, first, last = 0;
2854         uint32_t hdrlen = 0;
2855
2856         if (m_head->m_len < IGB_TXCSUM_MINHL &&
2857             ((m_head->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) ||
2858              (m_head->m_flags & M_VLANTAG))) {
2859                 /*
2860                  * Make sure that ethernet header and ip.ip_hl are in
2861                  * contiguous memory, since if TXCSUM or VLANTAG is
2862                  * enabled, later TX context descriptor's setup need
2863                  * to access ip.ip_hl.
2864                  */
2865                 error = igb_txctx_pullup(txr, m_headp);
2866                 if (error) {
2867                         KKASSERT(*m_headp == NULL);
2868                         return error;
2869                 }
2870                 m_head = *m_headp;
2871         }
2872
2873         /* Set basic descriptor constants */
2874         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
2875         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
2876         if (m_head->m_flags & M_VLANTAG)
2877                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2878
2879         /*
2880          * Map the packet for DMA.
2881          *
2882          * Capture the first descriptor index,
2883          * this descriptor will have the index
2884          * of the EOP which is the only one that
2885          * now gets a DONE bit writeback.
2886          */
2887         first = txr->next_avail_desc;
2888         tx_buf = &txr->tx_buf[first];
2889         tx_buf_mapped = tx_buf;
2890         map = tx_buf->map;
2891
2892         KASSERT(txr->tx_avail > 2, ("invalid avail TX desc\n"));
2893         maxsegs = txr->tx_avail - 2;
2894         KASSERT(maxsegs >= IGB_MAX_SCATTER - 2, ("not enough spare TX desc\n"));
2895         if (maxsegs > IGB_MAX_SCATTER)
2896                 maxsegs = IGB_MAX_SCATTER;
2897
2898         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
2899             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2900         if (error) {
2901                 if (error == ENOBUFS)
2902                         txr->sc->mbuf_defrag_failed++;
2903                 else
2904                         txr->sc->no_tx_dma_setup++;
2905
2906                 m_freem(*m_headp);
2907                 *m_headp = NULL;
2908                 return error;
2909         }
2910         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
2911
2912         m_head = *m_headp;
2913
2914 #if 0
2915         /*
2916          * Set up the context descriptor:
2917          * used when any hardware offload is done.
2918          * This includes CSUM, VLAN, and TSO. It
2919          * will use the first descriptor.
2920          */
2921         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2922                 if (igb_tso_setup(txr, m_head, &hdrlen)) {
2923                         cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2924                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2925                         olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2926                 } else
2927                         return (ENXIO); 
2928         } else if (igb_tx_ctx_setup(txr, m_head))
2929                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2930 #else
2931         if (igb_txctx(txr, m_head)) {
2932                 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
2933                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
2934                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
2935         }
2936 #endif
2937
2938         /* Calculate payload length */
2939         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
2940             << E1000_ADVTXD_PAYLEN_SHIFT);
2941
2942         /* 82575 needs the queue index added */
2943         if (txr->sc->hw.mac.type == e1000_82575)
2944                 olinfo_status |= txr->me << 4;
2945
2946         /* Set up our transmit descriptors */
2947         i = txr->next_avail_desc;
2948         for (j = 0; j < nsegs; j++) {
2949                 bus_size_t seg_len;
2950                 bus_addr_t seg_addr;
2951
2952                 tx_buf = &txr->tx_buf[i];
2953                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
2954                 seg_addr = segs[j].ds_addr;
2955                 seg_len = segs[j].ds_len;
2956
2957                 txd->read.buffer_addr = htole64(seg_addr);
2958                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
2959                 txd->read.olinfo_status = htole32(olinfo_status);
2960                 last = i;
2961                 if (++i == txr->sc->num_tx_desc)
2962                         i = 0;
2963                 tx_buf->m_head = NULL;
2964                 tx_buf->next_eop = -1;
2965         }
2966
2967         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
2968         txr->next_avail_desc = i;
2969         txr->tx_avail -= nsegs;
2970
2971         tx_buf->m_head = m_head;
2972         tx_buf_mapped->map = tx_buf->map;
2973         tx_buf->map = map;
2974
2975         /*
2976          * Last Descriptor of Packet
2977          * needs End Of Packet (EOP)
2978          * and Report Status (RS)
2979          */
2980         txd->read.cmd_type_len |=
2981             htole32(E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS);
2982         /*
2983          * Keep track in the first buffer which
2984          * descriptor will be written back
2985          */
2986         tx_buf = &txr->tx_buf[first];
2987         tx_buf->next_eop = last;
2988
2989         /*
2990          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
2991          * that this frame is available to transmit.
2992          */
2993         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
2994         ++txr->tx_packets;
2995
2996         return 0;
2997 }
2998
2999 static void
3000 igb_start(struct ifnet *ifp)
3001 {
3002         struct igb_softc *sc = ifp->if_softc;
3003         struct igb_tx_ring *txr = sc->queues[0].txr;
3004         struct mbuf *m_head;
3005
3006         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3007
3008         if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
3009                 return;
3010
3011         if (!sc->link_active) {
3012                 ifq_purge(&ifp->if_snd);
3013                 return;
3014         }
3015
3016         /* Call cleanup if number of TX descriptors low */
3017         if (txr->tx_avail <= IGB_TX_CLEANUP_THRESHOLD(sc))
3018                 igb_txeof(txr);
3019
3020         while (!ifq_is_empty(&ifp->if_snd)) {
3021                 if (txr->tx_avail < IGB_MAX_SCATTER) {
3022                         ifp->if_flags |= IFF_OACTIVE;
3023                         /* Set watchdog on */
3024                         ifp->if_timer = 5;
3025                         break;
3026                 }
3027
3028                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3029                 if (m_head == NULL)
3030                         break;
3031
3032                 if (igb_encap(txr, &m_head)) {
3033                         ifp->if_oerrors++;
3034                         continue;
3035                 }
3036
3037                 /* Send a copy of the frame to the BPF listener */
3038                 ETHER_BPF_MTAP(ifp, m_head);
3039         }
3040 }
3041
3042 static void
3043 igb_watchdog(struct ifnet *ifp)
3044 {
3045         struct igb_softc *sc = ifp->if_softc;
3046         struct igb_tx_ring *txr = sc->queues[0].txr;
3047
3048         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3049
3050         /* 
3051          * If flow control has paused us since last checking
3052          * it invalidates the watchdog timing, so dont run it.
3053          */
3054         if (sc->pause_frames) {
3055                 sc->pause_frames = 0;
3056                 ifp->if_timer = 5;
3057                 return;
3058         }
3059
3060         if_printf(ifp, "Watchdog timeout -- resetting\n");
3061         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3062             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3063             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3064         if_printf(ifp, "TX(%d) desc avail = %d, "
3065             "Next TX to Clean = %d\n",
3066             txr->me, txr->tx_avail, txr->next_to_clean);
3067
3068         ifp->if_oerrors++;
3069         sc->watchdog_events++;
3070
3071         igb_init(sc);
3072         if (!ifq_is_empty(&ifp->if_snd))
3073                 if_devstart(ifp);
3074 }
3075
3076 static void
3077 igb_set_itr(struct igb_softc *sc)
3078 {
3079         uint32_t itr = 0;
3080
3081         if (sc->intr_rate > 0) {
3082                 if (sc->hw.mac.type == e1000_82575) {
3083                         itr = 1000000000 / 256 / sc->intr_rate;
3084                         /*
3085                          * NOTE:
3086                          * Document is wrong on the 2 bits left shift
3087                          */
3088                 } else {
3089                         itr = 1000000 / sc->intr_rate;
3090                         itr <<= 2;
3091                 }
3092                 itr &= 0x7FFC;
3093         }
3094         if (sc->hw.mac.type == e1000_82575)
3095                 itr |= itr << 16;
3096         else
3097                 itr |= E1000_EITR_CNT_IGNR;
3098         E1000_WRITE_REG(&sc->hw, E1000_EITR(0), itr);
3099 }
3100
3101 static int
3102 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3103 {
3104         struct igb_softc *sc = (void *)arg1;
3105         struct ifnet *ifp = &sc->arpcom.ac_if;
3106         int error, intr_rate;
3107
3108         intr_rate = sc->intr_rate;
3109         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3110         if (error || req->newptr == NULL)
3111                 return error;
3112         if (intr_rate < 0)
3113                 return EINVAL;
3114
3115         ifnet_serialize_all(ifp);
3116
3117         sc->intr_rate = intr_rate;
3118         if (ifp->if_flags & IFF_RUNNING)
3119                 igb_set_itr(sc);
3120
3121         ifnet_deserialize_all(ifp);
3122
3123         if (bootverbose)
3124                 if_printf(ifp, "Interrupt rate set to %d/sec\n", sc->intr_rate);
3125         return 0;
3126 }