sys/dev/netif/igb/if_igb.c

   1 /*
   2  * Copyright (c) 2001-2011, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "opt_polling.h"
  33 #include "opt_igb.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/kernel.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mbuf.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/serialize.h>
  45 #include <sys/serialize2.h>
  46 #include <sys/socket.h>
  47 #include <sys/sockio.h>
  48 #include <sys/sysctl.h>
  49 #include <sys/systm.h>
  50
  51 #include <net/bpf.h>
  52 #include <net/ethernet.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <net/if_dl.h>
  56 #include <net/if_media.h>
  57 #include <net/ifq_var.h>
  58 #include <net/toeplitz.h>
  59 #include <net/toeplitz2.h>
  60 #include <net/vlan/if_vlan_var.h>
  61 #include <net/vlan/if_vlan_ether.h>
  62 #include <net/if_poll.h>
  63
  64 #include <netinet/in_systm.h>
  65 #include <netinet/in.h>
  66 #include <netinet/ip.h>
  67 #include <netinet/tcp.h>
  68 #include <netinet/udp.h>
  69
  70 #include <bus/pci/pcivar.h>
  71 #include <bus/pci/pcireg.h>
  72
  73 #include <dev/netif/ig_hal/e1000_api.h>
  74 #include <dev/netif/ig_hal/e1000_82575.h>
  75 #include <dev/netif/igb/if_igb.h>
  76
  77 #ifdef IGB_RSS_DEBUG
  78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
  79 do { \
  80         if (sc->rss_debug >= lvl) \
  81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  82 } while (0)
  83 #else   /* !IGB_RSS_DEBUG */
  84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  85 #endif  /* IGB_RSS_DEBUG */
  86
  87 #define IGB_NAME        "Intel(R) PRO/1000 "
  88 #define IGB_DEVICE(id)  \
  89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
  90 #define IGB_DEVICE_NULL { 0, 0, NULL }
  91
  92 static struct igb_device {
  93         uint16_t        vid;
  94         uint16_t        did;
  95         const char      *desc;
  96 } igb_devices[] = {
  97         IGB_DEVICE(82575EB_COPPER),
  98         IGB_DEVICE(82575EB_FIBER_SERDES),
  99         IGB_DEVICE(82575GB_QUAD_COPPER),
 100         IGB_DEVICE(82576),
 101         IGB_DEVICE(82576_NS),
 102         IGB_DEVICE(82576_NS_SERDES),
 103         IGB_DEVICE(82576_FIBER),
 104         IGB_DEVICE(82576_SERDES),
 105         IGB_DEVICE(82576_SERDES_QUAD),
 106         IGB_DEVICE(82576_QUAD_COPPER),
 107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
 108         IGB_DEVICE(82576_VF),
 109         IGB_DEVICE(82580_COPPER),
 110         IGB_DEVICE(82580_FIBER),
 111         IGB_DEVICE(82580_SERDES),
 112         IGB_DEVICE(82580_SGMII),
 113         IGB_DEVICE(82580_COPPER_DUAL),
 114         IGB_DEVICE(82580_QUAD_FIBER),
 115         IGB_DEVICE(DH89XXCC_SERDES),
 116         IGB_DEVICE(DH89XXCC_SGMII),
 117         IGB_DEVICE(DH89XXCC_SFP),
 118         IGB_DEVICE(DH89XXCC_BACKPLANE),
 119         IGB_DEVICE(I350_COPPER),
 120         IGB_DEVICE(I350_FIBER),
 121         IGB_DEVICE(I350_SERDES),
 122         IGB_DEVICE(I350_SGMII),
 123         IGB_DEVICE(I350_VF),
 124
 125         /* required last entry */
 126         IGB_DEVICE_NULL
 127 };
 128
 129 static int      igb_probe(device_t);
 130 static int      igb_attach(device_t);
 131 static int      igb_detach(device_t);
 132 static int      igb_shutdown(device_t);
 133 static int      igb_suspend(device_t);
 134 static int      igb_resume(device_t);
 135
 136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
 137 static void     igb_setup_ifp(struct igb_softc *);
 138 static int      igb_txctx_pullup(struct igb_tx_ring *, struct mbuf **);
 139 static boolean_t igb_txctx(struct igb_tx_ring *, struct mbuf *);
 140 static void     igb_add_sysctl(struct igb_softc *);
 141 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
 142 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
 143 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
 144 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
 145
 146 static void     igb_vf_init_stats(struct igb_softc *);
 147 static void     igb_reset(struct igb_softc *);
 148 static void     igb_update_stats_counters(struct igb_softc *);
 149 static void     igb_update_vf_stats_counters(struct igb_softc *);
 150 static void     igb_update_link_status(struct igb_softc *);
 151 static void     igb_init_tx_unit(struct igb_softc *);
 152 static void     igb_init_rx_unit(struct igb_softc *);
 153
 154 static void     igb_set_vlan(struct igb_softc *);
 155 static void     igb_set_multi(struct igb_softc *);
 156 static void     igb_set_promisc(struct igb_softc *);
 157 static void     igb_disable_promisc(struct igb_softc *);
 158
 159 static int      igb_alloc_rings(struct igb_softc *);
 160 static void     igb_free_rings(struct igb_softc *);
 161 static int      igb_create_tx_ring(struct igb_tx_ring *);
 162 static int      igb_create_rx_ring(struct igb_rx_ring *);
 163 static void     igb_free_tx_ring(struct igb_tx_ring *);
 164 static void     igb_free_rx_ring(struct igb_rx_ring *);
 165 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
 166 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
 167 static void     igb_init_tx_ring(struct igb_tx_ring *);
 168 static int      igb_init_rx_ring(struct igb_rx_ring *);
 169 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
 170 static int      igb_encap(struct igb_tx_ring *, struct mbuf **);
 171
 172 static void     igb_stop(struct igb_softc *);
 173 static void     igb_init(void *);
 174 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 175 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
 176 static int      igb_media_change(struct ifnet *);
 177 static void     igb_timer(void *);
 178 static void     igb_watchdog(struct ifnet *);
 179 static void     igb_start(struct ifnet *);
 180 #ifdef DEVICE_POLLING
 181 static void     igb_poll(struct ifnet *, enum poll_cmd, int);
 182 #endif
 183 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
 184 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
 185 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
 186 #ifdef INVARIANTS
 187 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
 188                     boolean_t);
 189 #endif
 190
 191 static void     igb_intr(void *);
 192 static void     igb_intr_shared(void *);
 193 static void     igb_rxeof(struct igb_rx_ring *, int);
 194 static void     igb_txeof(struct igb_tx_ring *);
 195 static void     igb_set_eitr(struct igb_softc *, int, int);
 196 static void     igb_enable_intr(struct igb_softc *);
 197 static void     igb_disable_intr(struct igb_softc *);
 198 static void     igb_init_unshared_intr(struct igb_softc *);
 199 static void     igb_init_intr(struct igb_softc *);
 200 static int      igb_setup_intr(struct igb_softc *);
 201 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
 202 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
 203 static void     igb_set_intr_mask(struct igb_softc *);
 204 static int      igb_alloc_intr(struct igb_softc *);
 205 static void     igb_free_intr(struct igb_softc *);
 206 static void     igb_teardown_intr(struct igb_softc *);
 207 static void     igb_msix_try_alloc(struct igb_softc *);
 208 static void     igb_msix_free(struct igb_softc *, boolean_t);
 209 static int      igb_msix_setup(struct igb_softc *);
 210 static void     igb_msix_teardown(struct igb_softc *, int);
 211 static void     igb_msix_rx(void *);
 212 static void     igb_msix_tx(void *);
 213 static void     igb_msix_status(void *);
 214
 215 /* Management and WOL Support */
 216 static void     igb_get_mgmt(struct igb_softc *);
 217 static void     igb_rel_mgmt(struct igb_softc *);
 218 static void     igb_get_hw_control(struct igb_softc *);
 219 static void     igb_rel_hw_control(struct igb_softc *);
 220 static void     igb_enable_wol(device_t);
 221
 222 static device_method_t igb_methods[] = {
 223         /* Device interface */
 224         DEVMETHOD(device_probe,         igb_probe),
 225         DEVMETHOD(device_attach,        igb_attach),
 226         DEVMETHOD(device_detach,        igb_detach),
 227         DEVMETHOD(device_shutdown,      igb_shutdown),
 228         DEVMETHOD(device_suspend,       igb_suspend),
 229         DEVMETHOD(device_resume,        igb_resume),
 230         { 0, 0 }
 231 };
 232
 233 static driver_t igb_driver = {
 234         "igb",
 235         igb_methods,
 236         sizeof(struct igb_softc),
 237 };
 238
 239 static devclass_t igb_devclass;
 240
 241 DECLARE_DUMMY_MODULE(if_igb);
 242 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
 243 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
 244
 245 static int      igb_rxd = IGB_DEFAULT_RXD;
 246 static int      igb_txd = IGB_DEFAULT_TXD;
 247 static int      igb_rxr = 0;
 248 static int      igb_msi_enable = 1;
 249 static int      igb_msix_enable = 1;
 250 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
 251 static int      igb_fc_setting = e1000_fc_full;
 252
 253 /*
 254  * DMA Coalescing, only for i350 - default to off,
 255  * this feature is for power savings
 256  */
 257 static int      igb_dma_coalesce = 0;
 258
 259 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 260 TUNABLE_INT("hw.igb.txd", &igb_txd);
 261 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
 262 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
 263 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
 264 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
 265
 266 /* i350 specific */
 267 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
 268 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
 269
 270 static __inline void
 271 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
 272 {
 273         /* Ignore Checksum bit is set */
 274         if (staterr & E1000_RXD_STAT_IXSM)
 275                 return;
 276
 277         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
 278             E1000_RXD_STAT_IPCS)
 279                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
 280
 281         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
 282                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
 283                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 284                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
 285                         mp->m_pkthdr.csum_data = htons(0xffff);
 286                 }
 287         }
 288 }
 289
 290 static __inline struct pktinfo *
 291 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
 292     uint32_t hash, uint32_t hashtype, uint32_t staterr)
 293 {
 294         switch (hashtype) {
 295         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
 296                 pi->pi_netisr = NETISR_IP;
 297                 pi->pi_flags = 0;
 298                 pi->pi_l3proto = IPPROTO_TCP;
 299                 break;
 300
 301         case E1000_RXDADV_RSSTYPE_IPV4:
 302                 if (staterr & E1000_RXD_STAT_IXSM)
 303                         return NULL;
 304
 305                 if ((staterr &
 306                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
 307                     E1000_RXD_STAT_TCPCS) {
 308                         pi->pi_netisr = NETISR_IP;
 309                         pi->pi_flags = 0;
 310                         pi->pi_l3proto = IPPROTO_UDP;
 311                         break;
 312                 }
 313                 /* FALL THROUGH */
 314         default:
 315                 return NULL;
 316         }
 317
 318         m->m_flags |= M_HASH;
 319         m->m_pkthdr.hash = toeplitz_hash(hash);
 320         return pi;
 321 }
 322
 323 static int
 324 igb_probe(device_t dev)
 325 {
 326         const struct igb_device *d;
 327         uint16_t vid, did;
 328
 329         vid = pci_get_vendor(dev);
 330         did = pci_get_device(dev);
 331
 332         for (d = igb_devices; d->desc != NULL; ++d) {
 333                 if (vid == d->vid && did == d->did) {
 334                         device_set_desc(dev, d->desc);
 335                         return 0;
 336                 }
 337         }
 338         return ENXIO;
 339 }
 340
 341 static int
 342 igb_attach(device_t dev)
 343 {
 344         struct igb_softc *sc = device_get_softc(dev);
 345         uint16_t eeprom_data;
 346         int error = 0, i, j, ring_max;
 347
 348 #ifdef notyet
 349         /* SYSCTL stuff */
 350         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 351             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 352             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 353             igb_sysctl_nvm_info, "I", "NVM Information");
 354
 355         SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
 356             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 357             OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
 358             &igb_enable_aim, 1, "Interrupt Moderation");
 359
 360         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 361             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 362             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
 363             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
 364 #endif
 365
 366         callout_init_mp(&sc->timer);
 367         lwkt_serialize_init(&sc->main_serialize);
 368
 369         sc->dev = sc->osdep.dev = dev;
 370
 371         /*
 372          * Determine hardware and mac type
 373          */
 374         sc->hw.vendor_id = pci_get_vendor(dev);
 375         sc->hw.device_id = pci_get_device(dev);
 376         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
 377         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 378         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 379
 380         if (e1000_set_mac_type(&sc->hw))
 381                 return ENXIO;
 382
 383         /* Are we a VF device? */
 384         if (sc->hw.mac.type == e1000_vfadapt ||
 385             sc->hw.mac.type == e1000_vfadapt_i350)
 386                 sc->vf_ifp = 1;
 387         else
 388                 sc->vf_ifp = 0;
 389
 390         /*
 391          * Configure total supported RX/TX ring count
 392          */
 393         switch (sc->hw.mac.type) {
 394         case e1000_82575:
 395                 ring_max = IGB_MAX_RING_82575;
 396                 break;
 397         case e1000_82580:
 398                 ring_max = IGB_MAX_RING_82580;
 399                 break;
 400         case e1000_i350:
 401                 ring_max = IGB_MAX_RING_I350;
 402                 break;
 403         case e1000_82576:
 404                 ring_max = IGB_MAX_RING_82576;
 405                 break;
 406         default:
 407                 ring_max = IGB_MIN_RING;
 408                 break;
 409         }
 410         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
 411         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
 412 #ifdef IGB_RSS_DEBUG
 413         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
 414 #endif
 415         sc->rx_ring_inuse = sc->rx_ring_cnt;
 416         sc->tx_ring_cnt = 1; /* XXX */
 417
 418         /* Enable bus mastering */
 419         pci_enable_busmaster(dev);
 420
 421         /*
 422          * Allocate IO memory
 423          */
 424         sc->mem_rid = PCIR_BAR(0);
 425         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 426             RF_ACTIVE);
 427         if (sc->mem_res == NULL) {
 428                 device_printf(dev, "Unable to allocate bus resource: memory\n");
 429                 error = ENXIO;
 430                 goto failed;
 431         }
 432         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
 433         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
 434
 435         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
 436
 437         /* Save PCI command register for Shared Code */
 438         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 439         sc->hw.back = &sc->osdep;
 440
 441         /* Do Shared Code initialization */
 442         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
 443                 device_printf(dev, "Setup of Shared code failed\n");
 444                 error = ENXIO;
 445                 goto failed;
 446         }
 447
 448         e1000_get_bus_info(&sc->hw);
 449
 450         sc->hw.mac.autoneg = DO_AUTO_NEG;
 451         sc->hw.phy.autoneg_wait_to_complete = FALSE;
 452         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 453
 454         /* Copper options */
 455         if (sc->hw.phy.media_type == e1000_media_type_copper) {
 456                 sc->hw.phy.mdix = AUTO_ALL_MODES;
 457                 sc->hw.phy.disable_polarity_correction = FALSE;
 458                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
 459         }
 460
 461         /* Set the frame limits assuming  standard ethernet sized frames. */
 462         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
 463
 464         /* Allocate RX/TX rings */
 465         error = igb_alloc_rings(sc);
 466         if (error)
 467                 goto failed;
 468
 469         /* Allocate interrupt */
 470         error = igb_alloc_intr(sc);
 471         if (error)
 472                 goto failed;
 473
 474         /*
 475          * Setup serializers
 476          */
 477         i = 0;
 478         sc->serializes[i++] = &sc->main_serialize;
 479
 480         sc->tx_serialize = i;
 481         for (j = 0; j < sc->tx_ring_cnt; ++j)
 482                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
 483
 484         sc->rx_serialize = i;
 485         for (j = 0; j < sc->rx_ring_cnt; ++j)
 486                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
 487
 488         sc->serialize_cnt = i;
 489         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
 490
 491         /* Allocate the appropriate stats memory */
 492         if (sc->vf_ifp) {
 493                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
 494                     M_WAITOK | M_ZERO);
 495                 igb_vf_init_stats(sc);
 496         } else {
 497                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
 498                     M_WAITOK | M_ZERO);
 499         }
 500
 501         /* Allocate multicast array memory. */
 502         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
 503             M_DEVBUF, M_WAITOK);
 504
 505         /* Some adapter-specific advanced features */
 506         if (sc->hw.mac.type >= e1000_i350) {
 507 #ifdef notyet
 508                 igb_set_sysctl_value(adapter, "dma_coalesce",
 509                     "configure dma coalesce",
 510                     &adapter->dma_coalesce, igb_dma_coalesce);
 511                 igb_set_sysctl_value(adapter, "eee_disabled",
 512                     "enable Energy Efficient Ethernet",
 513                     &adapter->hw.dev_spec._82575.eee_disable,
 514                     igb_eee_disabled);
 515 #else
 516                 sc->dma_coalesce = igb_dma_coalesce;
 517                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
 518 #endif
 519                 e1000_set_eee_i350(&sc->hw);
 520         }
 521
 522         /*
 523          * Start from a known state, this is important in reading the nvm and
 524          * mac from that.
 525          */
 526         e1000_reset_hw(&sc->hw);
 527
 528         /* Make sure we have a good EEPROM before we read from it */
 529         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 530                 /*
 531                  * Some PCI-E parts fail the first check due to
 532                  * the link being in sleep state, call it again,
 533                  * if it fails a second time its a real issue.
 534                  */
 535                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 536                         device_printf(dev,
 537                             "The EEPROM Checksum Is Not Valid\n");
 538                         error = EIO;
 539                         goto failed;
 540                 }
 541         }
 542
 543         /* Copy the permanent MAC address out of the EEPROM */
 544         if (e1000_read_mac_addr(&sc->hw) < 0) {
 545                 device_printf(dev, "EEPROM read error while reading MAC"
 546                     " address\n");
 547                 error = EIO;
 548                 goto failed;
 549         }
 550         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
 551                 device_printf(dev, "Invalid MAC address\n");
 552                 error = EIO;
 553                 goto failed;
 554         }
 555
 556 #ifdef notyet
 557         /*
 558         ** Configure Interrupts
 559         */
 560         if ((adapter->msix > 1) && (igb_enable_msix))
 561                 error = igb_allocate_msix(adapter);
 562         else /* MSI or Legacy */
 563                 error = igb_allocate_legacy(adapter);
 564         if (error)
 565                 goto err_late;
 566 #endif
 567
 568         /* Setup OS specific network interface */
 569         igb_setup_ifp(sc);
 570
 571         /* Add sysctl tree, must after igb_setup_ifp() */
 572         igb_add_sysctl(sc);
 573
 574         /* Now get a good starting state */
 575         igb_reset(sc);
 576
 577         /* Initialize statistics */
 578         igb_update_stats_counters(sc);
 579
 580         sc->hw.mac.get_link_status = 1;
 581         igb_update_link_status(sc);
 582
 583         /* Indicate SOL/IDER usage */
 584         if (e1000_check_reset_block(&sc->hw)) {
 585                 device_printf(dev,
 586                     "PHY reset is blocked due to SOL/IDER session.\n");
 587         }
 588
 589         /* Determine if we have to control management hardware */
 590         if (e1000_enable_mng_pass_thru(&sc->hw))
 591                 sc->flags |= IGB_FLAG_HAS_MGMT;
 592
 593         /*
 594          * Setup Wake-on-Lan
 595          */
 596         /* APME bit in EEPROM is mapped to WUC.APME */
 597         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
 598         if (eeprom_data)
 599                 sc->wol = E1000_WUFC_MAG;
 600         /* XXX disable WOL */
 601         sc->wol = 0;
 602
 603 #ifdef notyet
 604         /* Register for VLAN events */
 605         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 606              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 607         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 608              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 609 #endif
 610
 611 #ifdef notyet
 612         igb_add_hw_stats(adapter);
 613 #endif
 614
 615         error = igb_setup_intr(sc);
 616         if (error) {
 617                 ether_ifdetach(&sc->arpcom.ac_if);
 618                 goto failed;
 619         }
 620         return 0;
 621
 622 failed:
 623         igb_detach(dev);
 624         return error;
 625 }
 626
 627 static int
 628 igb_detach(device_t dev)
 629 {
 630         struct igb_softc *sc = device_get_softc(dev);
 631
 632         if (device_is_attached(dev)) {
 633                 struct ifnet *ifp = &sc->arpcom.ac_if;
 634
 635                 ifnet_serialize_all(ifp);
 636
 637                 igb_stop(sc);
 638
 639                 e1000_phy_hw_reset(&sc->hw);
 640
 641                 /* Give control back to firmware */
 642                 igb_rel_mgmt(sc);
 643                 igb_rel_hw_control(sc);
 644
 645                 if (sc->wol) {
 646                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 647                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 648                         igb_enable_wol(dev);
 649                 }
 650
 651                 igb_teardown_intr(sc);
 652
 653                 ifnet_deserialize_all(ifp);
 654
 655                 ether_ifdetach(ifp);
 656         } else if (sc->mem_res != NULL) {
 657                 igb_rel_hw_control(sc);
 658         }
 659         bus_generic_detach(dev);
 660
 661         if (sc->sysctl_tree != NULL)
 662                 sysctl_ctx_free(&sc->sysctl_ctx);
 663
 664         igb_free_intr(sc);
 665
 666         if (sc->msix_mem_res != NULL) {
 667                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
 668                     sc->msix_mem_res);
 669         }
 670         if (sc->mem_res != NULL) {
 671                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 672                     sc->mem_res);
 673         }
 674
 675         igb_free_rings(sc);
 676
 677         if (sc->mta != NULL)
 678                 kfree(sc->mta, M_DEVBUF);
 679         if (sc->stats != NULL)
 680                 kfree(sc->stats, M_DEVBUF);
 681
 682         return 0;
 683 }
 684
 685 static int
 686 igb_shutdown(device_t dev)
 687 {
 688         return igb_suspend(dev);
 689 }
 690
 691 static int
 692 igb_suspend(device_t dev)
 693 {
 694         struct igb_softc *sc = device_get_softc(dev);
 695         struct ifnet *ifp = &sc->arpcom.ac_if;
 696
 697         ifnet_serialize_all(ifp);
 698
 699         igb_stop(sc);
 700
 701         igb_rel_mgmt(sc);
 702         igb_rel_hw_control(sc);
 703
 704         if (sc->wol) {
 705                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 706                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 707                 igb_enable_wol(dev);
 708         }
 709
 710         ifnet_deserialize_all(ifp);
 711
 712         return bus_generic_suspend(dev);
 713 }
 714
 715 static int
 716 igb_resume(device_t dev)
 717 {
 718         struct igb_softc *sc = device_get_softc(dev);
 719         struct ifnet *ifp = &sc->arpcom.ac_if;
 720
 721         ifnet_serialize_all(ifp);
 722
 723         igb_init(sc);
 724         igb_get_mgmt(sc);
 725
 726         if_devstart(ifp);
 727
 728         ifnet_deserialize_all(ifp);
 729
 730         return bus_generic_resume(dev);
 731 }
 732
 733 static int
 734 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 735 {
 736         struct igb_softc *sc = ifp->if_softc;
 737         struct ifreq *ifr = (struct ifreq *)data;
 738         int max_frame_size, mask, reinit;
 739         int error = 0;
 740
 741         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 742
 743         switch (command) {
 744         case SIOCSIFMTU:
 745                 max_frame_size = 9234;
 746                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
 747                     ETHER_CRC_LEN) {
 748                         error = EINVAL;
 749                         break;
 750                 }
 751
 752                 ifp->if_mtu = ifr->ifr_mtu;
 753                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
 754                     ETHER_CRC_LEN;
 755
 756                 if (ifp->if_flags & IFF_RUNNING)
 757                         igb_init(sc);
 758                 break;
 759
 760         case SIOCSIFFLAGS:
 761                 if (ifp->if_flags & IFF_UP) {
 762                         if (ifp->if_flags & IFF_RUNNING) {
 763                                 if ((ifp->if_flags ^ sc->if_flags) &
 764                                     (IFF_PROMISC | IFF_ALLMULTI)) {
 765                                         igb_disable_promisc(sc);
 766                                         igb_set_promisc(sc);
 767                                 }
 768                         } else {
 769                                 igb_init(sc);
 770                         }
 771                 } else if (ifp->if_flags & IFF_RUNNING) {
 772                         igb_stop(sc);
 773                 }
 774                 sc->if_flags = ifp->if_flags;
 775                 break;
 776
 777         case SIOCADDMULTI:
 778         case SIOCDELMULTI:
 779                 if (ifp->if_flags & IFF_RUNNING) {
 780                         igb_disable_intr(sc);
 781                         igb_set_multi(sc);
 782 #ifdef DEVICE_POLLING
 783                         if (!(ifp->if_flags & IFF_POLLING))
 784 #endif
 785                                 igb_enable_intr(sc);
 786                 }
 787                 break;
 788
 789         case SIOCSIFMEDIA:
 790                 /*
 791                  * As the speed/duplex settings are being
 792                  * changed, we need toreset the PHY.
 793                  */
 794                 sc->hw.phy.reset_disable = FALSE;
 795
 796                 /* Check SOL/IDER usage */
 797                 if (e1000_check_reset_block(&sc->hw)) {
 798                         if_printf(ifp, "Media change is "
 799                             "blocked due to SOL/IDER session.\n");
 800                         break;
 801                 }
 802                 /* FALL THROUGH */
 803
 804         case SIOCGIFMEDIA:
 805                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 806                 break;
 807
 808         case SIOCSIFCAP:
 809                 reinit = 0;
 810                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 811                 if (mask & IFCAP_HWCSUM) {
 812                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
 813                         reinit = 1;
 814                 }
 815                 if (mask & IFCAP_VLAN_HWTAGGING) {
 816                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 817                         reinit = 1;
 818                 }
 819                 if (mask & IFCAP_RSS)
 820                         ifp->if_capenable ^= IFCAP_RSS;
 821                 if (reinit && (ifp->if_flags & IFF_RUNNING))
 822                         igb_init(sc);
 823                 break;
 824
 825         default:
 826                 error = ether_ioctl(ifp, command, data);
 827                 break;
 828         }
 829         return error;
 830 }
 831
 832 static void
 833 igb_init(void *xsc)
 834 {
 835         struct igb_softc *sc = xsc;
 836         struct ifnet *ifp = &sc->arpcom.ac_if;
 837         boolean_t polling;
 838         int i;
 839
 840         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 841
 842         igb_stop(sc);
 843
 844         /* Get the latest mac address, User can use a LAA */
 845         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
 846
 847         /* Put the address into the Receive Address Array */
 848         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
 849
 850         igb_reset(sc);
 851         igb_update_link_status(sc);
 852
 853         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
 854
 855         /* Set hardware offload abilities */
 856         if (ifp->if_capenable & IFCAP_TXCSUM)
 857                 ifp->if_hwassist = IGB_CSUM_FEATURES;
 858         else
 859                 ifp->if_hwassist = 0;
 860
 861         /* Configure for OS presence */
 862         igb_get_mgmt(sc);
 863
 864         polling = FALSE;
 865 #ifdef DEVICE_POLLING
 866         if (ifp->if_flags & IFF_POLLING)
 867                 polling = TRUE;
 868 #endif
 869
 870         /* Configured used RX/TX rings */
 871         igb_set_ring_inuse(sc, polling);
 872
 873         /* Initialize interrupt */
 874         igb_init_intr(sc);
 875
 876         /* Prepare transmit descriptors and buffers */
 877         for (i = 0; i < sc->tx_ring_cnt; ++i)
 878                 igb_init_tx_ring(&sc->tx_rings[i]);
 879         igb_init_tx_unit(sc);
 880
 881         /* Setup Multicast table */
 882         igb_set_multi(sc);
 883
 884 #if 0
 885         /*
 886          * Figure out the desired mbuf pool
 887          * for doing jumbo/packetsplit
 888          */
 889         if (adapter->max_frame_size <= 2048)
 890                 adapter->rx_mbuf_sz = MCLBYTES;
 891         else if (adapter->max_frame_size <= 4096)
 892                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
 893         else
 894                 adapter->rx_mbuf_sz = MJUM9BYTES;
 895 #endif
 896
 897         /* Prepare receive descriptors and buffers */
 898         for (i = 0; i < sc->rx_ring_inuse; ++i) {
 899                 int error;
 900
 901                 error = igb_init_rx_ring(&sc->rx_rings[i]);
 902                 if (error) {
 903                         if_printf(ifp, "Could not setup receive structures\n");
 904                         igb_stop(sc);
 905                         return;
 906                 }
 907         }
 908         igb_init_rx_unit(sc);
 909
 910         /* Enable VLAN support */
 911         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 912                 igb_set_vlan(sc);
 913
 914         /* Don't lose promiscuous settings */
 915         igb_set_promisc(sc);
 916
 917         ifp->if_flags |= IFF_RUNNING;
 918         ifp->if_flags &= ~IFF_OACTIVE;
 919
 920         callout_reset(&sc->timer, hz, igb_timer, sc);
 921         e1000_clear_hw_cntrs_base_generic(&sc->hw);
 922
 923 #if 0
 924         if (adapter->msix > 1) /* Set up queue routing */
 925                 igb_configure_queues(adapter);
 926 #endif
 927
 928         /* This clears any pending interrupts */
 929         E1000_READ_REG(&sc->hw, E1000_ICR);
 930
 931         /*
 932          * Only enable interrupts if we are not polling, make sure
 933          * they are off otherwise.
 934          */
 935         if (polling) {
 936                 igb_disable_intr(sc);
 937         } else {
 938                 igb_enable_intr(sc);
 939                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
 940         }
 941
 942         /* Set Energy Efficient Ethernet */
 943         e1000_set_eee_i350(&sc->hw);
 944
 945         /* Don't reset the phy next time init gets called */
 946         sc->hw.phy.reset_disable = TRUE;
 947 }
 948
 949 static void
 950 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
 951 {
 952         struct igb_softc *sc = ifp->if_softc;
 953         u_char fiber_type = IFM_1000_SX;
 954
 955         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 956
 957         igb_update_link_status(sc);
 958
 959         ifmr->ifm_status = IFM_AVALID;
 960         ifmr->ifm_active = IFM_ETHER;
 961
 962         if (!sc->link_active)
 963                 return;
 964
 965         ifmr->ifm_status |= IFM_ACTIVE;
 966
 967         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
 968             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
 969                 ifmr->ifm_active |= fiber_type | IFM_FDX;
 970         } else {
 971                 switch (sc->link_speed) {
 972                 case 10:
 973                         ifmr->ifm_active |= IFM_10_T;
 974                         break;
 975
 976                 case 100:
 977                         ifmr->ifm_active |= IFM_100_TX;
 978                         break;
 979
 980                 case 1000:
 981                         ifmr->ifm_active |= IFM_1000_T;
 982                         break;
 983                 }
 984                 if (sc->link_duplex == FULL_DUPLEX)
 985                         ifmr->ifm_active |= IFM_FDX;
 986                 else
 987                         ifmr->ifm_active |= IFM_HDX;
 988         }
 989 }
 990
 991 static int
 992 igb_media_change(struct ifnet *ifp)
 993 {
 994         struct igb_softc *sc = ifp->if_softc;
 995         struct ifmedia *ifm = &sc->media;
 996
 997         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 998
 999         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1000                 return EINVAL;
1001
1002         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1003         case IFM_AUTO:
1004                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1005                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1006                 break;
1007
1008         case IFM_1000_LX:
1009         case IFM_1000_SX:
1010         case IFM_1000_T:
1011                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1012                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1013                 break;
1014
1015         case IFM_100_TX:
1016                 sc->hw.mac.autoneg = FALSE;
1017                 sc->hw.phy.autoneg_advertised = 0;
1018                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1019                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1020                 else
1021                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1022                 break;
1023
1024         case IFM_10_T:
1025                 sc->hw.mac.autoneg = FALSE;
1026                 sc->hw.phy.autoneg_advertised = 0;
1027                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1028                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1029                 else
1030                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1031                 break;
1032
1033         default:
1034                 if_printf(ifp, "Unsupported media type\n");
1035                 break;
1036         }
1037
1038         igb_init(sc);
1039
1040         return 0;
1041 }
1042
1043 static void
1044 igb_set_promisc(struct igb_softc *sc)
1045 {
1046         struct ifnet *ifp = &sc->arpcom.ac_if;
1047         struct e1000_hw *hw = &sc->hw;
1048         uint32_t reg;
1049
1050         if (sc->vf_ifp) {
1051                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1052                 return;
1053         }
1054
1055         reg = E1000_READ_REG(hw, E1000_RCTL);
1056         if (ifp->if_flags & IFF_PROMISC) {
1057                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1058                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1059         } else if (ifp->if_flags & IFF_ALLMULTI) {
1060                 reg |= E1000_RCTL_MPE;
1061                 reg &= ~E1000_RCTL_UPE;
1062                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1063         }
1064 }
1065
1066 static void
1067 igb_disable_promisc(struct igb_softc *sc)
1068 {
1069         struct e1000_hw *hw = &sc->hw;
1070         uint32_t reg;
1071
1072         if (sc->vf_ifp) {
1073                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1074                 return;
1075         }
1076         reg = E1000_READ_REG(hw, E1000_RCTL);
1077         reg &= ~E1000_RCTL_UPE;
1078         reg &= ~E1000_RCTL_MPE;
1079         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1080 }
1081
1082 static void
1083 igb_set_multi(struct igb_softc *sc)
1084 {
1085         struct ifnet *ifp = &sc->arpcom.ac_if;
1086         struct ifmultiaddr *ifma;
1087         uint32_t reg_rctl = 0;
1088         uint8_t *mta;
1089         int mcnt = 0;
1090
1091         mta = sc->mta;
1092         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1093
1094         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1095                 if (ifma->ifma_addr->sa_family != AF_LINK)
1096                         continue;
1097
1098                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1099                         break;
1100
1101                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1102                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1103                 mcnt++;
1104         }
1105
1106         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1107                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1108                 reg_rctl |= E1000_RCTL_MPE;
1109                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1110         } else {
1111                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1112         }
1113 }
1114
1115 static void
1116 igb_timer(void *xsc)
1117 {
1118         struct igb_softc *sc = xsc;
1119
1120         lwkt_serialize_enter(&sc->main_serialize);
1121
1122         igb_update_link_status(sc);
1123         igb_update_stats_counters(sc);
1124
1125         callout_reset(&sc->timer, hz, igb_timer, sc);
1126
1127         lwkt_serialize_exit(&sc->main_serialize);
1128 }
1129
1130 static void
1131 igb_update_link_status(struct igb_softc *sc)
1132 {
1133         struct ifnet *ifp = &sc->arpcom.ac_if;
1134         struct e1000_hw *hw = &sc->hw;
1135         uint32_t link_check, thstat, ctrl;
1136
1137         link_check = thstat = ctrl = 0;
1138
1139         /* Get the cached link value or read for real */
1140         switch (hw->phy.media_type) {
1141         case e1000_media_type_copper:
1142                 if (hw->mac.get_link_status) {
1143                         /* Do the work to read phy */
1144                         e1000_check_for_link(hw);
1145                         link_check = !hw->mac.get_link_status;
1146                 } else {
1147                         link_check = TRUE;
1148                 }
1149                 break;
1150
1151         case e1000_media_type_fiber:
1152                 e1000_check_for_link(hw);
1153                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1154                 break;
1155
1156         case e1000_media_type_internal_serdes:
1157                 e1000_check_for_link(hw);
1158                 link_check = hw->mac.serdes_has_link;
1159                 break;
1160
1161         /* VF device is type_unknown */
1162         case e1000_media_type_unknown:
1163                 e1000_check_for_link(hw);
1164                 link_check = !hw->mac.get_link_status;
1165                 /* Fall thru */
1166         default:
1167                 break;
1168         }
1169
1170         /* Check for thermal downshift or shutdown */
1171         if (hw->mac.type == e1000_i350) {
1172                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1173                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1174         }
1175
1176         /* Now we check if a transition has happened */
1177         if (link_check && sc->link_active == 0) {
1178                 e1000_get_speed_and_duplex(hw,
1179                     &sc->link_speed, &sc->link_duplex);
1180                 if (bootverbose) {
1181                         if_printf(ifp, "Link is up %d Mbps %s\n",
1182                             sc->link_speed,
1183                             sc->link_duplex == FULL_DUPLEX ?
1184                             "Full Duplex" : "Half Duplex");
1185                 }
1186                 sc->link_active = 1;
1187
1188                 ifp->if_baudrate = sc->link_speed * 1000000;
1189                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1190                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1191                         if_printf(ifp, "Link: thermal downshift\n");
1192                 /* This can sleep */
1193                 ifp->if_link_state = LINK_STATE_UP;
1194                 if_link_state_change(ifp);
1195         } else if (!link_check && sc->link_active == 1) {
1196                 ifp->if_baudrate = sc->link_speed = 0;
1197                 sc->link_duplex = 0;
1198                 if (bootverbose)
1199                         if_printf(ifp, "Link is Down\n");
1200                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1201                     (thstat & E1000_THSTAT_PWR_DOWN))
1202                         if_printf(ifp, "Link: thermal shutdown\n");
1203                 sc->link_active = 0;
1204                 /* This can sleep */
1205                 ifp->if_link_state = LINK_STATE_DOWN;
1206                 if_link_state_change(ifp);
1207         }
1208 }
1209
1210 static void
1211 igb_stop(struct igb_softc *sc)
1212 {
1213         struct ifnet *ifp = &sc->arpcom.ac_if;
1214         int i;
1215
1216         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1217
1218         igb_disable_intr(sc);
1219
1220         callout_stop(&sc->timer);
1221
1222         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1223         ifp->if_timer = 0;
1224
1225         e1000_reset_hw(&sc->hw);
1226         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1227
1228         e1000_led_off(&sc->hw);
1229         e1000_cleanup_led(&sc->hw);
1230
1231         for (i = 0; i < sc->tx_ring_cnt; ++i)
1232                 igb_free_tx_ring(&sc->tx_rings[i]);
1233         for (i = 0; i < sc->rx_ring_cnt; ++i)
1234                 igb_free_rx_ring(&sc->rx_rings[i]);
1235 }
1236
1237 static void
1238 igb_reset(struct igb_softc *sc)
1239 {
1240         struct ifnet *ifp = &sc->arpcom.ac_if;
1241         struct e1000_hw *hw = &sc->hw;
1242         struct e1000_fc_info *fc = &hw->fc;
1243         uint32_t pba = 0;
1244         uint16_t hwm;
1245
1246         /* Let the firmware know the OS is in control */
1247         igb_get_hw_control(sc);
1248
1249         /*
1250          * Packet Buffer Allocation (PBA)
1251          * Writing PBA sets the receive portion of the buffer
1252          * the remainder is used for the transmit buffer.
1253          */
1254         switch (hw->mac.type) {
1255         case e1000_82575:
1256                 pba = E1000_PBA_32K;
1257                 break;
1258
1259         case e1000_82576:
1260         case e1000_vfadapt:
1261                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1262                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1263                 break;
1264
1265         case e1000_82580:
1266         case e1000_i350:
1267         case e1000_vfadapt_i350:
1268                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1269                 pba = e1000_rxpbs_adjust_82580(pba);
1270                 break;
1271                 /* XXX pba = E1000_PBA_35K; */
1272
1273         default:
1274                 break;
1275         }
1276
1277         /* Special needs in case of Jumbo frames */
1278         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1279                 uint32_t tx_space, min_tx, min_rx;
1280
1281                 pba = E1000_READ_REG(hw, E1000_PBA);
1282                 tx_space = pba >> 16;
1283                 pba &= 0xffff;
1284
1285                 min_tx = (sc->max_frame_size +
1286                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1287                 min_tx = roundup2(min_tx, 1024);
1288                 min_tx >>= 10;
1289                 min_rx = sc->max_frame_size;
1290                 min_rx = roundup2(min_rx, 1024);
1291                 min_rx >>= 10;
1292                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1293                         pba = pba - (min_tx - tx_space);
1294                         /*
1295                          * if short on rx space, rx wins
1296                          * and must trump tx adjustment
1297                          */
1298                         if (pba < min_rx)
1299                                 pba = min_rx;
1300                 }
1301                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1302         }
1303
1304         /*
1305          * These parameters control the automatic generation (Tx) and
1306          * response (Rx) to Ethernet PAUSE frames.
1307          * - High water mark should allow for at least two frames to be
1308          *   received after sending an XOFF.
1309          * - Low water mark works best when it is very near the high water mark.
1310          *   This allows the receiver to restart by sending XON when it has
1311          *   drained a bit.
1312          */
1313         hwm = min(((pba << 10) * 9 / 10),
1314             ((pba << 10) - 2 * sc->max_frame_size));
1315
1316         if (hw->mac.type < e1000_82576) {
1317                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1318                 fc->low_water = fc->high_water - 8;
1319         } else {
1320                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1321                 fc->low_water = fc->high_water - 16;
1322         }
1323         fc->pause_time = IGB_FC_PAUSE_TIME;
1324         fc->send_xon = TRUE;
1325
1326         /* Issue a global reset */
1327         e1000_reset_hw(hw);
1328         E1000_WRITE_REG(hw, E1000_WUC, 0);
1329
1330         if (e1000_init_hw(hw) < 0)
1331                 if_printf(ifp, "Hardware Initialization Failed\n");
1332
1333         /* Setup DMA Coalescing */
1334         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1335                 uint32_t reg;
1336
1337                 hwm = (pba - 4) << 10;
1338                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1339                     & E1000_DMACR_DMACTHR_MASK;
1340
1341                 /* transition to L0x or L1 if available..*/
1342                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1343
1344                 /* timer = +-1000 usec in 32usec intervals */
1345                 reg |= (1000 >> 5);
1346                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1347
1348                 /* No lower threshold */
1349                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1350
1351                 /* set hwm to PBA -  2 * max frame size */
1352                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1353
1354                 /* Set the interval before transition */
1355                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1356                 reg |= 0x800000FF; /* 255 usec */
1357                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1358
1359                 /* free space in tx packet buffer to wake from DMA coal */
1360                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1361                     (20480 - (2 * sc->max_frame_size)) >> 6);
1362
1363                 /* make low power state decision controlled by DMA coal */
1364                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1365                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1366                     reg | E1000_PCIEMISC_LX_DECISION);
1367                 if_printf(ifp, "DMA Coalescing enabled\n");
1368         }
1369
1370         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1371         e1000_get_phy_info(hw);
1372         e1000_check_for_link(hw);
1373 }
1374
1375 static void
1376 igb_setup_ifp(struct igb_softc *sc)
1377 {
1378         struct ifnet *ifp = &sc->arpcom.ac_if;
1379
1380         if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1381         ifp->if_softc = sc;
1382         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1383         ifp->if_init = igb_init;
1384         ifp->if_ioctl = igb_ioctl;
1385         ifp->if_start = igb_start;
1386         ifp->if_serialize = igb_serialize;
1387         ifp->if_deserialize = igb_deserialize;
1388         ifp->if_tryserialize = igb_tryserialize;
1389 #ifdef INVARIANTS
1390         ifp->if_serialize_assert = igb_serialize_assert;
1391 #endif
1392 #ifdef DEVICE_POLLING
1393         ifp->if_poll = igb_poll;
1394 #endif
1395         ifp->if_watchdog = igb_watchdog;
1396
1397         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1398         ifq_set_ready(&ifp->if_snd);
1399
1400         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1401
1402         ifp->if_capabilities =
1403             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1404         if (IGB_ENABLE_HWRSS(sc))
1405                 ifp->if_capabilities |= IFCAP_RSS;
1406         ifp->if_capenable = ifp->if_capabilities;
1407         ifp->if_hwassist = IGB_CSUM_FEATURES;
1408
1409         /*
1410          * Tell the upper layer(s) we support long frames
1411          */
1412         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1413
1414         /*
1415          * Specify the media types supported by this adapter and register
1416          * callbacks to update media and link information
1417          */
1418         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1419         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1420             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1421                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1422                     0, NULL);
1423                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1424         } else {
1425                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1426                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1427                     0, NULL);
1428                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1429                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1430                     0, NULL);
1431                 if (sc->hw.phy.type != e1000_phy_ife) {
1432                         ifmedia_add(&sc->media,
1433                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1434                         ifmedia_add(&sc->media,
1435                             IFM_ETHER | IFM_1000_T, 0, NULL);
1436                 }
1437         }
1438         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1439         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1440 }
1441
1442 static void
1443 igb_add_sysctl(struct igb_softc *sc)
1444 {
1445         char node[32];
1446         int i;
1447
1448         sysctl_ctx_init(&sc->sysctl_ctx);
1449         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1450             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1451             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1452         if (sc->sysctl_tree == NULL) {
1453                 device_printf(sc->dev, "can't add sysctl node\n");
1454                 return;
1455         }
1456
1457         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1458             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1459         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1460             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1461             "# of RX rings used");
1462         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1463             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1464             "# of RX descs");
1465         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1466             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1467             "# of TX descs");
1468
1469         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1470                 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1471                     SYSCTL_CHILDREN(sc->sysctl_tree),
1472                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1473                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1474         } else {
1475                 for (i = 0; i < sc->msix_cnt; ++i) {
1476                         struct igb_msix_data *msix = &sc->msix_data[i];
1477
1478                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1479                         SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1480                             SYSCTL_CHILDREN(sc->sysctl_tree),
1481                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1482                             msix, 0, igb_sysctl_msix_rate, "I",
1483                             msix->msix_rate_desc);
1484                 }
1485         }
1486
1487         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1488             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1489             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1490             "# of segments per TX interrupt");
1491
1492 #ifdef IGB_RSS_DEBUG
1493         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1494             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1495             "RSS debug level");
1496         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1497                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1498                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1499                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1500                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1501         }
1502 #endif
1503 }
1504
1505 static int
1506 igb_alloc_rings(struct igb_softc *sc)
1507 {
1508         int error, i;
1509
1510         /*
1511          * Create top level busdma tag
1512          */
1513         error = bus_dma_tag_create(NULL, 1, 0,
1514             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1515             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1516             &sc->parent_tag);
1517         if (error) {
1518                 device_printf(sc->dev, "could not create top level DMA tag\n");
1519                 return error;
1520         }
1521
1522         /*
1523          * Allocate TX descriptor rings and buffers
1524          */
1525         sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1526             M_DEVBUF, M_WAITOK | M_ZERO);
1527         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1528                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1529
1530                 /* Set up some basics */
1531                 txr->sc = sc;
1532                 txr->me = i;
1533                 lwkt_serialize_init(&txr->tx_serialize);
1534
1535                 error = igb_create_tx_ring(txr);
1536                 if (error)
1537                         return error;
1538         }
1539
1540         /*
1541          * Allocate RX descriptor rings and buffers
1542          */
1543         sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1544             M_DEVBUF, M_WAITOK | M_ZERO);
1545         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1546                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1547
1548                 /* Set up some basics */
1549                 rxr->sc = sc;
1550                 rxr->me = i;
1551                 lwkt_serialize_init(&rxr->rx_serialize);
1552
1553                 error = igb_create_rx_ring(rxr);
1554                 if (error)
1555                         return error;
1556         }
1557
1558         return 0;
1559 }
1560
1561 static void
1562 igb_free_rings(struct igb_softc *sc)
1563 {
1564         int i;
1565
1566         if (sc->tx_rings != NULL) {
1567                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1568                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1569
1570                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1571                 }
1572                 kfree(sc->tx_rings, M_DEVBUF);
1573         }
1574
1575         if (sc->rx_rings != NULL) {
1576                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1577                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1578
1579                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1580                 }
1581                 kfree(sc->rx_rings, M_DEVBUF);
1582         }
1583 }
1584
1585 static int
1586 igb_create_tx_ring(struct igb_tx_ring *txr)
1587 {
1588         int tsize, error, i;
1589
1590         /*
1591          * Validate number of transmit descriptors. It must not exceed
1592          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1593          */
1594         if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1595             (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1596                 device_printf(txr->sc->dev,
1597                     "Using %d TX descriptors instead of %d!\n",
1598                     IGB_DEFAULT_TXD, igb_txd);
1599                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1600         } else {
1601                 txr->num_tx_desc = igb_txd;
1602         }
1603
1604         /*
1605          * Allocate TX descriptor ring
1606          */
1607         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1608             IGB_DBA_ALIGN);
1609         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1610             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1611             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1612         if (txr->txdma.dma_vaddr == NULL) {
1613                 device_printf(txr->sc->dev,
1614                     "Unable to allocate TX Descriptor memory\n");
1615                 return ENOMEM;
1616         }
1617         txr->tx_base = txr->txdma.dma_vaddr;
1618         bzero(txr->tx_base, tsize);
1619
1620         txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1621             M_DEVBUF, M_WAITOK | M_ZERO);
1622
1623         /*
1624          * Allocate TX head write-back buffer
1625          */
1626         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1627             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1628             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1629         if (txr->tx_hdr == NULL) {
1630                 device_printf(txr->sc->dev,
1631                     "Unable to allocate TX head write-back buffer\n");
1632                 return ENOMEM;
1633         }
1634
1635         /*
1636          * Create DMA tag for TX buffers
1637          */
1638         error = bus_dma_tag_create(txr->sc->parent_tag,
1639             1, 0,               /* alignment, bounds */
1640             BUS_SPACE_MAXADDR,  /* lowaddr */
1641             BUS_SPACE_MAXADDR,  /* highaddr */
1642             NULL, NULL,         /* filter, filterarg */
1643             IGB_TSO_SIZE,       /* maxsize */
1644             IGB_MAX_SCATTER,    /* nsegments */
1645             PAGE_SIZE,          /* maxsegsize */
1646             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1647             BUS_DMA_ONEBPAGE,   /* flags */
1648             &txr->tx_tag);
1649         if (error) {
1650                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1651                 kfree(txr->tx_buf, M_DEVBUF);
1652                 txr->tx_buf = NULL;
1653                 return error;
1654         }
1655
1656         /*
1657          * Create DMA maps for TX buffers
1658          */
1659         for (i = 0; i < txr->num_tx_desc; ++i) {
1660                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1661
1662                 error = bus_dmamap_create(txr->tx_tag,
1663                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1664                 if (error) {
1665                         device_printf(txr->sc->dev,
1666                             "Unable to create TX DMA map\n");
1667                         igb_destroy_tx_ring(txr, i);
1668                         return error;
1669                 }
1670         }
1671
1672         /*
1673          * Initialize various watermark
1674          */
1675         txr->spare_desc = IGB_TX_SPARE;
1676         txr->intr_nsegs = txr->num_tx_desc / 16;
1677         txr->oact_hi_desc = txr->num_tx_desc / 2;
1678         txr->oact_lo_desc = txr->num_tx_desc / 8;
1679         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1680                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1681         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1682                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1683
1684         return 0;
1685 }
1686
1687 static void
1688 igb_free_tx_ring(struct igb_tx_ring *txr)
1689 {
1690         int i;
1691
1692         for (i = 0; i < txr->num_tx_desc; ++i) {
1693                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1694
1695                 if (txbuf->m_head != NULL) {
1696                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1697                         m_freem(txbuf->m_head);
1698                         txbuf->m_head = NULL;
1699                 }
1700         }
1701 }
1702
1703 static void
1704 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1705 {
1706         int i;
1707
1708         if (txr->txdma.dma_vaddr != NULL) {
1709                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1710                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1711                     txr->txdma.dma_map);
1712                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1713                 txr->txdma.dma_vaddr = NULL;
1714         }
1715
1716         if (txr->tx_hdr != NULL) {
1717                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1718                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1719                     txr->tx_hdr_dmap);
1720                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1721                 txr->tx_hdr = NULL;
1722         }
1723
1724         if (txr->tx_buf == NULL)
1725                 return;
1726
1727         for (i = 0; i < ndesc; ++i) {
1728                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1729
1730                 KKASSERT(txbuf->m_head == NULL);
1731                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1732         }
1733         bus_dma_tag_destroy(txr->tx_tag);
1734
1735         kfree(txr->tx_buf, M_DEVBUF);
1736         txr->tx_buf = NULL;
1737 }
1738
1739 static void
1740 igb_init_tx_ring(struct igb_tx_ring *txr)
1741 {
1742         /* Clear the old descriptor contents */
1743         bzero(txr->tx_base,
1744             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1745
1746         /* Clear TX head write-back buffer */
1747         *(txr->tx_hdr) = 0;
1748
1749         /* Reset indices */
1750         txr->next_avail_desc = 0;
1751         txr->next_to_clean = 0;
1752         txr->tx_nsegs = 0;
1753
1754         /* Set number of descriptors available */
1755         txr->tx_avail = txr->num_tx_desc;
1756 }
1757
1758 static void
1759 igb_init_tx_unit(struct igb_softc *sc)
1760 {
1761         struct e1000_hw *hw = &sc->hw;
1762         uint32_t tctl;
1763         int i;
1764
1765         /* Setup the Tx Descriptor Rings */
1766         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1767                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1768                 uint64_t bus_addr = txr->txdma.dma_paddr;
1769                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1770                 uint32_t txdctl = 0;
1771                 uint32_t dca_txctrl;
1772
1773                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1774                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1775                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1776                     (uint32_t)(bus_addr >> 32));
1777                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1778                     (uint32_t)bus_addr);
1779
1780                 /* Setup the HW Tx Head and Tail descriptor pointers */
1781                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1782                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1783
1784                 txdctl |= IGB_TX_PTHRESH;
1785                 txdctl |= IGB_TX_HTHRESH << 8;
1786                 txdctl |= IGB_TX_WTHRESH << 16;
1787                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1788                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1789
1790                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1791                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1792                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1793
1794                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1795                     (uint32_t)(hdr_paddr >> 32));
1796                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1797                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1798         }
1799
1800         if (sc->vf_ifp)
1801                 return;
1802
1803         e1000_config_collision_dist(hw);
1804
1805         /* Program the Transmit Control Register */
1806         tctl = E1000_READ_REG(hw, E1000_TCTL);
1807         tctl &= ~E1000_TCTL_CT;
1808         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1809             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1810
1811         /* This write will effectively turn on the transmit unit. */
1812         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1813 }
1814
1815 static boolean_t
1816 igb_txctx(struct igb_tx_ring *txr, struct mbuf *mp)
1817 {
1818         struct e1000_adv_tx_context_desc *TXD;
1819         struct igb_tx_buf *txbuf;
1820         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1821         struct ether_vlan_header *eh;
1822         struct ip *ip = NULL;
1823         int ehdrlen, ctxd, ip_hlen = 0;
1824         uint16_t etype, vlantag = 0;
1825         boolean_t offload = TRUE;
1826
1827         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1828                 offload = FALSE;
1829
1830         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1831         ctxd = txr->next_avail_desc;
1832         txbuf = &txr->tx_buf[ctxd];
1833         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1834
1835         /*
1836          * In advanced descriptors the vlan tag must
1837          * be placed into the context descriptor, thus
1838          * we need to be here just for that setup.
1839          */
1840         if (mp->m_flags & M_VLANTAG) {
1841                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1842                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1843         } else if (!offload) {
1844                 return FALSE;
1845         }
1846
1847         /*
1848          * Determine where frame payload starts.
1849          * Jump over vlan headers if already present,
1850          * helpful for QinQ too.
1851          */
1852         KASSERT(mp->m_len >= ETHER_HDR_LEN,
1853             ("igb_txctx_pullup is not called (eh)?\n"));
1854         eh = mtod(mp, struct ether_vlan_header *);
1855         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1856                 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
1857                     ("igb_txctx_pullup is not called (evh)?\n"));
1858                 etype = ntohs(eh->evl_proto);
1859                 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
1860         } else {
1861                 etype = ntohs(eh->evl_encap_proto);
1862                 ehdrlen = ETHER_HDR_LEN;
1863         }
1864
1865         /* Set the ether header length */
1866         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1867
1868         switch (etype) {
1869         case ETHERTYPE_IP:
1870                 KASSERT(mp->m_len >= ehdrlen + IGB_IPVHL_SIZE,
1871                     ("igb_txctx_pullup is not called (eh+ip_vhl)?\n"));
1872
1873                 /* NOTE: We could only safely access ip.ip_vhl part */
1874                 ip = (struct ip *)(mp->m_data + ehdrlen);
1875                 ip_hlen = ip->ip_hl << 2;
1876
1877                 if (mp->m_pkthdr.csum_flags & CSUM_IP)
1878                         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1879                 break;
1880
1881 #ifdef notyet
1882         case ETHERTYPE_IPV6:
1883                 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1884                 ip_hlen = sizeof(struct ip6_hdr);
1885                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
1886                 break;
1887 #endif
1888
1889         default:
1890                 offload = FALSE;
1891                 break;
1892         }
1893
1894         vlan_macip_lens |= ip_hlen;
1895         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1896
1897         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1898                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1899         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1900                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1901
1902         /* 82575 needs the queue index added */
1903         if (txr->sc->hw.mac.type == e1000_82575)
1904                 mss_l4len_idx = txr->me << 4;
1905
1906         /* Now copy bits into descriptor */
1907         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1908         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1909         TXD->seqnum_seed = htole32(0);
1910         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1911
1912         txbuf->m_head = NULL;
1913
1914         /* We've consumed the first desc, adjust counters */
1915         if (++ctxd == txr->num_tx_desc)
1916                 ctxd = 0;
1917         txr->next_avail_desc = ctxd;
1918         --txr->tx_avail;
1919
1920         return offload;
1921 }
1922
1923 static void
1924 igb_txeof(struct igb_tx_ring *txr)
1925 {
1926         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1927         int first, hdr, avail;
1928
1929         if (txr->tx_avail == txr->num_tx_desc)
1930                 return;
1931
1932         first = txr->next_to_clean;
1933         hdr = *(txr->tx_hdr);
1934
1935         if (first == hdr)
1936                 return;
1937
1938         avail = txr->tx_avail;
1939         while (first != hdr) {
1940                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1941
1942                 ++avail;
1943                 if (txbuf->m_head) {
1944                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1945                         m_freem(txbuf->m_head);
1946                         txbuf->m_head = NULL;
1947                         ++ifp->if_opackets;
1948                 }
1949                 if (++first == txr->num_tx_desc)
1950                         first = 0;
1951         }
1952         txr->next_to_clean = first;
1953         txr->tx_avail = avail;
1954
1955         /*
1956          * If we have a minimum free, clear IFF_OACTIVE
1957          * to tell the stack that it is OK to send packets.
1958          */
1959         if (IGB_IS_NOT_OACTIVE(txr)) {
1960                 ifp->if_flags &= ~IFF_OACTIVE;
1961
1962                 /*
1963                  * We have enough TX descriptors, turn off
1964                  * the watchdog.  We allow small amount of
1965                  * packets (roughly intr_nsegs) pending on
1966                  * the transmit ring.
1967                  */
1968                 ifp->if_timer = 0;
1969         }
1970 }
1971
1972 static int
1973 igb_create_rx_ring(struct igb_rx_ring *rxr)
1974 {
1975         int rsize, i, error;
1976
1977         /*
1978          * Validate number of receive descriptors. It must not exceed
1979          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1980          */
1981         if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1982             (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1983                 device_printf(rxr->sc->dev,
1984                     "Using %d RX descriptors instead of %d!\n",
1985                     IGB_DEFAULT_RXD, igb_rxd);
1986                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1987         } else {
1988                 rxr->num_rx_desc = igb_rxd;
1989         }
1990
1991         /*
1992          * Allocate RX descriptor ring
1993          */
1994         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1995             IGB_DBA_ALIGN);
1996         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1997             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1998             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1999             &rxr->rxdma.dma_paddr);
2000         if (rxr->rxdma.dma_vaddr == NULL) {
2001                 device_printf(rxr->sc->dev,
2002                     "Unable to allocate RxDescriptor memory\n");
2003                 return ENOMEM;
2004         }
2005         rxr->rx_base = rxr->rxdma.dma_vaddr;
2006         bzero(rxr->rx_base, rsize);
2007
2008         rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
2009             M_DEVBUF, M_WAITOK | M_ZERO);
2010
2011         /*
2012          * Create DMA tag for RX buffers
2013          */
2014         error = bus_dma_tag_create(rxr->sc->parent_tag,
2015             1, 0,               /* alignment, bounds */
2016             BUS_SPACE_MAXADDR,  /* lowaddr */
2017             BUS_SPACE_MAXADDR,  /* highaddr */
2018             NULL, NULL,         /* filter, filterarg */
2019             MCLBYTES,           /* maxsize */
2020             1,                  /* nsegments */
2021             MCLBYTES,           /* maxsegsize */
2022             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2023             &rxr->rx_tag);
2024         if (error) {
2025                 device_printf(rxr->sc->dev,
2026                     "Unable to create RX payload DMA tag\n");
2027                 kfree(rxr->rx_buf, M_DEVBUF);
2028                 rxr->rx_buf = NULL;
2029                 return error;
2030         }
2031
2032         /*
2033          * Create spare DMA map for RX buffers
2034          */
2035         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2036             &rxr->rx_sparemap);
2037         if (error) {
2038                 device_printf(rxr->sc->dev,
2039                     "Unable to create spare RX DMA maps\n");
2040                 bus_dma_tag_destroy(rxr->rx_tag);
2041                 kfree(rxr->rx_buf, M_DEVBUF);
2042                 rxr->rx_buf = NULL;
2043                 return error;
2044         }
2045
2046         /*
2047          * Create DMA maps for RX buffers
2048          */
2049         for (i = 0; i < rxr->num_rx_desc; i++) {
2050                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2051
2052                 error = bus_dmamap_create(rxr->rx_tag,
2053                     BUS_DMA_WAITOK, &rxbuf->map);
2054                 if (error) {
2055                         device_printf(rxr->sc->dev,
2056                             "Unable to create RX DMA maps\n");
2057                         igb_destroy_rx_ring(rxr, i);
2058                         return error;
2059                 }
2060         }
2061         return 0;
2062 }
2063
2064 static void
2065 igb_free_rx_ring(struct igb_rx_ring *rxr)
2066 {
2067         int i;
2068
2069         for (i = 0; i < rxr->num_rx_desc; ++i) {
2070                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2071
2072                 if (rxbuf->m_head != NULL) {
2073                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2074                         m_freem(rxbuf->m_head);
2075                         rxbuf->m_head = NULL;
2076                 }
2077         }
2078
2079         if (rxr->fmp != NULL)
2080                 m_freem(rxr->fmp);
2081         rxr->fmp = NULL;
2082         rxr->lmp = NULL;
2083 }
2084
2085 static void
2086 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2087 {
2088         int i;
2089
2090         if (rxr->rxdma.dma_vaddr != NULL) {
2091                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2092                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2093                     rxr->rxdma.dma_map);
2094                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2095                 rxr->rxdma.dma_vaddr = NULL;
2096         }
2097
2098         if (rxr->rx_buf == NULL)
2099                 return;
2100
2101         for (i = 0; i < ndesc; ++i) {
2102                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2103
2104                 KKASSERT(rxbuf->m_head == NULL);
2105                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2106         }
2107         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2108         bus_dma_tag_destroy(rxr->rx_tag);
2109
2110         kfree(rxr->rx_buf, M_DEVBUF);
2111         rxr->rx_buf = NULL;
2112 }
2113
2114 static void
2115 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2116 {
2117         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2118         rxd->wb.upper.status_error = 0;
2119 }
2120
2121 static int
2122 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2123 {
2124         struct mbuf *m;
2125         bus_dma_segment_t seg;
2126         bus_dmamap_t map;
2127         struct igb_rx_buf *rxbuf;
2128         int error, nseg;
2129
2130         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2131         if (m == NULL) {
2132                 if (wait) {
2133                         if_printf(&rxr->sc->arpcom.ac_if,
2134                             "Unable to allocate RX mbuf\n");
2135                 }
2136                 return ENOBUFS;
2137         }
2138         m->m_len = m->m_pkthdr.len = MCLBYTES;
2139
2140         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2141                 m_adj(m, ETHER_ALIGN);
2142
2143         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2144             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2145         if (error) {
2146                 m_freem(m);
2147                 if (wait) {
2148                         if_printf(&rxr->sc->arpcom.ac_if,
2149                             "Unable to load RX mbuf\n");
2150                 }
2151                 return error;
2152         }
2153
2154         rxbuf = &rxr->rx_buf[i];
2155         if (rxbuf->m_head != NULL)
2156                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2157
2158         map = rxbuf->map;
2159         rxbuf->map = rxr->rx_sparemap;
2160         rxr->rx_sparemap = map;
2161
2162         rxbuf->m_head = m;
2163         rxbuf->paddr = seg.ds_addr;
2164
2165         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2166         return 0;
2167 }
2168
2169 static int
2170 igb_init_rx_ring(struct igb_rx_ring *rxr)
2171 {
2172         int i;
2173
2174         /* Clear the ring contents */
2175         bzero(rxr->rx_base,
2176             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2177
2178         /* Now replenish the ring mbufs */
2179         for (i = 0; i < rxr->num_rx_desc; ++i) {
2180                 int error;
2181
2182                 error = igb_newbuf(rxr, i, TRUE);
2183                 if (error)
2184                         return error;
2185         }
2186
2187         /* Setup our descriptor indices */
2188         rxr->next_to_check = 0;
2189
2190         rxr->fmp = NULL;
2191         rxr->lmp = NULL;
2192         rxr->discard = FALSE;
2193
2194         return 0;
2195 }
2196
2197 static void
2198 igb_init_rx_unit(struct igb_softc *sc)
2199 {
2200         struct ifnet *ifp = &sc->arpcom.ac_if;
2201         struct e1000_hw *hw = &sc->hw;
2202         uint32_t rctl, rxcsum, srrctl = 0;
2203         int i;
2204
2205         /*
2206          * Make sure receives are disabled while setting
2207          * up the descriptor ring
2208          */
2209         rctl = E1000_READ_REG(hw, E1000_RCTL);
2210         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2211
2212 #if 0
2213         /*
2214         ** Set up for header split
2215         */
2216         if (igb_header_split) {
2217                 /* Use a standard mbuf for the header */
2218                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2219                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2220         } else
2221 #endif
2222                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2223
2224         /*
2225         ** Set up for jumbo frames
2226         */
2227         if (ifp->if_mtu > ETHERMTU) {
2228                 rctl |= E1000_RCTL_LPE;
2229 #if 0
2230                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2231                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2232                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2233                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2234                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2235                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2236                 }
2237                 /* Set maximum packet len */
2238                 psize = adapter->max_frame_size;
2239                 /* are we on a vlan? */
2240                 if (adapter->ifp->if_vlantrunk != NULL)
2241                         psize += VLAN_TAG_SIZE;
2242                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2243 #else
2244                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2245                 rctl |= E1000_RCTL_SZ_2048;
2246 #endif
2247         } else {
2248                 rctl &= ~E1000_RCTL_LPE;
2249                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2250                 rctl |= E1000_RCTL_SZ_2048;
2251         }
2252
2253         /* Setup the Base and Length of the Rx Descriptor Rings */
2254         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2255                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2256                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2257                 uint32_t rxdctl;
2258
2259                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2260                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2261                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2262                     (uint32_t)(bus_addr >> 32));
2263                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2264                     (uint32_t)bus_addr);
2265                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2266                 /* Enable this Queue */
2267                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2268                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2269                 rxdctl &= 0xFFF00000;
2270                 rxdctl |= IGB_RX_PTHRESH;
2271                 rxdctl |= IGB_RX_HTHRESH << 8;
2272                 rxdctl |= IGB_RX_WTHRESH << 16;
2273                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2274         }
2275
2276         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2277         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2278
2279         /*
2280          * Receive Checksum Offload for TCP and UDP
2281          *
2282          * Checksum offloading is also enabled if multiple receive
2283          * queue is to be supported, since we need it to figure out
2284          * fragments.
2285          */
2286         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2287                 /*
2288                  * NOTE:
2289                  * PCSD must be enabled to enable multiple
2290                  * receive queues.
2291                  */
2292                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2293                     E1000_RXCSUM_PCSD;
2294         } else {
2295                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2296                     E1000_RXCSUM_PCSD);
2297         }
2298         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2299
2300         if (IGB_ENABLE_HWRSS(sc)) {
2301                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2302                 uint32_t reta_shift;
2303                 int j, r;
2304
2305                 /*
2306                  * NOTE:
2307                  * When we reach here, RSS has already been disabled
2308                  * in igb_stop(), so we could safely configure RSS key
2309                  * and redirect table.
2310                  */
2311
2312                 /*
2313                  * Configure RSS key
2314                  */
2315                 toeplitz_get_key(key, sizeof(key));
2316                 for (i = 0; i < IGB_NRSSRK; ++i) {
2317                         uint32_t rssrk;
2318
2319                         rssrk = IGB_RSSRK_VAL(key, i);
2320                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2321
2322                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2323                 }
2324
2325                 /*
2326                  * Configure RSS redirect table in following fashion:
2327                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2328                  */
2329                 reta_shift = IGB_RETA_SHIFT;
2330                 if (hw->mac.type == e1000_82575)
2331                         reta_shift = IGB_RETA_SHIFT_82575;
2332
2333                 r = 0;
2334                 for (j = 0; j < IGB_NRETA; ++j) {
2335                         uint32_t reta = 0;
2336
2337                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2338                                 uint32_t q;
2339
2340                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2341                                 reta |= q << (8 * i);
2342                                 ++r;
2343                         }
2344                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2345                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2346                 }
2347
2348                 /*
2349                  * Enable multiple receive queues.
2350                  * Enable IPv4 RSS standard hash functions.
2351                  * Disable RSS interrupt on 82575
2352                  */
2353                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2354                                 E1000_MRQC_ENABLE_RSS_4Q |
2355                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2356                                 E1000_MRQC_RSS_FIELD_IPV4);
2357         }
2358
2359         /* Setup the Receive Control Register */
2360         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2361         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2362             E1000_RCTL_RDMTS_HALF |
2363             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2364         /* Strip CRC bytes. */
2365         rctl |= E1000_RCTL_SECRC;
2366         /* Make sure VLAN Filters are off */
2367         rctl &= ~E1000_RCTL_VFE;
2368         /* Don't store bad packets */
2369         rctl &= ~E1000_RCTL_SBP;
2370
2371         /* Enable Receives */
2372         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2373
2374         /*
2375          * Setup the HW Rx Head and Tail Descriptor Pointers
2376          *   - needs to be after enable
2377          */
2378         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2379                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2380
2381                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2382                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2383         }
2384 }
2385
2386 static void
2387 igb_rxeof(struct igb_rx_ring *rxr, int count)
2388 {
2389         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2390         union e1000_adv_rx_desc *cur;
2391         uint32_t staterr;
2392         int i;
2393
2394         i = rxr->next_to_check;
2395         cur = &rxr->rx_base[i];
2396         staterr = le32toh(cur->wb.upper.status_error);
2397
2398         if ((staterr & E1000_RXD_STAT_DD) == 0)
2399                 return;
2400
2401         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2402                 struct pktinfo *pi = NULL, pi0;
2403                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2404                 struct mbuf *m = NULL;
2405                 boolean_t eop;
2406
2407                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2408                 if (eop)
2409                         --count;
2410
2411                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2412                     !rxr->discard) {
2413                         struct mbuf *mp = rxbuf->m_head;
2414                         uint32_t hash, hashtype;
2415                         uint16_t vlan;
2416                         int len;
2417
2418                         len = le16toh(cur->wb.upper.length);
2419                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2420                             (staterr & E1000_RXDEXT_STATERR_LB))
2421                                 vlan = be16toh(cur->wb.upper.vlan);
2422                         else
2423                                 vlan = le16toh(cur->wb.upper.vlan);
2424
2425                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2426                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2427                             E1000_RXDADV_RSSTYPE_MASK;
2428
2429                         IGB_RSS_DPRINTF(rxr->sc, 10,
2430                             "ring%d, hash 0x%08x, hashtype %u\n",
2431                             rxr->me, hash, hashtype);
2432
2433                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2434                             BUS_DMASYNC_POSTREAD);
2435
2436                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2437                                 ifp->if_iqdrops++;
2438                                 goto discard;
2439                         }
2440
2441                         mp->m_len = len;
2442                         if (rxr->fmp == NULL) {
2443                                 mp->m_pkthdr.len = len;
2444                                 rxr->fmp = mp;
2445                                 rxr->lmp = mp;
2446                         } else {
2447                                 rxr->lmp->m_next = mp;
2448                                 rxr->lmp = rxr->lmp->m_next;
2449                                 rxr->fmp->m_pkthdr.len += len;
2450                         }
2451
2452                         if (eop) {
2453                                 m = rxr->fmp;
2454                                 rxr->fmp = NULL;
2455                                 rxr->lmp = NULL;
2456
2457                                 m->m_pkthdr.rcvif = ifp;
2458                                 ifp->if_ipackets++;
2459
2460                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2461                                         igb_rxcsum(staterr, m);
2462
2463                                 if (staterr & E1000_RXD_STAT_VP) {
2464                                         m->m_pkthdr.ether_vlantag = vlan;
2465                                         m->m_flags |= M_VLANTAG;
2466                                 }
2467
2468                                 if (ifp->if_capenable & IFCAP_RSS) {
2469                                         pi = igb_rssinfo(m, &pi0,
2470                                             hash, hashtype, staterr);
2471                                 }
2472 #ifdef IGB_RSS_DEBUG
2473                                 rxr->rx_packets++;
2474 #endif
2475                         }
2476                 } else {
2477                         ifp->if_ierrors++;
2478 discard:
2479                         igb_setup_rxdesc(cur, rxbuf);
2480                         if (!eop)
2481                                 rxr->discard = TRUE;
2482                         else
2483                                 rxr->discard = FALSE;
2484                         if (rxr->fmp != NULL) {
2485                                 m_freem(rxr->fmp);
2486                                 rxr->fmp = NULL;
2487                                 rxr->lmp = NULL;
2488                         }
2489                         m = NULL;
2490                 }
2491
2492                 if (m != NULL)
2493                         ether_input_pkt(ifp, m, pi);
2494
2495                 /* Advance our pointers to the next descriptor. */
2496                 if (++i == rxr->num_rx_desc)
2497                         i = 0;
2498
2499                 cur = &rxr->rx_base[i];
2500                 staterr = le32toh(cur->wb.upper.status_error);
2501         }
2502         rxr->next_to_check = i;
2503
2504         if (--i < 0)
2505                 i = rxr->num_rx_desc - 1;
2506         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2507 }
2508
2509
2510 static void
2511 igb_set_vlan(struct igb_softc *sc)
2512 {
2513         struct e1000_hw *hw = &sc->hw;
2514         uint32_t reg;
2515 #if 0
2516         struct ifnet *ifp = sc->arpcom.ac_if;
2517 #endif
2518
2519         if (sc->vf_ifp) {
2520                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2521                 return;
2522         }
2523
2524         reg = E1000_READ_REG(hw, E1000_CTRL);
2525         reg |= E1000_CTRL_VME;
2526         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2527
2528 #if 0
2529         /* Enable the Filter Table */
2530         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2531                 reg = E1000_READ_REG(hw, E1000_RCTL);
2532                 reg &= ~E1000_RCTL_CFIEN;
2533                 reg |= E1000_RCTL_VFE;
2534                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2535         }
2536 #endif
2537
2538         /* Update the frame size */
2539         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2540             sc->max_frame_size + VLAN_TAG_SIZE);
2541
2542 #if 0
2543         /* Don't bother with table if no vlans */
2544         if ((adapter->num_vlans == 0) ||
2545             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2546                 return;
2547         /*
2548         ** A soft reset zero's out the VFTA, so
2549         ** we need to repopulate it now.
2550         */
2551         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2552                 if (adapter->shadow_vfta[i] != 0) {
2553                         if (adapter->vf_ifp)
2554                                 e1000_vfta_set_vf(hw,
2555                                     adapter->shadow_vfta[i], TRUE);
2556                         else
2557                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2558                                  i, adapter->shadow_vfta[i]);
2559                 }
2560 #endif
2561 }
2562
2563 static void
2564 igb_enable_intr(struct igb_softc *sc)
2565 {
2566         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2567                 lwkt_serialize_handler_enable(&sc->main_serialize);
2568         } else {
2569                 int i;
2570
2571                 for (i = 0; i < sc->msix_cnt; ++i) {
2572                         lwkt_serialize_handler_enable(
2573                             sc->msix_data[i].msix_serialize);
2574                 }
2575         }
2576
2577         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2578                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2579                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2580                 else
2581                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2582                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2583                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2584                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2585         } else {
2586                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2587         }
2588         E1000_WRITE_FLUSH(&sc->hw);
2589 }
2590
2591 static void
2592 igb_disable_intr(struct igb_softc *sc)
2593 {
2594         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2595                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2596                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2597         }
2598         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2599         E1000_WRITE_FLUSH(&sc->hw);
2600
2601         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2602                 lwkt_serialize_handler_disable(&sc->main_serialize);
2603         } else {
2604                 int i;
2605
2606                 for (i = 0; i < sc->msix_cnt; ++i) {
2607                         lwkt_serialize_handler_disable(
2608                             sc->msix_data[i].msix_serialize);
2609                 }
2610         }
2611 }
2612
2613 /*
2614  * Bit of a misnomer, what this really means is
2615  * to enable OS management of the system... aka
2616  * to disable special hardware management features
2617  */
2618 static void
2619 igb_get_mgmt(struct igb_softc *sc)
2620 {
2621         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2622                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2623                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2624
2625                 /* disable hardware interception of ARP */
2626                 manc &= ~E1000_MANC_ARP_EN;
2627
2628                 /* enable receiving management packets to the host */
2629                 manc |= E1000_MANC_EN_MNG2HOST;
2630                 manc2h |= 1 << 5; /* Mng Port 623 */
2631                 manc2h |= 1 << 6; /* Mng Port 664 */
2632                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2633                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2634         }
2635 }
2636
2637 /*
2638  * Give control back to hardware management controller
2639  * if there is one.
2640  */
2641 static void
2642 igb_rel_mgmt(struct igb_softc *sc)
2643 {
2644         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2645                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2646
2647                 /* Re-enable hardware interception of ARP */
2648                 manc |= E1000_MANC_ARP_EN;
2649                 manc &= ~E1000_MANC_EN_MNG2HOST;
2650
2651                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2652         }
2653 }
2654
2655 /*
2656  * Sets CTRL_EXT:DRV_LOAD bit.
2657  *
2658  * For ASF and Pass Through versions of f/w this means that
2659  * the driver is loaded.
2660  */
2661 static void
2662 igb_get_hw_control(struct igb_softc *sc)
2663 {
2664         uint32_t ctrl_ext;
2665
2666         if (sc->vf_ifp)
2667                 return;
2668
2669         /* Let firmware know the driver has taken over */
2670         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2671         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2672             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2673 }
2674
2675 /*
2676  * Resets CTRL_EXT:DRV_LOAD bit.
2677  *
2678  * For ASF and Pass Through versions of f/w this means that the
2679  * driver is no longer loaded.
2680  */
2681 static void
2682 igb_rel_hw_control(struct igb_softc *sc)
2683 {
2684         uint32_t ctrl_ext;
2685
2686         if (sc->vf_ifp)
2687                 return;
2688
2689         /* Let firmware taken over control of h/w */
2690         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2691         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2692             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2693 }
2694
2695 static int
2696 igb_is_valid_ether_addr(const uint8_t *addr)
2697 {
2698         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2699
2700         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2701                 return FALSE;
2702         return TRUE;
2703 }
2704
2705 /*
2706  * Enable PCI Wake On Lan capability
2707  */
2708 static void
2709 igb_enable_wol(device_t dev)
2710 {
2711         uint16_t cap, status;
2712         uint8_t id;
2713
2714         /* First find the capabilities pointer*/
2715         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2716
2717         /* Read the PM Capabilities */
2718         id = pci_read_config(dev, cap, 1);
2719         if (id != PCIY_PMG)     /* Something wrong */
2720                 return;
2721
2722         /*
2723          * OK, we have the power capabilities,
2724          * so now get the status register
2725          */
2726         cap += PCIR_POWER_STATUS;
2727         status = pci_read_config(dev, cap, 2);
2728         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2729         pci_write_config(dev, cap, status, 2);
2730 }
2731
2732 static void
2733 igb_update_stats_counters(struct igb_softc *sc)
2734 {
2735         struct e1000_hw *hw = &sc->hw;
2736         struct e1000_hw_stats *stats;
2737         struct ifnet *ifp = &sc->arpcom.ac_if;
2738
2739         /*
2740          * The virtual function adapter has only a
2741          * small controlled set of stats, do only
2742          * those and return.
2743          */
2744         if (sc->vf_ifp) {
2745                 igb_update_vf_stats_counters(sc);
2746                 return;
2747         }
2748         stats = sc->stats;
2749
2750         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2751             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2752                 stats->symerrs +=
2753                     E1000_READ_REG(hw,E1000_SYMERRS);
2754                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2755         }
2756
2757         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2758         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2759         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2760         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2761
2762         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2763         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2764         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2765         stats->dc += E1000_READ_REG(hw, E1000_DC);
2766         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2767         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2768         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2769
2770         /*
2771          * For watchdog management we need to know if we have been
2772          * paused during the last interval, so capture that here.
2773          */
2774         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2775         stats->xoffrxc += sc->pause_frames;
2776         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2777         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2778         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2779         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2780         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2781         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2782         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2783         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2784         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2785         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2786         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2787         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2788
2789         /* For the 64-bit byte counters the low dword must be read first. */
2790         /* Both registers clear on the read of the high dword */
2791
2792         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2793             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2794         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2795             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2796
2797         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2798         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2799         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2800         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2801         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2802
2803         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2804         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2805
2806         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2807         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2808         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2809         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2810         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2811         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2812         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2813         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2814         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2815         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2816
2817         /* Interrupt Counts */
2818
2819         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2820         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2821         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2822         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2823         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2824         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2825         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2826         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2827         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2828
2829         /* Host to Card Statistics */
2830
2831         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2832         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2833         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2834         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2835         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2836         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2837         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2838         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2839             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2840         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2841             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2842         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2843         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2844         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2845
2846         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2847         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2848         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2849         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2850         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2851         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2852
2853         ifp->if_collisions = stats->colc;
2854
2855         /* Rx Errors */
2856         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2857             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2858
2859         /* Tx Errors */
2860         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2861
2862         /* Driver specific counters */
2863         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2864         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2865         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2866         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2867         sc->packet_buf_alloc_tx =
2868             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2869         sc->packet_buf_alloc_rx =
2870             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2871 }
2872
2873 static void
2874 igb_vf_init_stats(struct igb_softc *sc)
2875 {
2876         struct e1000_hw *hw = &sc->hw;
2877         struct e1000_vf_stats *stats;
2878
2879         stats = sc->stats;
2880         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2881         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2882         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2883         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2884         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2885 }
2886
2887 static void
2888 igb_update_vf_stats_counters(struct igb_softc *sc)
2889 {
2890         struct e1000_hw *hw = &sc->hw;
2891         struct e1000_vf_stats *stats;
2892
2893         if (sc->link_speed == 0)
2894                 return;
2895
2896         stats = sc->stats;
2897         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2898         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2899         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2900         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2901         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2902 }
2903
2904 #ifdef DEVICE_POLLING
2905
2906 static void
2907 igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2908 {
2909         struct igb_softc *sc = ifp->if_softc;
2910         uint32_t reg_icr;
2911
2912         switch (cmd) {
2913         case POLL_REGISTER:
2914         case POLL_DEREGISTER:
2915                 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2916                 igb_init(sc);
2917                 break;
2918
2919         case POLL_AND_CHECK_STATUS:
2920                 ASSERT_SERIALIZED(&sc->main_serialize);
2921                 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2922                 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2923                         sc->hw.mac.get_link_status = 1;
2924                         igb_update_link_status(sc);
2925                 }
2926                 /* FALL THROUGH */
2927         case POLL_ONLY:
2928                 ASSERT_SERIALIZED(&sc->main_serialize);
2929                 if (ifp->if_flags & IFF_RUNNING) {
2930                         struct igb_tx_ring *txr;
2931                         int i;
2932
2933                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2934                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2935
2936                                 lwkt_serialize_enter(&rxr->rx_serialize);
2937                                 igb_rxeof(rxr, count);
2938                                 lwkt_serialize_exit(&rxr->rx_serialize);
2939                         }
2940
2941                         txr = &sc->tx_rings[0];
2942                         lwkt_serialize_enter(&txr->tx_serialize);
2943                         igb_txeof(txr);
2944                         if (!ifq_is_empty(&ifp->if_snd))
2945                                 if_devstart(ifp);
2946                         lwkt_serialize_exit(&txr->tx_serialize);
2947                 }
2948                 break;
2949         }
2950 }
2951
2952 #endif /* DEVICE_POLLING */
2953
2954 static void
2955 igb_intr(void *xsc)
2956 {
2957         struct igb_softc *sc = xsc;
2958         struct ifnet *ifp = &sc->arpcom.ac_if;
2959         uint32_t eicr;
2960
2961         ASSERT_SERIALIZED(&sc->main_serialize);
2962
2963         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
2964
2965         if (eicr == 0)
2966                 return;
2967
2968         if (ifp->if_flags & IFF_RUNNING) {
2969                 struct igb_tx_ring *txr;
2970                 int i;
2971
2972                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2973                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
2974
2975                         if (eicr & rxr->rx_intr_mask) {
2976                                 lwkt_serialize_enter(&rxr->rx_serialize);
2977                                 igb_rxeof(rxr, -1);
2978                                 lwkt_serialize_exit(&rxr->rx_serialize);
2979                         }
2980                 }
2981
2982                 txr = &sc->tx_rings[0];
2983                 if (eicr & txr->tx_intr_mask) {
2984                         lwkt_serialize_enter(&txr->tx_serialize);
2985                         igb_txeof(txr);
2986                         if (!ifq_is_empty(&ifp->if_snd))
2987                                 if_devstart(ifp);
2988                         lwkt_serialize_exit(&txr->tx_serialize);
2989                 }
2990         }
2991
2992         if (eicr & E1000_EICR_OTHER) {
2993                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2994
2995                 /* Link status change */
2996                 if (icr & E1000_ICR_LSC) {
2997                         sc->hw.mac.get_link_status = 1;
2998                         igb_update_link_status(sc);
2999                 }
3000         }
3001
3002         /*
3003          * Reading EICR has the side effect to clear interrupt mask,
3004          * so all interrupts need to be enabled here.
3005          */
3006         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3007 }
3008
3009 static void
3010 igb_intr_shared(void *xsc)
3011 {
3012         struct igb_softc *sc = xsc;
3013         struct ifnet *ifp = &sc->arpcom.ac_if;
3014         uint32_t reg_icr;
3015
3016         ASSERT_SERIALIZED(&sc->main_serialize);
3017
3018         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3019
3020         /* Hot eject?  */
3021         if (reg_icr == 0xffffffff)
3022                 return;
3023
3024         /* Definitely not our interrupt.  */
3025         if (reg_icr == 0x0)
3026                 return;
3027
3028         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3029                 return;
3030
3031         if (ifp->if_flags & IFF_RUNNING) {
3032                 if (reg_icr &
3033                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3034                         int i;
3035
3036                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3037                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3038
3039                                 lwkt_serialize_enter(&rxr->rx_serialize);
3040                                 igb_rxeof(rxr, -1);
3041                                 lwkt_serialize_exit(&rxr->rx_serialize);
3042                         }
3043                 }
3044
3045                 if (reg_icr & E1000_ICR_TXDW) {
3046                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3047
3048                         lwkt_serialize_enter(&txr->tx_serialize);
3049                         igb_txeof(txr);
3050                         if (!ifq_is_empty(&ifp->if_snd))
3051                                 if_devstart(ifp);
3052                         lwkt_serialize_exit(&txr->tx_serialize);
3053                 }
3054         }
3055
3056         /* Link status change */
3057         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3058                 sc->hw.mac.get_link_status = 1;
3059                 igb_update_link_status(sc);
3060         }
3061
3062         if (reg_icr & E1000_ICR_RXO)
3063                 sc->rx_overruns++;
3064 }
3065
3066 static int
3067 igb_txctx_pullup(struct igb_tx_ring *txr, struct mbuf **m0)
3068 {
3069         struct mbuf *m = *m0;
3070         struct ether_header *eh;
3071         int len;
3072
3073         txr->ctx_try_pullup++;
3074
3075         len = ETHER_HDR_LEN + IGB_IPVHL_SIZE;
3076
3077         if (__predict_false(!M_WRITABLE(m))) {
3078                 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3079                         txr->ctx_drop1++;
3080                         m_freem(m);
3081                         *m0 = NULL;
3082                         return ENOBUFS;
3083                 }
3084                 eh = mtod(m, struct ether_header *);
3085
3086                 if (eh->ether_type == htons(ETHERTYPE_VLAN))
3087                         len += EVL_ENCAPLEN;
3088
3089                 if (m->m_len < len) {
3090                         txr->ctx_drop2++;
3091                         m_freem(m);
3092                         *m0 = NULL;
3093                         return ENOBUFS;
3094                 }
3095                 return 0;
3096         }
3097
3098         if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3099                 txr->ctx_pullup1++;
3100                 m = m_pullup(m, ETHER_HDR_LEN);
3101                 if (m == NULL) {
3102                         txr->ctx_pullup1_failed++;
3103                         *m0 = NULL;
3104                         return ENOBUFS;
3105                 }
3106                 *m0 = m;
3107         }
3108         eh = mtod(m, struct ether_header *);
3109
3110         if (eh->ether_type == htons(ETHERTYPE_VLAN))
3111                 len += EVL_ENCAPLEN;
3112
3113         if (m->m_len < len) {
3114                 txr->ctx_pullup2++;
3115                 m = m_pullup(m, len);
3116                 if (m == NULL) {
3117                         txr->ctx_pullup2_failed++;
3118                         *m0 = NULL;
3119                         return ENOBUFS;
3120                 }
3121                 *m0 = m;
3122         }
3123         return 0;
3124 }
3125
3126 static int
3127 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3128 {
3129         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3130         bus_dmamap_t map;
3131         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3132         union e1000_adv_tx_desc *txd = NULL;
3133         struct mbuf *m_head = *m_headp;
3134         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3135         int maxsegs, nsegs, i, j, error, last = 0;
3136         uint32_t hdrlen = 0;
3137
3138         if (m_head->m_len < IGB_TXCSUM_MINHL &&
3139             ((m_head->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) ||
3140              (m_head->m_flags & M_VLANTAG))) {
3141                 /*
3142                  * Make sure that ethernet header and ip.ip_hl are in
3143                  * contiguous memory, since if TXCSUM or VLANTAG is
3144                  * enabled, later TX context descriptor's setup need
3145                  * to access ip.ip_hl.
3146                  */
3147                 error = igb_txctx_pullup(txr, m_headp);
3148                 if (error) {
3149                         KKASSERT(*m_headp == NULL);
3150                         return error;
3151                 }
3152                 m_head = *m_headp;
3153         }
3154
3155         /* Set basic descriptor constants */
3156         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3157         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3158         if (m_head->m_flags & M_VLANTAG)
3159                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3160
3161         /*
3162          * Map the packet for DMA.
3163          */
3164         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3165         tx_buf_mapped = tx_buf;
3166         map = tx_buf->map;
3167
3168         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3169         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3170         if (maxsegs > IGB_MAX_SCATTER)
3171                 maxsegs = IGB_MAX_SCATTER;
3172
3173         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3174             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3175         if (error) {
3176                 if (error == ENOBUFS)
3177                         txr->sc->mbuf_defrag_failed++;
3178                 else
3179                         txr->sc->no_tx_dma_setup++;
3180
3181                 m_freem(*m_headp);
3182                 *m_headp = NULL;
3183                 return error;
3184         }
3185         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3186
3187         m_head = *m_headp;
3188
3189 #if 0
3190         /*
3191          * Set up the context descriptor:
3192          * used when any hardware offload is done.
3193          * This includes CSUM, VLAN, and TSO. It
3194          * will use the first descriptor.
3195          */
3196         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3197                 if (igb_tso_setup(txr, m_head, &hdrlen)) {
3198                         cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3199                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3200                         olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3201                 } else
3202                         return (ENXIO);
3203         } else if (igb_tx_ctx_setup(txr, m_head))
3204                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3205 #else
3206         if (igb_txctx(txr, m_head)) {
3207                 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3208                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3209                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3210                 txr->tx_nsegs++;
3211         }
3212 #endif
3213
3214         txr->tx_nsegs += nsegs;
3215         if (txr->tx_nsegs >= txr->intr_nsegs) {
3216                 /*
3217                  * Report Status (RS) is turned on every intr_nsegs
3218                  * descriptors (roughly).
3219                  */
3220                 txr->tx_nsegs = 0;
3221                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3222         }
3223
3224         /* Calculate payload length */
3225         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3226             << E1000_ADVTXD_PAYLEN_SHIFT);
3227
3228         /* 82575 needs the queue index added */
3229         if (txr->sc->hw.mac.type == e1000_82575)
3230                 olinfo_status |= txr->me << 4;
3231
3232         /* Set up our transmit descriptors */
3233         i = txr->next_avail_desc;
3234         for (j = 0; j < nsegs; j++) {
3235                 bus_size_t seg_len;
3236                 bus_addr_t seg_addr;
3237
3238                 tx_buf = &txr->tx_buf[i];
3239                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3240                 seg_addr = segs[j].ds_addr;
3241                 seg_len = segs[j].ds_len;
3242
3243                 txd->read.buffer_addr = htole64(seg_addr);
3244                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3245                 txd->read.olinfo_status = htole32(olinfo_status);
3246                 last = i;
3247                 if (++i == txr->num_tx_desc)
3248                         i = 0;
3249                 tx_buf->m_head = NULL;
3250         }
3251
3252         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3253         txr->next_avail_desc = i;
3254         txr->tx_avail -= nsegs;
3255
3256         tx_buf->m_head = m_head;
3257         tx_buf_mapped->map = tx_buf->map;
3258         tx_buf->map = map;
3259
3260         /*
3261          * Last Descriptor of Packet needs End Of Packet (EOP)
3262          */
3263         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3264
3265         /*
3266          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3267          * that this frame is available to transmit.
3268          */
3269         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3270         ++txr->tx_packets;
3271
3272         return 0;
3273 }
3274
3275 static void
3276 igb_start(struct ifnet *ifp)
3277 {
3278         struct igb_softc *sc = ifp->if_softc;
3279         struct igb_tx_ring *txr = &sc->tx_rings[0];
3280         struct mbuf *m_head;
3281
3282         ASSERT_SERIALIZED(&txr->tx_serialize);
3283
3284         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3285                 return;
3286
3287         if (!sc->link_active) {
3288                 ifq_purge(&ifp->if_snd);
3289                 return;
3290         }
3291
3292         if (!IGB_IS_NOT_OACTIVE(txr))
3293                 igb_txeof(txr);
3294
3295         while (!ifq_is_empty(&ifp->if_snd)) {
3296                 if (IGB_IS_OACTIVE(txr)) {
3297                         ifp->if_flags |= IFF_OACTIVE;
3298                         /* Set watchdog on */
3299                         ifp->if_timer = 5;
3300                         break;
3301                 }
3302
3303                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3304                 if (m_head == NULL)
3305                         break;
3306
3307                 if (igb_encap(txr, &m_head)) {
3308                         ifp->if_oerrors++;
3309                         continue;
3310                 }
3311
3312                 /* Send a copy of the frame to the BPF listener */
3313                 ETHER_BPF_MTAP(ifp, m_head);
3314         }
3315 }
3316
3317 static void
3318 igb_watchdog(struct ifnet *ifp)
3319 {
3320         struct igb_softc *sc = ifp->if_softc;
3321         struct igb_tx_ring *txr = &sc->tx_rings[0];
3322
3323         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3324
3325         /*
3326          * If flow control has paused us since last checking
3327          * it invalidates the watchdog timing, so dont run it.
3328          */
3329         if (sc->pause_frames) {
3330                 sc->pause_frames = 0;
3331                 ifp->if_timer = 5;
3332                 return;
3333         }
3334
3335         if_printf(ifp, "Watchdog timeout -- resetting\n");
3336         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3337             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3338             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3339         if_printf(ifp, "TX(%d) desc avail = %d, "
3340             "Next TX to Clean = %d\n",
3341             txr->me, txr->tx_avail, txr->next_to_clean);
3342
3343         ifp->if_oerrors++;
3344         sc->watchdog_events++;
3345
3346         igb_init(sc);
3347         if (!ifq_is_empty(&ifp->if_snd))
3348                 if_devstart(ifp);
3349 }
3350
3351 static void
3352 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3353 {
3354         uint32_t eitr = 0;
3355
3356         if (rate > 0) {
3357                 if (sc->hw.mac.type == e1000_82575) {
3358                         eitr = 1000000000 / 256 / rate;
3359                         /*
3360                          * NOTE:
3361                          * Document is wrong on the 2 bits left shift
3362                          */
3363                 } else {
3364                         eitr = 1000000 / rate;
3365                         eitr <<= 2;
3366                 }
3367                 eitr &= 0x7FFC;
3368         }
3369         if (sc->hw.mac.type == e1000_82575)
3370                 eitr |= eitr << 16;
3371         else
3372                 eitr |= E1000_EITR_CNT_IGNR;
3373         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3374 }
3375
3376 static int
3377 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3378 {
3379         struct igb_softc *sc = (void *)arg1;
3380         struct ifnet *ifp = &sc->arpcom.ac_if;
3381         int error, intr_rate;
3382
3383         intr_rate = sc->intr_rate;
3384         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3385         if (error || req->newptr == NULL)
3386                 return error;
3387         if (intr_rate < 0)
3388                 return EINVAL;
3389
3390         ifnet_serialize_all(ifp);
3391
3392         sc->intr_rate = intr_rate;
3393         if (ifp->if_flags & IFF_RUNNING)
3394                 igb_set_eitr(sc, 0, sc->intr_rate);
3395
3396         if (bootverbose)
3397                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3398
3399         ifnet_deserialize_all(ifp);
3400
3401         return 0;
3402 }
3403
3404 static int
3405 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3406 {
3407         struct igb_msix_data *msix = (void *)arg1;
3408         struct igb_softc *sc = msix->msix_sc;
3409         struct ifnet *ifp = &sc->arpcom.ac_if;
3410         int error, msix_rate;
3411
3412         msix_rate = msix->msix_rate;
3413         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3414         if (error || req->newptr == NULL)
3415                 return error;
3416         if (msix_rate < 0)
3417                 return EINVAL;
3418
3419         lwkt_serialize_enter(msix->msix_serialize);
3420
3421         msix->msix_rate = msix_rate;
3422         if (ifp->if_flags & IFF_RUNNING)
3423                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3424
3425         if (bootverbose) {
3426                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3427                     msix->msix_rate);
3428         }
3429
3430         lwkt_serialize_exit(msix->msix_serialize);
3431
3432         return 0;
3433 }
3434
3435 static int
3436 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3437 {
3438         struct igb_softc *sc = (void *)arg1;
3439         struct ifnet *ifp = &sc->arpcom.ac_if;
3440         struct igb_tx_ring *txr = &sc->tx_rings[0];
3441         int error, nsegs;
3442
3443         nsegs = txr->intr_nsegs;
3444         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3445         if (error || req->newptr == NULL)
3446                 return error;
3447         if (nsegs <= 0)
3448                 return EINVAL;
3449
3450         ifnet_serialize_all(ifp);
3451
3452         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3453             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3454                 error = EINVAL;
3455         } else {
3456                 error = 0;
3457                 txr->intr_nsegs = nsegs;
3458         }
3459
3460         ifnet_deserialize_all(ifp);
3461
3462         return error;
3463 }
3464
3465 static void
3466 igb_init_intr(struct igb_softc *sc)
3467 {
3468         igb_set_intr_mask(sc);
3469
3470         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3471                 igb_init_unshared_intr(sc);
3472
3473         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3474                 igb_set_eitr(sc, 0, sc->intr_rate);
3475         } else {
3476                 int i;
3477
3478                 for (i = 0; i < sc->msix_cnt; ++i)
3479                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3480         }
3481 }
3482
3483 static void
3484 igb_init_unshared_intr(struct igb_softc *sc)
3485 {
3486         struct e1000_hw *hw = &sc->hw;
3487         const struct igb_rx_ring *rxr;
3488         const struct igb_tx_ring *txr;
3489         uint32_t ivar, index;
3490         int i;
3491
3492         /*
3493          * Enable extended mode
3494          */
3495         if (sc->hw.mac.type != e1000_82575) {
3496                 uint32_t gpie;
3497                 int ivar_max;
3498
3499                 gpie = E1000_GPIE_NSICR;
3500                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3501                         gpie |= E1000_GPIE_MSIX_MODE |
3502                             E1000_GPIE_EIAME |
3503                             E1000_GPIE_PBA;
3504                 }
3505                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3506
3507                 /*
3508                  * Clear IVARs
3509                  */
3510                 switch (sc->hw.mac.type) {
3511                 case e1000_82580:
3512                         ivar_max = IGB_MAX_IVAR_82580;
3513                         break;
3514
3515                 case e1000_i350:
3516                         ivar_max = IGB_MAX_IVAR_I350;
3517                         break;
3518
3519                 case e1000_vfadapt:
3520                 case e1000_vfadapt_i350:
3521                         ivar_max = IGB_MAX_IVAR_VF;
3522                         break;
3523
3524                 case e1000_82576:
3525                         ivar_max = IGB_MAX_IVAR_82576;
3526                         break;
3527
3528                 default:
3529                         panic("unknown mac type %d\n", sc->hw.mac.type);
3530                 }
3531                 for (i = 0; i < ivar_max; ++i)
3532                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3533                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3534         } else {
3535                 uint32_t tmp;
3536
3537                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3538                     ("82575 w/ MSI-X"));
3539                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3540                 tmp |= E1000_CTRL_EXT_IRCA;
3541                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3542         }
3543
3544         /*
3545          * Map TX/RX interrupts to EICR
3546          */
3547         switch (sc->hw.mac.type) {
3548         case e1000_82580:
3549         case e1000_i350:
3550         case e1000_vfadapt:
3551         case e1000_vfadapt_i350:
3552                 /* RX entries */
3553                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3554                         rxr = &sc->rx_rings[i];
3555
3556                         index = i >> 1;
3557                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3558
3559                         if (i & 1) {
3560                                 ivar &= 0xff00ffff;
3561                                 ivar |=
3562                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3563                         } else {
3564                                 ivar &= 0xffffff00;
3565                                 ivar |=
3566                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3567                         }
3568                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3569                 }
3570                 /* TX entries */
3571                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3572                         txr = &sc->tx_rings[i];
3573
3574                         index = i >> 1;
3575                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3576
3577                         if (i & 1) {
3578                                 ivar &= 0x00ffffff;
3579                                 ivar |=
3580                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3581                         } else {
3582                                 ivar &= 0xffff00ff;
3583                                 ivar |=
3584                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3585                         }
3586                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3587                 }
3588                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3589                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3590                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3591                 }
3592                 break;
3593
3594         case e1000_82576:
3595                 /* RX entries */
3596                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3597                         rxr = &sc->rx_rings[i];
3598
3599                         index = i & 0x7; /* Each IVAR has two entries */
3600                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3601
3602                         if (i < 8) {
3603                                 ivar &= 0xffffff00;
3604                                 ivar |=
3605                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3606                         } else {
3607                                 ivar &= 0xff00ffff;
3608                                 ivar |=
3609                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3610                         }
3611                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3612                 }
3613                 /* TX entries */
3614                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3615                         txr = &sc->tx_rings[i];
3616
3617                         index = i & 0x7; /* Each IVAR has two entries */
3618                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3619
3620                         if (i < 8) {
3621                                 ivar &= 0xffff00ff;
3622                                 ivar |=
3623                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3624                         } else {
3625                                 ivar &= 0x00ffffff;
3626                                 ivar |=
3627                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3628                         }
3629                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3630                 }
3631                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3632                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3633                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3634                 }
3635                 break;
3636
3637         case e1000_82575:
3638                 /*
3639                  * Enable necessary interrupt bits.
3640                  *
3641                  * The name of the register is confusing; in addition to
3642                  * configuring the first vector of MSI-X, it also configures
3643                  * which bits of EICR could be set by the hardware even when
3644                  * MSI or line interrupt is used; it thus controls interrupt
3645                  * generation.  It MUST be configured explicitly; the default
3646                  * value mentioned in the datasheet is wrong: RX queue0 and
3647                  * TX queue0 are NOT enabled by default.
3648                  */
3649                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3650                 break;
3651
3652         default:
3653                 panic("unknown mac type %d\n", sc->hw.mac.type);
3654         }
3655 }
3656
3657 static int
3658 igb_setup_intr(struct igb_softc *sc)
3659 {
3660         struct ifnet *ifp = &sc->arpcom.ac_if;
3661         int error;
3662
3663         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3664                 return igb_msix_setup(sc);
3665
3666         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3667                 int unshared;
3668
3669                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3670                 if (!unshared) {
3671                         sc->flags |= IGB_FLAG_SHARED_INTR;
3672                         if (bootverbose)
3673                                 device_printf(sc->dev, "IRQ shared\n");
3674                 } else if (bootverbose) {
3675                         device_printf(sc->dev, "IRQ unshared\n");
3676                 }
3677         }
3678
3679         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3680             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3681             sc, &sc->intr_tag, &sc->main_serialize);
3682         if (error) {
3683                 device_printf(sc->dev, "Failed to register interrupt handler");
3684                 return error;
3685         }
3686
3687         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3688         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3689
3690         return 0;
3691 }
3692
3693 static void
3694 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3695 {
3696         if (txr->sc->hw.mac.type == e1000_82575) {
3697                 txr->tx_intr_bit = 0;   /* unused */
3698                 switch (txr->me) {
3699                 case 0:
3700                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3701                         break;
3702                 case 1:
3703                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3704                         break;
3705                 case 2:
3706                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3707                         break;
3708                 case 3:
3709                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3710                         break;
3711                 default:
3712                         panic("unsupported # of TX ring, %d\n", txr->me);
3713                 }
3714         } else {
3715                 int intr_bit = *intr_bit0;
3716
3717                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3718                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3719
3720                 *intr_bit0 = intr_bit + 1;
3721         }
3722 }
3723
3724 static void
3725 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3726 {
3727         if (rxr->sc->hw.mac.type == e1000_82575) {
3728                 rxr->rx_intr_bit = 0;   /* unused */
3729                 switch (rxr->me) {
3730                 case 0:
3731                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3732                         break;
3733                 case 1:
3734                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3735                         break;
3736                 case 2:
3737                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3738                         break;
3739                 case 3:
3740                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3741                         break;
3742                 default:
3743                         panic("unsupported # of RX ring, %d\n", rxr->me);
3744                 }
3745         } else {
3746                 int intr_bit = *intr_bit0;
3747
3748                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3749                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3750
3751                 *intr_bit0 = intr_bit + 1;
3752         }
3753 }
3754
3755 static void
3756 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3757 {
3758         struct igb_softc *sc = ifp->if_softc;
3759
3760         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3761             sc->tx_serialize, sc->rx_serialize, slz);
3762 }
3763
3764 static void
3765 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3766 {
3767         struct igb_softc *sc = ifp->if_softc;
3768
3769         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3770             sc->tx_serialize, sc->rx_serialize, slz);
3771 }
3772
3773 static int
3774 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3775 {
3776         struct igb_softc *sc = ifp->if_softc;
3777
3778         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3779             sc->tx_serialize, sc->rx_serialize, slz);
3780 }
3781
3782 #ifdef INVARIANTS
3783
3784 static void
3785 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3786     boolean_t serialized)
3787 {
3788         struct igb_softc *sc = ifp->if_softc;
3789
3790         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3791             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3792 }
3793
3794 #endif  /* INVARIANTS */
3795
3796 static void
3797 igb_set_intr_mask(struct igb_softc *sc)
3798 {
3799         int i;
3800
3801         sc->intr_mask = sc->sts_intr_mask;
3802         for (i = 0; i < sc->rx_ring_inuse; ++i)
3803                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3804         for (i = 0; i < sc->tx_ring_cnt; ++i)
3805                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3806         if (bootverbose)
3807                 device_printf(sc->dev, "intr mask 0x%08x\n", sc->intr_mask);
3808 }
3809
3810 static int
3811 igb_alloc_intr(struct igb_softc *sc)
3812 {
3813         int i, intr_bit, intr_bitmax;
3814         u_int intr_flags;
3815
3816         igb_msix_try_alloc(sc);
3817         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3818                 goto done;
3819
3820         /*
3821          * Allocate MSI/legacy interrupt resource
3822          */
3823         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3824             &sc->intr_rid, &intr_flags);
3825
3826         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3827             &sc->intr_rid, intr_flags);
3828         if (sc->intr_res == NULL) {
3829                 device_printf(sc->dev, "Unable to allocate bus resource: "
3830                     "interrupt\n");
3831                 return ENXIO;
3832         }
3833
3834         /*
3835          * Setup MSI/legacy interrupt mask
3836          */
3837         switch (sc->hw.mac.type) {
3838         case e1000_82575:
3839                 intr_bitmax = IGB_MAX_TXRXINT_82575;
3840                 break;
3841         case e1000_82580:
3842                 intr_bitmax = IGB_MAX_TXRXINT_82580;
3843                 break;
3844         case e1000_i350:
3845                 intr_bitmax = IGB_MAX_TXRXINT_I350;
3846                 break;
3847         case e1000_82576:
3848                 intr_bitmax = IGB_MAX_TXRXINT_82576;
3849                 break;
3850         default:
3851                 intr_bitmax = IGB_MIN_TXRXINT;
3852                 break;
3853         }
3854         intr_bit = 0;
3855         for (i = 0; i < sc->tx_ring_cnt; ++i)
3856                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3857         for (i = 0; i < sc->rx_ring_cnt; ++i)
3858                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3859         sc->sts_intr_bit = 0;
3860         sc->sts_intr_mask = E1000_EICR_OTHER;
3861
3862         /* Initialize interrupt rate */
3863         sc->intr_rate = IGB_INTR_RATE;
3864 done:
3865         igb_set_ring_inuse(sc, FALSE);
3866         igb_set_intr_mask(sc);
3867         return 0;
3868 }
3869
3870 static void
3871 igb_free_intr(struct igb_softc *sc)
3872 {
3873         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3874                 if (sc->intr_res != NULL) {
3875                         bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
3876                             sc->intr_res);
3877                 }
3878                 if (sc->intr_type == PCI_INTR_TYPE_MSI)
3879                         pci_release_msi(sc->dev);
3880         } else {
3881                 igb_msix_free(sc, TRUE);
3882         }
3883 }
3884
3885 static void
3886 igb_teardown_intr(struct igb_softc *sc)
3887 {
3888         if (sc->intr_type != PCI_INTR_TYPE_MSIX)
3889                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
3890         else
3891                 igb_msix_teardown(sc, sc->msix_cnt);
3892 }
3893
3894 static void
3895 igb_msix_try_alloc(struct igb_softc *sc)
3896 {
3897         int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
3898         int i, x, error;
3899         struct igb_msix_data *msix;
3900         boolean_t aggregate, setup = FALSE;
3901
3902         /*
3903          * MSI-X must not be enable on 82575.
3904          * See 82575EB specification update
3905          */
3906         if (sc->hw.mac.type == e1000_82575)
3907                 return;
3908
3909         /* Don't enable MSI-X on VF */
3910         if (sc->vf_ifp)
3911                 return;
3912
3913         msix_enable = device_getenv_int(sc->dev, "msix.enable",
3914             igb_msix_enable);
3915         if (!msix_enable)
3916                 return;
3917
3918         msix_cnt = pci_msix_count(sc->dev);
3919 #ifdef IGB_MSIX_DEBUG
3920         msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
3921 #endif
3922         if (msix_cnt <= 1) {
3923                 /* One MSI-X model does not make sense */
3924                 return;
3925         }
3926
3927         i = 0;
3928         while ((1 << (i + 1)) <= msix_cnt)
3929                 ++i;
3930         msix_cnt2 = 1 << i;
3931
3932         if (bootverbose) {
3933                 device_printf(sc->dev, "MSI-X count %d/%d\n",
3934                     msix_cnt2, msix_cnt);
3935         }
3936
3937         KKASSERT(msix_cnt2 <= msix_cnt);
3938         if (msix_cnt == msix_cnt2) {
3939                 /* We need at least one MSI-X for link status */
3940                 msix_cnt2 >>= 1;
3941                 if (msix_cnt2 <= 1) {
3942                         /* One MSI-X for RX/TX does not make sense */
3943                         device_printf(sc->dev, "not enough MSI-X for TX/RX, "
3944                             "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
3945                         return;
3946                 }
3947                 KKASSERT(msix_cnt > msix_cnt2);
3948
3949                 if (bootverbose) {
3950                         device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
3951                             msix_cnt2, msix_cnt);
3952                 }
3953         }
3954
3955         sc->rx_ring_msix = sc->rx_ring_cnt;
3956         if (sc->rx_ring_msix > msix_cnt2)
3957                 sc->rx_ring_msix = msix_cnt2;
3958
3959         if (msix_cnt >= sc->tx_ring_cnt + sc->rx_ring_msix + 1) {
3960                 /*
3961                  * Independent TX/RX MSI-X
3962                  */
3963                 aggregate = FALSE;
3964                 if (bootverbose)
3965                         device_printf(sc->dev, "independent TX/RX MSI-X\n");
3966                 alloc_cnt = sc->tx_ring_cnt + sc->rx_ring_msix;
3967         } else {
3968                 /*
3969                  * Aggregate TX/RX MSI-X
3970                  */
3971                 aggregate = TRUE;
3972                 if (bootverbose)
3973                         device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
3974                 alloc_cnt = msix_cnt2;
3975                 if (alloc_cnt > ncpus2)
3976                         alloc_cnt = ncpus2;
3977                 if (sc->rx_ring_msix > alloc_cnt)
3978                         sc->rx_ring_msix = alloc_cnt;
3979         }
3980         ++alloc_cnt;    /* For link status */
3981
3982         if (bootverbose) {
3983                 device_printf(sc->dev, "MSI-X alloc %d, RX ring %d\n",
3984                     alloc_cnt, sc->rx_ring_msix);
3985         }
3986
3987         sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
3988         sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
3989             &sc->msix_mem_rid, RF_ACTIVE);
3990         if (sc->msix_mem_res == NULL) {
3991                 device_printf(sc->dev, "Unable to map MSI-X table\n");
3992                 return;
3993         }
3994
3995         sc->msix_cnt = alloc_cnt;
3996         sc->msix_data = kmalloc(sizeof(struct igb_msix_data) * sc->msix_cnt,
3997             M_DEVBUF, M_WAITOK | M_ZERO);
3998         for (x = 0; x < sc->msix_cnt; ++x) {
3999                 msix = &sc->msix_data[x];
4000
4001                 lwkt_serialize_init(&msix->msix_serialize0);
4002                 msix->msix_sc = sc;
4003                 msix->msix_rid = -1;
4004                 msix->msix_vector = x;
4005                 msix->msix_mask = 1 << msix->msix_vector;
4006                 msix->msix_rate = IGB_INTR_RATE;
4007         }
4008
4009         x = 0;
4010         if (!aggregate) {
4011                 int offset, offset_def;
4012
4013                 if (sc->rx_ring_msix == ncpus2) {
4014                         offset = 0;
4015                 } else {
4016                         offset_def = (sc->rx_ring_msix *
4017                             device_get_unit(sc->dev)) % ncpus2;
4018
4019                         offset = device_getenv_int(sc->dev,
4020                             "msix.rxoff", offset_def);
4021                         if (offset >= ncpus2 ||
4022                             offset % sc->rx_ring_msix != 0) {
4023                                 device_printf(sc->dev,
4024                                     "invalid msix.rxoff %d, use %d\n",
4025                                     offset, offset_def);
4026                                 offset = offset_def;
4027                         }
4028                 }
4029
4030                 /* RX rings */
4031                 for (i = 0; i < sc->rx_ring_msix; ++i) {
4032                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
4033
4034                         KKASSERT(x < sc->msix_cnt);
4035                         msix = &sc->msix_data[x++];
4036                         rxr->rx_intr_bit = msix->msix_vector;
4037                         rxr->rx_intr_mask = msix->msix_mask;
4038
4039                         msix->msix_serialize = &rxr->rx_serialize;
4040                         msix->msix_func = igb_msix_rx;
4041                         msix->msix_arg = rxr;
4042                         msix->msix_cpuid = i + offset;
4043                         KKASSERT(msix->msix_cpuid < ncpus2);
4044                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4045                             "%s rx%d", device_get_nameunit(sc->dev), i);
4046                         msix->msix_rate = IGB_MSIX_RX_RATE;
4047                         ksnprintf(msix->msix_rate_desc,
4048                             sizeof(msix->msix_rate_desc),
4049                             "RX%d interrupt rate", i);
4050                 }
4051
4052                 offset_def = device_get_unit(sc->dev) % ncpus2;
4053                 offset = device_getenv_int(sc->dev, "msix.txoff", offset_def);
4054                 if (offset >= ncpus2) {
4055                         device_printf(sc->dev, "invalid msix.txoff %d, "
4056                             "use %d\n", offset, offset_def);
4057                         offset = offset_def;
4058                 }
4059
4060                 /* TX rings */
4061                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4062                         struct igb_tx_ring *txr = &sc->tx_rings[i];
4063
4064                         KKASSERT(x < sc->msix_cnt);
4065                         msix = &sc->msix_data[x++];
4066                         txr->tx_intr_bit = msix->msix_vector;
4067                         txr->tx_intr_mask = msix->msix_mask;
4068
4069                         msix->msix_serialize = &txr->tx_serialize;
4070                         msix->msix_func = igb_msix_tx;
4071                         msix->msix_arg = txr;
4072                         msix->msix_cpuid = i + offset;
4073                         sc->msix_tx_cpuid = msix->msix_cpuid; /* XXX */
4074                         KKASSERT(msix->msix_cpuid < ncpus2);
4075                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4076                             "%s tx%d", device_get_nameunit(sc->dev), i);
4077                         msix->msix_rate = IGB_MSIX_TX_RATE;
4078                         ksnprintf(msix->msix_rate_desc,
4079                             sizeof(msix->msix_rate_desc),
4080                             "TX%d interrupt rate", i);
4081                 }
4082         } else {
4083                 /* TODO */
4084                 error = EOPNOTSUPP;
4085                 goto back;
4086         }
4087
4088         /*
4089          * Link status
4090          */
4091         KKASSERT(x < sc->msix_cnt);
4092         msix = &sc->msix_data[x++];
4093         sc->sts_intr_bit = msix->msix_vector;
4094         sc->sts_intr_mask = msix->msix_mask;
4095
4096         msix->msix_serialize = &sc->main_serialize;
4097         msix->msix_func = igb_msix_status;
4098         msix->msix_arg = sc;
4099         msix->msix_cpuid = 0; /* TODO tunable */
4100         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4101             device_get_nameunit(sc->dev));
4102         ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4103             "status interrupt rate");
4104
4105         KKASSERT(x == sc->msix_cnt);
4106
4107         error = pci_setup_msix(sc->dev);
4108         if (error) {
4109                 device_printf(sc->dev, "Setup MSI-X failed\n");
4110                 goto back;
4111         }
4112         setup = TRUE;
4113
4114         for (i = 0; i < sc->msix_cnt; ++i) {
4115                 msix = &sc->msix_data[i];
4116
4117                 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4118                     &msix->msix_rid, msix->msix_cpuid);
4119                 if (error) {
4120                         device_printf(sc->dev,
4121                             "Unable to allocate MSI-X %d on cpu%d\n",
4122                             msix->msix_vector, msix->msix_cpuid);
4123                         goto back;
4124                 }
4125
4126                 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4127                     &msix->msix_rid, RF_ACTIVE);
4128                 if (msix->msix_res == NULL) {
4129                         device_printf(sc->dev,
4130                             "Unable to allocate MSI-X %d resource\n",
4131                             msix->msix_vector);
4132                         error = ENOMEM;
4133                         goto back;
4134                 }
4135         }
4136
4137         pci_enable_msix(sc->dev);
4138         sc->intr_type = PCI_INTR_TYPE_MSIX;
4139 back:
4140         if (error)
4141                 igb_msix_free(sc, setup);
4142 }
4143
4144 static void
4145 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4146 {
4147         int i;
4148
4149         KKASSERT(sc->msix_cnt > 1);
4150
4151         for (i = 0; i < sc->msix_cnt; ++i) {
4152                 struct igb_msix_data *msix = &sc->msix_data[i];
4153
4154                 if (msix->msix_res != NULL) {
4155                         bus_release_resource(sc->dev, SYS_RES_IRQ,
4156                             msix->msix_rid, msix->msix_res);
4157                 }
4158                 if (msix->msix_rid >= 0)
4159                         pci_release_msix_vector(sc->dev, msix->msix_rid);
4160         }
4161         if (setup)
4162                 pci_teardown_msix(sc->dev);
4163
4164         sc->msix_cnt = 0;
4165         kfree(sc->msix_data, M_DEVBUF);
4166         sc->msix_data = NULL;
4167 }
4168
4169 static int
4170 igb_msix_setup(struct igb_softc *sc)
4171 {
4172         struct ifnet *ifp = &sc->arpcom.ac_if;
4173         int i;
4174
4175         for (i = 0; i < sc->msix_cnt; ++i) {
4176                 struct igb_msix_data *msix = &sc->msix_data[i];
4177                 int error;
4178
4179                 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4180                     INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4181                     &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4182                 if (error) {
4183                         device_printf(sc->dev, "could not set up %s "
4184                             "interrupt handler.\n", msix->msix_desc);
4185                         igb_msix_teardown(sc, i);
4186                         return error;
4187                 }
4188         }
4189         ifp->if_cpuid = sc->msix_tx_cpuid;
4190
4191         return 0;
4192 }
4193
4194 static void
4195 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4196 {
4197         int i;
4198
4199         for (i = 0; i < msix_cnt; ++i) {
4200                 struct igb_msix_data *msix = &sc->msix_data[i];
4201
4202                 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4203         }
4204 }
4205
4206 static void
4207 igb_msix_rx(void *arg)
4208 {
4209         struct igb_rx_ring *rxr = arg;
4210
4211         ASSERT_SERIALIZED(&rxr->rx_serialize);
4212         igb_rxeof(rxr, -1);
4213
4214         E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4215 }
4216
4217 static void
4218 igb_msix_tx(void *arg)
4219 {
4220         struct igb_tx_ring *txr = arg;
4221         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
4222
4223         ASSERT_SERIALIZED(&txr->tx_serialize);
4224
4225         igb_txeof(txr);
4226         if (!ifq_is_empty(&ifp->if_snd))
4227                 if_devstart(ifp);
4228
4229         E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4230 }
4231
4232 static void
4233 igb_msix_status(void *arg)
4234 {
4235         struct igb_softc *sc = arg;
4236         uint32_t icr;
4237
4238         ASSERT_SERIALIZED(&sc->main_serialize);
4239
4240         icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4241         if (icr & E1000_ICR_LSC) {
4242                 sc->hw.mac.get_link_status = 1;
4243                 igb_update_link_status(sc);
4244         }
4245
4246         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4247 }
4248
4249 static void
4250 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4251 {
4252         if (!IGB_ENABLE_HWRSS(sc))
4253                 return;
4254
4255         if (sc->intr_type != PCI_INTR_TYPE_MSIX || polling)
4256                 sc->rx_ring_inuse = IGB_MIN_RING_RSS;
4257         else
4258                 sc->rx_ring_inuse = sc->rx_ring_msix;
4259         if (bootverbose) {
4260                 device_printf(sc->dev, "RX rings %d/%d\n",
4261                     sc->rx_ring_inuse, sc->rx_ring_cnt);
4262         }
4263 }