2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
30 #include "opt_polling.h"
33 #include <sys/param.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
37 #include <sys/interrupt.h>
38 #include <sys/malloc.h>
41 #include <sys/serialize.h>
42 #include <sys/serialize2.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
47 #include <net/ethernet.h>
50 #include <net/if_arp.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/ifq_var.h>
54 #include <net/toeplitz.h>
55 #include <net/toeplitz2.h>
56 #include <net/vlan/if_vlan_var.h>
57 #include <net/vlan/if_vlan_ether.h>
59 #include <netinet/in.h>
61 #include <dev/netif/mii_layer/miivar.h>
62 #include <dev/netif/mii_layer/jmphyreg.h>
64 #include <bus/pci/pcireg.h>
65 #include <bus/pci/pcivar.h>
66 #include <bus/pci/pcidevs.h>
68 #include <dev/netif/jme/if_jmereg.h>
69 #include <dev/netif/jme/if_jmevar.h>
71 #include "miibus_if.h"
73 /* Define the following to disable printing Rx errors. */
74 #undef JME_SHOW_ERRORS
76 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
79 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
81 if ((sc)->jme_rss_debug >= (lvl)) \
82 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
84 #else /* !JME_RSS_DEBUG */
85 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
86 #endif /* JME_RSS_DEBUG */
88 static int jme_probe(device_t);
89 static int jme_attach(device_t);
90 static int jme_detach(device_t);
91 static int jme_shutdown(device_t);
92 static int jme_suspend(device_t);
93 static int jme_resume(device_t);
95 static int jme_miibus_readreg(device_t, int, int);
96 static int jme_miibus_writereg(device_t, int, int, int);
97 static void jme_miibus_statchg(device_t);
99 static void jme_init(void *);
100 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
101 static void jme_start(struct ifnet *);
102 static void jme_watchdog(struct ifnet *);
103 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
104 static int jme_mediachange(struct ifnet *);
105 #ifdef DEVICE_POLLING
106 static void jme_poll(struct ifnet *, enum poll_cmd, int);
108 static void jme_serialize(struct ifnet *, enum ifnet_serialize);
109 static void jme_deserialize(struct ifnet *, enum ifnet_serialize);
110 static int jme_tryserialize(struct ifnet *, enum ifnet_serialize);
112 static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
116 static void jme_intr(void *);
117 static void jme_msix_tx(void *);
118 static void jme_msix_rx(void *);
119 static void jme_txeof(struct jme_softc *);
120 static void jme_rxeof(struct jme_rxdata *, int);
121 static void jme_rx_intr(struct jme_softc *, uint32_t);
123 static int jme_msix_setup(device_t);
124 static void jme_msix_teardown(device_t, int);
125 static int jme_intr_setup(device_t);
126 static void jme_intr_teardown(device_t);
127 static void jme_msix_try_alloc(device_t);
128 static void jme_msix_free(device_t);
129 static int jme_intr_alloc(device_t);
130 static void jme_intr_free(device_t);
131 static int jme_dma_alloc(struct jme_softc *);
132 static void jme_dma_free(struct jme_softc *);
133 static int jme_init_rx_ring(struct jme_rxdata *);
134 static void jme_init_tx_ring(struct jme_softc *);
135 static void jme_init_ssb(struct jme_softc *);
136 static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
137 static int jme_encap(struct jme_softc *, struct mbuf **);
138 static void jme_rxpkt(struct jme_rxdata *);
139 static int jme_rxring_dma_alloc(struct jme_rxdata *);
140 static int jme_rxbuf_dma_alloc(struct jme_rxdata *);
142 static void jme_tick(void *);
143 static void jme_stop(struct jme_softc *);
144 static void jme_reset(struct jme_softc *);
145 static void jme_set_msinum(struct jme_softc *);
146 static void jme_set_vlan(struct jme_softc *);
147 static void jme_set_filter(struct jme_softc *);
148 static void jme_stop_tx(struct jme_softc *);
149 static void jme_stop_rx(struct jme_softc *);
150 static void jme_mac_config(struct jme_softc *);
151 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
152 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
153 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
155 static void jme_setwol(struct jme_softc *);
156 static void jme_setlinkspeed(struct jme_softc *);
158 static void jme_set_tx_coal(struct jme_softc *);
159 static void jme_set_rx_coal(struct jme_softc *);
160 static void jme_enable_rss(struct jme_softc *);
161 static void jme_disable_rss(struct jme_softc *);
163 static void jme_sysctl_node(struct jme_softc *);
164 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
165 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
166 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
167 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
170 * Devices supported by this driver.
172 static const struct jme_dev {
173 uint16_t jme_vendorid;
174 uint16_t jme_deviceid;
176 const char *jme_name;
178 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
180 "JMicron Inc, JMC250 Gigabit Ethernet" },
181 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
183 "JMicron Inc, JMC260 Fast Ethernet" },
187 static device_method_t jme_methods[] = {
188 /* Device interface. */
189 DEVMETHOD(device_probe, jme_probe),
190 DEVMETHOD(device_attach, jme_attach),
191 DEVMETHOD(device_detach, jme_detach),
192 DEVMETHOD(device_shutdown, jme_shutdown),
193 DEVMETHOD(device_suspend, jme_suspend),
194 DEVMETHOD(device_resume, jme_resume),
197 DEVMETHOD(bus_print_child, bus_generic_print_child),
198 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
201 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
202 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
203 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
208 static driver_t jme_driver = {
211 sizeof(struct jme_softc)
214 static devclass_t jme_devclass;
216 DECLARE_DUMMY_MODULE(if_jme);
217 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
218 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
219 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
221 static const struct {
225 } jme_rx_status[JME_NRXRING_MAX] = {
226 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
227 INTR_RXQ0_DESC_EMPTY },
228 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
229 INTR_RXQ1_DESC_EMPTY },
230 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
231 INTR_RXQ2_DESC_EMPTY },
232 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
233 INTR_RXQ3_DESC_EMPTY }
236 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
237 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
238 static int jme_rx_ring_count = 1;
239 static int jme_msi_enable = 1;
240 static int jme_msix_enable = 1;
242 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
243 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
244 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
245 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
246 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
249 * Read a PHY register on the MII of the JMC250.
252 jme_miibus_readreg(device_t dev, int phy, int reg)
254 struct jme_softc *sc = device_get_softc(dev);
258 /* For FPGA version, PHY address 0 should be ignored. */
259 if (sc->jme_caps & JME_CAP_FPGA) {
263 if (sc->jme_phyaddr != phy)
267 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
268 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
270 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
272 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
276 device_printf(sc->jme_dev, "phy read timeout: "
277 "phy %d, reg %d\n", phy, reg);
281 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
285 * Write a PHY register on the MII of the JMC250.
288 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
290 struct jme_softc *sc = device_get_softc(dev);
293 /* For FPGA version, PHY address 0 should be ignored. */
294 if (sc->jme_caps & JME_CAP_FPGA) {
298 if (sc->jme_phyaddr != phy)
302 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
303 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
304 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
306 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
308 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
312 device_printf(sc->jme_dev, "phy write timeout: "
313 "phy %d, reg %d\n", phy, reg);
320 * Callback from MII layer when media changes.
323 jme_miibus_statchg(device_t dev)
325 struct jme_softc *sc = device_get_softc(dev);
326 struct ifnet *ifp = &sc->arpcom.ac_if;
327 struct mii_data *mii;
328 struct jme_txdesc *txd;
332 ASSERT_IFNET_SERIALIZED_ALL(ifp);
334 if ((ifp->if_flags & IFF_RUNNING) == 0)
337 mii = device_get_softc(sc->jme_miibus);
339 sc->jme_flags &= ~JME_FLAG_LINK;
340 if ((mii->mii_media_status & IFM_AVALID) != 0) {
341 switch (IFM_SUBTYPE(mii->mii_media_active)) {
344 sc->jme_flags |= JME_FLAG_LINK;
347 if (sc->jme_caps & JME_CAP_FASTETH)
349 sc->jme_flags |= JME_FLAG_LINK;
357 * Disabling Rx/Tx MACs have a side-effect of resetting
358 * JME_TXNDA/JME_RXNDA register to the first address of
359 * Tx/Rx descriptor address. So driver should reset its
360 * internal procucer/consumer pointer and reclaim any
361 * allocated resources. Note, just saving the value of
362 * JME_TXNDA and JME_RXNDA registers before stopping MAC
363 * and restoring JME_TXNDA/JME_RXNDA register is not
364 * sufficient to make sure correct MAC state because
365 * stopping MAC operation can take a while and hardware
366 * might have updated JME_TXNDA/JME_RXNDA registers
367 * during the stop operation.
370 /* Disable interrupts */
371 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
374 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
376 callout_stop(&sc->jme_tick_ch);
378 /* Stop receiver/transmitter. */
382 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
383 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
385 jme_rxeof(rdata, -1);
386 if (rdata->jme_rxhead != NULL)
387 m_freem(rdata->jme_rxhead);
388 JME_RXCHAIN_RESET(rdata);
391 * Reuse configured Rx descriptors and reset
392 * procuder/consumer index.
394 rdata->jme_rx_cons = 0;
398 if (sc->jme_cdata.jme_tx_cnt != 0) {
399 /* Remove queued packets for transmit. */
400 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
401 txd = &sc->jme_cdata.jme_txdesc[i];
402 if (txd->tx_m != NULL) {
404 sc->jme_cdata.jme_tx_tag,
413 jme_init_tx_ring(sc);
415 /* Initialize shadow status block. */
418 /* Program MAC with resolved speed/duplex/flow-control. */
419 if (sc->jme_flags & JME_FLAG_LINK) {
422 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
424 /* Set Tx ring address to the hardware. */
425 paddr = sc->jme_cdata.jme_tx_ring_paddr;
426 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
427 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
429 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
430 CSR_WRITE_4(sc, JME_RXCSR,
431 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
433 /* Set Rx ring address to the hardware. */
434 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
435 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
436 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
439 /* Restart receiver/transmitter. */
440 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
442 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
445 ifp->if_flags |= IFF_RUNNING;
446 ifp->if_flags &= ~IFF_OACTIVE;
447 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
449 #ifdef DEVICE_POLLING
450 if (!(ifp->if_flags & IFF_POLLING))
452 /* Reenable interrupts. */
453 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
457 * Get the current interface media status.
460 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
462 struct jme_softc *sc = ifp->if_softc;
463 struct mii_data *mii = device_get_softc(sc->jme_miibus);
465 ASSERT_IFNET_SERIALIZED_ALL(ifp);
468 ifmr->ifm_status = mii->mii_media_status;
469 ifmr->ifm_active = mii->mii_media_active;
473 * Set hardware to newly-selected media.
476 jme_mediachange(struct ifnet *ifp)
478 struct jme_softc *sc = ifp->if_softc;
479 struct mii_data *mii = device_get_softc(sc->jme_miibus);
482 ASSERT_IFNET_SERIALIZED_ALL(ifp);
484 if (mii->mii_instance != 0) {
485 struct mii_softc *miisc;
487 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
488 mii_phy_reset(miisc);
490 error = mii_mediachg(mii);
496 jme_probe(device_t dev)
498 const struct jme_dev *sp;
501 vid = pci_get_vendor(dev);
502 did = pci_get_device(dev);
503 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
504 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
505 struct jme_softc *sc = device_get_softc(dev);
507 sc->jme_caps = sp->jme_caps;
508 device_set_desc(dev, sp->jme_name);
516 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
522 for (i = JME_TIMEOUT; i > 0; i--) {
523 reg = CSR_READ_4(sc, JME_SMBCSR);
524 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
530 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
534 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
535 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
536 for (i = JME_TIMEOUT; i > 0; i--) {
538 reg = CSR_READ_4(sc, JME_SMBINTF);
539 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
544 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
548 reg = CSR_READ_4(sc, JME_SMBINTF);
549 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
555 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
557 uint8_t fup, reg, val;
562 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
563 fup != JME_EEPROM_SIG0)
565 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
566 fup != JME_EEPROM_SIG1)
570 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
572 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
573 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
574 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
576 if (reg >= JME_PAR0 &&
577 reg < JME_PAR0 + ETHER_ADDR_LEN) {
578 if (jme_eeprom_read_byte(sc, offset + 2,
581 eaddr[reg - JME_PAR0] = val;
585 /* Check for the end of EEPROM descriptor. */
586 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
588 /* Try next eeprom descriptor. */
589 offset += JME_EEPROM_DESC_BYTES;
590 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
592 if (match == ETHER_ADDR_LEN)
599 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
603 /* Read station address. */
604 par0 = CSR_READ_4(sc, JME_PAR0);
605 par1 = CSR_READ_4(sc, JME_PAR1);
607 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
608 device_printf(sc->jme_dev,
609 "generating fake ethernet address.\n");
610 par0 = karc4random();
611 /* Set OUI to JMicron. */
615 eaddr[3] = (par0 >> 16) & 0xff;
616 eaddr[4] = (par0 >> 8) & 0xff;
617 eaddr[5] = par0 & 0xff;
619 eaddr[0] = (par0 >> 0) & 0xFF;
620 eaddr[1] = (par0 >> 8) & 0xFF;
621 eaddr[2] = (par0 >> 16) & 0xFF;
622 eaddr[3] = (par0 >> 24) & 0xFF;
623 eaddr[4] = (par1 >> 0) & 0xFF;
624 eaddr[5] = (par1 >> 8) & 0xFF;
629 jme_attach(device_t dev)
631 struct jme_softc *sc = device_get_softc(dev);
632 struct ifnet *ifp = &sc->arpcom.ac_if;
635 uint8_t pcie_ptr, rev;
636 int error = 0, i, j, rx_desc_cnt;
637 uint8_t eaddr[ETHER_ADDR_LEN];
639 lwkt_serialize_init(&sc->jme_serialize);
640 lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
641 for (i = 0; i < JME_NRXRING_MAX; ++i) {
643 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
646 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
648 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
649 if (rx_desc_cnt > JME_NDESC_MAX)
650 rx_desc_cnt = JME_NDESC_MAX;
652 sc->jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
654 sc->jme_tx_desc_cnt = roundup(sc->jme_tx_desc_cnt, JME_NDESC_ALIGN);
655 if (sc->jme_tx_desc_cnt > JME_NDESC_MAX)
656 sc->jme_tx_desc_cnt = JME_NDESC_MAX;
661 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
663 sc->jme_cdata.jme_rx_ring_cnt =
664 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
667 sc->jme_serialize_arr[i++] = &sc->jme_serialize;
668 sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
669 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
670 sc->jme_serialize_arr[i++] =
671 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
673 KKASSERT(i <= JME_NSERIALIZE);
674 sc->jme_serialize_cnt = i;
676 sc->jme_cdata.jme_sc = sc;
677 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
678 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
681 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
682 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
683 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
684 rdata->jme_rx_idx = i;
685 rdata->jme_rx_desc_cnt = rx_desc_cnt;
689 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
691 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
693 callout_init(&sc->jme_tick_ch);
696 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
699 irq = pci_read_config(dev, PCIR_INTLINE, 4);
700 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
702 device_printf(dev, "chip is in D%d power mode "
703 "-- setting to D0\n", pci_get_powerstate(dev));
705 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
707 pci_write_config(dev, PCIR_INTLINE, irq, 4);
708 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
710 #endif /* !BURN_BRIDGE */
712 /* Enable bus mastering */
713 pci_enable_busmaster(dev);
718 * JMC250 supports both memory mapped and I/O register space
719 * access. Because I/O register access should use different
720 * BARs to access registers it's waste of time to use I/O
721 * register spce access. JMC250 uses 16K to map entire memory
724 sc->jme_mem_rid = JME_PCIR_BAR;
725 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
726 &sc->jme_mem_rid, RF_ACTIVE);
727 if (sc->jme_mem_res == NULL) {
728 device_printf(dev, "can't allocate IO memory\n");
731 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
732 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
737 error = jme_intr_alloc(dev);
744 reg = CSR_READ_4(sc, JME_CHIPMODE);
745 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
747 sc->jme_caps |= JME_CAP_FPGA;
749 device_printf(dev, "FPGA revision: 0x%04x\n",
750 (reg & CHIPMODE_FPGA_REV_MASK) >>
751 CHIPMODE_FPGA_REV_SHIFT);
755 /* NOTE: FM revision is put in the upper 4 bits */
756 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
757 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
759 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
761 did = pci_get_device(dev);
763 case PCI_PRODUCT_JMICRON_JMC250:
764 if (rev == JME_REV1_A2)
765 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
768 case PCI_PRODUCT_JMICRON_JMC260:
770 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
774 panic("unknown device id 0x%04x\n", did);
776 if (rev >= JME_REV2) {
777 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
778 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
779 GHC_TXMAC_CLKSRC_1000;
782 /* Reset the ethernet controller. */
785 /* Map MSI/MSI-X vectors */
788 /* Get station address. */
789 reg = CSR_READ_4(sc, JME_SMBCSR);
790 if (reg & SMBCSR_EEPROM_PRESENT)
791 error = jme_eeprom_macaddr(sc, eaddr);
792 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
793 if (error != 0 && (bootverbose)) {
794 device_printf(dev, "ethernet hardware address "
795 "not found in EEPROM.\n");
797 jme_reg_macaddr(sc, eaddr);
802 * Integrated JR0211 has fixed PHY address whereas FPGA version
803 * requires PHY probing to get correct PHY address.
805 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
806 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
807 GPREG0_PHY_ADDR_MASK;
809 device_printf(dev, "PHY is at address %d.\n",
816 /* Set max allowable DMA size. */
817 pcie_ptr = pci_get_pciecap_ptr(dev);
821 sc->jme_caps |= JME_CAP_PCIE;
822 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
824 device_printf(dev, "Read request size : %d bytes.\n",
825 128 << ((ctrl >> 12) & 0x07));
826 device_printf(dev, "TLP payload size : %d bytes.\n",
827 128 << ((ctrl >> 5) & 0x07));
829 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
830 case PCIEM_DEVCTL_MAX_READRQ_128:
831 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
833 case PCIEM_DEVCTL_MAX_READRQ_256:
834 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
837 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
840 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
842 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
843 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
847 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
848 sc->jme_caps |= JME_CAP_PMCAP;
856 /* Allocate DMA stuffs */
857 error = jme_dma_alloc(sc);
862 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
863 ifp->if_init = jme_init;
864 ifp->if_ioctl = jme_ioctl;
865 ifp->if_start = jme_start;
866 #ifdef DEVICE_POLLING
867 ifp->if_poll = jme_poll;
869 ifp->if_watchdog = jme_watchdog;
870 ifp->if_serialize = jme_serialize;
871 ifp->if_deserialize = jme_deserialize;
872 ifp->if_tryserialize = jme_tryserialize;
874 ifp->if_serialize_assert = jme_serialize_assert;
876 ifq_set_maxlen(&ifp->if_snd, sc->jme_tx_desc_cnt - JME_TXD_RSVD);
877 ifq_set_ready(&ifp->if_snd);
879 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
880 ifp->if_capabilities = IFCAP_HWCSUM |
882 IFCAP_VLAN_HWTAGGING;
883 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
884 ifp->if_capabilities |= IFCAP_RSS;
885 ifp->if_capenable = ifp->if_capabilities;
888 * Disable TXCSUM by default to improve bulk data
889 * transmit performance (+20Mbps improvement).
891 ifp->if_capenable &= ~IFCAP_TXCSUM;
893 if (ifp->if_capenable & IFCAP_TXCSUM)
894 ifp->if_hwassist = JME_CSUM_FEATURES;
896 /* Set up MII bus. */
897 error = mii_phy_probe(dev, &sc->jme_miibus,
898 jme_mediachange, jme_mediastatus);
900 device_printf(dev, "no PHY found!\n");
905 * Save PHYADDR for FPGA mode PHY.
907 if (sc->jme_caps & JME_CAP_FPGA) {
908 struct mii_data *mii = device_get_softc(sc->jme_miibus);
910 if (mii->mii_instance != 0) {
911 struct mii_softc *miisc;
913 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
914 if (miisc->mii_phy != 0) {
915 sc->jme_phyaddr = miisc->mii_phy;
919 if (sc->jme_phyaddr != 0) {
920 device_printf(sc->jme_dev,
921 "FPGA PHY is at %d\n", sc->jme_phyaddr);
923 jme_miibus_writereg(dev, sc->jme_phyaddr,
924 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
926 /* XXX should we clear JME_WA_EXTFIFO */
931 ether_ifattach(ifp, eaddr, NULL);
933 /* Tell the upper layer(s) we support long frames. */
934 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
936 error = jme_intr_setup(dev);
949 jme_detach(device_t dev)
951 struct jme_softc *sc = device_get_softc(dev);
953 if (device_is_attached(dev)) {
954 struct ifnet *ifp = &sc->arpcom.ac_if;
956 ifnet_serialize_all(ifp);
958 jme_intr_teardown(dev);
959 ifnet_deserialize_all(ifp);
964 if (sc->jme_sysctl_tree != NULL)
965 sysctl_ctx_free(&sc->jme_sysctl_ctx);
967 if (sc->jme_miibus != NULL)
968 device_delete_child(dev, sc->jme_miibus);
969 bus_generic_detach(dev);
973 if (sc->jme_mem_res != NULL) {
974 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
984 jme_sysctl_node(struct jme_softc *sc)
991 sysctl_ctx_init(&sc->jme_sysctl_ctx);
992 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
993 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
994 device_get_nameunit(sc->jme_dev),
996 if (sc->jme_sysctl_tree == NULL) {
997 device_printf(sc->jme_dev, "can't add sysctl node\n");
1001 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1002 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1003 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1004 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1006 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1007 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1008 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1009 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1011 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1012 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1013 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1014 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1016 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1017 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1018 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1019 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1021 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1022 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1023 "rx_desc_count", CTLFLAG_RD,
1024 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
1025 0, "RX desc count");
1026 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1027 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1028 "tx_desc_count", CTLFLAG_RD, &sc->jme_tx_desc_cnt,
1029 0, "TX desc count");
1030 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1031 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1032 "rx_ring_count", CTLFLAG_RD,
1033 &sc->jme_cdata.jme_rx_ring_cnt,
1034 0, "RX ring count");
1035 #ifdef JME_RSS_DEBUG
1036 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1037 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1038 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1039 0, "RSS debug level");
1040 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1041 char rx_ring_pkt[32];
1043 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
1044 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1045 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1046 rx_ring_pkt, CTLFLAG_RW,
1047 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
1052 * Set default coalesce valves
1054 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1055 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1056 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1057 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1060 * Adjust coalesce valves, in case that the number of TX/RX
1061 * descs are set to small values by users.
1063 * NOTE: coal_max will not be zero, since number of descs
1064 * must aligned by JME_NDESC_ALIGN (16 currently)
1066 coal_max = sc->jme_tx_desc_cnt / 6;
1067 if (coal_max < sc->jme_tx_coal_pkt)
1068 sc->jme_tx_coal_pkt = coal_max;
1070 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 4;
1071 if (coal_max < sc->jme_rx_coal_pkt)
1072 sc->jme_rx_coal_pkt = coal_max;
1076 jme_dma_alloc(struct jme_softc *sc)
1078 struct jme_txdesc *txd;
1082 sc->jme_cdata.jme_txdesc =
1083 kmalloc(sc->jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1084 M_DEVBUF, M_WAITOK | M_ZERO);
1085 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1086 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1089 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1090 M_DEVBUF, M_WAITOK | M_ZERO);
1093 /* Create parent ring tag. */
1094 error = bus_dma_tag_create(NULL,/* parent */
1095 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1096 sc->jme_lowaddr, /* lowaddr */
1097 BUS_SPACE_MAXADDR, /* highaddr */
1098 NULL, NULL, /* filter, filterarg */
1099 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1101 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1103 &sc->jme_cdata.jme_ring_tag);
1105 device_printf(sc->jme_dev,
1106 "could not create parent ring DMA tag.\n");
1111 * Create DMA stuffs for TX ring
1113 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1114 JME_TX_RING_ALIGN, 0,
1115 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1116 JME_TX_RING_SIZE(sc),
1117 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1119 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1122 sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1123 sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1124 sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1125 sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1128 * Create DMA stuffs for RX rings
1130 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1131 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1136 /* Create parent buffer tag. */
1137 error = bus_dma_tag_create(NULL,/* parent */
1138 1, 0, /* algnmnt, boundary */
1139 sc->jme_lowaddr, /* lowaddr */
1140 BUS_SPACE_MAXADDR, /* highaddr */
1141 NULL, NULL, /* filter, filterarg */
1142 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1144 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1146 &sc->jme_cdata.jme_buffer_tag);
1148 device_printf(sc->jme_dev,
1149 "could not create parent buffer DMA tag.\n");
1154 * Create DMA stuffs for shadow status block
1156 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1157 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1158 JME_SSB_SIZE, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1160 device_printf(sc->jme_dev,
1161 "could not create shadow status block.\n");
1164 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1165 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1166 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1167 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1170 * Create DMA stuffs for TX buffers
1173 /* Create tag for Tx buffers. */
1174 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1175 1, 0, /* algnmnt, boundary */
1176 BUS_SPACE_MAXADDR, /* lowaddr */
1177 BUS_SPACE_MAXADDR, /* highaddr */
1178 NULL, NULL, /* filter, filterarg */
1179 JME_JUMBO_FRAMELEN, /* maxsize */
1180 JME_MAXTXSEGS, /* nsegments */
1181 JME_MAXSEGSIZE, /* maxsegsize */
1182 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1183 &sc->jme_cdata.jme_tx_tag);
1185 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1189 /* Create DMA maps for Tx buffers. */
1190 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1191 txd = &sc->jme_cdata.jme_txdesc[i];
1192 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1193 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1198 device_printf(sc->jme_dev,
1199 "could not create %dth Tx dmamap.\n", i);
1201 for (j = 0; j < i; ++j) {
1202 txd = &sc->jme_cdata.jme_txdesc[j];
1203 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1206 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1207 sc->jme_cdata.jme_tx_tag = NULL;
1213 * Create DMA stuffs for RX buffers
1215 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1216 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1224 jme_dma_free(struct jme_softc *sc)
1226 struct jme_txdesc *txd;
1227 struct jme_rxdesc *rxd;
1228 struct jme_rxdata *rdata;
1232 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1233 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1234 sc->jme_cdata.jme_tx_ring_map);
1235 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1236 sc->jme_cdata.jme_tx_ring,
1237 sc->jme_cdata.jme_tx_ring_map);
1238 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1239 sc->jme_cdata.jme_tx_ring_tag = NULL;
1243 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1244 rdata = &sc->jme_cdata.jme_rx_data[r];
1245 if (rdata->jme_rx_ring_tag != NULL) {
1246 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1247 rdata->jme_rx_ring_map);
1248 bus_dmamem_free(rdata->jme_rx_ring_tag,
1250 rdata->jme_rx_ring_map);
1251 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1252 rdata->jme_rx_ring_tag = NULL;
1257 if (sc->jme_cdata.jme_tx_tag != NULL) {
1258 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1259 txd = &sc->jme_cdata.jme_txdesc[i];
1260 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1263 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1264 sc->jme_cdata.jme_tx_tag = NULL;
1268 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1269 rdata = &sc->jme_cdata.jme_rx_data[r];
1270 if (rdata->jme_rx_tag != NULL) {
1271 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
1272 rxd = &rdata->jme_rxdesc[i];
1273 bus_dmamap_destroy(rdata->jme_rx_tag,
1276 bus_dmamap_destroy(rdata->jme_rx_tag,
1277 rdata->jme_rx_sparemap);
1278 bus_dma_tag_destroy(rdata->jme_rx_tag);
1279 rdata->jme_rx_tag = NULL;
1283 /* Shadow status block. */
1284 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1285 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1286 sc->jme_cdata.jme_ssb_map);
1287 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1288 sc->jme_cdata.jme_ssb_block,
1289 sc->jme_cdata.jme_ssb_map);
1290 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1291 sc->jme_cdata.jme_ssb_tag = NULL;
1294 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1295 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1296 sc->jme_cdata.jme_buffer_tag = NULL;
1298 if (sc->jme_cdata.jme_ring_tag != NULL) {
1299 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1300 sc->jme_cdata.jme_ring_tag = NULL;
1303 if (sc->jme_cdata.jme_txdesc != NULL) {
1304 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1305 sc->jme_cdata.jme_txdesc = NULL;
1307 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1308 rdata = &sc->jme_cdata.jme_rx_data[r];
1309 if (rdata->jme_rxdesc != NULL) {
1310 kfree(rdata->jme_rxdesc, M_DEVBUF);
1311 rdata->jme_rxdesc = NULL;
1317 * Make sure the interface is stopped at reboot time.
1320 jme_shutdown(device_t dev)
1322 return jme_suspend(dev);
1327 * Unlike other ethernet controllers, JMC250 requires
1328 * explicit resetting link speed to 10/100Mbps as gigabit
1329 * link will cunsume more power than 375mA.
1330 * Note, we reset the link speed to 10/100Mbps with
1331 * auto-negotiation but we don't know whether that operation
1332 * would succeed or not as we have no control after powering
1333 * off. If the renegotiation fail WOL may not work. Running
1334 * at 1Gbps draws more power than 375mA at 3.3V which is
1335 * specified in PCI specification and that would result in
1336 * complete shutdowning power to ethernet controller.
1339 * Save current negotiated media speed/duplex/flow-control
1340 * to softc and restore the same link again after resuming.
1341 * PHY handling such as power down/resetting to 100Mbps
1342 * may be better handled in suspend method in phy driver.
1345 jme_setlinkspeed(struct jme_softc *sc)
1347 struct mii_data *mii;
1350 JME_LOCK_ASSERT(sc);
1352 mii = device_get_softc(sc->jme_miibus);
1355 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1356 switch IFM_SUBTYPE(mii->mii_media_active) {
1366 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1367 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1368 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1369 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1370 BMCR_AUTOEN | BMCR_STARTNEG);
1373 /* Poll link state until jme(4) get a 10/100 link. */
1374 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1376 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1377 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1387 pause("jmelnk", hz);
1390 if (i == MII_ANEGTICKS_GIGE)
1391 device_printf(sc->jme_dev, "establishing link failed, "
1392 "WOL may not work!");
1395 * No link, force MAC to have 100Mbps, full-duplex link.
1396 * This is the last resort and may/may not work.
1398 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1399 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1404 jme_setwol(struct jme_softc *sc)
1406 struct ifnet *ifp = &sc->arpcom.ac_if;
1411 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1412 /* No PME capability, PHY power down. */
1413 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1414 MII_BMCR, BMCR_PDOWN);
1418 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1419 pmcs = CSR_READ_4(sc, JME_PMCS);
1420 pmcs &= ~PMCS_WOL_ENB_MASK;
1421 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1422 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1423 /* Enable PME message. */
1424 gpr |= GPREG0_PME_ENB;
1425 /* For gigabit controllers, reset link speed to 10/100. */
1426 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1427 jme_setlinkspeed(sc);
1430 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1431 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1434 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1435 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1436 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1437 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1438 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1439 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1440 /* No WOL, PHY power down. */
1441 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1442 MII_BMCR, BMCR_PDOWN);
1448 jme_suspend(device_t dev)
1450 struct jme_softc *sc = device_get_softc(dev);
1451 struct ifnet *ifp = &sc->arpcom.ac_if;
1453 ifnet_serialize_all(ifp);
1458 ifnet_deserialize_all(ifp);
1464 jme_resume(device_t dev)
1466 struct jme_softc *sc = device_get_softc(dev);
1467 struct ifnet *ifp = &sc->arpcom.ac_if;
1472 ifnet_serialize_all(ifp);
1475 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1478 pmstat = pci_read_config(sc->jme_dev,
1479 pmc + PCIR_POWER_STATUS, 2);
1480 /* Disable PME clear PME status. */
1481 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1482 pci_write_config(sc->jme_dev,
1483 pmc + PCIR_POWER_STATUS, pmstat, 2);
1487 if (ifp->if_flags & IFF_UP)
1490 ifnet_deserialize_all(ifp);
1496 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1498 struct jme_txdesc *txd;
1499 struct jme_desc *desc;
1501 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1503 int error, i, prod, symbol_desc;
1504 uint32_t cflags, flag64;
1506 M_ASSERTPKTHDR((*m_head));
1508 prod = sc->jme_cdata.jme_tx_prod;
1509 txd = &sc->jme_cdata.jme_txdesc[prod];
1511 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1516 maxsegs = (sc->jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1517 (JME_TXD_RSVD + symbol_desc);
1518 if (maxsegs > JME_MAXTXSEGS)
1519 maxsegs = JME_MAXTXSEGS;
1520 KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
1521 ("not enough segments %d\n", maxsegs));
1523 error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1524 txd->tx_dmamap, m_head,
1525 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1529 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1530 BUS_DMASYNC_PREWRITE);
1535 /* Configure checksum offload. */
1536 if (m->m_pkthdr.csum_flags & CSUM_IP)
1537 cflags |= JME_TD_IPCSUM;
1538 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1539 cflags |= JME_TD_TCPCSUM;
1540 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1541 cflags |= JME_TD_UDPCSUM;
1543 /* Configure VLAN. */
1544 if (m->m_flags & M_VLANTAG) {
1545 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1546 cflags |= JME_TD_VLAN_TAG;
1549 desc = &sc->jme_cdata.jme_tx_ring[prod];
1550 desc->flags = htole32(cflags);
1551 desc->addr_hi = htole32(m->m_pkthdr.len);
1552 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1554 * Use 64bits TX desc chain format.
1556 * The first TX desc of the chain, which is setup here,
1557 * is just a symbol TX desc carrying no payload.
1559 flag64 = JME_TD_64BIT;
1563 /* No effective TX desc is consumed */
1567 * Use 32bits TX desc chain format.
1569 * The first TX desc of the chain, which is setup here,
1570 * is an effective TX desc carrying the first segment of
1574 desc->buflen = htole32(txsegs[0].ds_len);
1575 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1577 /* One effective TX desc is consumed */
1580 sc->jme_cdata.jme_tx_cnt++;
1581 KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1582 sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1583 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1585 txd->tx_ndesc = 1 - i;
1586 for (; i < nsegs; i++) {
1587 desc = &sc->jme_cdata.jme_tx_ring[prod];
1588 desc->flags = htole32(JME_TD_OWN | flag64);
1589 desc->buflen = htole32(txsegs[i].ds_len);
1590 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1591 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1593 sc->jme_cdata.jme_tx_cnt++;
1594 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1595 sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1596 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1599 /* Update producer index. */
1600 sc->jme_cdata.jme_tx_prod = prod;
1602 * Finally request interrupt and give the first descriptor
1603 * owenership to hardware.
1605 desc = txd->tx_desc;
1606 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1609 txd->tx_ndesc += nsegs;
1619 jme_start(struct ifnet *ifp)
1621 struct jme_softc *sc = ifp->if_softc;
1622 struct mbuf *m_head;
1625 ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
1627 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1628 ifq_purge(&ifp->if_snd);
1632 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1635 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1638 while (!ifq_is_empty(&ifp->if_snd)) {
1640 * Check number of available TX descs, always
1641 * leave JME_TXD_RSVD free TX descs.
1643 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1644 sc->jme_tx_desc_cnt - JME_TXD_RSVD) {
1645 ifp->if_flags |= IFF_OACTIVE;
1649 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1654 * Pack the data into the transmit ring. If we
1655 * don't have room, set the OACTIVE flag and wait
1656 * for the NIC to drain the ring.
1658 if (jme_encap(sc, &m_head)) {
1659 KKASSERT(m_head == NULL);
1661 ifp->if_flags |= IFF_OACTIVE;
1667 * If there's a BPF listener, bounce a copy of this frame
1670 ETHER_BPF_MTAP(ifp, m_head);
1675 * Reading TXCSR takes very long time under heavy load
1676 * so cache TXCSR value and writes the ORed value with
1677 * the kick command to the TXCSR. This saves one register
1680 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1681 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1682 /* Set a timeout in case the chip goes out to lunch. */
1683 ifp->if_timer = JME_TX_TIMEOUT;
1688 jme_watchdog(struct ifnet *ifp)
1690 struct jme_softc *sc = ifp->if_softc;
1692 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1694 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1695 if_printf(ifp, "watchdog timeout (missed link)\n");
1702 if (sc->jme_cdata.jme_tx_cnt == 0) {
1703 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1705 if (!ifq_is_empty(&ifp->if_snd))
1710 if_printf(ifp, "watchdog timeout\n");
1713 if (!ifq_is_empty(&ifp->if_snd))
1718 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1720 struct jme_softc *sc = ifp->if_softc;
1721 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1722 struct ifreq *ifr = (struct ifreq *)data;
1723 int error = 0, mask;
1725 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1729 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1730 (!(sc->jme_caps & JME_CAP_JUMBO) &&
1731 ifr->ifr_mtu > JME_MAX_MTU)) {
1736 if (ifp->if_mtu != ifr->ifr_mtu) {
1738 * No special configuration is required when interface
1739 * MTU is changed but availability of Tx checksum
1740 * offload should be chcked against new MTU size as
1741 * FIFO size is just 2K.
1743 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1744 ifp->if_capenable &= ~IFCAP_TXCSUM;
1745 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1747 ifp->if_mtu = ifr->ifr_mtu;
1748 if (ifp->if_flags & IFF_RUNNING)
1754 if (ifp->if_flags & IFF_UP) {
1755 if (ifp->if_flags & IFF_RUNNING) {
1756 if ((ifp->if_flags ^ sc->jme_if_flags) &
1757 (IFF_PROMISC | IFF_ALLMULTI))
1763 if (ifp->if_flags & IFF_RUNNING)
1766 sc->jme_if_flags = ifp->if_flags;
1771 if (ifp->if_flags & IFF_RUNNING)
1777 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1781 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1783 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1784 ifp->if_capenable ^= IFCAP_TXCSUM;
1785 if (IFCAP_TXCSUM & ifp->if_capenable)
1786 ifp->if_hwassist |= JME_CSUM_FEATURES;
1788 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1790 if (mask & IFCAP_RXCSUM) {
1793 ifp->if_capenable ^= IFCAP_RXCSUM;
1794 reg = CSR_READ_4(sc, JME_RXMAC);
1795 reg &= ~RXMAC_CSUM_ENB;
1796 if (ifp->if_capenable & IFCAP_RXCSUM)
1797 reg |= RXMAC_CSUM_ENB;
1798 CSR_WRITE_4(sc, JME_RXMAC, reg);
1801 if (mask & IFCAP_VLAN_HWTAGGING) {
1802 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1806 if (mask & IFCAP_RSS)
1807 ifp->if_capenable ^= IFCAP_RSS;
1811 error = ether_ioctl(ifp, cmd, data);
1818 jme_mac_config(struct jme_softc *sc)
1820 struct mii_data *mii;
1821 uint32_t ghc, rxmac, txmac, txpause, gp1;
1822 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1824 mii = device_get_softc(sc->jme_miibus);
1826 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1828 CSR_WRITE_4(sc, JME_GHC, 0);
1830 rxmac = CSR_READ_4(sc, JME_RXMAC);
1831 rxmac &= ~RXMAC_FC_ENB;
1832 txmac = CSR_READ_4(sc, JME_TXMAC);
1833 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1834 txpause = CSR_READ_4(sc, JME_TXPFC);
1835 txpause &= ~TXPFC_PAUSE_ENB;
1836 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1837 ghc |= GHC_FULL_DUPLEX;
1838 rxmac &= ~RXMAC_COLL_DET_ENB;
1839 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1840 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1843 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1844 txpause |= TXPFC_PAUSE_ENB;
1845 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1846 rxmac |= RXMAC_FC_ENB;
1848 /* Disable retry transmit timer/retry limit. */
1849 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1850 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1852 rxmac |= RXMAC_COLL_DET_ENB;
1853 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1854 /* Enable retry transmit timer/retry limit. */
1855 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1856 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1860 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1862 gp1 = CSR_READ_4(sc, JME_GPREG1);
1863 gp1 &= ~GPREG1_WA_HDX;
1865 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1868 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1870 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1872 gp1 |= GPREG1_WA_HDX;
1876 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1878 gp1 |= GPREG1_WA_HDX;
1881 * Use extended FIFO depth to workaround CRC errors
1882 * emitted by chips before JMC250B
1884 phyconf = JMPHY_CONF_EXTFIFO;
1888 if (sc->jme_caps & JME_CAP_FASTETH)
1891 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1893 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1899 CSR_WRITE_4(sc, JME_GHC, ghc);
1900 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1901 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1902 CSR_WRITE_4(sc, JME_TXPFC, txpause);
1904 if (sc->jme_workaround & JME_WA_EXTFIFO) {
1905 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1906 JMPHY_CONF, phyconf);
1908 if (sc->jme_workaround & JME_WA_HDX)
1909 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1915 struct jme_softc *sc = xsc;
1916 struct ifnet *ifp = &sc->arpcom.ac_if;
1920 ASSERT_SERIALIZED(&sc->jme_serialize);
1922 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1923 if (status == 0 || status == 0xFFFFFFFF)
1926 /* Disable interrupts. */
1927 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1929 status = CSR_READ_4(sc, JME_INTR_STATUS);
1930 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1933 /* Reset PCC counter/timer and Ack interrupts. */
1934 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1936 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1937 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1939 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1940 if (status & jme_rx_status[r].jme_coal) {
1941 status |= jme_rx_status[r].jme_coal |
1942 jme_rx_status[r].jme_comp;
1946 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1948 if (ifp->if_flags & IFF_RUNNING) {
1949 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1950 jme_rx_intr(sc, status);
1952 if (status & INTR_RXQ_DESC_EMPTY) {
1954 * Notify hardware availability of new Rx buffers.
1955 * Reading RXCSR takes very long time under heavy
1956 * load so cache RXCSR value and writes the ORed
1957 * value with the kick command to the RXCSR. This
1958 * saves one register access cycle.
1960 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1961 RXCSR_RX_ENB | RXCSR_RXQ_START);
1964 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
1965 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
1967 if (!ifq_is_empty(&ifp->if_snd))
1969 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
1973 /* Reenable interrupts. */
1974 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
1978 jme_txeof(struct jme_softc *sc)
1980 struct ifnet *ifp = &sc->arpcom.ac_if;
1981 struct jme_txdesc *txd;
1985 cons = sc->jme_cdata.jme_tx_cons;
1986 if (cons == sc->jme_cdata.jme_tx_prod)
1990 * Go through our Tx list and free mbufs for those
1991 * frames which have been transmitted.
1993 while (cons != sc->jme_cdata.jme_tx_prod) {
1994 txd = &sc->jme_cdata.jme_txdesc[cons];
1995 KASSERT(txd->tx_m != NULL,
1996 ("%s: freeing NULL mbuf!\n", __func__));
1998 status = le32toh(txd->tx_desc->flags);
1999 if ((status & JME_TD_OWN) == JME_TD_OWN)
2002 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2006 if (status & JME_TD_COLLISION) {
2007 ifp->if_collisions +=
2008 le32toh(txd->tx_desc->buflen) &
2009 JME_TD_BUF_LEN_MASK;
2014 * Only the first descriptor of multi-descriptor
2015 * transmission is updated so driver have to skip entire
2016 * chained buffers for the transmiited frame. In other
2017 * words, JME_TD_OWN bit is valid only at the first
2018 * descriptor of a multi-descriptor transmission.
2020 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2021 sc->jme_cdata.jme_tx_ring[cons].flags = 0;
2022 JME_DESC_INC(cons, sc->jme_tx_desc_cnt);
2025 /* Reclaim transferred mbufs. */
2026 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2029 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2030 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2031 ("%s: Active Tx desc counter was garbled\n", __func__));
2034 sc->jme_cdata.jme_tx_cons = cons;
2036 if (sc->jme_cdata.jme_tx_cnt == 0)
2039 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
2040 sc->jme_tx_desc_cnt - JME_TXD_RSVD)
2041 ifp->if_flags &= ~IFF_OACTIVE;
2044 static __inline void
2045 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
2049 for (i = 0; i < count; ++i) {
2050 struct jme_desc *desc = &rdata->jme_rx_ring[cons];
2052 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2053 desc->buflen = htole32(MCLBYTES);
2054 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2058 static __inline struct pktinfo *
2059 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2061 if (flags & JME_RD_IPV4)
2062 pi->pi_netisr = NETISR_IP;
2063 else if (flags & JME_RD_IPV6)
2064 pi->pi_netisr = NETISR_IPV6;
2069 pi->pi_l3proto = IPPROTO_UNKNOWN;
2071 if (flags & JME_RD_MORE_FRAG)
2072 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2073 else if (flags & JME_RD_TCP)
2074 pi->pi_l3proto = IPPROTO_TCP;
2075 else if (flags & JME_RD_UDP)
2076 pi->pi_l3proto = IPPROTO_UDP;
2082 /* Receive a frame. */
2084 jme_rxpkt(struct jme_rxdata *rdata)
2086 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
2087 struct jme_desc *desc;
2088 struct jme_rxdesc *rxd;
2089 struct mbuf *mp, *m;
2090 uint32_t flags, status, hash, hashinfo;
2091 int cons, count, nsegs;
2093 cons = rdata->jme_rx_cons;
2094 desc = &rdata->jme_rx_ring[cons];
2095 flags = le32toh(desc->flags);
2096 status = le32toh(desc->buflen);
2097 hash = le32toh(desc->addr_hi);
2098 hashinfo = le32toh(desc->addr_lo);
2099 nsegs = JME_RX_NSEGS(status);
2101 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
2102 "hash 0x%08x, hash info 0x%08x\n",
2103 rdata->jme_rx_idx, flags, hash, hashinfo);
2105 if (status & JME_RX_ERR_STAT) {
2107 jme_discard_rxbufs(rdata, cons, nsegs);
2108 #ifdef JME_SHOW_ERRORS
2109 if_printf(ifp, "%s : receive error = 0x%b\n",
2110 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2112 rdata->jme_rx_cons += nsegs;
2113 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2117 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2118 for (count = 0; count < nsegs; count++,
2119 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
2120 rxd = &rdata->jme_rxdesc[cons];
2123 /* Add a new receive buffer to the ring. */
2124 if (jme_newbuf(rdata, rxd, 0) != 0) {
2127 jme_discard_rxbufs(rdata, cons, nsegs - count);
2128 if (rdata->jme_rxhead != NULL) {
2129 m_freem(rdata->jme_rxhead);
2130 JME_RXCHAIN_RESET(rdata);
2136 * Assume we've received a full sized frame.
2137 * Actual size is fixed when we encounter the end of
2138 * multi-segmented frame.
2140 mp->m_len = MCLBYTES;
2142 /* Chain received mbufs. */
2143 if (rdata->jme_rxhead == NULL) {
2144 rdata->jme_rxhead = mp;
2145 rdata->jme_rxtail = mp;
2148 * Receive processor can receive a maximum frame
2149 * size of 65535 bytes.
2151 rdata->jme_rxtail->m_next = mp;
2152 rdata->jme_rxtail = mp;
2155 if (count == nsegs - 1) {
2156 struct pktinfo pi0, *pi;
2158 /* Last desc. for this frame. */
2159 m = rdata->jme_rxhead;
2160 m->m_pkthdr.len = rdata->jme_rxlen;
2162 /* Set first mbuf size. */
2163 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2164 /* Set last mbuf size. */
2165 mp->m_len = rdata->jme_rxlen -
2166 ((MCLBYTES - JME_RX_PAD_BYTES) +
2167 (MCLBYTES * (nsegs - 2)));
2169 m->m_len = rdata->jme_rxlen;
2171 m->m_pkthdr.rcvif = ifp;
2174 * Account for 10bytes auto padding which is used
2175 * to align IP header on 32bit boundary. Also note,
2176 * CRC bytes is automatically removed by the
2179 m->m_data += JME_RX_PAD_BYTES;
2181 /* Set checksum information. */
2182 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2183 (flags & JME_RD_IPV4)) {
2184 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2185 if (flags & JME_RD_IPCSUM)
2186 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2187 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2188 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2189 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2190 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2191 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2192 m->m_pkthdr.csum_flags |=
2193 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2194 m->m_pkthdr.csum_data = 0xffff;
2198 /* Check for VLAN tagged packets. */
2199 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2200 (flags & JME_RD_VLAN_TAG)) {
2201 m->m_pkthdr.ether_vlantag =
2202 flags & JME_RD_VLAN_MASK;
2203 m->m_flags |= M_VLANTAG;
2208 if (ifp->if_capenable & IFCAP_RSS)
2209 pi = jme_pktinfo(&pi0, flags);
2214 (hashinfo & JME_RD_HASH_FN_MASK) != 0) {
2215 m->m_flags |= M_HASH;
2216 m->m_pkthdr.hash = toeplitz_hash(hash);
2219 #ifdef JME_RSS_DEBUG
2221 JME_RSS_DPRINTF(rdata->jme_sc, 10,
2222 "isr %d flags %08x, l3 %d %s\n",
2223 pi->pi_netisr, pi->pi_flags,
2225 (m->m_flags & M_HASH) ? "hash" : "");
2230 ether_input_pkt(ifp, m, pi);
2232 /* Reset mbuf chains. */
2233 JME_RXCHAIN_RESET(rdata);
2234 #ifdef JME_RSS_DEBUG
2235 rdata->jme_rx_pkt++;
2240 rdata->jme_rx_cons += nsegs;
2241 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2245 jme_rxeof(struct jme_rxdata *rdata, int count)
2247 struct jme_desc *desc;
2251 #ifdef DEVICE_POLLING
2252 if (count >= 0 && count-- == 0)
2255 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2256 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2258 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2262 * Check number of segments against received bytes.
2263 * Non-matching value would indicate that hardware
2264 * is still trying to update Rx descriptors. I'm not
2265 * sure whether this check is needed.
2267 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2268 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2269 if (nsegs != howmany(pktlen, MCLBYTES)) {
2270 if_printf(&rdata->jme_sc->arpcom.ac_if,
2271 "RX fragment count(%d) and "
2272 "packet size(%d) mismach\n", nsegs, pktlen);
2276 /* Received a frame. */
2284 struct jme_softc *sc = xsc;
2285 struct ifnet *ifp = &sc->arpcom.ac_if;
2286 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2288 ifnet_serialize_all(ifp);
2291 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2293 ifnet_deserialize_all(ifp);
2297 jme_reset(struct jme_softc *sc)
2301 /* Make sure that TX and RX are stopped */
2306 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2310 * Hold reset bit before stop reset
2313 /* Disable TXMAC and TXOFL clock sources */
2314 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2315 /* Disable RXMAC clock source */
2316 val = CSR_READ_4(sc, JME_GPREG1);
2317 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2319 CSR_READ_4(sc, JME_GHC);
2322 CSR_WRITE_4(sc, JME_GHC, 0);
2324 CSR_READ_4(sc, JME_GHC);
2327 * Clear reset bit after stop reset
2330 /* Enable TXMAC and TXOFL clock sources */
2331 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2332 /* Enable RXMAC clock source */
2333 val = CSR_READ_4(sc, JME_GPREG1);
2334 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2336 CSR_READ_4(sc, JME_GHC);
2338 /* Disable TXMAC and TXOFL clock sources */
2339 CSR_WRITE_4(sc, JME_GHC, 0);
2340 /* Disable RXMAC clock source */
2341 val = CSR_READ_4(sc, JME_GPREG1);
2342 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2344 CSR_READ_4(sc, JME_GHC);
2346 /* Enable TX and RX */
2347 val = CSR_READ_4(sc, JME_TXCSR);
2348 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2349 val = CSR_READ_4(sc, JME_RXCSR);
2350 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2352 CSR_READ_4(sc, JME_TXCSR);
2353 CSR_READ_4(sc, JME_RXCSR);
2355 /* Enable TXMAC and TXOFL clock sources */
2356 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2357 /* Eisable RXMAC clock source */
2358 val = CSR_READ_4(sc, JME_GPREG1);
2359 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2361 CSR_READ_4(sc, JME_GHC);
2363 /* Stop TX and RX */
2371 struct jme_softc *sc = xsc;
2372 struct ifnet *ifp = &sc->arpcom.ac_if;
2373 struct mii_data *mii;
2374 uint8_t eaddr[ETHER_ADDR_LEN];
2379 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2382 * Cancel any pending I/O.
2387 * Reset the chip to a known state.
2392 * Setup MSI/MSI-X vectors to interrupts mapping
2397 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2398 KKASSERT(sc->jme_txd_spare >= 1);
2401 * If we use 64bit address mode for transmitting, each Tx request
2402 * needs one more symbol descriptor.
2404 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2405 sc->jme_txd_spare += 1;
2407 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
2410 jme_disable_rss(sc);
2412 /* Init RX descriptors */
2413 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2414 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
2416 if_printf(ifp, "initialization failed: "
2417 "no memory for %dth RX ring.\n", r);
2423 /* Init TX descriptors */
2424 jme_init_tx_ring(sc);
2426 /* Initialize shadow status block. */
2429 /* Reprogram the station address. */
2430 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2431 CSR_WRITE_4(sc, JME_PAR0,
2432 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2433 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2436 * Configure Tx queue.
2437 * Tx priority queue weight value : 0
2438 * Tx FIFO threshold for processing next packet : 16QW
2439 * Maximum Tx DMA length : 512
2440 * Allow Tx DMA burst.
2442 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2443 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2444 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2445 sc->jme_txcsr |= sc->jme_tx_dma_size;
2446 sc->jme_txcsr |= TXCSR_DMA_BURST;
2447 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2449 /* Set Tx descriptor counter. */
2450 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_tx_desc_cnt);
2452 /* Set Tx ring address to the hardware. */
2453 paddr = sc->jme_cdata.jme_tx_ring_paddr;
2454 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2455 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2457 /* Configure TxMAC parameters. */
2458 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2459 reg |= TXMAC_THRESH_1_PKT;
2460 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2461 CSR_WRITE_4(sc, JME_TXMAC, reg);
2464 * Configure Rx queue.
2465 * FIFO full threshold for transmitting Tx pause packet : 128T
2466 * FIFO threshold for processing next packet : 128QW
2468 * Max Rx DMA length : 128
2469 * Rx descriptor retry : 32
2470 * Rx descriptor retry time gap : 256ns
2471 * Don't receive runt/bad frame.
2473 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2476 * Since Rx FIFO size is 4K bytes, receiving frames larger
2477 * than 4K bytes will suffer from Rx FIFO overruns. So
2478 * decrease FIFO threshold to reduce the FIFO overruns for
2479 * frames larger than 4000 bytes.
2480 * For best performance of standard MTU sized frames use
2481 * maximum allowable FIFO threshold, 128QW.
2483 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2485 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2487 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2489 /* Improve PCI Express compatibility */
2490 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2492 sc->jme_rxcsr |= sc->jme_rx_dma_size;
2493 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2494 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2495 /* XXX TODO DROP_BAD */
2497 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2498 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2500 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2502 /* Set Rx descriptor counter. */
2503 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
2505 /* Set Rx ring address to the hardware. */
2506 paddr = rdata->jme_rx_ring_paddr;
2507 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2508 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2511 /* Clear receive filter. */
2512 CSR_WRITE_4(sc, JME_RXMAC, 0);
2514 /* Set up the receive filter. */
2519 * Disable all WOL bits as WOL can interfere normal Rx
2520 * operation. Also clear WOL detection status bits.
2522 reg = CSR_READ_4(sc, JME_PMCS);
2523 reg &= ~PMCS_WOL_ENB_MASK;
2524 CSR_WRITE_4(sc, JME_PMCS, reg);
2527 * Pad 10bytes right before received frame. This will greatly
2528 * help Rx performance on strict-alignment architectures as
2529 * it does not need to copy the frame to align the payload.
2531 reg = CSR_READ_4(sc, JME_RXMAC);
2532 reg |= RXMAC_PAD_10BYTES;
2534 if (ifp->if_capenable & IFCAP_RXCSUM)
2535 reg |= RXMAC_CSUM_ENB;
2536 CSR_WRITE_4(sc, JME_RXMAC, reg);
2538 /* Configure general purpose reg0 */
2539 reg = CSR_READ_4(sc, JME_GPREG0);
2540 reg &= ~GPREG0_PCC_UNIT_MASK;
2541 /* Set PCC timer resolution to micro-seconds unit. */
2542 reg |= GPREG0_PCC_UNIT_US;
2544 * Disable all shadow register posting as we have to read
2545 * JME_INTR_STATUS register in jme_intr. Also it seems
2546 * that it's hard to synchronize interrupt status between
2547 * hardware and software with shadow posting due to
2548 * requirements of bus_dmamap_sync(9).
2550 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2551 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2552 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2553 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2554 /* Disable posting of DW0. */
2555 reg &= ~GPREG0_POST_DW0_ENB;
2556 /* Clear PME message. */
2557 reg &= ~GPREG0_PME_ENB;
2558 /* Set PHY address. */
2559 reg &= ~GPREG0_PHY_ADDR_MASK;
2560 reg |= sc->jme_phyaddr;
2561 CSR_WRITE_4(sc, JME_GPREG0, reg);
2563 /* Configure Tx queue 0 packet completion coalescing. */
2564 jme_set_tx_coal(sc);
2566 /* Configure Rx queues packet completion coalescing. */
2567 jme_set_rx_coal(sc);
2569 /* Configure shadow status block but don't enable posting. */
2570 paddr = sc->jme_cdata.jme_ssb_block_paddr;
2571 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2572 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2574 /* Disable Timer 1 and Timer 2. */
2575 CSR_WRITE_4(sc, JME_TIMER1, 0);
2576 CSR_WRITE_4(sc, JME_TIMER2, 0);
2578 /* Configure retry transmit period, retry limit value. */
2579 CSR_WRITE_4(sc, JME_TXTRHD,
2580 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2581 TXTRHD_RT_PERIOD_MASK) |
2582 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2583 TXTRHD_RT_LIMIT_SHIFT));
2585 #ifdef DEVICE_POLLING
2586 if (!(ifp->if_flags & IFF_POLLING))
2588 /* Initialize the interrupt mask. */
2589 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2590 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2593 * Enabling Tx/Rx DMA engines and Rx queue processing is
2594 * done after detection of valid link in jme_miibus_statchg.
2596 sc->jme_flags &= ~JME_FLAG_LINK;
2598 /* Set the current media. */
2599 mii = device_get_softc(sc->jme_miibus);
2602 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2604 ifp->if_flags |= IFF_RUNNING;
2605 ifp->if_flags &= ~IFF_OACTIVE;
2609 jme_stop(struct jme_softc *sc)
2611 struct ifnet *ifp = &sc->arpcom.ac_if;
2612 struct jme_txdesc *txd;
2613 struct jme_rxdesc *rxd;
2614 struct jme_rxdata *rdata;
2617 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2620 * Mark the interface down and cancel the watchdog timer.
2622 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2625 callout_stop(&sc->jme_tick_ch);
2626 sc->jme_flags &= ~JME_FLAG_LINK;
2629 * Disable interrupts.
2631 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2632 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2634 /* Disable updating shadow status block. */
2635 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2636 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2638 /* Stop receiver, transmitter. */
2643 * Free partial finished RX segments
2645 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2646 rdata = &sc->jme_cdata.jme_rx_data[r];
2647 if (rdata->jme_rxhead != NULL)
2648 m_freem(rdata->jme_rxhead);
2649 JME_RXCHAIN_RESET(rdata);
2653 * Free RX and TX mbufs still in the queues.
2655 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2656 rdata = &sc->jme_cdata.jme_rx_data[r];
2657 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2658 rxd = &rdata->jme_rxdesc[i];
2659 if (rxd->rx_m != NULL) {
2660 bus_dmamap_unload(rdata->jme_rx_tag,
2667 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2668 txd = &sc->jme_cdata.jme_txdesc[i];
2669 if (txd->tx_m != NULL) {
2670 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2680 jme_stop_tx(struct jme_softc *sc)
2685 reg = CSR_READ_4(sc, JME_TXCSR);
2686 if ((reg & TXCSR_TX_ENB) == 0)
2688 reg &= ~TXCSR_TX_ENB;
2689 CSR_WRITE_4(sc, JME_TXCSR, reg);
2690 for (i = JME_TIMEOUT; i > 0; i--) {
2692 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2696 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2700 jme_stop_rx(struct jme_softc *sc)
2705 reg = CSR_READ_4(sc, JME_RXCSR);
2706 if ((reg & RXCSR_RX_ENB) == 0)
2708 reg &= ~RXCSR_RX_ENB;
2709 CSR_WRITE_4(sc, JME_RXCSR, reg);
2710 for (i = JME_TIMEOUT; i > 0; i--) {
2712 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2716 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2720 jme_init_tx_ring(struct jme_softc *sc)
2722 struct jme_chain_data *cd;
2723 struct jme_txdesc *txd;
2726 sc->jme_cdata.jme_tx_prod = 0;
2727 sc->jme_cdata.jme_tx_cons = 0;
2728 sc->jme_cdata.jme_tx_cnt = 0;
2730 cd = &sc->jme_cdata;
2731 bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2732 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2733 txd = &sc->jme_cdata.jme_txdesc[i];
2735 txd->tx_desc = &cd->jme_tx_ring[i];
2741 jme_init_ssb(struct jme_softc *sc)
2743 struct jme_chain_data *cd;
2745 cd = &sc->jme_cdata;
2746 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2750 jme_init_rx_ring(struct jme_rxdata *rdata)
2752 struct jme_rxdesc *rxd;
2755 KKASSERT(rdata->jme_rxhead == NULL &&
2756 rdata->jme_rxtail == NULL &&
2757 rdata->jme_rxlen == 0);
2758 rdata->jme_rx_cons = 0;
2760 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
2761 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2764 rxd = &rdata->jme_rxdesc[i];
2766 rxd->rx_desc = &rdata->jme_rx_ring[i];
2767 error = jme_newbuf(rdata, rxd, 1);
2775 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
2777 struct jme_desc *desc;
2779 bus_dma_segment_t segs;
2783 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2787 * JMC250 has 64bit boundary alignment limitation so jme(4)
2788 * takes advantage of 10 bytes padding feature of hardware
2789 * in order not to copy entire frame to align IP header on
2792 m->m_len = m->m_pkthdr.len = MCLBYTES;
2794 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2795 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2800 if_printf(&rdata->jme_sc->arpcom.ac_if,
2801 "can't load RX mbuf\n");
2806 if (rxd->rx_m != NULL) {
2807 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2808 BUS_DMASYNC_POSTREAD);
2809 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2811 map = rxd->rx_dmamap;
2812 rxd->rx_dmamap = rdata->jme_rx_sparemap;
2813 rdata->jme_rx_sparemap = map;
2816 desc = rxd->rx_desc;
2817 desc->buflen = htole32(segs.ds_len);
2818 desc->addr_lo = htole32(JME_ADDR_LO(segs.ds_addr));
2819 desc->addr_hi = htole32(JME_ADDR_HI(segs.ds_addr));
2820 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2826 jme_set_vlan(struct jme_softc *sc)
2828 struct ifnet *ifp = &sc->arpcom.ac_if;
2831 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2833 reg = CSR_READ_4(sc, JME_RXMAC);
2834 reg &= ~RXMAC_VLAN_ENB;
2835 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2836 reg |= RXMAC_VLAN_ENB;
2837 CSR_WRITE_4(sc, JME_RXMAC, reg);
2841 jme_set_filter(struct jme_softc *sc)
2843 struct ifnet *ifp = &sc->arpcom.ac_if;
2844 struct ifmultiaddr *ifma;
2849 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2851 rxcfg = CSR_READ_4(sc, JME_RXMAC);
2852 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2856 * Always accept frames destined to our station address.
2857 * Always accept broadcast frames.
2859 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2861 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2862 if (ifp->if_flags & IFF_PROMISC)
2863 rxcfg |= RXMAC_PROMISC;
2864 if (ifp->if_flags & IFF_ALLMULTI)
2865 rxcfg |= RXMAC_ALLMULTI;
2866 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2867 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2868 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2873 * Set up the multicast address filter by passing all multicast
2874 * addresses through a CRC generator, and then using the low-order
2875 * 6 bits as an index into the 64 bit multicast hash table. The
2876 * high order bits select the register, while the rest of the bits
2877 * select the bit within the register.
2879 rxcfg |= RXMAC_MULTICAST;
2880 bzero(mchash, sizeof(mchash));
2882 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2883 if (ifma->ifma_addr->sa_family != AF_LINK)
2885 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2886 ifma->ifma_addr), ETHER_ADDR_LEN);
2888 /* Just want the 6 least significant bits. */
2891 /* Set the corresponding bit in the hash table. */
2892 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2895 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2896 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2897 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2901 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
2903 struct jme_softc *sc = arg1;
2904 struct ifnet *ifp = &sc->arpcom.ac_if;
2907 ifnet_serialize_all(ifp);
2909 v = sc->jme_tx_coal_to;
2910 error = sysctl_handle_int(oidp, &v, 0, req);
2911 if (error || req->newptr == NULL)
2914 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
2919 if (v != sc->jme_tx_coal_to) {
2920 sc->jme_tx_coal_to = v;
2921 if (ifp->if_flags & IFF_RUNNING)
2922 jme_set_tx_coal(sc);
2925 ifnet_deserialize_all(ifp);
2930 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
2932 struct jme_softc *sc = arg1;
2933 struct ifnet *ifp = &sc->arpcom.ac_if;
2936 ifnet_serialize_all(ifp);
2938 v = sc->jme_tx_coal_pkt;
2939 error = sysctl_handle_int(oidp, &v, 0, req);
2940 if (error || req->newptr == NULL)
2943 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
2948 if (v != sc->jme_tx_coal_pkt) {
2949 sc->jme_tx_coal_pkt = v;
2950 if (ifp->if_flags & IFF_RUNNING)
2951 jme_set_tx_coal(sc);
2954 ifnet_deserialize_all(ifp);
2959 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
2961 struct jme_softc *sc = arg1;
2962 struct ifnet *ifp = &sc->arpcom.ac_if;
2965 ifnet_serialize_all(ifp);
2967 v = sc->jme_rx_coal_to;
2968 error = sysctl_handle_int(oidp, &v, 0, req);
2969 if (error || req->newptr == NULL)
2972 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
2977 if (v != sc->jme_rx_coal_to) {
2978 sc->jme_rx_coal_to = v;
2979 if (ifp->if_flags & IFF_RUNNING)
2980 jme_set_rx_coal(sc);
2983 ifnet_deserialize_all(ifp);
2988 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
2990 struct jme_softc *sc = arg1;
2991 struct ifnet *ifp = &sc->arpcom.ac_if;
2994 ifnet_serialize_all(ifp);
2996 v = sc->jme_rx_coal_pkt;
2997 error = sysctl_handle_int(oidp, &v, 0, req);
2998 if (error || req->newptr == NULL)
3001 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3006 if (v != sc->jme_rx_coal_pkt) {
3007 sc->jme_rx_coal_pkt = v;
3008 if (ifp->if_flags & IFF_RUNNING)
3009 jme_set_rx_coal(sc);
3012 ifnet_deserialize_all(ifp);
3017 jme_set_tx_coal(struct jme_softc *sc)
3021 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3023 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3024 PCCTX_COAL_PKT_MASK;
3025 reg |= PCCTX_COAL_TXQ0;
3026 CSR_WRITE_4(sc, JME_PCCTX, reg);
3030 jme_set_rx_coal(struct jme_softc *sc)
3035 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3037 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3038 PCCRX_COAL_PKT_MASK;
3039 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
3040 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3043 #ifdef DEVICE_POLLING
3046 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3048 struct jme_softc *sc = ifp->if_softc;
3052 ASSERT_SERIALIZED(&sc->jme_serialize);
3056 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3059 case POLL_DEREGISTER:
3060 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3063 case POLL_AND_CHECK_STATUS:
3065 status = CSR_READ_4(sc, JME_INTR_STATUS);
3067 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3068 struct jme_rxdata *rdata =
3069 &sc->jme_cdata.jme_rx_data[r];
3071 lwkt_serialize_enter(&rdata->jme_rx_serialize);
3072 jme_rxeof(rdata, count);
3073 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3076 if (status & INTR_RXQ_DESC_EMPTY) {
3077 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3078 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3079 RXCSR_RX_ENB | RXCSR_RXQ_START);
3082 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3084 if (!ifq_is_empty(&ifp->if_snd))
3086 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3091 #endif /* DEVICE_POLLING */
3094 jme_rxring_dma_alloc(struct jme_rxdata *rdata)
3099 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
3100 JME_RX_RING_ALIGN, 0,
3101 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3102 JME_RX_RING_SIZE(rdata),
3103 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3105 device_printf(rdata->jme_sc->jme_dev,
3106 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
3109 rdata->jme_rx_ring_tag = dmem.dmem_tag;
3110 rdata->jme_rx_ring_map = dmem.dmem_map;
3111 rdata->jme_rx_ring = dmem.dmem_addr;
3112 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3118 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
3122 /* Create tag for Rx buffers. */
3123 error = bus_dma_tag_create(
3124 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
3125 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
3126 BUS_SPACE_MAXADDR, /* lowaddr */
3127 BUS_SPACE_MAXADDR, /* highaddr */
3128 NULL, NULL, /* filter, filterarg */
3129 MCLBYTES, /* maxsize */
3131 MCLBYTES, /* maxsegsize */
3132 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3133 &rdata->jme_rx_tag);
3135 device_printf(rdata->jme_sc->jme_dev,
3136 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
3140 /* Create DMA maps for Rx buffers. */
3141 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3142 &rdata->jme_rx_sparemap);
3144 device_printf(rdata->jme_sc->jme_dev,
3145 "could not create %dth spare Rx dmamap.\n",
3147 bus_dma_tag_destroy(rdata->jme_rx_tag);
3148 rdata->jme_rx_tag = NULL;
3151 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
3152 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3154 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3159 device_printf(rdata->jme_sc->jme_dev,
3160 "could not create %dth Rx dmamap "
3161 "for %dth RX ring.\n", i, rdata->jme_rx_idx);
3163 for (j = 0; j < i; ++j) {
3164 rxd = &rdata->jme_rxdesc[j];
3165 bus_dmamap_destroy(rdata->jme_rx_tag,
3168 bus_dmamap_destroy(rdata->jme_rx_tag,
3169 rdata->jme_rx_sparemap);
3170 bus_dma_tag_destroy(rdata->jme_rx_tag);
3171 rdata->jme_rx_tag = NULL;
3179 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3183 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3184 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3186 if (status & rdata->jme_rx_coal) {
3187 lwkt_serialize_enter(&rdata->jme_rx_serialize);
3188 jme_rxeof(rdata, -1);
3189 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3195 jme_enable_rss(struct jme_softc *sc)
3198 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3201 KASSERT(sc->jme_rx_ring_cnt == JME_NRXRING_2 ||
3202 sc->jme_rx_ring_cnt == JME_NRXRING_4,
3203 ("%s: invalid # of RX rings (%d)\n",
3204 sc->arpcom.ac_if.if_xname, sc->jme_rx_ring_cnt));
3206 rssc = RSSC_HASH_64_ENTRY;
3207 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3208 rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
3209 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3210 CSR_WRITE_4(sc, JME_RSSC, rssc);
3212 toeplitz_get_key(key, sizeof(key));
3213 for (i = 0; i < RSSKEY_NREGS; ++i) {
3216 keyreg = RSSKEY_REGVAL(key, i);
3217 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3219 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3223 * Create redirect table in following fashion:
3224 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3227 for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3230 q = i % sc->jme_cdata.jme_rx_ring_cnt;
3231 ind |= q << (i * 8);
3233 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3235 for (i = 0; i < RSSTBL_NREGS; ++i)
3236 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3240 jme_disable_rss(struct jme_softc *sc)
3242 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3246 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3248 struct jme_softc *sc = ifp->if_softc;
3251 case IFNET_SERIALIZE_ALL:
3252 lwkt_serialize_array_enter(sc->jme_serialize_arr,
3253 sc->jme_serialize_cnt, 0);
3256 case IFNET_SERIALIZE_MAIN:
3257 lwkt_serialize_enter(&sc->jme_serialize);
3260 case IFNET_SERIALIZE_TX:
3261 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3264 case IFNET_SERIALIZE_RX(0):
3265 lwkt_serialize_enter(
3266 &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3269 case IFNET_SERIALIZE_RX(1):
3270 lwkt_serialize_enter(
3271 &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3274 case IFNET_SERIALIZE_RX(2):
3275 lwkt_serialize_enter(
3276 &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3279 case IFNET_SERIALIZE_RX(3):
3280 lwkt_serialize_enter(
3281 &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3285 panic("%s unsupported serialize type\n", ifp->if_xname);
3290 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3292 struct jme_softc *sc = ifp->if_softc;
3295 case IFNET_SERIALIZE_ALL:
3296 lwkt_serialize_array_exit(sc->jme_serialize_arr,
3297 sc->jme_serialize_cnt, 0);
3300 case IFNET_SERIALIZE_MAIN:
3301 lwkt_serialize_exit(&sc->jme_serialize);
3304 case IFNET_SERIALIZE_TX:
3305 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3308 case IFNET_SERIALIZE_RX(0):
3309 lwkt_serialize_exit(
3310 &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3313 case IFNET_SERIALIZE_RX(1):
3314 lwkt_serialize_exit(
3315 &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3318 case IFNET_SERIALIZE_RX(2):
3319 lwkt_serialize_exit(
3320 &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3323 case IFNET_SERIALIZE_RX(3):
3324 lwkt_serialize_exit(
3325 &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3329 panic("%s unsupported serialize type\n", ifp->if_xname);
3334 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3336 struct jme_softc *sc = ifp->if_softc;
3339 case IFNET_SERIALIZE_ALL:
3340 return lwkt_serialize_array_try(sc->jme_serialize_arr,
3341 sc->jme_serialize_cnt, 0);
3343 case IFNET_SERIALIZE_MAIN:
3344 return lwkt_serialize_try(&sc->jme_serialize);
3346 case IFNET_SERIALIZE_TX:
3347 return lwkt_serialize_try(&sc->jme_cdata.jme_tx_serialize);
3349 case IFNET_SERIALIZE_RX(0):
3350 return lwkt_serialize_try(
3351 &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3353 case IFNET_SERIALIZE_RX(1):
3354 return lwkt_serialize_try(
3355 &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3357 case IFNET_SERIALIZE_RX(2):
3358 return lwkt_serialize_try(
3359 &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3361 case IFNET_SERIALIZE_RX(3):
3362 return lwkt_serialize_try(
3363 &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3366 panic("%s unsupported serialize type\n", ifp->if_xname);
3373 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3374 boolean_t serialized)
3376 struct jme_softc *sc = ifp->if_softc;
3377 struct jme_rxdata *rdata;
3381 case IFNET_SERIALIZE_ALL:
3383 for (i = 0; i < sc->jme_serialize_cnt; ++i)
3384 ASSERT_SERIALIZED(sc->jme_serialize_arr[i]);
3386 for (i = 0; i < sc->jme_serialize_cnt; ++i)
3387 ASSERT_NOT_SERIALIZED(sc->jme_serialize_arr[i]);
3391 case IFNET_SERIALIZE_MAIN:
3393 ASSERT_SERIALIZED(&sc->jme_serialize);
3395 ASSERT_NOT_SERIALIZED(&sc->jme_serialize);
3398 case IFNET_SERIALIZE_TX:
3400 ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3402 ASSERT_NOT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3405 case IFNET_SERIALIZE_RX(0):
3406 rdata = &sc->jme_cdata.jme_rx_data[0];
3408 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3410 ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3413 case IFNET_SERIALIZE_RX(1):
3414 rdata = &sc->jme_cdata.jme_rx_data[1];
3416 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3418 ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3421 case IFNET_SERIALIZE_RX(2):
3422 rdata = &sc->jme_cdata.jme_rx_data[2];
3424 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3426 ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3429 case IFNET_SERIALIZE_RX(3):
3430 rdata = &sc->jme_cdata.jme_rx_data[3];
3432 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3434 ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3438 panic("%s unsupported serialize type\n", ifp->if_xname);
3442 #endif /* INVARIANTS */
3445 jme_msix_try_alloc(device_t dev)
3447 struct jme_softc *sc = device_get_softc(dev);
3448 struct jme_msix_data *msix;
3449 int error, i, r, msix_enable, msix_count;
3451 msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt;
3452 KKASSERT(msix_count <= JME_NMSIX);
3454 msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
3457 * We leave the 1st MSI-X vector unused, so we
3458 * actually need msix_count + 1 MSI-X vectors.
3460 if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3463 for (i = 0; i < msix_count; ++i)
3464 sc->jme_msix[i].jme_msix_rid = -1;
3468 msix = &sc->jme_msix[i++];
3469 msix->jme_msix_cpuid = 0; /* XXX Put TX to cpu0 */
3470 msix->jme_msix_arg = &sc->jme_cdata;
3471 msix->jme_msix_func = jme_msix_tx;
3472 msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3473 msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3474 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3475 device_get_nameunit(dev));
3477 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3478 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3480 msix = &sc->jme_msix[i++];
3481 msix->jme_msix_cpuid = r; /* XXX Put RX to cpuX */
3482 msix->jme_msix_arg = rdata;
3483 msix->jme_msix_func = jme_msix_rx;
3484 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3485 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3486 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3487 "%s rx%d", device_get_nameunit(dev), r);
3490 KKASSERT(i == msix_count);
3492 error = pci_setup_msix(dev);
3496 /* Setup jme_msix_cnt early, so we could cleanup */
3497 sc->jme_msix_cnt = msix_count;
3499 for (i = 0; i < msix_count; ++i) {
3500 msix = &sc->jme_msix[i];
3502 msix->jme_msix_vector = i + 1;
3503 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3504 &msix->jme_msix_rid, msix->jme_msix_cpuid);
3508 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3509 &msix->jme_msix_rid, RF_ACTIVE);
3510 if (msix->jme_msix_res == NULL) {
3516 for (i = 0; i < JME_INTR_CNT; ++i) {
3517 uint32_t intr_mask = (1 << i);
3520 if ((JME_INTRS & intr_mask) == 0)
3523 for (x = 0; x < msix_count; ++x) {
3524 msix = &sc->jme_msix[x];
3525 if (msix->jme_msix_intrs & intr_mask) {
3528 reg = i / JME_MSINUM_FACTOR;
3529 KKASSERT(reg < JME_MSINUM_CNT);
3531 shift = (i % JME_MSINUM_FACTOR) * 4;
3533 sc->jme_msinum[reg] |=
3534 (msix->jme_msix_vector << shift);
3542 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3543 device_printf(dev, "MSINUM%d: %#x\n", i,
3548 pci_enable_msix(dev);
3549 sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3557 jme_intr_alloc(device_t dev)
3559 struct jme_softc *sc = device_get_softc(dev);
3562 jme_msix_try_alloc(dev);
3564 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3565 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3566 &sc->jme_irq_rid, &irq_flags);
3568 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3569 &sc->jme_irq_rid, irq_flags);
3570 if (sc->jme_irq_res == NULL) {
3571 device_printf(dev, "can't allocate irq\n");
3579 jme_msix_free(device_t dev)
3581 struct jme_softc *sc = device_get_softc(dev);
3584 KKASSERT(sc->jme_msix_cnt > 1);
3586 for (i = 0; i < sc->jme_msix_cnt; ++i) {
3587 struct jme_msix_data *msix = &sc->jme_msix[i];
3589 if (msix->jme_msix_res != NULL) {
3590 bus_release_resource(dev, SYS_RES_IRQ,
3591 msix->jme_msix_rid, msix->jme_msix_res);
3592 msix->jme_msix_res = NULL;
3594 if (msix->jme_msix_rid >= 0) {
3595 pci_release_msix_vector(dev, msix->jme_msix_rid);
3596 msix->jme_msix_rid = -1;
3599 pci_teardown_msix(dev);
3603 jme_intr_free(device_t dev)
3605 struct jme_softc *sc = device_get_softc(dev);
3607 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3608 if (sc->jme_irq_res != NULL) {
3609 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3612 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3613 pci_release_msi(dev);
3620 jme_msix_tx(void *xcd)
3622 struct jme_chain_data *cd = xcd;
3623 struct jme_softc *sc = cd->jme_sc;
3624 struct ifnet *ifp = &sc->arpcom.ac_if;
3626 ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3628 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3630 CSR_WRITE_4(sc, JME_INTR_STATUS,
3631 INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3633 if (ifp->if_flags & IFF_RUNNING) {
3635 if (!ifq_is_empty(&ifp->if_snd))
3639 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3643 jme_msix_rx(void *xrdata)
3645 struct jme_rxdata *rdata = xrdata;
3646 struct jme_softc *sc = rdata->jme_sc;
3647 struct ifnet *ifp = &sc->arpcom.ac_if;
3650 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3652 CSR_WRITE_4(sc, JME_INTR_MASK_CLR,
3653 (rdata->jme_rx_coal | rdata->jme_rx_empty));
3655 status = CSR_READ_4(sc, JME_INTR_STATUS);
3656 status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3658 if (status & rdata->jme_rx_coal)
3659 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
3660 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3662 if (ifp->if_flags & IFF_RUNNING) {
3663 if (status & rdata->jme_rx_coal)
3664 jme_rxeof(rdata, -1);
3666 if (status & rdata->jme_rx_empty) {
3667 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3668 RXCSR_RX_ENB | RXCSR_RXQ_START);
3672 CSR_WRITE_4(sc, JME_INTR_MASK_SET,
3673 (rdata->jme_rx_coal | rdata->jme_rx_empty));
3677 jme_set_msinum(struct jme_softc *sc)
3681 for (i = 0; i < JME_MSINUM_CNT; ++i)
3682 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3686 jme_intr_setup(device_t dev)
3688 struct jme_softc *sc = device_get_softc(dev);
3689 struct ifnet *ifp = &sc->arpcom.ac_if;
3692 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3693 return jme_msix_setup(dev);
3695 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3696 jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3698 device_printf(dev, "could not set up interrupt handler.\n");
3702 ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3703 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3708 jme_intr_teardown(device_t dev)
3710 struct jme_softc *sc = device_get_softc(dev);
3712 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3713 jme_msix_teardown(dev, sc->jme_msix_cnt);
3715 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3719 jme_msix_setup(device_t dev)
3721 struct jme_softc *sc = device_get_softc(dev);
3722 struct ifnet *ifp = &sc->arpcom.ac_if;
3725 for (x = 0; x < sc->jme_msix_cnt; ++x) {
3726 struct jme_msix_data *msix = &sc->jme_msix[x];
3729 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
3730 INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
3731 &msix->jme_msix_handle, msix->jme_msix_serialize,
3732 msix->jme_msix_desc);
3734 device_printf(dev, "could not set up %s "
3735 "interrupt handler.\n", msix->jme_msix_desc);
3736 jme_msix_teardown(dev, x);
3740 ifp->if_cpuid = 0; /* XXX */
3745 jme_msix_teardown(device_t dev, int msix_count)
3747 struct jme_softc *sc = device_get_softc(dev);
3750 for (x = 0; x < msix_count; ++x) {
3751 struct jme_msix_data *msix = &sc->jme_msix[x];
3753 bus_teardown_intr(dev, msix->jme_msix_res,
3754 msix->jme_msix_handle);