sys/net/i4b/layer1/ifpi/i4b_ifpi_pci.c

   1 /*
   2  *   Copyright (c) 1999, 2000 Gary Jennejohn. All rights reserved.
   3  *
   4  *   Redistribution and use in source and binary forms, with or without
   5  *   modification, are permitted provided that the following conditions
   6  *   are met:
   7  *
   8  *   1. Redistributions of source code must retain the above copyright
   9  *      notice, this list of conditions and the following disclaimer.
  10  *   2. Redistributions in binary form must reproduce the above copyright
  11  *      notice, this list of conditions and the following disclaimer in the
  12  *      documentation and/or other materials provided with the distribution.
  13  *   3. Neither the name of the author nor the names of any co-contributors
  14  *      may be used to endorse or promote products derived from this software
  15  *      without specific prior written permission.
  16  *   4. Altered versions must be plainly marked as such, and must not be
  17  *      misrepresented as being the original software and/or documentation.
  18  *
  19  *   THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  *   ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  23  *   FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  *   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  *   OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  *   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  *   LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  *   OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  *   SUCH DAMAGE.
  30  *
  31  *---------------------------------------------------------------------------
  32  *
  33  *      i4b_ifpi_pci.c: AVM Fritz!Card PCI hardware driver
  34  *      --------------------------------------------------
  35  *
  36  *      $Id: i4b_ifpi_pci.c,v 1.4 2000/06/02 11:58:56 hm Exp $
  37  *
  38  * $FreeBSD: src/sys/i4b/layer1/ifpi/i4b_ifpi_pci.c,v 1.6.2.1 2001/08/10 14:08:37 obrien Exp $
  39  * $DragonFly: src/sys/net/i4b/layer1/ifpi/i4b_ifpi_pci.c,v 1.13 2006/01/14 11:05:18 swildner Exp $
  40  *
  41  *      last edit-date: [Fri Jan 12 17:01:26 2001]
  42  *
  43  *---------------------------------------------------------------------------*/
  44
  45 #include "use_ifpi.h"
  46 #include "use_pci.h"
  47 #include "opt_i4b.h"
  48
  49 #if (NIFPI > 0) && (NPCI > 0)
  50
  51 #include <sys/param.h>
  52 #include <sys/kernel.h>
  53 #include <sys/systm.h>
  54 #include <sys/mbuf.h>
  55
  56 #include <machine/bus.h>
  57 #include <sys/bus.h>
  58 #include <sys/rman.h>
  59 #include <sys/thread2.h>
  60
  61 #include <bus/pci/pcireg.h>
  62 #include <bus/pci/pcivar.h>
  63
  64 #include <sys/socket.h>
  65 #include <net/if.h>
  66
  67 #include <net/i4b/include/machine/i4b_debug.h>
  68 #include <net/i4b/include/machine/i4b_ioctl.h>
  69 #include <net/i4b/include/machine/i4b_trace.h>
  70
  71 #include "../../include/i4b_global.h"
  72 #include "../../include/i4b_mbuf.h"
  73
  74 #include "../i4b_l1.h"
  75 #include "../isic/i4b_isic.h"
  76 #include "../isic/i4b_isac.h"
  77 #include "../isic/i4b_hscx.h"
  78
  79 #include "i4b_ifpi_ext.h"
  80
  81 #define PCI_AVMA1_VID 0x1244
  82 #define PCI_AVMA1_DID 0x0a00
  83
  84 /* prototypes */
  85 static void avma1pp_disable(device_t);
  86
  87 static void avma1pp_intr(void *);
  88 static void hscx_write_reg(int, u_int, u_int, struct l1_softc *);
  89 static u_char hscx_read_reg(int, u_int, struct l1_softc *);
  90 static u_int hscx_read_reg_int(int, u_int, struct l1_softc *);
  91 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
  92 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
  93 static void avma1pp_hscx_int_handler(struct l1_softc *);
  94 static void avma1pp_hscx_intr(int, u_int, struct l1_softc *);
  95 static void avma1pp_init_linktab(struct l1_softc *);
  96 static void avma1pp_bchannel_setup(int, int, int, int);
  97 static void avma1pp_bchannel_start(int, int);
  98 static void avma1pp_hscx_init(struct l1_softc *, int, int);
  99 static void avma1pp_bchannel_stat(int, int, bchan_statistics_t *);
 100 static void avma1pp_set_linktab(int, int, drvr_link_t *);
 101 static isdn_link_t * avma1pp_ret_linktab(int, int);
 102 static int avma1pp_pci_probe(device_t);
 103 static int avma1pp_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
 104 int avma1pp_attach_avma1pp(device_t);
 105 static void ifpi_isac_intr(struct l1_softc *sc);
 106
 107 static device_method_t avma1pp_pci_methods[] = {
 108         /* Device interface */
 109         DEVMETHOD(device_probe,         avma1pp_pci_probe),
 110         DEVMETHOD(device_attach,        avma1pp_attach_avma1pp),
 111         DEVMETHOD(device_shutdown,      avma1pp_disable),
 112
 113         /* bus interface */
 114         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 115         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 116
 117         { 0, 0 }
 118 };
 119
 120 #if 0 /* use what's in l1_softc */
 121 /* a minimal softc for the Fritz!Card PCI */
 122 struct avma1pp_softc
 123 {
 124         bus_space_handle_t      avma1pp_bhandle;
 125         bus_space_tag_t         avma1pp_btag;
 126         void                    *avma1pp_intrhand;
 127         struct resource         *avma1pp_irq;
 128         struct resource         *avma1pp_res;
 129         /* pointer to ifpi_sc */
 130         struct l1_softc *avma1pp_isc;
 131 };
 132 #endif
 133
 134 static driver_t avma1pp_pci_driver = {
 135         "ifpi",
 136         avma1pp_pci_methods,
 137         sizeof(struct l1_softc)
 138 };
 139
 140 static devclass_t avma1pp_pci_devclass;
 141
 142 DRIVER_MODULE(avma1pp, pci, avma1pp_pci_driver, avma1pp_pci_devclass, 0, 0);
 143
 144 /* jump table for multiplex routines */
 145
 146 struct i4b_l1mux_func avma1pp_l1mux_func = {
 147         avma1pp_ret_linktab,
 148         avma1pp_set_linktab,
 149         ifpi_mph_command_req,
 150         ifpi_ph_data_req,
 151         ifpi_ph_activate_req,
 152 };
 153
 154 struct l1_softc *ifpi_scp[IFPI_MAXUNIT];
 155
 156 /*---------------------------------------------------------------------------*
 157  *      AVM PCI Fritz!Card special registers
 158  *---------------------------------------------------------------------------*/
 159
 160 /*
 161  *      register offsets from i/o base
 162  */
 163 #define STAT0_OFFSET            0x02
 164 #define STAT1_OFFSET            0x03
 165 #define ADDR_REG_OFFSET         0x04
 166 /*#define MODREG_OFFSET         0x06
 167 #define VERREG_OFFSET           0x07*/
 168
 169 /* these 2 are used to select an ISAC register set */
 170 #define ISAC_LO_REG_OFFSET      0x04
 171 #define ISAC_HI_REG_OFFSET      0x06
 172
 173 /* offset higher than this goes to the HI register set */
 174 #define MAX_LO_REG_OFFSET       0x2f
 175
 176 /* mask for the offset */
 177 #define ISAC_REGSET_MASK        0x0f
 178
 179 /* the offset from the base to the ISAC registers */
 180 #define ISAC_REG_OFFSET         0x10
 181
 182 /* the offset from the base to the ISAC FIFO */
 183 #define ISAC_FIFO               0x02
 184
 185 /* not really the HSCX, but sort of */
 186 #define HSCX_FIFO               0x00
 187 #define HSCX_STAT               0x04
 188
 189 /*
 190  *      AVM PCI Status Latch 0 read only bits
 191  */
 192 #define ASL_IRQ_ISAC            0x01    /* ISAC  interrupt, active low */
 193 #define ASL_IRQ_HSCX            0x02    /* HSX   interrupt, active low */
 194 #define ASL_IRQ_TIMER           0x04    /* Timer interrupt, active low */
 195 #define ASL_IRQ_BCHAN           ASL_IRQ_HSCX
 196 /* actually active LOW */
 197 #define ASL_IRQ_Pending         (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
 198
 199 /*
 200  *      AVM Status Latch 0 write only bits
 201  */
 202 #define ASL_RESET_ALL           0x01  /* reset siemens IC's, active 1 */
 203 #define ASL_TIMERDISABLE        0x02  /* active high */
 204 #define ASL_TIMERRESET          0x04  /* active high */
 205 #define ASL_ENABLE_INT          0x08  /* active high */
 206 #define ASL_TESTBIT             0x10  /* active high */
 207
 208 /*
 209  *      AVM Status Latch 1 write only bits
 210  */
 211 #define ASL1_INTSEL              0x0f  /* active high */
 212 #define ASL1_ENABLE_IOM          0x80  /* active high */
 213
 214 /*
 215  * "HSCX" mode bits
 216  */
 217 #define  HSCX_MODE_ITF_FLG      0x01
 218 #define  HSCX_MODE_TRANS        0x02
 219 #define  HSCX_MODE_CCR_7        0x04
 220 #define  HSCX_MODE_CCR_16       0x08
 221 #define  HSCX_MODE_TESTLOOP     0x80
 222
 223 /*
 224  * "HSCX" status bits
 225  */
 226 #define  HSCX_STAT_RME          0x01
 227 #define  HSCX_STAT_RDO          0x10
 228 #define  HSCX_STAT_CRCVFRRAB    0x0E
 229 #define  HSCX_STAT_CRCVFR       0x06
 230 #define  HSCX_STAT_RML_MASK     0x3f00
 231
 232 /*
 233  * "HSCX" interrupt bits
 234  */
 235 #define  HSCX_INT_XPR           0x80
 236 #define  HSCX_INT_XDU           0x40
 237 #define  HSCX_INT_RPR           0x20
 238 #define  HSCX_INT_MASK          0xE0
 239
 240 /*
 241  * "HSCX" command bits
 242  */
 243 #define  HSCX_CMD_XRS           0x80
 244 #define  HSCX_CMD_XME           0x01
 245 #define  HSCX_CMD_RRS           0x20
 246 #define  HSCX_CMD_XML_MASK      0x3f00
 247
 248 /*
 249  * Commands and parameters are sent to the "HSCX" as a long, but the
 250  * fields are handled as bytes.
 251  *
 252  * The long contains:
 253  *      (prot << 16)|(txl << 8)|cmd
 254  *
 255  * where:
 256  *      prot = protocol to use
 257  *      txl = transmit length
 258  *      cmd = the command to be executed
 259  *
 260  * The fields are defined as u_char in struct l1_softc.
 261  *
 262  * Macro to coalesce the byte fields into a u_int
 263  */
 264 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
 265                                         | (sc->avma1pp_prot << 16))
 266
 267 /*
 268  * to prevent deactivating the "HSCX" when both channels are active we
 269  * define an HSCX_ACTIVE flag which is or'd into the channel's state
 270  * flag in avma1pp_bchannel_setup upon active and cleared upon deactivation.
 271  * It is set high to allow room for new flags.
 272  */
 273 #define HSCX_AVMA1PP_ACTIVE     0x1000
 274
 275 /*---------------------------------------------------------------------------*
 276  *      AVM read fifo routines
 277  *---------------------------------------------------------------------------*/
 278
 279 static void
 280 avma1pp_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 281 {
 282         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 283         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 284
 285         switch (what) {
 286                 case ISIC_WHAT_ISAC:
 287                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 288                         bus_space_read_multi_1(btag, bhandle,  ISAC_REG_OFFSET, buf, size);
 289                         break;
 290                 case ISIC_WHAT_HSCXA:
 291                         hscx_read_fifo(0, buf, size, sc);
 292                         break;
 293                 case ISIC_WHAT_HSCXB:
 294                         hscx_read_fifo(1, buf, size, sc);
 295                         break;
 296         }
 297 }
 298
 299 static void
 300 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 301 {
 302         u_int32_t *ip;
 303         size_t cnt;
 304         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 305         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 306
 307         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 308         ip = (u_int32_t *)buf;
 309         cnt = 0;
 310         /* what if len isn't a multiple of sizeof(int) and buf is */
 311         /* too small ???? */
 312         while (cnt < len)
 313         {
 314                 *ip++ = bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET);
 315                 cnt += 4;
 316         }
 317 }
 318
 319 /*---------------------------------------------------------------------------*
 320  *      AVM write fifo routines
 321  *---------------------------------------------------------------------------*/
 322 static void
 323 avma1pp_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 324 {
 325         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 326         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 327
 328         switch (what) {
 329                 case ISIC_WHAT_ISAC:
 330                         bus_space_write_1(btag, bhandle,  ADDR_REG_OFFSET, ISAC_FIFO);
 331                         bus_space_write_multi_1(btag, bhandle,  ISAC_REG_OFFSET, (u_int8_t*)buf, size);
 332                         break;
 333                 case ISIC_WHAT_HSCXA:
 334                         hscx_write_fifo(0, buf, size, sc);
 335                         break;
 336                 case ISIC_WHAT_HSCXB:
 337                         hscx_write_fifo(1, buf, size, sc);
 338                         break;
 339         }
 340 }
 341
 342 static void
 343 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
 344 {
 345         u_int32_t *ip;
 346         size_t cnt;
 347         l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
 348         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 349         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 350
 351
 352         sc->avma1pp_cmd &= ~HSCX_CMD_XME;
 353         sc->avma1pp_txl = 0;
 354         if (Bchan->out_mbuf_cur == NULL)
 355         {
 356           if (Bchan->bprot != BPROT_NONE)
 357                  sc->avma1pp_cmd |= HSCX_CMD_XME;
 358         }
 359         if (len != sc->sc_bfifolen)
 360                 sc->avma1pp_txl = len;
 361
 362         cnt = 0; /* borrow cnt */
 363         AVMA1PPSETCMDLONG(cnt);
 364         hscx_write_reg(chan, HSCX_STAT, cnt, sc);
 365
 366         ip = (u_int32_t *)buf;
 367         cnt = 0;
 368         while (cnt < len)
 369         {
 370                 bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET, *ip);
 371                 ip++;
 372                 cnt += 4;
 373         }
 374 }
 375
 376 /*---------------------------------------------------------------------------*
 377  *      AVM write register routines
 378  *---------------------------------------------------------------------------*/
 379
 380 static void
 381 avma1pp_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
 382 {
 383         u_char reg_bank;
 384         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 385         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 386
 387         switch (what) {
 388                 case ISIC_WHAT_ISAC:
 389                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 390 #ifdef AVMA1PCI_DEBUG
 391                         printf("write_reg bank %d  off %ld.. ", (int)reg_bank, (long)offs);
 392 #endif
 393                         /* set the register bank */
 394                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 395                         bus_space_write_1(btag, bhandle, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
 396                         break;
 397                 case ISIC_WHAT_HSCXA:
 398                         hscx_write_reg(0, offs, data, sc);
 399                         break;
 400                 case ISIC_WHAT_HSCXB:
 401                         hscx_write_reg(1, offs, data, sc);
 402                         break;
 403         }
 404 }
 405
 406 static void
 407 hscx_write_reg(int chan, u_int off, u_int val, struct l1_softc *sc)
 408 {
 409         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 410         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 411
 412         /* point at the correct channel */
 413         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 414         bus_space_write_4(btag, bhandle, ISAC_REG_OFFSET + off, val);
 415 }
 416
 417 /*---------------------------------------------------------------------------*
 418  *      AVM read register routines
 419  *---------------------------------------------------------------------------*/
 420 static u_int8_t
 421 avma1pp_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
 422 {
 423         u_char reg_bank;
 424         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 425         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 426
 427         switch (what) {
 428                 case ISIC_WHAT_ISAC:
 429                         reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
 430 #ifdef AVMA1PCI_DEBUG
 431                         printf("read_reg bank %d  off %ld.. ", (int)reg_bank, (long)offs);
 432 #endif
 433                         /* set the register bank */
 434                         bus_space_write_1(btag, bhandle, ADDR_REG_OFFSET, reg_bank);
 435                         return(bus_space_read_1(btag, bhandle, ISAC_REG_OFFSET +
 436                                 (offs & ISAC_REGSET_MASK)));
 437                 case ISIC_WHAT_HSCXA:
 438                         return hscx_read_reg(0, offs, sc);
 439                 case ISIC_WHAT_HSCXB:
 440                         return hscx_read_reg(1, offs, sc);
 441         }
 442         return 0;
 443 }
 444
 445 static u_char
 446 hscx_read_reg(int chan, u_int off, struct l1_softc *sc)
 447 {
 448         return(hscx_read_reg_int(chan, off, sc) & 0xff);
 449 }
 450
 451 /*
 452  * need to be able to return an int because the RBCH is in the 2nd
 453  * byte.
 454  */
 455 static u_int
 456 hscx_read_reg_int(int chan, u_int off, struct l1_softc *sc)
 457 {
 458         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 459         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 460
 461         /* point at the correct channel */
 462         bus_space_write_4(btag, bhandle, ADDR_REG_OFFSET, chan);
 463         return(bus_space_read_4(btag, bhandle, ISAC_REG_OFFSET + off));
 464 }
 465
 466 /*---------------------------------------------------------------------------*
 467  *      avma1pp_probe - probe for a card
 468  *---------------------------------------------------------------------------*/
 469 static int
 470 avma1pp_pci_probe(device_t dev)
 471 {
 472         u_int16_t               did, vid;
 473
 474         vid = pci_get_vendor(dev);
 475         did = pci_get_device(dev);
 476
 477         if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_DID)) {
 478                 device_set_desc(dev, "AVM Fritz!Card PCI");
 479                 return(0);
 480         }
 481
 482         return(ENXIO);
 483 }
 484
 485 /*---------------------------------------------------------------------------*
 486  *      avma1pp_attach_avma1pp - attach Fritz!Card PCI
 487  *---------------------------------------------------------------------------*/
 488 int
 489 avma1pp_attach_avma1pp(device_t dev)
 490 {
 491         struct l1_softc *sc;
 492         u_int v;
 493         int unit, error = 0;
 494         u_int16_t did, vid;
 495         void *ih = 0;
 496         bus_space_handle_t bhandle;
 497         bus_space_tag_t btag;
 498
 499         crit_enter();
 500
 501         vid = pci_get_vendor(dev);
 502         did = pci_get_device(dev);
 503         sc = device_get_softc(dev);
 504         unit = device_get_unit(dev);
 505         bzero(sc, sizeof(struct l1_softc));
 506
 507         /* probably not really required */
 508         if(unit > IFPI_MAXUNIT) {
 509                 printf("avma1pp%d: Error, unit > IFPI_MAXUNIT!\n", unit);
 510                 crit_exit();
 511                 return(ENXIO);
 512         }
 513
 514         if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_DID)) {
 515                 printf("avma1pp%d: unknown device!?\n", unit);
 516                 goto fail;
 517         }
 518
 519         ifpi_scp[unit] = sc;
 520
 521         sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
 522         sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
 523                 &sc->sc_resources.io_rid[0],
 524                 0, ~0, 1, RF_ACTIVE);
 525
 526         if (sc->sc_resources.io_base[0] == NULL) {
 527                 printf("avma1pp%d: couldn't map IO port\n", unit);
 528                 error = ENXIO;
 529                 goto fail;
 530         }
 531
 532         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
 533         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
 534
 535         /* Allocate interrupt */
 536         sc->sc_resources.irq_rid = 0;
 537         sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
 538                 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
 539
 540         if (sc->sc_resources.irq == NULL) {
 541                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 542                 printf("avma1pp%d: couldn't map interrupt\n", unit);
 543                 error = ENXIO;
 544                 goto fail;
 545         }
 546
 547         error = bus_setup_intr(dev, sc->sc_resources.irq, 0,
 548                                avma1pp_intr, sc, &ih, NULL);
 549
 550         if (error) {
 551                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
 552                 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
 553                 printf("avma1pp%d: couldn't set up irq\n", unit);
 554                 goto fail;
 555         }
 556
 557         sc->sc_unit = unit;
 558
 559         /* end of new-bus stuff */
 560
 561         ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
 562
 563         HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
 564         HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
 565
 566         /* setup access routines */
 567
 568         sc->clearirq = NULL;
 569         sc->readreg = avma1pp_read_reg;
 570         sc->writereg = avma1pp_write_reg;
 571
 572         sc->readfifo = avma1pp_read_fifo;
 573         sc->writefifo = avma1pp_write_fifo;
 574
 575         /* setup card type */
 576
 577         sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI;
 578
 579         /* setup IOM bus type */
 580
 581         sc->sc_bustyp = BUS_TYPE_IOM2;
 582
 583         /* set up some other miscellaneous things */
 584         sc->sc_ipac = 0;
 585         sc->sc_bfifolen = HSCX_FIFO_LEN;
 586
 587         /* reset the card */
 588         /* the Linux driver does this to clear any pending ISAC interrupts */
 589         v = 0;
 590         v = ISAC_READ(I_STAR);
 591 #ifdef AVMA1PCI_DEBUG
 592         printf("avma1pp_attach: I_STAR %x...", v);
 593 #endif
 594         v = ISAC_READ(I_MODE);
 595 #ifdef AVMA1PCI_DEBUG
 596         printf("avma1pp_attach: I_MODE %x...", v);
 597 #endif
 598         v = ISAC_READ(I_ADF2);
 599 #ifdef AVMA1PCI_DEBUG
 600         printf("avma1pp_attach: I_ADF2 %x...", v);
 601 #endif
 602         v = ISAC_READ(I_ISTA);
 603 #ifdef AVMA1PCI_DEBUG
 604         printf("avma1pp_attach: I_ISTA %x...", v);
 605 #endif
 606         if (v & ISAC_ISTA_EXI)
 607         {
 608                  v = ISAC_READ(I_EXIR);
 609 #ifdef AVMA1PCI_DEBUG
 610                  printf("avma1pp_attach: I_EXIR %x...", v);
 611 #endif
 612         }
 613         v = ISAC_READ(I_CIRR);
 614 #ifdef AVMA1PCI_DEBUG
 615         printf("avma1pp_attach: I_CIRR %x...", v);
 616 #endif
 617         ISAC_WRITE(I_MASK, 0xff);
 618         /* the Linux driver does this to clear any pending HSCX interrupts */
 619         v = hscx_read_reg_int(0, HSCX_STAT, sc);
 620 #ifdef AVMA1PCI_DEBUG
 621         printf("avma1pp_attach: 0 HSCX_STAT %x...", v);
 622 #endif
 623         v = hscx_read_reg_int(1, HSCX_STAT, sc);
 624 #ifdef AVMA1PCI_DEBUG
 625         printf("avma1pp_attach: 1 HSCX_STAT %x\n", v);
 626 #endif
 627
 628         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
 629         DELAY(SEC_DELAY/100); /* 10 ms */
 630         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
 631         DELAY(SEC_DELAY/100); /* 10 ms */
 632 #ifdef AVMA1PCI_DEBUG
 633         bus_space_write_1(btag, bhandle, STAT1_OFFSET, ASL1_ENABLE_IOM|sc->sc_irq);
 634         DELAY(SEC_DELAY/100); /* 10 ms */
 635         v = bus_space_read_1(btag, bhandle, STAT1_OFFSET);
 636         printf("after reset: S1 %#x\n", v);
 637
 638         v = bus_space_read_4(btag, bhandle, 0);
 639         printf("avma1pp_attach_avma1pp: v %#x\n", v);
 640 #endif
 641
 642    /* from here to the end would normally be done in isic_pciattach */
 643
 644          printf("ifpi%d: ISAC %s (IOM-%c)\n", unit,
 645                 "2085 Version A1/A2 or 2086/2186 Version 1.1",
 646                  sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
 647
 648         /* init the ISAC */
 649         ifpi_isac_init(sc);
 650
 651         /* init the "HSCX" */
 652         avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
 653
 654         avma1pp_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
 655
 656         /* can't use the normal B-Channel stuff */
 657         avma1pp_init_linktab(sc);
 658
 659         /* set trace level */
 660
 661         sc->sc_trace = TRACE_OFF;
 662
 663         sc->sc_state = ISAC_IDLE;
 664
 665         sc->sc_ibuf = NULL;
 666         sc->sc_ib = NULL;
 667         sc->sc_ilen = 0;
 668
 669         sc->sc_obuf = NULL;
 670         sc->sc_op = NULL;
 671         sc->sc_ol = 0;
 672         sc->sc_freeflag = 0;
 673
 674         sc->sc_obuf2 = NULL;
 675         sc->sc_freeflag2 = 0;
 676
 677         callout_init(&sc->sc_T3_timeout);
 678         callout_init(&sc->sc_T4_timeout);
 679
 680         /* init higher protocol layers */
 681
 682         i4b_l1_mph_status_ind(L0IFPIUNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp_l1mux_func);
 683
 684   fail:
 685         crit_exit();
 686         return(error);
 687 }
 688
 689 /*
 690  * this is the real interrupt routine
 691  */
 692 static void
 693 avma1pp_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
 694 {
 695         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
 696         int activity = -1;
 697         u_int param = 0;
 698
 699         NDBGL1(L1_H_IRQ, "%#x", stat);
 700
 701         if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
 702         {
 703                 chan->stat_XDU++;
 704                 NDBGL1(L1_H_XFRERR, "xmit data underrun");
 705                 /* abort the transmission */
 706                 sc->avma1pp_txl = 0;
 707                 sc->avma1pp_cmd |= HSCX_CMD_XRS;
 708                 AVMA1PPSETCMDLONG(param);
 709                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 710                 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
 711                 AVMA1PPSETCMDLONG(param);
 712                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 713
 714                 if (chan->out_mbuf_head != NULL)  /* don't continue to transmit this buffer */
 715                 {
 716                         i4b_Bfreembuf(chan->out_mbuf_head);
 717                         chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
 718                 }
 719         }
 720
 721         /*
 722          * The following is based on examination of the Linux driver.
 723          *
 724          * The logic here is different than with a "real" HSCX; all kinds
 725          * of information (interrupt/status bits) are in stat.
 726          *              HSCX_INT_RPR indicates a receive interrupt
 727          *                      HSCX_STAT_RDO indicates an overrun condition, abort -
 728          *                      otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
 729          *                      HSCX_STAT_RME indicates end-of-frame and apparently any
 730          *                      CRC/framing errors are only reported in this state.
 731          *                              if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
 732          *                                      CRC/framing error
 733          */
 734
 735         if(stat & HSCX_INT_RPR)
 736         {
 737                 int fifo_data_len;
 738                 int error = 0;
 739                 /* always have to read the FIFO, so use a scratch buffer */
 740                 u_char scrbuf[HSCX_FIFO_LEN];
 741
 742                 if(stat & HSCX_STAT_RDO)
 743                 {
 744                         chan->stat_RDO++;
 745                         NDBGL1(L1_H_XFRERR, "receive data overflow");
 746                         error++;
 747                 }
 748
 749                 /*
 750                  * check whether we're receiving data for an inactive B-channel
 751                  * and discard it. This appears to happen for telephony when
 752                  * both B-channels are active and one is deactivated. Since
 753                  * it is not really possible to deactivate the channel in that
 754                  * case (the ASIC seems to deactivate _both_ channels), the
 755                  * "deactivated" channel keeps receiving data which can lead
 756                  * to exhaustion of mbufs and a kernel panic.
 757                  *
 758                  * This is a hack, but it's the only solution I can think of
 759                  * without having the documentation for the ASIC.
 760                  * GJ - 28 Nov 1999
 761                  */
 762                  if (chan->state == HSCX_IDLE)
 763                  {
 764                         NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
 765                         error++;
 766                  }
 767
 768                 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
 769
 770                 if(fifo_data_len == 0)
 771                         fifo_data_len = sc->sc_bfifolen;
 772
 773                 /* ALWAYS read data from HSCX fifo */
 774
 775                 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
 776                 chan->rxcount += fifo_data_len;
 777
 778                 /* all error conditions checked, now decide and take action */
 779
 780                 if(error == 0)
 781                 {
 782                         if(chan->in_mbuf == NULL)
 783                         {
 784                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 785                                         panic("L1 avma1pp_hscx_intr: RME, cannot allocate mbuf!\n");
 786                                 chan->in_cbptr = chan->in_mbuf->m_data;
 787                                 chan->in_len = 0;
 788                         }
 789
 790                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 791                         {
 792                                 /* OK to copy the data */
 793                                 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 794                                 chan->in_cbptr += fifo_data_len;
 795                                 chan->in_len += fifo_data_len;
 796
 797                                 /* setup mbuf data length */
 798
 799                                 chan->in_mbuf->m_len = chan->in_len;
 800                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 801
 802                                 if(sc->sc_trace & TRACE_B_RX)
 803                                 {
 804                                         i4b_trace_hdr_t hdr;
 805                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 806                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 807                                         hdr.dir = FROM_NT;
 808                                         hdr.count = ++sc->sc_trace_bcount;
 809                                         MICROTIME(hdr.time);
 810                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 811                                 }
 812
 813                                 if (stat & HSCX_STAT_RME)
 814                                 {
 815                                   if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
 816                                   {
 817                                          (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 818                                          activity = ACT_RX;
 819
 820                                          /* mark buffer ptr as unused */
 821
 822                                          chan->in_mbuf = NULL;
 823                                          chan->in_cbptr = NULL;
 824                                          chan->in_len = 0;
 825                                   }
 826                                   else
 827                                   {
 828                                                 chan->stat_CRC++;
 829                                                 NDBGL1(L1_H_XFRERR, "CRC/RAB");
 830                                           if (chan->in_mbuf != NULL)
 831                                           {
 832                                                   i4b_Bfreembuf(chan->in_mbuf);
 833                                                   chan->in_mbuf = NULL;
 834                                                   chan->in_cbptr = NULL;
 835                                                   chan->in_len = 0;
 836                                           }
 837                                   }
 838                                 }
 839                         } /* END enough space in mbuf */
 840                         else
 841                         {
 842                                  if(chan->bprot == BPROT_NONE)
 843                                  {
 844                                           /* setup mbuf data length */
 845
 846                                           chan->in_mbuf->m_len = chan->in_len;
 847                                           chan->in_mbuf->m_pkthdr.len = chan->in_len;
 848
 849                                           if(sc->sc_trace & TRACE_B_RX)
 850                                           {
 851                                                         i4b_trace_hdr_t hdr;
 852                                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 853                                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 854                                                         hdr.dir = FROM_NT;
 855                                                         hdr.count = ++sc->sc_trace_bcount;
 856                                                         MICROTIME(hdr.time);
 857                                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 858                                                 }
 859
 860                                           if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 861                                                  activity = ACT_RX;
 862
 863                                           /* move rx'd data to rx queue */
 864
 865                                           if(!(IF_QFULL(&chan->rx_queue)))
 866                                           {
 867                                                 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 868                                           }
 869                                           else
 870                                           {
 871                                                 i4b_Bfreembuf(chan->in_mbuf);
 872                                           }
 873                                           /* signal upper layer that data are available */
 874                                           (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
 875
 876                                           /* alloc new buffer */
 877
 878                                           if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 879                                                  panic("L1 avma1pp_hscx_intr: RPF, cannot allocate new mbuf!\n");
 880
 881                                           /* setup new data ptr */
 882
 883                                           chan->in_cbptr = chan->in_mbuf->m_data;
 884
 885                                           /* OK to copy the data */
 886                                           bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
 887
 888                                           chan->in_cbptr += fifo_data_len;
 889                                           chan->in_len = fifo_data_len;
 890
 891                                           chan->rxcount += fifo_data_len;
 892                                         }
 893                                  else
 894                                         {
 895                                           NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 896                                           chan->in_cbptr = chan->in_mbuf->m_data;
 897                                           chan->in_len = 0;
 898                                         }
 899                           }
 900                 } /* if(error == 0) */
 901                 else
 902                 {
 903                         /* land here for RDO */
 904                         if (chan->in_mbuf != NULL)
 905                         {
 906                                 i4b_Bfreembuf(chan->in_mbuf);
 907                                 chan->in_mbuf = NULL;
 908                                 chan->in_cbptr = NULL;
 909                                 chan->in_len = 0;
 910                         }
 911                         sc->avma1pp_txl = 0;
 912                         sc->avma1pp_cmd |= HSCX_CMD_RRS;
 913                         AVMA1PPSETCMDLONG(param);
 914                         hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 915                         sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
 916                         AVMA1PPSETCMDLONG(param);
 917                         hscx_write_reg(h_chan, HSCX_STAT, param, sc);
 918                 }
 919         }
 920
 921
 922         /* transmit fifo empty, new data can be written to fifo */
 923
 924         if(stat & HSCX_INT_XPR)
 925         {
 926                 /*
 927                  * for a description what is going on here, please have
 928                  * a look at isic_bchannel_start() in i4b_bchan.c !
 929                  */
 930
 931                 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
 932
 933                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 934                 {
 935                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 936
 937                         if(chan->out_mbuf_head == NULL)
 938                         {
 939                                 chan->state &= ~HSCX_TX_ACTIVE;
 940                                 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
 941                         }
 942                         else
 943                         {
 944                                 chan->state |= HSCX_TX_ACTIVE;
 945                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 946                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 947                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 948
 949                                 if(sc->sc_trace & TRACE_B_TX)
 950                                 {
 951                                         i4b_trace_hdr_t hdr;
 952                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
 953                                         hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
 954                                         hdr.dir = FROM_TE;
 955                                         hdr.count = ++sc->sc_trace_bcount;
 956                                         MICROTIME(hdr.time);
 957                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 958                                 }
 959
 960                                 if(chan->bprot == BPROT_NONE)
 961                                 {
 962                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 963                                                 activity = ACT_TX;
 964                                 }
 965                                 else
 966                                 {
 967                                         activity = ACT_TX;
 968                                 }
 969                         }
 970                 }
 971
 972                 avma1pp_hscx_fifo(chan, sc);
 973         }
 974
 975         /* call timeout handling routine */
 976
 977         if(activity == ACT_RX || activity == ACT_TX)
 978                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
 979 }
 980
 981 /*
 982  * this is the main routine which checks each channel and then calls
 983  * the real interrupt routine as appropriate
 984  */
 985 static void
 986 avma1pp_hscx_int_handler(struct l1_softc *sc)
 987 {
 988         u_int stat;
 989
 990         /* has to be a u_int because the byte count is in the 2nd byte */
 991         stat = hscx_read_reg_int(0, HSCX_STAT, sc);
 992         if (stat & HSCX_INT_MASK)
 993           avma1pp_hscx_intr(0, stat, sc);
 994         stat = hscx_read_reg_int(1, HSCX_STAT, sc);
 995         if (stat & HSCX_INT_MASK)
 996           avma1pp_hscx_intr(1, stat, sc);
 997 }
 998
 999 static void
1000 avma1pp_disable(device_t dev)
1001 {
1002         struct l1_softc *sc = device_get_softc(dev);
1003         bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1004         bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1005
1006         bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
1007 }
1008
1009 static void
1010 avma1pp_intr(void *xsc)
1011 {
1012         u_char stat;
1013         struct l1_softc *sc;
1014         bus_space_handle_t bhandle;
1015         bus_space_tag_t btag;
1016
1017         sc = xsc;
1018         bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
1019         btag = rman_get_bustag(sc->sc_resources.io_base[0]);
1020
1021         stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
1022         NDBGL1(L1_H_IRQ, "stat %x", stat);
1023         /* was there an interrupt from this card ? */
1024         if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
1025                 return; /* no */
1026         /* interrupts are low active */
1027         if (!(stat & ASL_IRQ_TIMER))
1028           NDBGL1(L1_H_IRQ, "timer interrupt ???");
1029         if (!(stat & ASL_IRQ_HSCX))
1030         {
1031           NDBGL1(L1_H_IRQ, "HSCX");
1032                 avma1pp_hscx_int_handler(sc);
1033         }
1034         if (!(stat & ASL_IRQ_ISAC))
1035         {
1036           NDBGL1(L1_H_IRQ, "ISAC");
1037                 ifpi_isac_intr(sc);
1038         }
1039 }
1040
1041 static void
1042 avma1pp_hscx_init(struct l1_softc *sc, int h_chan, int activate)
1043 {
1044         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1045         u_int param = 0;
1046
1047         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1048                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1049
1050         if (activate == 0)
1051         {
1052                 /* only deactivate if both channels are idle */
1053                 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
1054                         sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
1055                 {
1056                         return;
1057                 }
1058                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1059                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1060                 AVMA1PPSETCMDLONG(param);
1061                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1062                 return;
1063         }
1064         if(chan->bprot == BPROT_RHDLC)
1065         {
1066                   NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1067
1068                 /* HDLC Frames, transparent mode 0 */
1069                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1070                 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1071                 AVMA1PPSETCMDLONG(param);
1072                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1073                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1074                 AVMA1PPSETCMDLONG(param);
1075                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1076                 sc->avma1pp_cmd = 0;
1077         }
1078         else
1079         {
1080                   NDBGL1(L1_BCHAN, "BPROT_NONE??");
1081
1082                 /* Raw Telephony, extended transparent mode 1 */
1083                 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1084                 sc->avma1pp_prot = HSCX_MODE_TRANS;
1085                 AVMA1PPSETCMDLONG(param);
1086                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1087                 sc->avma1pp_cmd = HSCX_CMD_XRS;
1088                 AVMA1PPSETCMDLONG(param);
1089                 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1090                 sc->avma1pp_cmd = 0;
1091         }
1092 }
1093
1094 static void
1095 avma1pp_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1096 {
1097         struct l1_softc *sc = ifpi_scp[unit];
1098         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1099
1100         crit_enter();
1101
1102         if(activate == 0)
1103         {
1104                 /* deactivation */
1105                 chan->state = HSCX_IDLE;
1106                 avma1pp_hscx_init(sc, h_chan, activate);
1107         }
1108
1109         NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1110                 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1111
1112         /* general part */
1113
1114         chan->unit = sc->sc_unit;       /* unit number */
1115         chan->channel = h_chan;         /* B channel */
1116         chan->bprot = bprot;            /* B channel protocol */
1117         chan->state = HSCX_IDLE;        /* B channel state */
1118
1119         /* receiver part */
1120
1121         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1122
1123         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1124
1125         chan->rxcount = 0;              /* reset rx counter */
1126
1127         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
1128
1129         chan->in_mbuf = NULL;           /* reset mbuf ptr */
1130         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
1131         chan->in_len = 0;               /* reset mbuf data len */
1132
1133         /* transmitter part */
1134
1135         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1136
1137         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1138
1139         chan->txcount = 0;              /* reset tx counter */
1140
1141         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
1142
1143         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
1144         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
1145         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
1146         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
1147
1148         if(activate != 0)
1149         {
1150                 /* activation */
1151                 avma1pp_hscx_init(sc, h_chan, activate);
1152                 chan->state |= HSCX_AVMA1PP_ACTIVE;
1153         }
1154
1155         crit_exit();
1156 }
1157
1158 static void
1159 avma1pp_bchannel_start(int unit, int h_chan)
1160 {
1161         struct l1_softc *sc = ifpi_scp[unit];
1162         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1163         int activity = -1;
1164
1165         crit_enter();
1166         if(chan->state & HSCX_TX_ACTIVE)        /* already running ? */
1167         {
1168                 crit_exit();
1169                 return;                         /* yes, leave */
1170         }
1171
1172         /* get next mbuf from queue */
1173
1174         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1175
1176         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
1177         {
1178                 crit_exit();
1179                 return;                         /* yes, exit */
1180         }
1181
1182         /* init current mbuf values */
1183
1184         chan->out_mbuf_cur = chan->out_mbuf_head;
1185         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1186         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1187
1188         /* activity indicator for timeout handling */
1189
1190         if(chan->bprot == BPROT_NONE)
1191         {
1192                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1193                         activity = ACT_TX;
1194         }
1195         else
1196         {
1197                 activity = ACT_TX;
1198         }
1199
1200         chan->state |= HSCX_TX_ACTIVE;          /* we start transmitting */
1201
1202         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
1203         {
1204                 i4b_trace_hdr_t hdr;
1205                 hdr.unit = L0IFPIUNIT(sc->sc_unit);
1206                 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1207                 hdr.dir = FROM_TE;
1208                 hdr.count = ++sc->sc_trace_bcount;
1209                 MICROTIME(hdr.time);
1210                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1211         }
1212
1213         avma1pp_hscx_fifo(chan, sc);
1214
1215         /* call timeout handling routine */
1216
1217         if(activity == ACT_RX || activity == ACT_TX)
1218                 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1219
1220         crit_exit();
1221 }
1222
1223 /*---------------------------------------------------------------------------*
1224  *      return the address of isic drivers linktab
1225  *---------------------------------------------------------------------------*/
1226 static isdn_link_t *
1227 avma1pp_ret_linktab(int unit, int channel)
1228 {
1229         struct l1_softc *sc = ifpi_scp[unit];
1230         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1231
1232         return(&chan->isic_isdn_linktab);
1233 }
1234
1235 /*---------------------------------------------------------------------------*
1236  *      set the driver linktab in the b channel softc
1237  *---------------------------------------------------------------------------*/
1238 static void
1239 avma1pp_set_linktab(int unit, int channel, drvr_link_t *dlt)
1240 {
1241         struct l1_softc *sc = ifpi_scp[unit];
1242         l1_bchan_state_t *chan = &sc->sc_chan[channel];
1243
1244         chan->isic_drvr_linktab = dlt;
1245 }
1246
1247
1248 /*---------------------------------------------------------------------------*
1249  *      initialize our local linktab
1250  *---------------------------------------------------------------------------*/
1251 static void
1252 avma1pp_init_linktab(struct l1_softc *sc)
1253 {
1254         l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1255         isdn_link_t *lt = &chan->isic_isdn_linktab;
1256
1257         /* make sure the hardware driver is known to layer 4 */
1258         /* avoid overwriting if already set */
1259         if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1260         {
1261                 ctrl_types[CTRL_PASSIVE].set_linktab = avma1pp_set_linktab;
1262                 ctrl_types[CTRL_PASSIVE].get_linktab = avma1pp_ret_linktab;
1263         }
1264
1265         /* local setup */
1266         lt->unit = sc->sc_unit;
1267         lt->channel = HSCX_CH_A;
1268         lt->bch_config = avma1pp_bchannel_setup;
1269         lt->bch_tx_start = avma1pp_bchannel_start;
1270         lt->bch_stat = avma1pp_bchannel_stat;
1271         lt->tx_queue = &chan->tx_queue;
1272
1273         /* used by non-HDLC data transfers, i.e. telephony drivers */
1274         lt->rx_queue = &chan->rx_queue;
1275
1276         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1277         lt->rx_mbuf = &chan->in_mbuf;
1278
1279         chan = &sc->sc_chan[HSCX_CH_B];
1280         lt = &chan->isic_isdn_linktab;
1281
1282         lt->unit = sc->sc_unit;
1283         lt->channel = HSCX_CH_B;
1284         lt->bch_config = avma1pp_bchannel_setup;
1285         lt->bch_tx_start = avma1pp_bchannel_start;
1286         lt->bch_stat = avma1pp_bchannel_stat;
1287         lt->tx_queue = &chan->tx_queue;
1288
1289         /* used by non-HDLC data transfers, i.e. telephony drivers */
1290         lt->rx_queue = &chan->rx_queue;
1291
1292         /* used by HDLC data transfers, i.e. ipr and isp drivers */
1293         lt->rx_mbuf = &chan->in_mbuf;
1294 }
1295
1296 /*
1297  * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1298  */
1299 static void
1300 avma1pp_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1301 {
1302         struct l1_softc *sc = ifpi_scp[unit];
1303         l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1304
1305         crit_enter();
1306
1307         bsp->outbytes = chan->txcount;
1308         bsp->inbytes = chan->rxcount;
1309
1310         chan->txcount = 0;
1311         chan->rxcount = 0;
1312
1313         crit_exit();
1314 }
1315
1316 /*---------------------------------------------------------------------------*
1317  *      fill HSCX fifo with data from the current mbuf
1318  *      Put this here until it can go into i4b_hscx.c
1319  *---------------------------------------------------------------------------*/
1320 static int
1321 avma1pp_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1322 {
1323         int len;
1324         int nextlen;
1325         int i;
1326         int cmd = 0;
1327         /* using a scratch buffer simplifies writing to the FIFO */
1328         u_char scrbuf[HSCX_FIFO_LEN];
1329
1330         len = 0;
1331
1332         /*
1333          * fill the HSCX tx fifo with data from the current mbuf. if
1334          * current mbuf holds less data than HSCX fifo length, try to
1335          * get the next mbuf from (a possible) mbuf chain. if there is
1336          * not enough data in a single mbuf or in a chain, then this
1337          * is the last mbuf and we tell the HSCX that it has to send
1338          * CRC and closing flag
1339          */
1340
1341         while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1342         {
1343                 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1344
1345 #ifdef NOTDEF
1346                 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1347                         chan->out_mbuf_head,
1348                         chan->out_mbuf_cur,
1349                         chan->out_mbuf_cur_ptr,
1350                         chan->out_mbuf_cur_len,
1351                         len,
1352                         nextlen);
1353 #endif
1354
1355                 cmd |= HSCX_CMDR_XTF;
1356                 /* collect the data in the scratch buffer */
1357                 for (i = 0; i < nextlen; i++)
1358                         scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1359
1360                 len += nextlen;
1361                 chan->txcount += nextlen;
1362
1363                 chan->out_mbuf_cur_ptr += nextlen;
1364                 chan->out_mbuf_cur_len -= nextlen;
1365
1366                 if(chan->out_mbuf_cur_len == 0)
1367                 {
1368                         if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1369                         {
1370                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1371                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1372
1373                                 if(sc->sc_trace & TRACE_B_TX)
1374                                 {
1375                                         i4b_trace_hdr_t hdr;
1376                                         hdr.unit = L0IFPIUNIT(sc->sc_unit);
1377                                         hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1378                                         hdr.dir = FROM_TE;
1379                                         hdr.count = ++sc->sc_trace_bcount;
1380                                         MICROTIME(hdr.time);
1381                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1382                                 }
1383                         }
1384                         else
1385                         {
1386                                 if (chan->bprot != BPROT_NONE)
1387                                         cmd |= HSCX_CMDR_XME;
1388                                 i4b_Bfreembuf(chan->out_mbuf_head);
1389                                 chan->out_mbuf_head = NULL;
1390                         }
1391                 }
1392         }
1393         /* write what we have from the scratch buf to the HSCX fifo */
1394         if (len != 0)
1395                 HSCX_WRFIFO(chan->channel, scrbuf, len);
1396         return(cmd);
1397 }
1398
1399 /*---------------------------------------------------------------------------*
1400  *      ifpi - ISAC interrupt routine
1401  *---------------------------------------------------------------------------*/
1402 static void
1403 ifpi_isac_intr(struct l1_softc *sc)
1404 {
1405         u_char isac_irq_stat;
1406
1407         for(;;)
1408         {
1409                 /* get isac irq status */
1410                 isac_irq_stat = ISAC_READ(I_ISTA);
1411
1412                 if(isac_irq_stat)
1413                         ifpi_isac_irq(sc, isac_irq_stat); /* isac handler */
1414                 else
1415                         break;
1416         }
1417
1418         ISAC_WRITE(I_MASK, 0xff);
1419
1420         DELAY(100);
1421
1422         ISAC_WRITE(I_MASK, ISAC_IMASK);
1423 }
1424
1425 /*---------------------------------------------------------------------------*
1426  *      ifpi_recover - try to recover from irq lockup
1427  *---------------------------------------------------------------------------*/
1428 void
1429 ifpi_recover(struct l1_softc *sc)
1430 {
1431         u_char byte;
1432
1433         /* get isac irq status */
1434
1435         byte = ISAC_READ(I_ISTA);
1436
1437         NDBGL1(L1_ERROR, "  ISAC: ISTA = 0x%x", byte);
1438
1439         if(byte & ISAC_ISTA_EXI)
1440                 NDBGL1(L1_ERROR, "  ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1441
1442         if(byte & ISAC_ISTA_CISQ)
1443         {
1444                 byte = ISAC_READ(I_CIRR);
1445
1446                 NDBGL1(L1_ERROR, "  ISAC: CISQ = 0x%x", byte);
1447
1448                 if(byte & ISAC_CIRR_SQC)
1449                         NDBGL1(L1_ERROR, "  ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1450         }
1451
1452         NDBGL1(L1_ERROR, "  ISAC: IMASK = 0x%x", ISAC_IMASK);
1453
1454         ISAC_WRITE(I_MASK, 0xff);
1455         DELAY(100);
1456         ISAC_WRITE(I_MASK, ISAC_IMASK);
1457 }
1458
1459
1460 #endif /* NIFPI > 0 */