3c0fbb9b89c25d85812d5b9546aa1099ac656997
[dragonfly.git] / sys / dev / raid / ciss / cissreg.h
1 /*-
2  * Copyright (c) 2001 Michael Smith
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  *      $FreeBSD: src/sys/dev/ciss/cissreg.h,v 1.1.2.9 2005/12/31 06:28:57 ps Exp $
27  *      $DragonFly: src/sys/dev/raid/ciss/cissreg.h,v 1.2 2003/06/17 04:28:23 dillon Exp $
28  */
29
30 /*
31  * Structure and I/O definitions for the Command Interface for SCSI-3 Support.
32  *
33  * Data in command CDBs are in big-endian format.  All other data is little-endian.
34  * This header only supports little-endian hosts at this time.
35  */
36
37 union ciss_device_address
38 {
39     struct                              /* MODE_PERIPHERAL and MODE_MASK_PERIPHERAL */
40     {
41         u_int32_t       target:24;      /* SCSI target */
42         u_int32_t       bus:6;          /* SCSI bus */
43         u_int32_t       mode:2;         /* CISS_HDR_ADDRESS_MODE_* */
44         u_int32_t       extra_address;  /* SCSI-3 level-2 and level-3 address bytes */
45     } physical;
46     struct                              /* MODE_LOGICAL */
47     {
48         u_int32_t       lun:30;         /* logical device ID */
49         u_int32_t       mode:2;         /* CISS_HDR_ADDRESS_MODE_LOGICAL */
50         u_int32_t       :32;            /* reserved */
51     } logical;
52     struct
53     {
54         u_int32_t       :30;
55         u_int32_t       mode:2;
56         u_int32_t       :32;
57     } mode;
58 };
59 #define CISS_HDR_ADDRESS_MODE_PERIPHERAL        0x0
60 #define CISS_HDR_ADDRESS_MODE_LOGICAL           0x1
61 #define CISS_HDR_ADDRESS_MODE_MASK_PERIPHERAL   0x3
62
63 #define CISS_EXTRA_MODE2(extra)         ((extra & 0xc0000000) >> 30)
64 #define CISS_EXTRA_BUS2(extra)          ((extra & 0x3f000000) >> 24)
65 #define CISS_EXTRA_TARGET2(extra)       ((extra & 0x00ff0000) >> 16)
66 #define CISS_EXTRA_MODE3(extra)         ((extra & 0x0000c000) >> 14)
67 #define CISS_EXTRA_BUS3(extra)          ((extra & 0x00003f00) >> 8)
68 #define CISS_EXTRA_TARGET3(extra)       ((extra & 0x000000ff))
69
70 struct ciss_header
71 {
72     u_int8_t    :8;                     /* reserved */
73     u_int8_t    sg_in_list;             /* SG's in the command structure */
74     u_int16_t   sg_total;               /* total count of SGs for this command */
75     u_int32_t   host_tag;               /* host identifier, bits 0&1 must be clear */
76 #define CISS_HDR_HOST_TAG_ERROR (1<<1)
77     u_int32_t   host_tag_zeroes;        /* tag is 64 bits, but interface only supports 32 */
78     union ciss_device_address address;
79 } __attribute__ ((packed));
80
81 struct ciss_cdb
82 {
83     u_int8_t    cdb_length;             /* valid CDB bytes */
84     u_int8_t    type:3;
85 #define CISS_CDB_TYPE_COMMAND                   0
86 #define CISS_CDB_TYPE_MESSAGE                   1
87     u_int8_t    attribute:3;
88 #define CISS_CDB_ATTRIBUTE_UNTAGGED             0
89 #define CISS_CDB_ATTRIBUTE_SIMPLE               4
90 #define CISS_CDB_ATTRIBUTE_HEAD_OF_QUEUE        5
91 #define CISS_CDB_ATTRIBUTE_ORDERED              6
92 #define CISS_CDB_ATTRIBUTE_AUTO_CONTINGENT      7
93     u_int8_t    direction:2;
94 #define CISS_CDB_DIRECTION_NONE                 0
95 #define CISS_CDB_DIRECTION_WRITE                1
96 #define CISS_CDB_DIRECTION_READ                 2
97     u_int16_t   timeout;                /* seconds */
98 #define CISS_CDB_BUFFER_SIZE    16
99     u_int8_t    cdb[CISS_CDB_BUFFER_SIZE];
100 } __attribute__ ((packed));
101
102 struct ciss_error_info_pointer
103 {
104     u_int64_t   error_info_address;     /* points to ciss_error_info structure */
105     u_int32_t   error_info_length;
106 } __attribute__ ((packed));
107
108 struct ciss_error_info
109 {
110     u_int8_t    scsi_status;
111 #define CISS_SCSI_STATUS_GOOD                   0x00    /* these are scsi-standard values */
112 #define CISS_SCSI_STATUS_CHECK_CONDITION        0x02
113 #define CISS_SCSI_STATUS_CONDITION_MET          0x04
114 #define CISS_SCSI_STATUS_BUSY                   0x08
115 #define CISS_SCSI_STATUS_INDETERMINATE          0x10
116 #define CISS_SCSI_STATUS_INDETERMINATE_CM       0x14
117 #define CISS_SCSI_STATUS_RESERVATION_CONFLICT   0x18
118 #define CISS_SCSI_STATUS_COMMAND_TERMINATED     0x22
119 #define CISS_SCSI_STATUS_QUEUE_FULL             0x28
120 #define CISS_SCSI_STATUS_ACA_ACTIVE             0x30
121     u_int8_t    sense_length;
122     u_int16_t   command_status;
123 #define CISS_CMD_STATUS_SUCCESS                 0
124 #define CISS_CMD_STATUS_TARGET_STATUS           1
125 #define CISS_CMD_STATUS_DATA_UNDERRUN           2
126 #define CISS_CMD_STATUS_DATA_OVERRUN            3
127 #define CISS_CMD_STATUS_INVALID_COMMAND         4
128 #define CISS_CMD_STATUS_PROTOCOL_ERROR          5
129 #define CISS_CMD_STATUS_HARDWARE_ERROR          6
130 #define CISS_CMD_STATUS_CONNECTION_LOST         7
131 #define CISS_CMD_STATUS_ABORTED                 8
132 #define CISS_CMD_STATUS_ABORT_FAILED            9
133 #define CISS_CMD_STATUS_UNSOLICITED_ABORT       10
134 #define CISS_CMD_STATUS_TIMEOUT                 11
135 #define CISS_CMD_STATUS_UNABORTABLE             12
136     u_int32_t   residual_count;
137     union {
138         struct {
139             u_int8_t    res1[3];
140             u_int8_t    type;
141             u_int32_t   error_info;
142         } common_info __attribute__ ((packed));
143         struct {
144             u_int8_t    res1[2];
145             u_int8_t    offense_size;
146             u_int8_t    offense_offset;
147             u_int32_t   offense_value;
148         } invalid_command __attribute__ ((packed));
149     } additional_error_info;
150     u_int8_t    sense_info[0];
151 } __attribute__ ((packed));
152
153 struct ciss_sg_entry
154 {
155     u_int64_t   address;
156 #define CISS_SG_ADDRESS_BITBUCKET       (~(u_int64_t)0)
157     u_int32_t   length;
158     u_int32_t   :31;
159     u_int32_t   extension:1;            /* address points to another s/g chain */
160 } __attribute__ ((packed));
161
162 struct ciss_command
163 {
164     struct ciss_header                  header;
165     struct ciss_cdb                     cdb;
166     struct ciss_error_info_pointer      error_info;
167     struct ciss_sg_entry                sg[0];
168 } __attribute__ ((packed));
169
170 #define CISS_OPCODE_REPORT_LOGICAL_LUNS         0xc2
171 #define CISS_OPCODE_REPORT_PHYSICAL_LUNS        0xc3
172
173 struct ciss_lun_report
174 {
175     u_int32_t   list_size;              /* big-endian */
176     u_int32_t   :32;
177     union ciss_device_address lun[0];
178 } __attribute__ ((packed));
179
180 #define CISS_VPD_LOGICAL_DRIVE_GEOMETRY         0xc1
181 struct ciss_ldrive_geometry
182 {
183     u_int8_t    periph_qualifier:3;
184     u_int8_t    periph_devtype:5;
185     u_int8_t    page_code;
186     u_int8_t    res1;
187     u_int8_t    page_length;
188     u_int16_t   cylinders;              /* big-endian */
189     u_int8_t    heads;
190     u_int8_t    sectors;
191     u_int8_t    fault_tolerance;
192     u_int8_t    res2[3];
193 } __attribute__ ((packed));
194
195 struct ciss_report_cdb
196 {
197     u_int8_t    opcode;
198     u_int8_t    reserved[5];
199     u_int32_t   length;                 /* big-endian */
200     u_int8_t    :8;
201     u_int8_t    control;
202 } __attribute__ ((packed));
203
204 /*
205  * Note that it's not clear whether we have to set the detail field to
206  * the tag of the command to be aborted, or the tag field in the command itself;
207  * documentation conflicts on this.
208  */
209 #define CISS_OPCODE_MESSAGE_ABORT               0x00
210 #define CISS_MESSAGE_ABORT_TASK                 0x00
211 #define CISS_MESSAGE_ABORT_TASK_SET             0x01
212 #define CISS_MESSAGE_ABORT_CLEAR_ACA            0x02
213 #define CISS_MESSAGE_ABORT_CLEAR_TASK_SET       0x03
214
215 #define CISS_OPCODE_MESSAGE_RESET               0x01
216 #define CISS_MESSAGE_RESET_CONTROLLER           0x00
217 #define CISS_MESSAGE_RESET_BUS                  0x01
218 #define CISS_MESSAGE_RESET_TARGET               0x03
219 #define CISS_MESSAGE_RESET_LOGICAL_UNIT         0x04
220
221 #define CISS_OPCODE_MESSAGE_SCAN                0x02
222 #define CISS_MESSAGE_SCAN_CONTROLLER            0x00
223 #define CISS_MESSAGE_SCAN_BUS                   0x01
224 #define CISS_MESSAGE_SCAN_TARGET                0x03
225 #define CISS_MESSAGE_SCAN_LOGICAL_UNIT          0x04
226
227 #define CISS_OPCODE_MESSAGE_NOP                 0x03
228
229 struct ciss_message_cdb
230 {
231     u_int8_t    opcode;
232     u_int8_t    type;
233     u_int16_t   :16;
234     u_int32_t   abort_tag;                                      /* XXX endianness? */
235     u_int8_t    reserved[8];
236 } __attribute__ ((packed));
237
238 /*
239  * CISS vendor-specific commands/messages.
240  *
241  * Note that while messages and vendor-specific commands are
242  * differentiated, they are handled in basically the same way and can
243  * be considered to be basically the same thing, as long as the cdb
244  * type field is set correctly.
245  */
246 #define CISS_OPCODE_READ                0xc0
247 #define CISS_OPCODE_WRITE               0xc1
248 #define CISS_COMMAND_NOTIFY_ON_EVENT    0xd0
249 #define CISS_COMMAND_ABORT_NOTIFY       0xd1
250
251 struct ciss_notify_cdb
252 {
253     u_int8_t    opcode;
254     u_int8_t    command;
255     u_int8_t    res1[2];
256     u_int16_t   timeout;                /* seconds, little-endian */
257     u_int8_t    res2;                   /* reserved */
258     u_int8_t    synchronous:1;          /* return immediately */
259     u_int8_t    ordered:1;              /* return events in recorded order */
260     u_int8_t    seek_to_oldest:1;       /* reset read counter to oldest event */
261     u_int8_t    new_only:1;             /* ignore any queued events */
262     u_int8_t    :4;
263     u_int32_t   length;                 /* must be 512, little-endian */
264 #define CISS_NOTIFY_DATA_SIZE   512
265     u_int8_t    control;
266 } __attribute__ ((packed));
267
268 #define CISS_NOTIFY_NOTIFIER            0
269 #define CISS_NOTIFY_NOTIFIER_STATUS             0
270 #define CISS_NOTIFY_NOTIFIER_PROTOCOL           1
271
272 #define CISS_NOTIFY_HOTPLUG             1
273 #define CISS_NOTIFY_HOTPLUG_PHYSICAL            0
274 #define CISS_NOTIFY_HOTPLUG_POWERSUPPLY         1
275 #define CISS_NOTIFY_HOTPLUG_FAN                 2
276 #define CISS_NOTIFY_HOTPLUG_POWER               3
277 #define CISS_NOTIFY_HOTPLUG_REDUNDANT           4
278 #define CISS_NOTIFY_HOTPLUG_NONDISK             5
279
280 #define CISS_NOTIFY_HARDWARE            2
281 #define CISS_NOTIFY_HARDWARE_CABLES             0
282 #define CISS_NOTIFY_HARDWARE_MEMORY             1
283 #define CISS_NOTIFY_HARDWARE_FAN                2
284 #define CISS_NOTIFY_HARDWARE_VRM                3
285
286 #define CISS_NOTIFY_ENVIRONMENT         3
287 #define CISS_NOTIFY_ENVIRONMENT_TEMPERATURE     0
288 #define CISS_NOTIFY_ENVIRONMENT_POWERSUPPLY     1
289 #define CISS_NOTIFY_ENVIRONMENT_CHASSIS         2
290 #define CISS_NOTIFY_ENVIRONMENT_POWER           3
291
292 #define CISS_NOTIFY_PHYSICAL            4
293 #define CISS_NOTIFY_PHYSICAL_STATE              0
294
295 #define CISS_NOTIFY_LOGICAL             5
296 #define CISS_NOTIFY_LOGICAL_STATUS              0
297 #define CISS_NOTIFY_LOGICAL_ERROR               1
298 #define CISS_NOTIFY_LOGICAL_SURFACE             2
299
300 #define CISS_NOTIFY_REDUNDANT           6
301 #define CISS_NOTIFY_REDUNDANT_STATUS            0
302
303 #define CISS_NOTIFY_CISS                8
304 #define CISS_NOTIFY_CISS_REDUNDANT_CHANGE       0
305 #define CISS_NOTIFY_CISS_PATH_STATUS            1
306 #define CISS_NOTIFY_CISS_HARDWARE_ERROR         2
307 #define CISS_NOTIFY_CISS_LOGICAL                3
308
309 struct ciss_notify_drive
310 {
311     u_int16_t   physical_drive_number;
312     u_int8_t    configured_drive_flag;
313     u_int8_t    spare_drive_flag;
314     u_int8_t    big_physical_drive_number;
315     u_int8_t    enclosure_bay_number;
316 } __attribute__ ((packed));
317
318 struct ciss_notify_locator
319 {
320     u_int16_t   port;
321     u_int16_t   id;
322     u_int16_t   box;
323 } __attribute__ ((packed));
324
325 struct ciss_notify_redundant_controller
326 {
327     u_int16_t   slot;
328 } __attribute__ ((packed));
329
330 struct ciss_notify_logical_status
331 {
332     u_int16_t   logical_drive;
333     u_int8_t    previous_state;
334     u_int8_t    new_state;
335     u_int8_t    spare_state;
336 } __attribute__ ((packed));
337  
338 struct ciss_notify_rebuild_aborted
339 {
340     u_int16_t   logical_drive;
341     u_int8_t    replacement_drive;
342     u_int8_t    error_drive;
343     u_int8_t    big_replacement_drive;
344     u_int8_t    big_error_drive;
345 } __attribute__ ((packed));
346
347 struct ciss_notify_io_error
348 {
349     u_int16_t   logical_drive;
350     u_int32_t   lba;
351     u_int16_t   block_count;
352     u_int8_t    command;
353     u_int8_t    failure_bus;
354     u_int8_t    failure_drive;
355     u_int64_t   big_lba;
356 } __attribute__ ((packed));
357
358 struct ciss_notify_consistency_completed
359 {
360     u_int16_t   logical_drive;
361 } __attribute__ ((packed));
362
363 struct ciss_notify
364 {
365     u_int32_t   timestamp;              /* seconds since controller power-on */
366     u_int16_t   class;
367     u_int16_t   subclass;
368     u_int16_t   detail;
369     union
370     {
371         struct ciss_notify_drive                drive;
372         struct ciss_notify_locator              location;
373         struct ciss_notify_redundant_controller redundant_controller;
374         struct ciss_notify_logical_status       logical_status;
375         struct ciss_notify_rebuild_aborted      rebuild_aborted;
376         struct ciss_notify_io_error             io_error;
377         struct ciss_notify_consistency_completed consistency_completed;
378         u_int8_t        data[64];
379     } data;
380     char        message[80];
381     u_int32_t   tag;
382     u_int16_t   date;
383     u_int16_t   year;
384     u_int32_t   time;
385     u_int16_t   pre_power_up_time;
386     union ciss_device_address   device;
387     /* XXX pads to 512 bytes */
388 } __attribute__ ((packed));
389
390 /*
391  * CISS config table, which describes the controller's
392  * supported interface(s) and capabilities.
393  *
394  * This is mapped directly via PCI.
395  */
396 struct ciss_config_table
397 {
398     char        signature[4];           /* "CISS" */
399     u_int32_t   valence;
400     u_int32_t   supported_methods;
401 #define CISS_TRANSPORT_METHOD_READY     (1<<0)
402 #define CISS_TRANSPORT_METHOD_SIMPLE    (1<<1)
403     u_int32_t   active_method;
404     u_int32_t   requested_method;
405     u_int32_t   command_physlimit;
406     u_int32_t   interrupt_coalesce_delay;
407     u_int32_t   interrupt_coalesce_count;
408     u_int32_t   max_outstanding_commands;
409     u_int32_t   bus_types;
410 #define CISS_TRANSPORT_BUS_TYPE_ULTRA2  (1<<0)
411 #define CISS_TRANSPORT_BUS_TYPE_ULTRA3  (1<<1)
412 #define CISS_TRANSPORT_BUS_TYPE_FIBRE1  (1<<8)
413 #define CISS_TRANSPORT_BUS_TYPE_FIBRE2  (1<<9)
414     u_int32_t   transport_offset;
415     char        server_name[16];
416     u_int32_t   heartbeat;
417     u_int32_t   host_driver;
418 #define CISS_DRIVER_SUPPORT_UNIT_ATTENTION      (1<<0)
419 #define CISS_DRIVER_QUICK_INIT                  (1<<1)
420 #define CISS_DRIVER_INTERRUPT_ON_LOCKUP         (1<<2)
421 #define CISS_DRIVER_SUPPORT_MIXED_Q_TAGS        (1<<3)
422 #define CISS_DRIVER_HOST_IS_ALPHA               (1<<4)
423 #define CISS_DRIVER_MULTI_LUN_SUPPORT           (1<<5)
424 #define CISS_DRIVER_MESSAGE_REQUESTS_SUPPORTED  (1<<7)
425 #define CISS_DRIVER_DAUGHTER_ATTACHED           (1<<8)
426 #define CISS_DRIVER_SCSI_PREFETCH               (1<<9)
427     u_int32_t   max_sg_length;          /* 31 in older firmware */
428 } __attribute__ ((packed));
429
430 /*
431  * In a flagrant violation of what CISS seems to be meant to be about,
432  * Compaq recycle a goodly portion of their previous generation's
433  * command set (and all the legacy baggage related to a design
434  * originally aimed at narrow SCSI) through the Array Controller Read
435  * and Array Controller Write interface.
436  *
437  * Command ID values here can be looked up for in the
438  * publically-available documentation for the older controllers; note
439  * that the command layout is necessarily different to fit within the
440  * CDB.
441  */
442 #define CISS_ARRAY_CONTROLLER_READ      0x26
443 #define CISS_ARRAY_CONTROLLER_WRITE     0x27
444
445 #define CISS_BMIC_ID_LDRIVE             0x10
446 #define CISS_BMIC_ID_CTLR               0x11
447 #define CISS_BMIC_ID_LSTATUS            0x12
448 #define CISS_BMIC_ID_PDRIVE             0x15
449 #define CISS_BMIC_BLINK_PDRIVE          0x16
450 #define CISS_BMIC_SENSE_BLINK_PDRIVE    0x17
451 #define CISS_BMIC_FLUSH_CACHE           0xc2
452 #define CISS_BMIC_ACCEPT_MEDIA          0xe0
453
454 /*
455  * When numbering drives, the original design assumed that
456  * drives 0-7 are on the first SCSI bus, 8-15 on the second,
457  * and so forth.  In order to handle modern SCSI configurations,
458  * the MSB is set in the drive ID field, in which case the
459  * modulus changes from 8 to the number of supported drives
460  * per SCSI bus (as obtained from the ID_CTLR command).
461  * This feature is referred to as BIG_MAP support, and we assume
462  * that all CISS controllers support it.
463  */
464
465 #define CISS_BIG_MAP_ID(sc, bus, target)                \
466         (0x80 |                                         \
467          ((sc)->ciss_id->drives_per_scsi_bus * (bus)) | \
468          (target))
469
470 #define CISS_BIG_MAP_BUS(sc, id)                        \
471         (((id) & 0x80) ? (((id) & ~0x80) / (sc)->ciss_id->drives_per_scsi_bus) : -1)
472
473 #define CISS_BIG_MAP_TARGET(sc, id)                     \
474         (((id) & 0x80) ? (((id) & ~0x80) % (sc)->ciss_id->drives_per_scsi_bus) : -1)
475
476 #define CISS_BIG_MAP_ENTRIES    128     /* number of entries in a BIG_MAP */
477
478 /*
479  * In the device address of a logical volume, the bus number
480  * is encoded into the logical lun volume number starting
481  * at the second byte, with the first byte defining the
482  * logical drive number.
483  */
484 #define CISS_LUN_TO_BUS(x)    (((x) >> 16) & 0xFF)
485 #define CISS_LUN_TO_TARGET(x) ((x) & 0xFF)
486
487 /*
488  * BMIC CDB
489  *
490  * Note that the phys_drive/res1 field is nominally the 32-bit
491  * "block number" field, but the only BMIC command(s) of interest
492  * implemented overload the MSB (note big-endian format here)
493  * to be the physical drive ID, so we define accordingly.
494  */
495 struct ciss_bmic_cdb {
496     u_int8_t    opcode;
497     u_int8_t    log_drive;
498     u_int8_t    phys_drive;
499     u_int8_t    res1[3];
500     u_int8_t    bmic_opcode;
501     u_int16_t   size;                   /* big-endian */
502     u_int8_t    res2;
503 } __attribute__ ((packed));
504
505 /*
506  * BMIC command command/return structures.
507  */
508
509 /* CISS_BMIC_ID_LDRIVE */
510 struct ciss_bmic_id_ldrive {
511     u_int16_t   block_size;
512     u_int32_t   blocks_available;
513     u_int8_t    drive_parameter_table[16];      /* XXX define */
514     u_int8_t    fault_tolerance;
515 #define CISS_LDRIVE_RAID0       0
516 #define CISS_LDRIVE_RAID4       1
517 #define CISS_LDRIVE_RAID1       2
518 #define CISS_LDRIVE_RAID5       3
519 #define CISS_LDRIVE_RAID51      4
520 #define CISS_LDRIVE_RAIDADG     5
521     u_int8_t    res1;
522     u_int8_t    bios_disable_flag;
523     u_int8_t    res2;
524     u_int32_t   logical_drive_identifier;
525     char        logical_drive_label[64];
526     u_int64_t   big_blocks_available;
527     u_int8_t    res3[410];
528 } __attribute__ ((packed));
529
530 /* CISS_BMIC_ID_LSTATUS */
531 struct ciss_bmic_id_lstatus {
532     u_int8_t    status;
533 #define CISS_LSTATUS_OK                         0
534 #define CISS_LSTATUS_FAILED                     1
535 #define CISS_LSTATUS_NOT_CONFIGURED             2
536 #define CISS_LSTATUS_INTERIM_RECOVERY           3
537 #define CISS_LSTATUS_READY_RECOVERY             4
538 #define CISS_LSTATUS_RECOVERING                 5
539 #define CISS_LSTATUS_WRONG_PDRIVE               6
540 #define CISS_LSTATUS_MISSING_PDRIVE             7
541 #define CISS_LSTATUS_EXPANDING                  10
542 #define CISS_LSTATUS_BECOMING_READY             11
543 #define CISS_LSTATUS_QUEUED_FOR_EXPANSION       12
544     u_int32_t   deprecated_drive_failure_map;
545     u_int8_t    res1[416];
546     u_int32_t   blocks_to_recover;
547     u_int8_t    deprecated_drive_rebuilding;
548     u_int16_t   deprecated_remap_count[32];
549     u_int32_t   deprecated_replacement_map;
550     u_int32_t   deprecated_active_spare_map;
551     u_int8_t    spare_configured:1;
552     u_int8_t    spare_rebuilding:1;
553     u_int8_t    spare_rebuilt:1;
554     u_int8_t    spare_failed:1;
555     u_int8_t    spare_switched:1;
556     u_int8_t    spare_available:1;
557     u_int8_t    res2:2;
558     u_int8_t    deprecated_spare_to_replace_map[32];
559     u_int32_t   deprecated_replaced_marked_ok_map;
560     u_int8_t    media_exchanged;
561     u_int8_t    cache_failure;
562     u_int8_t    expand_failure;
563     u_int8_t    rebuild_read_failure:1;
564     u_int8_t    rebuild_write_failure:1;
565     u_int8_t    res3:6;
566     u_int8_t    drive_failure_map[CISS_BIG_MAP_ENTRIES / 8];
567     u_int16_t   remap_count[CISS_BIG_MAP_ENTRIES];
568     u_int8_t    replacement_map[CISS_BIG_MAP_ENTRIES / 8];
569     u_int8_t    active_spare_map[CISS_BIG_MAP_ENTRIES / 8];
570     u_int8_t    spare_to_replace_map[CISS_BIG_MAP_ENTRIES];
571     u_int8_t    replaced_marked_ok_map[CISS_BIG_MAP_ENTRIES / 8];
572     u_int8_t    drive_rebuilding;
573     u_int64_t   big_blocks_to_recover;
574     u_int8_t    res4[28];
575 } __attribute__ ((packed));
576
577 /* CISS_BMIC_ID_CTLR */
578 struct ciss_bmic_id_table {
579     u_int8_t    configured_logical_drives;
580     u_int32_t   config_signature;
581     char        running_firmware_revision[4];
582     char        stored_firmware_revision[4];
583     u_int8_t    hardware_revision;
584     u_int8_t    res1[4];
585     u_int32_t   deprecated_drive_present_map;
586     u_int32_t   deprecated_external_drive_present_map;
587     u_int32_t   board_id;
588     u_int8_t    res2;
589     u_int32_t   deprecated_non_disk_map;
590     u_int8_t    res3[5];
591     char        marketting_revision;
592     u_int8_t    res4:3;
593     u_int8_t    more_than_seven_supported:1;
594     u_int8_t    res5:3;
595     u_int8_t    big_map_supported:1;            /* must be set! */
596     u_int8_t    res6[2];
597     u_int8_t    scsi_bus_count;
598     u_int32_t   res7;
599     u_int32_t   controller_clock;
600     u_int8_t    drives_per_scsi_bus;
601     u_int8_t    big_drive_present_map[CISS_BIG_MAP_ENTRIES / 8];
602     u_int8_t    big_external_drive_present_map[CISS_BIG_MAP_ENTRIES / 8];
603     u_int8_t    big_non_disk_map[CISS_BIG_MAP_ENTRIES / 8];
604 } __attribute__ ((packed));
605
606 /* CISS_BMIC_ID_PDRIVE */
607 struct ciss_bmic_id_pdrive {
608     u_int8_t    scsi_bus;
609     u_int8_t    scsi_id;
610     u_int16_t   block_size;
611     u_int32_t   total_blocks;
612     u_int32_t   reserved_blocks;
613     char        model[40];
614     char        serial[40];
615     char        revision[8];
616     u_int8_t    inquiry_bits;
617     u_int8_t    res1[2];
618     u_int8_t    drive_present:1;
619     u_int8_t    non_disk:1;
620     u_int8_t    wide:1;
621     u_int8_t    synchronous:1;
622     u_int8_t    narrow:1;
623     u_int8_t    wide_downgraded_to_narrow:1;
624     u_int8_t    ultra:1;
625     u_int8_t    ultra2:1;
626     u_int8_t    SMART:1;
627     u_int8_t    SMART_errors_recorded:1;
628     u_int8_t    SMART_errors_enabled:1;
629     u_int8_t    SMART_errors_detected:1;
630     u_int8_t    external:1;
631     u_int8_t    configured:1;
632     u_int8_t    configured_spare:1;
633     u_int8_t    cache_saved_enabled:1;
634     u_int8_t    res2;
635     u_int8_t    res3:6;
636     u_int8_t    cache_currently_enabled:1;
637     u_int8_t    cache_safe:1;
638     u_int8_t    res4[5];
639     char        connector[2];
640     u_int8_t    res5;
641     u_int8_t    bay;
642     u_int16_t   rpm;
643     u_int8_t    drive_type;
644     u_int8_t    res6[393];
645 } __attribute__ ((packed));
646
647 /* CISS_BMIC_BLINK_PDRIVE */
648 /* CISS_BMIC_SENSE_BLINK_PDRIVE */
649 struct ciss_bmic_blink_pdrive {
650     u_int32_t   blink_duration;         /* 10ths of a second */
651     u_int32_t   duration_elapsed;       /* only for sense command  */
652     u_int8_t    blinktab[256];
653 #define CISS_BMIC_BLINK_ALL     1
654 #define CISS_BMIC_BLINK_TIMED   2
655     u_int8_t    res2[248];
656 } __attribute__ ((packed));
657
658 /* CISS_BMIC_FLUSH_CACHE */
659 struct ciss_bmic_flush_cache {
660     u_int16_t   flag;
661 #define CISS_BMIC_FLUSH_AND_ENABLE      0
662 #define CISS_BMIC_FLUSH_AND_DISABLE     1
663     u_int8_t    res1[510];
664 } __attribute__ ((packed));
665
666 #ifdef _KERNEL
667 /*
668  * CISS "simple" transport layer.
669  *
670  * Note that there are two slightly different versions of this interface
671  * with different interrupt mask bits.  There's nothing like consistency...
672  */
673 #define CISS_TL_SIMPLE_BAR_REGS 0x10    /* BAR pointing to register space */
674 #define CISS_TL_SIMPLE_BAR_CFG  0x14    /* BAR pointing to space containing config table */
675
676 #define CISS_TL_SIMPLE_IDBR     0x20    /* inbound doorbell register */
677 #define CISS_TL_SIMPLE_IDBR_CFG_TABLE   (1<<0)  /* notify controller of config table update */
678
679 #define CISS_TL_SIMPLE_ISR      0x30    /* interrupt status register */
680 #define CISS_TL_SIMPLE_IMR      0x34    /* interrupt mask register */
681 #define CISS_TL_SIMPLE_INTR_OPQ_SA5     (1<<3)  /* OPQ not empty interrupt, SA5 boards */
682 #define CISS_TL_SIMPLE_INTR_OPQ_SA5B    (1<<2)  /* OPQ not empty interrupt, SA5B boards */
683
684 #define CISS_TL_SIMPLE_IPQ      0x40    /* inbound post queue */
685 #define CISS_TL_SIMPLE_OPQ      0x44    /* outbound post queue */
686 #define CISS_TL_SIMPLE_OPQ_EMPTY        (~(u_int32_t)0)
687
688 #define CISS_TL_SIMPLE_CFG_BAR  0xb4    /* should be 0x14 */
689 #define CISS_TL_SIMPLE_CFG_OFF  0xb8    /* offset in BAR at which config table is located */
690
691 /*
692  * Register access primitives.
693  */
694 #define CISS_TL_SIMPLE_READ(sc, ofs) \
695         bus_space_read_4(sc->ciss_regs_btag, sc->ciss_regs_bhandle, ofs)
696 #define CISS_TL_SIMPLE_WRITE(sc, ofs, val) \
697         bus_space_write_4(sc->ciss_regs_btag, sc->ciss_regs_bhandle, ofs, val)
698
699 #define CISS_TL_SIMPLE_POST_CMD(sc, phys)       CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IPQ, phys)
700 #define CISS_TL_SIMPLE_FETCH_CMD(sc)            CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_OPQ)
701
702 /*
703  * XXX documentation conflicts with the Linux driver as to whether setting or clearing
704  *     bits masks interrupts
705  */
706 #define CISS_TL_SIMPLE_DISABLE_INTERRUPTS(sc) \
707         CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, \
708                              CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR) | (sc)->ciss_interrupt_mask)
709 #define CISS_TL_SIMPLE_ENABLE_INTERRUPTS(sc) \
710         CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, \
711                              CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR) & ~(sc)->ciss_interrupt_mask)
712
713 #define CISS_TL_SIMPLE_OPQ_INTERRUPT(sc) \
714         (CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_ISR) & (sc)->ciss_interrupt_mask)
715
716 #endif /* _KERNEL */