kernel - Fix a case in if_re which could lockup the system
[dragonfly.git] / sys / dev / netif / re / if_re.c
1 /*
2  * Copyright (c) 2004
3  *      Joerg Sonnenberger <joerg@bec.de>.  All rights reserved.
4  *
5  * Copyright (c) 1997, 1998-2003
6  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *      This product includes software developed by Bill Paul.
19  * 4. Neither the name of the author nor the names of any co-contributors
20  *    may be used to endorse or promote products derived from this software
21  *    without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33  * THE POSSIBILITY OF SUCH DAMAGE.
34  *
35  * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36  */
37
38 /*
39  * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
40  *
41  * Written by Bill Paul <wpaul@windriver.com>
42  * Senior Networking Software Engineer
43  * Wind River Systems
44  */
45
46 /*
47  * This driver is designed to support RealTek's next generation of
48  * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
49  * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
50  * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
51  *
52  * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
53  * with the older 8139 family, however it also supports a special
54  * C+ mode of operation that provides several new performance enhancing
55  * features. These include:
56  *
57  *      o Descriptor based DMA mechanism. Each descriptor represents
58  *        a single packet fragment. Data buffers may be aligned on
59  *        any byte boundary.
60  *
61  *      o 64-bit DMA
62  *
63  *      o TCP/IP checksum offload for both RX and TX
64  *
65  *      o High and normal priority transmit DMA rings
66  *
67  *      o VLAN tag insertion and extraction
68  *
69  *      o TCP large send (segmentation offload)
70  *
71  * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
72  * programming API is fairly straightforward. The RX filtering, EEPROM
73  * access and PHY access is the same as it is on the older 8139 series
74  * chips.
75  *
76  * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
77  * same programming API and feature set as the 8139C+ with the following
78  * differences and additions:
79  *
80  *      o 1000Mbps mode
81  *
82  *      o Jumbo frames
83  *
84  *      o GMII and TBI ports/registers for interfacing with copper
85  *        or fiber PHYs
86  *
87  *      o RX and TX DMA rings can have up to 1024 descriptors
88  *        (the 8139C+ allows a maximum of 64)
89  *
90  *      o Slight differences in register layout from the 8139C+
91  *
92  * The TX start and timer interrupt registers are at different locations
93  * on the 8169 than they are on the 8139C+. Also, the status word in the
94  * RX descriptor has a slightly different bit layout. The 8169 does not
95  * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96  * copper gigE PHY.
97  *
98  * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
99  * (the 'S' stands for 'single-chip'). These devices have the same
100  * programming API as the older 8169, but also have some vendor-specific
101  * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
102  * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
103  * 
104  * This driver takes advantage of the RX and TX checksum offload and
105  * VLAN tag insertion/extraction features. It also implements TX
106  * interrupt moderation using the timer interrupt registers, which
107  * significantly reduces TX interrupt load. There is also support
108  * for jumbo frames, however the 8169/8169S/8110S can not transmit
109  * jumbo frames larger than 7440, so the max MTU possible with this
110  * driver is 7422 bytes.
111  */
112
113 #define _IP_VHL
114
115 #include "opt_polling.h"
116
117 #include <sys/param.h>
118 #include <sys/bus.h>
119 #include <sys/endian.h>
120 #include <sys/kernel.h>
121 #include <sys/in_cksum.h>
122 #include <sys/interrupt.h>
123 #include <sys/malloc.h>
124 #include <sys/mbuf.h>
125 #include <sys/rman.h>
126 #include <sys/serialize.h>
127 #include <sys/socket.h>
128 #include <sys/sockio.h>
129 #include <sys/sysctl.h>
130
131 #include <net/bpf.h>
132 #include <net/ethernet.h>
133 #include <net/if.h>
134 #include <net/ifq_var.h>
135 #include <net/if_arp.h>
136 #include <net/if_dl.h>
137 #include <net/if_media.h>
138 #include <net/if_types.h>
139 #include <net/vlan/if_vlan_var.h>
140 #include <net/vlan/if_vlan_ether.h>
141
142 #include <netinet/ip.h>
143
144 #include <dev/netif/mii_layer/mii.h>
145 #include <dev/netif/mii_layer/miivar.h>
146
147 #include <bus/pci/pcidevs.h>
148 #include <bus/pci/pcireg.h>
149 #include <bus/pci/pcivar.h>
150
151 /* "device miibus" required.  See GENERIC if you get errors here. */
152 #include "miibus_if.h"
153
154 #include <dev/netif/re/if_rereg.h>
155 #include <dev/netif/re/if_revar.h>
156
157 #define RE_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
158
159 /*
160  * Various supported device vendors/types and their names.
161  */
162 static const struct re_type {
163         uint16_t        re_vid;
164         uint16_t        re_did;
165         const char      *re_name;
166 } re_devs[] = {
167         { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T,
168           "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
169
170         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
171           "RealTek 8139C+ 10/100BaseTX" },
172
173         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E,
174           "RealTek 810x PCIe 10/100baseTX" },
175
176         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168,
177           "RealTek 8111/8168 PCIe Gigabit Ethernet" },
178
179         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169,
180           "RealTek 8110/8169 Gigabit Ethernet" },
181
182         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC,
183           "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
184
185         { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT,
186           "Corega CG-LAPCIGT Gigabit Ethernet" },
187
188         { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032,
189           "Linksys EG1032 Gigabit Ethernet" },
190
191         { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902,
192           "US Robotics 997902 Gigabit Ethernet" },
193
194         { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322,
195           "TTTech MC322 Gigabit Ethernet" },
196
197         { 0, 0, NULL }
198 };
199
200 static const struct re_hwrev re_hwrevs[] = {
201         { RE_HWREV_8139CPLUS,   RE_MACVER_UNKN,         ETHERMTU,
202           RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE },
203
204         { RE_HWREV_8169,        RE_MACVER_UNKN,         ETHERMTU,
205           RE_C_HWCSUM | RE_C_8169 },
206
207         { RE_HWREV_8110S,       RE_MACVER_03,           RE_MTU_6K,
208           RE_C_HWCSUM | RE_C_8169 },
209
210         { RE_HWREV_8169S,       RE_MACVER_03,           RE_MTU_6K,
211           RE_C_HWCSUM | RE_C_8169 },
212
213         { RE_HWREV_8169SB,      RE_MACVER_04,           RE_MTU_6K,
214           RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
215
216         { RE_HWREV_8169SC1,     RE_MACVER_05,           RE_MTU_6K,
217           RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
218
219         { RE_HWREV_8169SC2,     RE_MACVER_06,           RE_MTU_6K,
220           RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
221
222         { RE_HWREV_8168B1,      RE_MACVER_21,           RE_MTU_6K,
223           RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT },
224
225         { RE_HWREV_8168B2,      RE_MACVER_23,           RE_MTU_6K,
226           RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
227
228         { RE_HWREV_8168B3,      RE_MACVER_23,           RE_MTU_6K,
229           RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
230
231         { RE_HWREV_8168C,       RE_MACVER_29,           RE_MTU_6K,
232           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
233           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
234
235         { RE_HWREV_8168CP,      RE_MACVER_2B,           RE_MTU_6K,
236           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
237           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
238
239         { RE_HWREV_8168D,       RE_MACVER_2A,           RE_MTU_9K,
240           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
241           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
242
243         { RE_HWREV_8168DP,      RE_MACVER_2D,           RE_MTU_9K,
244           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
245           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
246
247         { RE_HWREV_8168E,       RE_MACVER_UNKN,         RE_MTU_9K,
248           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
249           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
250
251         { RE_HWREV_8168F,       RE_MACVER_UNKN,         RE_MTU_9K,
252           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
253           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
254
255         { RE_HWREV_8100E,       RE_MACVER_UNKN,         ETHERMTU,
256           RE_C_HWCSUM | RE_C_FASTE },
257
258         { RE_HWREV_8101E1,      RE_MACVER_16,           ETHERMTU,
259           RE_C_HWCSUM | RE_C_FASTE },
260
261         { RE_HWREV_8101E2,      RE_MACVER_16,           ETHERMTU,
262           RE_C_HWCSUM | RE_C_FASTE },
263
264         { RE_HWREV_8102E,       RE_MACVER_15,           ETHERMTU,
265           RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
266           RE_C_FASTE },
267
268         { RE_HWREV_8102EL,      RE_MACVER_15,           ETHERMTU,
269           RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
270           RE_C_FASTE },
271
272         { RE_HWREV_NULL, 0, 0, 0 }
273 };
274
275 static int      re_probe(device_t);
276 static int      re_attach(device_t);
277 static int      re_detach(device_t);
278 static int      re_suspend(device_t);
279 static int      re_resume(device_t);
280 static void     re_shutdown(device_t);
281
282 static int      re_allocmem(device_t);
283 static void     re_freemem(device_t);
284 static void     re_freebufmem(struct re_softc *, int, int);
285 static int      re_encap(struct re_softc *, struct mbuf **, int *);
286 static int      re_newbuf_std(struct re_softc *, int, int);
287 static int      re_newbuf_jumbo(struct re_softc *, int, int);
288 static void     re_setup_rxdesc(struct re_softc *, int);
289 static int      re_rx_list_init(struct re_softc *);
290 static int      re_tx_list_init(struct re_softc *);
291 static int      re_rxeof(struct re_softc *);
292 static int      re_txeof(struct re_softc *);
293 static int      re_tx_collect(struct re_softc *);
294 static void     re_intr(void *);
295 static void     re_tick(void *);
296 static void     re_tick_serialized(void *);
297
298 static void     re_start(struct ifnet *);
299 static int      re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
300 static void     re_init(void *);
301 static void     re_stop(struct re_softc *);
302 static void     re_watchdog(struct ifnet *);
303 static int      re_ifmedia_upd(struct ifnet *);
304 static void     re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
305
306 static void     re_eeprom_putbyte(struct re_softc *, int);
307 static void     re_eeprom_getword(struct re_softc *, int, u_int16_t *);
308 static void     re_read_eeprom(struct re_softc *, caddr_t, int, int);
309 static void     re_get_eewidth(struct re_softc *);
310
311 static int      re_gmii_readreg(device_t, int, int);
312 static int      re_gmii_writereg(device_t, int, int, int);
313
314 static int      re_miibus_readreg(device_t, int, int);
315 static int      re_miibus_writereg(device_t, int, int, int);
316 static void     re_miibus_statchg(device_t);
317
318 static void     re_setmulti(struct re_softc *);
319 static void     re_reset(struct re_softc *, int);
320 static void     re_get_eaddr(struct re_softc *, uint8_t *);
321
322 static void     re_setup_hw_im(struct re_softc *);
323 static void     re_setup_sim_im(struct re_softc *);
324 static void     re_disable_hw_im(struct re_softc *);
325 static void     re_disable_sim_im(struct re_softc *);
326 static void     re_config_imtype(struct re_softc *, int);
327 static void     re_setup_intr(struct re_softc *, int, int);
328
329 static int      re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *);
330 static int      re_sysctl_rxtime(SYSCTL_HANDLER_ARGS);
331 static int      re_sysctl_txtime(SYSCTL_HANDLER_ARGS);
332 static int      re_sysctl_simtime(SYSCTL_HANDLER_ARGS);
333 static int      re_sysctl_imtype(SYSCTL_HANDLER_ARGS);
334
335 static int      re_jpool_alloc(struct re_softc *);
336 static void     re_jpool_free(struct re_softc *);
337 static struct re_jbuf *re_jbuf_alloc(struct re_softc *);
338 static void     re_jbuf_free(void *);
339 static void     re_jbuf_ref(void *);
340
341 #ifdef RE_DIAG
342 static int      re_diag(struct re_softc *);
343 #endif
344
345 #ifdef DEVICE_POLLING
346 static void     re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
347 #endif
348
349 static device_method_t re_methods[] = {
350         /* Device interface */
351         DEVMETHOD(device_probe,         re_probe),
352         DEVMETHOD(device_attach,        re_attach),
353         DEVMETHOD(device_detach,        re_detach),
354         DEVMETHOD(device_suspend,       re_suspend),
355         DEVMETHOD(device_resume,        re_resume),
356         DEVMETHOD(device_shutdown,      re_shutdown),
357
358         /* bus interface */
359         DEVMETHOD(bus_print_child,      bus_generic_print_child),
360         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
361
362         /* MII interface */
363         DEVMETHOD(miibus_readreg,       re_miibus_readreg),
364         DEVMETHOD(miibus_writereg,      re_miibus_writereg),
365         DEVMETHOD(miibus_statchg,       re_miibus_statchg),
366
367         { 0, 0 }
368 };
369
370 static driver_t re_driver = {
371         "re",
372         re_methods,
373         sizeof(struct re_softc)
374 };
375
376 static devclass_t re_devclass;
377
378 DECLARE_DUMMY_MODULE(if_re);
379 MODULE_DEPEND(if_re, miibus, 1, 1, 1);
380 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, NULL, NULL);
381 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, NULL, NULL);
382 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, NULL, NULL);
383
384 static int      re_rx_desc_count = RE_RX_DESC_CNT_DEF;
385 static int      re_tx_desc_count = RE_TX_DESC_CNT_DEF;
386
387 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count);
388 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count);
389
390 #define EE_SET(x)       \
391         CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
392
393 #define EE_CLR(x)       \
394         CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
395
396 static __inline void
397 re_free_rxchain(struct re_softc *sc)
398 {
399         if (sc->re_head != NULL) {
400                 m_freem(sc->re_head);
401                 sc->re_head = sc->re_tail = NULL;
402         }
403 }
404
405 /*
406  * Send a read command and address to the EEPROM, check for ACK.
407  */
408 static void
409 re_eeprom_putbyte(struct re_softc *sc, int addr)
410 {
411         int d, i;
412
413         d = addr | (RE_9346_READ << sc->re_eewidth);
414
415         /*
416          * Feed in each bit and strobe the clock.
417          */
418         for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
419                 if (d & i)
420                         EE_SET(RE_EE_DATAIN);
421                 else
422                         EE_CLR(RE_EE_DATAIN);
423                 DELAY(100);
424                 EE_SET(RE_EE_CLK);
425                 DELAY(150);
426                 EE_CLR(RE_EE_CLK);
427                 DELAY(100);
428         }
429 }
430
431 /*
432  * Read a word of data stored in the EEPROM at address 'addr.'
433  */
434 static void
435 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
436 {
437         int i;
438         uint16_t word = 0;
439
440         /*
441          * Send address of word we want to read.
442          */
443         re_eeprom_putbyte(sc, addr);
444
445         /*
446          * Start reading bits from EEPROM.
447          */
448         for (i = 0x8000; i != 0; i >>= 1) {
449                 EE_SET(RE_EE_CLK);
450                 DELAY(100);
451                 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
452                         word |= i;
453                 EE_CLR(RE_EE_CLK);
454                 DELAY(100);
455         }
456
457         *dest = word;
458 }
459
460 /*
461  * Read a sequence of words from the EEPROM.
462  */
463 static void
464 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
465 {
466         int i;
467         uint16_t word = 0, *ptr;
468
469         CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
470         DELAY(100);
471
472         for (i = 0; i < cnt; i++) {
473                 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
474                 re_eeprom_getword(sc, off + i, &word);
475                 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
476                 ptr = (uint16_t *)(dest + (i * 2));
477                 *ptr = word;
478         }
479
480         CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
481 }
482
483 static void
484 re_get_eewidth(struct re_softc *sc)
485 {
486         uint16_t re_did = 0;
487
488         sc->re_eewidth = 6;
489         re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
490         if (re_did != 0x8129)
491                 sc->re_eewidth = 8;
492 }
493
494 static int
495 re_gmii_readreg(device_t dev, int phy, int reg)
496 {
497         struct re_softc *sc = device_get_softc(dev);
498         u_int32_t rval;
499         int i;
500
501         if (phy != 1)
502                 return(0);
503
504         /* Let the rgephy driver read the GMEDIASTAT register */
505
506         if (reg == RE_GMEDIASTAT)
507                 return(CSR_READ_1(sc, RE_GMEDIASTAT));
508
509         CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
510         DELAY(1000);
511
512         for (i = 0; i < RE_TIMEOUT; i++) {
513                 rval = CSR_READ_4(sc, RE_PHYAR);
514                 if (rval & RE_PHYAR_BUSY)
515                         break;
516                 DELAY(100);
517         }
518
519         if (i == RE_TIMEOUT) {
520                 device_printf(dev, "PHY read failed\n");
521                 return(0);
522         }
523
524         return(rval & RE_PHYAR_PHYDATA);
525 }
526
527 static int
528 re_gmii_writereg(device_t dev, int phy, int reg, int data)
529 {
530         struct re_softc *sc = device_get_softc(dev);
531         uint32_t rval;
532         int i;
533
534         CSR_WRITE_4(sc, RE_PHYAR,
535                     (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
536         DELAY(1000);
537
538         for (i = 0; i < RE_TIMEOUT; i++) {
539                 rval = CSR_READ_4(sc, RE_PHYAR);
540                 if ((rval & RE_PHYAR_BUSY) == 0)
541                         break;
542                 DELAY(100);
543         }
544
545         if (i == RE_TIMEOUT)
546                 device_printf(dev, "PHY write failed\n");
547
548         return(0);
549 }
550
551 static int
552 re_miibus_readreg(device_t dev, int phy, int reg)
553 {
554         struct re_softc *sc = device_get_softc(dev);
555         uint16_t rval = 0;
556         uint16_t re8139_reg = 0;
557
558         if (!RE_IS_8139CP(sc)) {
559                 rval = re_gmii_readreg(dev, phy, reg);
560                 return(rval);
561         }
562
563         /* Pretend the internal PHY is only at address 0 */
564         if (phy)
565                 return(0);
566
567         switch(reg) {
568         case MII_BMCR:
569                 re8139_reg = RE_BMCR;
570                 break;
571         case MII_BMSR:
572                 re8139_reg = RE_BMSR;
573                 break;
574         case MII_ANAR:
575                 re8139_reg = RE_ANAR;
576                 break;
577         case MII_ANER:
578                 re8139_reg = RE_ANER;
579                 break;
580         case MII_ANLPAR:
581                 re8139_reg = RE_LPAR;
582                 break;
583         case MII_PHYIDR1:
584         case MII_PHYIDR2:
585                 return(0);
586         /*
587          * Allow the rlphy driver to read the media status
588          * register. If we have a link partner which does not
589          * support NWAY, this is the register which will tell
590          * us the results of parallel detection.
591          */
592         case RE_MEDIASTAT:
593                 return(CSR_READ_1(sc, RE_MEDIASTAT));
594         default:
595                 device_printf(dev, "bad phy register\n");
596                 return(0);
597         }
598         rval = CSR_READ_2(sc, re8139_reg);
599         if (re8139_reg == RE_BMCR) {
600                 /* 8139C+ has different bit layout. */
601                 rval &= ~(BMCR_LOOP | BMCR_ISO);
602         }
603         return(rval);
604 }
605
606 static int
607 re_miibus_writereg(device_t dev, int phy, int reg, int data)
608 {
609         struct re_softc *sc= device_get_softc(dev);
610         u_int16_t re8139_reg = 0;
611
612         if (!RE_IS_8139CP(sc))
613                 return(re_gmii_writereg(dev, phy, reg, data));
614
615         /* Pretend the internal PHY is only at address 0 */
616         if (phy)
617                 return(0);
618
619         switch(reg) {
620         case MII_BMCR:
621                 re8139_reg = RE_BMCR;
622                 /* 8139C+ has different bit layout. */
623                 data &= ~(BMCR_LOOP | BMCR_ISO);
624                 break;
625         case MII_BMSR:
626                 re8139_reg = RE_BMSR;
627                 break;
628         case MII_ANAR:
629                 re8139_reg = RE_ANAR;
630                 break;
631         case MII_ANER:
632                 re8139_reg = RE_ANER;
633                 break;
634         case MII_ANLPAR:
635                 re8139_reg = RE_LPAR;
636                 break;
637         case MII_PHYIDR1:
638         case MII_PHYIDR2:
639                 return(0);
640         default:
641                 device_printf(dev, "bad phy register\n");
642                 return(0);
643         }
644         CSR_WRITE_2(sc, re8139_reg, data);
645         return(0);
646 }
647
648 static void
649 re_miibus_statchg(device_t dev)
650 {
651 }
652
653 /*
654  * Program the 64-bit multicast hash filter.
655  */
656 static void
657 re_setmulti(struct re_softc *sc)
658 {
659         struct ifnet *ifp = &sc->arpcom.ac_if;
660         int h = 0;
661         uint32_t hashes[2] = { 0, 0 };
662         struct ifmultiaddr *ifma;
663         uint32_t rxfilt;
664         int mcnt = 0;
665
666         rxfilt = CSR_READ_4(sc, RE_RXCFG);
667
668         /* Set the individual bit to receive frames for this host only. */
669         rxfilt |= RE_RXCFG_RX_INDIV;
670         /* Set capture broadcast bit to capture broadcast frames. */
671         rxfilt |= RE_RXCFG_RX_BROAD;
672
673         rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI);
674         if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) {
675                 rxfilt |= RE_RXCFG_RX_MULTI;
676
677                 /* If we want promiscuous mode, set the allframes bit. */
678                 if (ifp->if_flags & IFF_PROMISC)
679                         rxfilt |= RE_RXCFG_RX_ALLPHYS;
680
681                 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
682                 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
683                 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
684                 return;
685         }
686
687         /* first, zot all the existing hash bits */
688         CSR_WRITE_4(sc, RE_MAR0, 0);
689         CSR_WRITE_4(sc, RE_MAR4, 0);
690
691         /* now program new ones */
692         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
693                 if (ifma->ifma_addr->sa_family != AF_LINK)
694                         continue;
695                 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
696                     ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
697                 if (h < 32)
698                         hashes[0] |= (1 << h);
699                 else
700                         hashes[1] |= (1 << (h - 32));
701                 mcnt++;
702         }
703
704         if (mcnt)
705                 rxfilt |= RE_RXCFG_RX_MULTI;
706         else
707                 rxfilt &= ~RE_RXCFG_RX_MULTI;
708
709         CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
710
711         /*
712          * For some unfathomable reason, RealTek decided to reverse
713          * the order of the multicast hash registers in the PCI Express
714          * parts. This means we have to write the hash pattern in reverse
715          * order for those devices.
716          */
717         if (sc->re_caps & RE_C_PCIE) {
718                 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[1]));
719                 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[0]));
720         } else {
721                 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
722                 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
723         }
724 }
725
726 static void
727 re_reset(struct re_softc *sc, int running)
728 {
729         int i;
730
731         if ((sc->re_caps & RE_C_STOP_RXTX) && running) {
732                 CSR_WRITE_1(sc, RE_COMMAND,
733                             RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB);
734                 DELAY(100);
735         }
736
737         CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
738
739         for (i = 0; i < RE_TIMEOUT; i++) {
740                 DELAY(10);
741                 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
742                         break;
743         }
744         if (i == RE_TIMEOUT)
745                 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
746 }
747
748 #ifdef RE_DIAG
749 /*
750  * The following routine is designed to test for a defect on some
751  * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
752  * lines connected to the bus, however for a 32-bit only card, they
753  * should be pulled high. The result of this defect is that the
754  * NIC will not work right if you plug it into a 64-bit slot: DMA
755  * operations will be done with 64-bit transfers, which will fail
756  * because the 64-bit data lines aren't connected.
757  *
758  * There's no way to work around this (short of talking a soldering
759  * iron to the board), however we can detect it. The method we use
760  * here is to put the NIC into digital loopback mode, set the receiver
761  * to promiscuous mode, and then try to send a frame. We then compare
762  * the frame data we sent to what was received. If the data matches,
763  * then the NIC is working correctly, otherwise we know the user has
764  * a defective NIC which has been mistakenly plugged into a 64-bit PCI
765  * slot. In the latter case, there's no way the NIC can work correctly,
766  * so we print out a message on the console and abort the device attach.
767  */
768
769 static int
770 re_diag(struct re_softc *sc)
771 {
772         struct ifnet *ifp = &sc->arpcom.ac_if;
773         struct mbuf *m0;
774         struct ether_header *eh;
775         struct re_desc *cur_rx;
776         uint16_t status;
777         uint32_t rxstat;
778         int total_len, i, error = 0, phyaddr;
779         uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
780         uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
781
782         /* Allocate a single mbuf */
783
784         MGETHDR(m0, MB_DONTWAIT, MT_DATA);
785         if (m0 == NULL)
786                 return(ENOBUFS);
787
788         /*
789          * Initialize the NIC in test mode. This sets the chip up
790          * so that it can send and receive frames, but performs the
791          * following special functions:
792          * - Puts receiver in promiscuous mode
793          * - Enables digital loopback mode
794          * - Leaves interrupts turned off
795          */
796
797         ifp->if_flags |= IFF_PROMISC;
798         sc->re_flags |= RE_F_TESTMODE;
799         re_init(sc);
800         sc->re_flags |= RE_F_LINKED;
801         if (!RE_IS_8139CP(sc))
802                 phyaddr = 1;
803         else
804                 phyaddr = 0;
805
806         re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
807         for (i = 0; i < RE_TIMEOUT; i++) {
808                 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
809                 if (!(status & BMCR_RESET))
810                         break;
811         }
812
813         re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
814         CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
815
816         DELAY(100000);
817
818         /* Put some data in the mbuf */
819
820         eh = mtod(m0, struct ether_header *);
821         bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
822         bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
823         eh->ether_type = htons(ETHERTYPE_IP);
824         m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
825
826         /*
827          * Queue the packet, start transmission.
828          * Note: ifq_handoff() ultimately calls re_start() for us.
829          */
830
831         CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
832         error = ifq_handoff(ifp, m0, NULL);
833         if (error) {
834                 m0 = NULL;
835                 goto done;
836         }
837         m0 = NULL;
838
839         /* Wait for it to propagate through the chip */
840
841         DELAY(100000);
842         for (i = 0; i < RE_TIMEOUT; i++) {
843                 status = CSR_READ_2(sc, RE_ISR);
844                 CSR_WRITE_2(sc, RE_ISR, status);
845                 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
846                     (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
847                         break;
848                 DELAY(10);
849         }
850
851         if (i == RE_TIMEOUT) {
852                 if_printf(ifp, "diagnostic failed to receive packet "
853                           "in loopback mode\n");
854                 error = EIO;
855                 goto done;
856         }
857
858         /*
859          * The packet should have been dumped into the first
860          * entry in the RX DMA ring. Grab it from there.
861          */
862
863         bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0],
864                         BUS_DMASYNC_POSTREAD);
865         bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
866                           sc->re_ldata.re_rx_dmamap[0]);
867
868         m0 = sc->re_ldata.re_rx_mbuf[0];
869         sc->re_ldata.re_rx_mbuf[0] = NULL;
870         eh = mtod(m0, struct ether_header *);
871
872         cur_rx = &sc->re_ldata.re_rx_list[0];
873         total_len = RE_RXBYTES(cur_rx);
874         rxstat = le32toh(cur_rx->re_cmdstat);
875
876         if (total_len != ETHER_MIN_LEN) {
877                 if_printf(ifp, "diagnostic failed, received short packet\n");
878                 error = EIO;
879                 goto done;
880         }
881
882         /* Test that the received packet data matches what we sent. */
883
884         if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
885             bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
886             be16toh(eh->ether_type) != ETHERTYPE_IP) {
887                 if_printf(ifp, "WARNING, DMA FAILURE!\n");
888                 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
889                     dst, ":", src, ":", ETHERTYPE_IP);
890                 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
891                     eh->ether_dhost, ":",  eh->ether_shost, ":",
892                     ntohs(eh->ether_type));
893                 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
894                     "into a 64-bit PCI slot.\n");
895                 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
896                     "for proper operation.\n");
897                 if_printf(ifp, "Read the re(4) man page for more details.\n");
898                 error = EIO;
899         }
900
901 done:
902         /* Turn interface off, release resources */
903
904         sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE);
905         ifp->if_flags &= ~IFF_PROMISC;
906         re_stop(sc);
907         if (m0 != NULL)
908                 m_freem(m0);
909
910         return (error);
911 }
912 #endif  /* RE_DIAG */
913
914 /*
915  * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
916  * IDs against our list and return a device name if we find a match.
917  */
918 static int
919 re_probe(device_t dev)
920 {
921         const struct re_type *t;
922         const struct re_hwrev *hw_rev;
923         struct re_softc *sc;
924         int rid;
925         uint32_t hwrev, macmode, txcfg;
926         uint16_t vendor, product;
927
928         vendor = pci_get_vendor(dev);
929         product = pci_get_device(dev);
930
931         /*
932          * Only attach to rev.3 of the Linksys EG1032 adapter.
933          * Rev.2 is supported by sk(4).
934          */
935         if (vendor == PCI_VENDOR_LINKSYS &&
936             product == PCI_PRODUCT_LINKSYS_EG1032 &&
937             pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
938                 return ENXIO;
939
940         if (vendor == PCI_VENDOR_REALTEK &&
941             product == PCI_PRODUCT_REALTEK_RT8139 &&
942             pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) {
943                 /* Poor 8139 */
944                 return ENXIO;
945         }
946
947         for (t = re_devs; t->re_name != NULL; t++) {
948                 if (product == t->re_did && vendor == t->re_vid)
949                         break;
950         }
951
952         /*
953          * Check if we found a RealTek device.
954          */
955         if (t->re_name == NULL)
956                 return ENXIO;
957
958         /*
959          * Temporarily map the I/O space so we can read the chip ID register.
960          */
961         sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
962         rid = RE_PCI_LOIO;
963         sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
964                                             RF_ACTIVE);
965         if (sc->re_res == NULL) {
966                 device_printf(dev, "couldn't map ports/memory\n");
967                 kfree(sc, M_TEMP);
968                 return ENXIO;
969         }
970
971         sc->re_btag = rman_get_bustag(sc->re_res);
972         sc->re_bhandle = rman_get_bushandle(sc->re_res);
973
974         txcfg = CSR_READ_4(sc, RE_TXCFG);
975         hwrev = txcfg & RE_TXCFG_HWREV;
976         macmode = txcfg & RE_TXCFG_MACMODE;
977         bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
978         kfree(sc, M_TEMP);
979
980         /*
981          * and continue matching for the specific chip...
982          */
983         for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) {
984                 if (hw_rev->re_hwrev == hwrev) {
985                         sc = device_get_softc(dev);
986
987                         sc->re_hwrev = hw_rev->re_hwrev;
988                         sc->re_macver = hw_rev->re_macver;
989                         sc->re_caps = hw_rev->re_caps;
990                         sc->re_maxmtu = hw_rev->re_maxmtu;
991
992                         /*
993                          * Apply chip property fixup
994                          */
995                         switch (sc->re_hwrev) {
996                         case RE_HWREV_8101E1:
997                         case RE_HWREV_8101E2:
998                                 if (macmode == 0)
999                                         sc->re_macver = RE_MACVER_11;
1000                                 else if (macmode == 0x200000)
1001                                         sc->re_macver = RE_MACVER_12;
1002                                 break;
1003                         case RE_HWREV_8102E:
1004                         case RE_HWREV_8102EL:
1005                                 if (macmode == 0)
1006                                         sc->re_macver = RE_MACVER_13;
1007                                 else if (macmode == 0x100000)
1008                                         sc->re_macver = RE_MACVER_14;
1009                                 break;
1010                         case RE_HWREV_8168B2:
1011                         case RE_HWREV_8168B3:
1012                                 if (macmode == 0)
1013                                         sc->re_macver = RE_MACVER_22;
1014                                 break;
1015                         case RE_HWREV_8168C:
1016                                 if (macmode == 0)
1017                                         sc->re_macver = RE_MACVER_24;
1018                                 else if (macmode == 0x200000)
1019                                         sc->re_macver = RE_MACVER_25;
1020                                 else if (macmode == 0x300000)
1021                                         sc->re_macver = RE_MACVER_27;
1022                                 break;
1023                         case RE_HWREV_8168CP:
1024                                 if (macmode == 0)
1025                                         sc->re_macver = RE_MACVER_26;
1026                                 else if (macmode == 0x100000)
1027                                         sc->re_macver = RE_MACVER_28;
1028                                 break;
1029                         case RE_HWREV_8168DP:
1030                                 if (macmode == 0)
1031                                         sc->re_macver = RE_MACVER_2B;
1032                                 else if (macmode == 0x200000)
1033                                         sc->re_macver = RE_MACVER_2C;
1034                                 break;
1035                         case RE_HWREV_8168E:
1036                                 if (macmode == 0x100000)
1037                                         sc->re_macver = RE_MACVER_2E;
1038                                 else if (macmode == 0x200000)
1039                                         sc->re_macver = RE_MACVER_2F;
1040                                 break;
1041                         case RE_HWREV_8168F:
1042                                 if (macmode == 0x000000)
1043                                         sc->re_macver = RE_MACVER_30;
1044                                 else if (macmode == 0x100000)
1045                                         sc->re_macver = RE_MACVER_31;
1046                                 break;
1047                         }
1048                         if (pci_is_pcie(dev))
1049                                 sc->re_caps |= RE_C_PCIE;
1050
1051                         device_set_desc(dev, t->re_name);
1052                         return 0;
1053                 }
1054         }
1055
1056         if (bootverbose) {
1057                 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n",
1058                               hwrev, macmode);
1059         }
1060         return ENXIO;
1061 }
1062
1063 static int
1064 re_allocmem(device_t dev)
1065 {
1066         struct re_softc *sc = device_get_softc(dev);
1067         bus_dmamem_t dmem;
1068         int error, i;
1069
1070         /*
1071          * Allocate list data
1072          */
1073         sc->re_ldata.re_tx_mbuf =
1074         kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *),
1075                 M_DEVBUF, M_ZERO | M_WAITOK);
1076
1077         sc->re_ldata.re_rx_mbuf =
1078         kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *),
1079                 M_DEVBUF, M_ZERO | M_WAITOK);
1080
1081         sc->re_ldata.re_rx_paddr =
1082         kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t),
1083                 M_DEVBUF, M_ZERO | M_WAITOK);
1084
1085         sc->re_ldata.re_tx_dmamap =
1086         kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t),
1087                 M_DEVBUF, M_ZERO | M_WAITOK);
1088
1089         sc->re_ldata.re_rx_dmamap =
1090         kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t),
1091                 M_DEVBUF, M_ZERO | M_WAITOK);
1092
1093         /*
1094          * Allocate the parent bus DMA tag appropriate for PCI.
1095          */
1096         error = bus_dma_tag_create(NULL,        /* parent */
1097                         1, 0,                   /* alignment, boundary */
1098                         BUS_SPACE_MAXADDR,      /* lowaddr */
1099                         BUS_SPACE_MAXADDR,      /* highaddr */
1100                         NULL, NULL,             /* filter, filterarg */
1101                         BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
1102                         0,                      /* nsegments */
1103                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1104                         0,                      /* flags */
1105                         &sc->re_parent_tag);
1106         if (error) {
1107                 device_printf(dev, "could not allocate parent dma tag\n");
1108                 return error;
1109         }
1110
1111         /* Allocate TX descriptor list. */
1112         error = bus_dmamem_coherent(sc->re_parent_tag,
1113                         RE_RING_ALIGN, 0,
1114                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1115                         RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
1116                         &dmem);
1117         if (error) {
1118                 device_printf(dev, "could not allocate TX ring\n");
1119                 return error;
1120         }
1121         sc->re_ldata.re_tx_list_tag = dmem.dmem_tag;
1122         sc->re_ldata.re_tx_list_map = dmem.dmem_map;
1123         sc->re_ldata.re_tx_list = dmem.dmem_addr;
1124         sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr;
1125
1126         /* Allocate RX descriptor list. */
1127         error = bus_dmamem_coherent(sc->re_parent_tag,
1128                         RE_RING_ALIGN, 0,
1129                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1130                         RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
1131                         &dmem);
1132         if (error) {
1133                 device_printf(dev, "could not allocate RX ring\n");
1134                 return error;
1135         }
1136         sc->re_ldata.re_rx_list_tag = dmem.dmem_tag;
1137         sc->re_ldata.re_rx_list_map = dmem.dmem_map;
1138         sc->re_ldata.re_rx_list = dmem.dmem_addr;
1139         sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr;
1140
1141         /* Allocate maps for TX mbufs. */
1142         error = bus_dma_tag_create(sc->re_parent_tag,
1143                         1, 0,
1144                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1145                         NULL, NULL,
1146                         RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES,
1147                         BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1148                         &sc->re_ldata.re_tx_mtag);
1149         if (error) {
1150                 device_printf(dev, "could not allocate TX buf dma tag\n");
1151                 return(error);
1152         }
1153
1154         /* Create DMA maps for TX buffers */
1155         for (i = 0; i < sc->re_tx_desc_cnt; i++) {
1156                 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag,
1157                                 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1158                                 &sc->re_ldata.re_tx_dmamap[i]);
1159                 if (error) {
1160                         device_printf(dev, "can't create DMA map for TX buf\n");
1161                         re_freebufmem(sc, i, 0);
1162                         return(error);
1163                 }
1164         }
1165
1166         /* Allocate maps for RX mbufs. */
1167         error = bus_dma_tag_create(sc->re_parent_tag,
1168                         RE_RXBUF_ALIGN, 0,
1169                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1170                         NULL, NULL,
1171                         MCLBYTES, 1, MCLBYTES,
1172                         BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,
1173                         &sc->re_ldata.re_rx_mtag);
1174         if (error) {
1175                 device_printf(dev, "could not allocate RX buf dma tag\n");
1176                 return(error);
1177         }
1178
1179         /* Create spare DMA map for RX */
1180         error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK,
1181                         &sc->re_ldata.re_rx_spare);
1182         if (error) {
1183                 device_printf(dev, "can't create spare DMA map for RX\n");
1184                 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
1185                 sc->re_ldata.re_rx_mtag = NULL;
1186                 return error;
1187         }
1188
1189         /* Create DMA maps for RX buffers */
1190         for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1191                 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag,
1192                                 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]);
1193                 if (error) {
1194                         device_printf(dev, "can't create DMA map for RX buf\n");
1195                         re_freebufmem(sc, sc->re_tx_desc_cnt, i);
1196                         return(error);
1197                 }
1198         }
1199
1200         /* Create jumbo buffer pool for RX if required */
1201         if (sc->re_caps & RE_C_CONTIGRX) {
1202                 error = re_jpool_alloc(sc);
1203                 if (error) {
1204                         re_jpool_free(sc);
1205                         /* Disable jumbo frame support */
1206                         sc->re_maxmtu = ETHERMTU;
1207                 }
1208         }
1209         return(0);
1210 }
1211
1212 static void
1213 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt)
1214 {
1215         int i;
1216
1217         /* Destroy all the RX and TX buffer maps */
1218         if (sc->re_ldata.re_tx_mtag) {
1219                 for (i = 0; i < tx_cnt; i++) {
1220                         bus_dmamap_destroy(sc->re_ldata.re_tx_mtag,
1221                                            sc->re_ldata.re_tx_dmamap[i]);
1222                 }
1223                 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag);
1224                 sc->re_ldata.re_tx_mtag = NULL;
1225         }
1226
1227         if (sc->re_ldata.re_rx_mtag) {
1228                 for (i = 0; i < rx_cnt; i++) {
1229                         bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
1230                                            sc->re_ldata.re_rx_dmamap[i]);
1231                 }
1232                 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
1233                                    sc->re_ldata.re_rx_spare);
1234                 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
1235                 sc->re_ldata.re_rx_mtag = NULL;
1236         }
1237 }
1238
1239 static void
1240 re_freemem(device_t dev)
1241 {
1242         struct re_softc *sc = device_get_softc(dev);
1243
1244         /* Unload and free the RX DMA ring memory and map */
1245         if (sc->re_ldata.re_rx_list_tag) {
1246                 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1247                                   sc->re_ldata.re_rx_list_map);
1248                 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1249                                 sc->re_ldata.re_rx_list,
1250                                 sc->re_ldata.re_rx_list_map);
1251                 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1252         }
1253
1254         /* Unload and free the TX DMA ring memory and map */
1255         if (sc->re_ldata.re_tx_list_tag) {
1256                 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1257                                   sc->re_ldata.re_tx_list_map);
1258                 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1259                                 sc->re_ldata.re_tx_list,
1260                                 sc->re_ldata.re_tx_list_map);
1261                 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1262         }
1263
1264         /* Free RX/TX buf DMA stuffs */
1265         re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt);
1266
1267         /* Unload and free the stats buffer and map */
1268         if (sc->re_ldata.re_stag) {
1269                 bus_dmamap_unload(sc->re_ldata.re_stag, sc->re_ldata.re_smap);
1270                 bus_dmamem_free(sc->re_ldata.re_stag,
1271                                 sc->re_ldata.re_stats,
1272                                 sc->re_ldata.re_smap);
1273                 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1274         }
1275
1276         if (sc->re_caps & RE_C_CONTIGRX)
1277                 re_jpool_free(sc);
1278
1279         if (sc->re_parent_tag)
1280                 bus_dma_tag_destroy(sc->re_parent_tag);
1281
1282         if (sc->re_ldata.re_tx_mbuf != NULL)
1283                 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF);
1284         if (sc->re_ldata.re_rx_mbuf != NULL)
1285                 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF);
1286         if (sc->re_ldata.re_rx_paddr != NULL)
1287                 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF);
1288         if (sc->re_ldata.re_tx_dmamap != NULL)
1289                 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF);
1290         if (sc->re_ldata.re_rx_dmamap != NULL)
1291                 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF);
1292 }
1293
1294 /*
1295  * Attach the interface. Allocate softc structures, do ifmedia
1296  * setup and ethernet/BPF attach.
1297  */
1298 static int
1299 re_attach(device_t dev)
1300 {
1301         struct re_softc *sc = device_get_softc(dev);
1302         struct ifnet *ifp;
1303         uint8_t eaddr[ETHER_ADDR_LEN];
1304         int error = 0, rid, qlen;
1305
1306         callout_init(&sc->re_timer);
1307         sc->re_dev = dev;
1308
1309         if (RE_IS_8139CP(sc)) {
1310                 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP;
1311                 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP;
1312         } else {
1313                 sc->re_rx_desc_cnt = re_rx_desc_count;
1314                 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX)
1315                         sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX;
1316
1317                 sc->re_tx_desc_cnt = re_tx_desc_count;
1318                 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX)
1319                         sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX;
1320         }
1321
1322         qlen = RE_IFQ_MAXLEN;
1323         if (sc->re_tx_desc_cnt > qlen)
1324                 qlen = sc->re_tx_desc_cnt;
1325
1326         sc->re_rxbuf_size = MCLBYTES;
1327         sc->re_newbuf = re_newbuf_std;
1328
1329         sc->re_tx_time = 5;             /* 125us */
1330         sc->re_rx_time = 2;             /* 50us */
1331         if (sc->re_caps & RE_C_PCIE)
1332                 sc->re_sim_time = 75;   /* 75us */
1333         else
1334                 sc->re_sim_time = 125;  /* 125us */
1335         if (!RE_IS_8139CP(sc)) {
1336                 /* simulated interrupt moderation */
1337                 sc->re_imtype = RE_IMTYPE_SIM;
1338         } else {
1339                 sc->re_imtype = RE_IMTYPE_NONE;
1340         }
1341         re_config_imtype(sc, sc->re_imtype);
1342
1343         sysctl_ctx_init(&sc->re_sysctl_ctx);
1344         sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1345                                              SYSCTL_STATIC_CHILDREN(_hw),
1346                                              OID_AUTO,
1347                                              device_get_nameunit(dev),
1348                                              CTLFLAG_RD, 0, "");
1349         if (sc->re_sysctl_tree == NULL) {
1350                 device_printf(dev, "can't add sysctl node\n");
1351                 error = ENXIO;
1352                 goto fail;
1353         }
1354         SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1355                        SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1356                        "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt,
1357                        0, "RX desc count");
1358         SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1359                        SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1360                        "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt,
1361                        0, "TX desc count");
1362         SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1363                         SYSCTL_CHILDREN(sc->re_sysctl_tree),
1364                         OID_AUTO, "sim_time",
1365                         CTLTYPE_INT | CTLFLAG_RW,
1366                         sc, 0, re_sysctl_simtime, "I",
1367                         "Simulated interrupt moderation time (usec).");
1368         SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1369                         SYSCTL_CHILDREN(sc->re_sysctl_tree),
1370                         OID_AUTO, "imtype",
1371                         CTLTYPE_INT | CTLFLAG_RW,
1372                         sc, 0, re_sysctl_imtype, "I",
1373                         "Interrupt moderation type -- "
1374                         "0:disable, 1:simulated, "
1375                         "2:hardware(if supported)");
1376         if (sc->re_caps & RE_C_HWIM) {
1377                 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1378                                 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1379                                 OID_AUTO, "hw_rxtime",
1380                                 CTLTYPE_INT | CTLFLAG_RW,
1381                                 sc, 0, re_sysctl_rxtime, "I",
1382                                 "Hardware interrupt moderation time "
1383                                 "(unit: 25usec).");
1384                 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1385                                 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1386                                 OID_AUTO, "hw_txtime",
1387                                 CTLTYPE_INT | CTLFLAG_RW,
1388                                 sc, 0, re_sysctl_txtime, "I",
1389                                 "Hardware interrupt moderation time "
1390                                 "(unit: 25usec).");
1391         }
1392
1393 #ifndef BURN_BRIDGES
1394         /*
1395          * Handle power management nonsense.
1396          */
1397
1398         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1399                 uint32_t membase, irq;
1400
1401                 /* Save important PCI config data. */
1402                 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1403                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1404
1405                 /* Reset the power state. */
1406                 device_printf(dev, "chip is in D%d power mode "
1407                     "-- setting to D0\n", pci_get_powerstate(dev));
1408
1409                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1410
1411                 /* Restore PCI config data. */
1412                 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1413                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1414         }
1415 #endif
1416         /*
1417          * Map control/status registers.
1418          */
1419         pci_enable_busmaster(dev);
1420
1421         rid = RE_PCI_LOIO;
1422         sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1423                                             RF_ACTIVE);
1424
1425         if (sc->re_res == NULL) {
1426                 device_printf(dev, "couldn't map ports\n");
1427                 error = ENXIO;
1428                 goto fail;
1429         }
1430
1431         sc->re_btag = rman_get_bustag(sc->re_res);
1432         sc->re_bhandle = rman_get_bushandle(sc->re_res);
1433
1434         /* Allocate interrupt */
1435         rid = 0;
1436         sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1437                                             RF_SHAREABLE | RF_ACTIVE);
1438
1439         if (sc->re_irq == NULL) {
1440                 device_printf(dev, "couldn't map interrupt\n");
1441                 error = ENXIO;
1442                 goto fail;
1443         }
1444
1445         /* Reset the adapter. */
1446         re_reset(sc, 0);
1447
1448         if (RE_IS_8139CP(sc)) {
1449                 sc->re_bus_speed = 33; /* XXX */
1450         } else if (sc->re_caps & RE_C_PCIE) {
1451                 sc->re_bus_speed = 125;
1452         } else {
1453                 uint8_t cfg2;
1454
1455                 cfg2 = CSR_READ_1(sc, RE_CFG2);
1456                 switch (cfg2 & RE_CFG2_PCICLK_MASK) {
1457                 case RE_CFG2_PCICLK_33MHZ:
1458                         sc->re_bus_speed = 33;
1459                         break;
1460                 case RE_CFG2_PCICLK_66MHZ:
1461                         sc->re_bus_speed = 66;
1462                         break;
1463                 default:
1464                         device_printf(dev, "unknown bus speed, assume 33MHz\n");
1465                         sc->re_bus_speed = 33;
1466                         break;
1467                 }
1468                 if (cfg2 & RE_CFG2_PCI64)
1469                         sc->re_caps |= RE_C_PCI64;
1470         }
1471         device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; "
1472                       "PCI%s %dMHz\n",
1473                       sc->re_hwrev, sc->re_macver,
1474                       (sc->re_caps & RE_C_PCIE) ?
1475                       "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"),
1476                       sc->re_bus_speed);
1477
1478         /*
1479          * NOTE:
1480          * DO NOT try to adjust config1 and config5 which was spotted in
1481          * Realtek's Linux drivers.  It will _permanently_ damage certain
1482          * cards EEPROM, e.g. one of my 8168B (0x38000000) card ...
1483          */
1484
1485         re_get_eaddr(sc, eaddr);
1486
1487         if (!RE_IS_8139CP(sc)) {
1488                 /* Set RX length mask */
1489                 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1490                 sc->re_txstart = RE_GTXSTART;
1491         } else {
1492                 /* Set RX length mask */
1493                 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1494                 sc->re_txstart = RE_TXSTART;
1495         }
1496
1497         /* Allocate DMA stuffs */
1498         error = re_allocmem(dev);
1499         if (error)
1500                 goto fail;
1501
1502         /*
1503          * Apply some magic PCI settings from Realtek ...
1504          */
1505         if (RE_IS_8169(sc)) {
1506                 CSR_WRITE_1(sc, 0x82, 1);
1507                 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1);
1508         }
1509         pci_write_config(dev, PCIR_LATTIMER, 0x40, 1);
1510
1511         if (sc->re_caps & RE_C_MAC2) {
1512                 /*
1513                  * Following part is extracted from Realtek BSD driver v176.
1514                  * However, this does _not_ make much/any sense:
1515                  * 8168C's PCI Express device control is located at 0x78,
1516                  * so the reading from 0x79 (higher part of 0x78) and setting
1517                  * the 4~6bits intend to enlarge the "max read request size"
1518                  * (we will do it).  The content of the rest part of this
1519                  * register is not meaningful to other PCI registers, so
1520                  * writing the value to 0x54 could be completely wrong.
1521                  * 0x80 is the lower part of PCI Express device status, non-
1522                  * reserved bits are RW1C, writing 0 to them will not have
1523                  * any effect at all.
1524                  */
1525 #ifdef foo
1526                 uint8_t val;
1527
1528                 val = pci_read_config(dev, 0x79, 1);
1529                 val = (val & ~0x70) | 0x50;
1530                 pci_write_config(dev, 0x54, val, 1);
1531                 pci_write_config(dev, 0x80, 0, 1);
1532 #endif
1533         }
1534
1535         /*
1536          * Apply some PHY fixup from Realtek ...
1537          */
1538         if (sc->re_hwrev == RE_HWREV_8110S) {
1539                 CSR_WRITE_1(sc, 0x82, 1);
1540                 re_miibus_writereg(dev, 1, 0xb, 0);
1541         }
1542         if (sc->re_caps & RE_C_PHYPMGT) {
1543                 /* Power up PHY */
1544                 re_miibus_writereg(dev, 1, 0x1f, 0);
1545                 re_miibus_writereg(dev, 1, 0xe, 0);
1546         }
1547
1548         /* Do MII setup */
1549         if (mii_phy_probe(dev, &sc->re_miibus,
1550             re_ifmedia_upd, re_ifmedia_sts)) {
1551                 device_printf(dev, "MII without any phy!\n");
1552                 error = ENXIO;
1553                 goto fail;
1554         }
1555
1556         ifp = &sc->arpcom.ac_if;
1557         ifp->if_softc = sc;
1558         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1559         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1560         ifp->if_ioctl = re_ioctl;
1561         ifp->if_start = re_start;
1562 #ifdef DEVICE_POLLING
1563         ifp->if_poll = re_poll;
1564 #endif
1565         ifp->if_watchdog = re_watchdog;
1566         ifp->if_init = re_init;
1567         if (!RE_IS_8139CP(sc)) /* XXX */
1568                 ifp->if_baudrate = 1000000000;
1569         else
1570                 ifp->if_baudrate = 100000000;
1571         ifq_set_maxlen(&ifp->if_snd, qlen);
1572         ifq_set_ready(&ifp->if_snd);
1573
1574         ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1575         if (sc->re_caps & RE_C_HWCSUM)
1576                 ifp->if_capabilities |= IFCAP_HWCSUM;
1577
1578         ifp->if_capenable = ifp->if_capabilities;
1579         if (ifp->if_capabilities & IFCAP_HWCSUM)
1580                 ifp->if_hwassist = RE_CSUM_FEATURES;
1581         else
1582                 ifp->if_hwassist = 0;
1583
1584         /*
1585          * Call MI attach routine.
1586          */
1587         ether_ifattach(ifp, eaddr, NULL);
1588
1589 #ifdef RE_DIAG
1590         /*
1591          * Perform hardware diagnostic on the original RTL8169.
1592          * Some 32-bit cards were incorrectly wired and would
1593          * malfunction if plugged into a 64-bit slot.
1594          */
1595         if (sc->re_hwrev == RE_HWREV_8169) {
1596                 lwkt_serialize_enter(ifp->if_serializer);
1597                 error = re_diag(sc);
1598                 lwkt_serialize_exit(ifp->if_serializer);
1599
1600                 if (error) {
1601                         device_printf(dev, "hardware diagnostic failure\n");
1602                         ether_ifdetach(ifp);
1603                         goto fail;
1604                 }
1605         }
1606 #endif  /* RE_DIAG */
1607
1608         /* Hook interrupt last to avoid having to lock softc */
1609         error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc,
1610                                &sc->re_intrhand, ifp->if_serializer);
1611
1612         if (error) {
1613                 device_printf(dev, "couldn't set up irq\n");
1614                 ether_ifdetach(ifp);
1615                 goto fail;
1616         }
1617
1618         ifp->if_cpuid = rman_get_cpuid(sc->re_irq);
1619         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1620
1621 fail:
1622         if (error)
1623                 re_detach(dev);
1624
1625         return (error);
1626 }
1627
1628 /*
1629  * Shutdown hardware and free up resources. This can be called any
1630  * time after the mutex has been initialized. It is called in both
1631  * the error case in attach and the normal detach case so it needs
1632  * to be careful about only freeing resources that have actually been
1633  * allocated.
1634  */
1635 static int
1636 re_detach(device_t dev)
1637 {
1638         struct re_softc *sc = device_get_softc(dev);
1639         struct ifnet *ifp = &sc->arpcom.ac_if;
1640
1641         /* These should only be active if attach succeeded */
1642         if (device_is_attached(dev)) {
1643                 lwkt_serialize_enter(ifp->if_serializer);
1644                 re_stop(sc);
1645                 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1646                 lwkt_serialize_exit(ifp->if_serializer);
1647
1648                 ether_ifdetach(ifp);
1649         }
1650         if (sc->re_miibus)
1651                 device_delete_child(dev, sc->re_miibus);
1652         bus_generic_detach(dev);
1653
1654         if (sc->re_sysctl_tree != NULL)
1655                 sysctl_ctx_free(&sc->re_sysctl_ctx);
1656
1657         if (sc->re_irq)
1658                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1659         if (sc->re_res) {
1660                 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1661                                      sc->re_res);
1662         }
1663
1664         /* Free DMA stuffs */
1665         re_freemem(dev);
1666
1667         return(0);
1668 }
1669
1670 static void
1671 re_setup_rxdesc(struct re_softc *sc, int idx)
1672 {
1673         bus_addr_t paddr;
1674         uint32_t cmdstat;
1675         struct re_desc *d;
1676
1677         paddr = sc->re_ldata.re_rx_paddr[idx];
1678         d = &sc->re_ldata.re_rx_list[idx];
1679
1680         d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr));
1681         d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr));
1682
1683         cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN;
1684         if (idx == (sc->re_rx_desc_cnt - 1))
1685                 cmdstat |= RE_RDESC_CMD_EOR;
1686         d->re_cmdstat = htole32(cmdstat);
1687 }
1688
1689 static int
1690 re_newbuf_std(struct re_softc *sc, int idx, int init)
1691 {
1692         bus_dma_segment_t seg;
1693         bus_dmamap_t map;
1694         struct mbuf *m;
1695         int error, nsegs;
1696
1697         m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1698         if (m == NULL) {
1699                 error = ENOBUFS;
1700
1701                 if (init) {
1702                         if_printf(&sc->arpcom.ac_if, "m_getcl failed\n");
1703                         return error;
1704                 } else {
1705                         goto back;
1706                 }
1707         }
1708         m->m_len = m->m_pkthdr.len = MCLBYTES;
1709
1710         /*
1711          * NOTE:
1712          * re(4) chips need address of the receive buffer to be 8-byte
1713          * aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1714          */
1715
1716         error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag,
1717                         sc->re_ldata.re_rx_spare, m,
1718                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
1719         if (error) {
1720                 m_freem(m);
1721                 if (init) {
1722                         if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1723                         return error;
1724                 } else {
1725                         goto back;
1726                 }
1727         }
1728
1729         if (!init) {
1730                 bus_dmamap_sync(sc->re_ldata.re_rx_mtag,
1731                                 sc->re_ldata.re_rx_dmamap[idx],
1732                                 BUS_DMASYNC_POSTREAD);
1733                 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
1734                                   sc->re_ldata.re_rx_dmamap[idx]);
1735         }
1736         sc->re_ldata.re_rx_mbuf[idx] = m;
1737         sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr;
1738
1739         map = sc->re_ldata.re_rx_dmamap[idx];
1740         sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare;
1741         sc->re_ldata.re_rx_spare = map;
1742 back:
1743         re_setup_rxdesc(sc, idx);
1744         return error;
1745 }
1746
1747 static int
1748 re_newbuf_jumbo(struct re_softc *sc, int idx, int init)
1749 {
1750         struct mbuf *m;
1751         struct re_jbuf *jbuf;
1752         int error = 0;
1753
1754         MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1755         if (m == NULL) {
1756                 error = ENOBUFS;
1757                 if (init) {
1758                         if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n");
1759                         return error;
1760                 } else {
1761                         goto back;
1762                 }
1763         }
1764
1765         jbuf = re_jbuf_alloc(sc);
1766         if (jbuf == NULL) {
1767                 m_freem(m);
1768
1769                 error = ENOBUFS;
1770                 if (init) {
1771                         if_printf(&sc->arpcom.ac_if, "jpool is empty\n");
1772                         return error;
1773                 } else {
1774                         goto back;
1775                 }
1776         }
1777
1778         m->m_ext.ext_arg = jbuf;
1779         m->m_ext.ext_buf = jbuf->re_buf;
1780         m->m_ext.ext_free = re_jbuf_free;
1781         m->m_ext.ext_ref = re_jbuf_ref;
1782         m->m_ext.ext_size = sc->re_rxbuf_size;
1783
1784         m->m_data = m->m_ext.ext_buf;
1785         m->m_flags |= M_EXT;
1786         m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1787
1788         /*
1789          * NOTE:
1790          * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1791          * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1792          */
1793
1794         sc->re_ldata.re_rx_mbuf[idx] = m;
1795         sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr;
1796 back:
1797         re_setup_rxdesc(sc, idx);
1798         return error;
1799 }
1800
1801 static int
1802 re_tx_list_init(struct re_softc *sc)
1803 {
1804         bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
1805
1806         sc->re_ldata.re_tx_prodidx = 0;
1807         sc->re_ldata.re_tx_considx = 0;
1808         sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt;
1809
1810         return(0);
1811 }
1812
1813 static int
1814 re_rx_list_init(struct re_softc *sc)
1815 {
1816         int i, error;
1817
1818         bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc));
1819
1820         for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1821                 error = sc->re_newbuf(sc, i, 1);
1822                 if (error)
1823                         return(error);
1824         }
1825
1826         sc->re_ldata.re_rx_prodidx = 0;
1827         sc->re_head = sc->re_tail = NULL;
1828
1829         return(0);
1830 }
1831
1832 #define RE_IP4_PACKET   0x1
1833 #define RE_TCP_PACKET   0x2
1834 #define RE_UDP_PACKET   0x4
1835
1836 static __inline uint8_t
1837 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl)
1838 {
1839         uint8_t packet_type = 0;
1840
1841         if (sc->re_caps & RE_C_MAC2) {
1842                 if (rxctrl & RE_RDESC_CTL_PROTOIP4)
1843                         packet_type |= RE_IP4_PACKET;
1844         } else {
1845                 if (rxstat & RE_RDESC_STAT_PROTOID)
1846                         packet_type |= RE_IP4_PACKET;
1847         }
1848         if (RE_TCPPKT(rxstat))
1849                 packet_type |= RE_TCP_PACKET;
1850         else if (RE_UDPPKT(rxstat))
1851                 packet_type |= RE_UDP_PACKET;
1852         return packet_type;
1853 }
1854
1855 /*
1856  * RX handler for C+ and 8169. For the gigE chips, we support
1857  * the reception of jumbo frames that have been fragmented
1858  * across multiple 2K mbuf cluster buffers.
1859  */
1860 static int
1861 re_rxeof(struct re_softc *sc)
1862 {
1863         struct ifnet *ifp = &sc->arpcom.ac_if;
1864         struct mbuf *m;
1865         struct re_desc  *cur_rx;
1866         uint32_t rxstat, rxctrl;
1867         int i, total_len, rx = 0;
1868         struct mbuf_chain chain[MAXCPU];
1869
1870         ether_input_chain_init(chain);
1871
1872         for (i = sc->re_ldata.re_rx_prodidx;
1873              RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) {
1874                 cur_rx = &sc->re_ldata.re_rx_list[i];
1875                 m = sc->re_ldata.re_rx_mbuf[i];
1876                 total_len = RE_RXBYTES(cur_rx);
1877                 rxstat = le32toh(cur_rx->re_cmdstat);
1878                 rxctrl = le32toh(cur_rx->re_control);
1879
1880                 rx = 1;
1881
1882 #ifdef INVARIANTS
1883                 if (sc->re_flags & RE_F_USE_JPOOL)
1884                         KKASSERT(rxstat & RE_RDESC_STAT_EOF);
1885 #endif
1886
1887                 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1888                         if (sc->re_flags & RE_F_DROP_RXFRAG) {
1889                                 re_setup_rxdesc(sc, i);
1890                                 continue;
1891                         }
1892
1893                         if (sc->re_newbuf(sc, i, 0)) {
1894                                 /* Drop upcoming fragments */
1895                                 sc->re_flags |= RE_F_DROP_RXFRAG;
1896                                 continue;
1897                         }
1898
1899                         m->m_len = MCLBYTES;
1900                         if (sc->re_head == NULL) {
1901                                 sc->re_head = sc->re_tail = m;
1902                         } else {
1903                                 sc->re_tail->m_next = m;
1904                                 sc->re_tail = m;
1905                         }
1906                         continue;
1907                 } else if (sc->re_flags & RE_F_DROP_RXFRAG) {
1908                         /*
1909                          * Last fragment of a multi-fragment packet.
1910                          *
1911                          * Since error already happened, this fragment
1912                          * must be dropped as well as the fragment chain.
1913                          */
1914                         re_setup_rxdesc(sc, i);
1915                         re_free_rxchain(sc);
1916                         sc->re_flags &= ~RE_F_DROP_RXFRAG;
1917                         continue;
1918                 }
1919
1920                 /*
1921                  * NOTE: for the 8139C+, the frame length field
1922                  * is always 12 bits in size, but for the gigE chips,
1923                  * it is 13 bits (since the max RX frame length is 16K).
1924                  * Unfortunately, all 32 bits in the status word
1925                  * were already used, so to make room for the extra
1926                  * length bit, RealTek took out the 'frame alignment
1927                  * error' bit and shifted the other status bits
1928                  * over one slot. The OWN, EOR, FS and LS bits are
1929                  * still in the same places. We have already extracted
1930                  * the frame length and checked the OWN bit, so rather
1931                  * than using an alternate bit mapping, we shift the
1932                  * status bits one space to the right so we can evaluate
1933                  * them using the 8169 status as though it was in the
1934                  * same format as that of the 8139C+.
1935                  */
1936                 if (!RE_IS_8139CP(sc))
1937                         rxstat >>= 1;
1938
1939                 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1940                         ifp->if_ierrors++;
1941                         /*
1942                          * If this is part of a multi-fragment packet,
1943                          * discard all the pieces.
1944                          */
1945                         re_free_rxchain(sc);
1946                         re_setup_rxdesc(sc, i);
1947                         continue;
1948                 }
1949
1950                 /*
1951                  * If allocating a replacement mbuf fails,
1952                  * reload the current one.
1953                  */
1954
1955                 if (sc->re_newbuf(sc, i, 0)) {
1956                         ifp->if_ierrors++;
1957                         continue;
1958                 }
1959
1960                 if (sc->re_head != NULL) {
1961                         m->m_len = total_len % MCLBYTES;
1962                         /* 
1963                          * Special case: if there's 4 bytes or less
1964                          * in this buffer, the mbuf can be discarded:
1965                          * the last 4 bytes is the CRC, which we don't
1966                          * care about anyway.
1967                          */
1968                         if (m->m_len <= ETHER_CRC_LEN) {
1969                                 sc->re_tail->m_len -=
1970                                     (ETHER_CRC_LEN - m->m_len);
1971                                 m_freem(m);
1972                         } else {
1973                                 m->m_len -= ETHER_CRC_LEN;
1974                                 sc->re_tail->m_next = m;
1975                         }
1976                         m = sc->re_head;
1977                         sc->re_head = sc->re_tail = NULL;
1978                         m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1979                 } else {
1980                         m->m_pkthdr.len = m->m_len =
1981                             (total_len - ETHER_CRC_LEN);
1982                 }
1983
1984                 ifp->if_ipackets++;
1985                 m->m_pkthdr.rcvif = ifp;
1986
1987                 /* Do RX checksumming if enabled */
1988
1989                 if (ifp->if_capenable & IFCAP_RXCSUM) {
1990                         uint8_t packet_type;
1991
1992                         packet_type = re_packet_type(sc, rxstat, rxctrl);
1993
1994                         /* Check IP header checksum */
1995                         if (packet_type & RE_IP4_PACKET) {
1996                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1997                                 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1998                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1999                         }
2000
2001                         /* Check TCP/UDP checksum */
2002                         if (((packet_type & RE_TCP_PACKET) &&
2003                              (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
2004                             ((packet_type & RE_UDP_PACKET) &&
2005                              (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) {
2006                                 m->m_pkthdr.csum_flags |=
2007                                     CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
2008                                     CSUM_FRAG_NOT_CHECKED;
2009                                 m->m_pkthdr.csum_data = 0xffff;
2010                         }
2011                 }
2012
2013                 if (rxctrl & RE_RDESC_CTL_HASTAG) {
2014                         m->m_flags |= M_VLANTAG;
2015                         m->m_pkthdr.ether_vlantag =
2016                                 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA));
2017                 }
2018                 ether_input_chain(ifp, m, NULL, chain);
2019         }
2020
2021         ether_input_dispatch(chain);
2022
2023         sc->re_ldata.re_rx_prodidx = i;
2024
2025         return rx;
2026 }
2027
2028 #undef RE_IP4_PACKET
2029 #undef RE_TCP_PACKET
2030 #undef RE_UDP_PACKET
2031
2032 static int
2033 re_tx_collect(struct re_softc *sc)
2034 {
2035         struct ifnet *ifp = &sc->arpcom.ac_if;
2036         uint32_t txstat;
2037         int idx, tx = 0;
2038
2039         for (idx = sc->re_ldata.re_tx_considx;
2040              sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt;
2041              RE_TXDESC_INC(sc, idx)) {
2042                 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
2043                 if (txstat & RE_TDESC_CMD_OWN)
2044                         break;
2045
2046                 tx = 1;
2047
2048                 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
2049
2050                 /*
2051                  * We only stash mbufs in the last descriptor
2052                  * in a fragment chain, which also happens to
2053                  * be the only place where the TX status bits
2054                  * are valid.
2055                  */
2056                 if (txstat & RE_TDESC_CMD_EOF) {
2057                         bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
2058                             sc->re_ldata.re_tx_dmamap[idx]);
2059                         m_freem(sc->re_ldata.re_tx_mbuf[idx]);
2060                         sc->re_ldata.re_tx_mbuf[idx] = NULL;
2061                         if (txstat & (RE_TDESC_STAT_EXCESSCOL|
2062                             RE_TDESC_STAT_COLCNT))
2063                                 ifp->if_collisions++;
2064                         if (txstat & RE_TDESC_STAT_TXERRSUM)
2065                                 ifp->if_oerrors++;
2066                         else
2067                                 ifp->if_opackets++;
2068                 }
2069                 sc->re_ldata.re_tx_free++;
2070         }
2071         sc->re_ldata.re_tx_considx = idx;
2072
2073         return tx;
2074 }
2075
2076 static int
2077 re_txeof(struct re_softc *sc)
2078 {
2079         struct ifnet *ifp = &sc->arpcom.ac_if;
2080         int tx;
2081
2082         tx = re_tx_collect(sc);
2083
2084         /* There is enough free TX descs */
2085         if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE)
2086                 ifp->if_flags &= ~IFF_OACTIVE;
2087
2088         /*
2089          * Some chips will ignore a second TX request issued while an
2090          * existing transmission is in progress. If the transmitter goes
2091          * idle but there are still packets waiting to be sent, we need
2092          * to restart the channel here to flush them out. This only seems
2093          * to be required with the PCIe devices.
2094          */
2095         if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt)
2096                 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2097         else
2098                 ifp->if_timer = 0;
2099
2100         return tx;
2101 }
2102
2103 static void
2104 re_tick(void *xsc)
2105 {
2106         struct re_softc *sc = xsc;
2107
2108         lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2109         re_tick_serialized(xsc);
2110         lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2111 }
2112
2113 static void
2114 re_tick_serialized(void *xsc)
2115 {
2116         struct re_softc *sc = xsc;
2117         struct ifnet *ifp = &sc->arpcom.ac_if;
2118         struct mii_data *mii;
2119
2120         ASSERT_SERIALIZED(ifp->if_serializer);
2121
2122         mii = device_get_softc(sc->re_miibus);
2123         mii_tick(mii);
2124         if (sc->re_flags & RE_F_LINKED) {
2125                 if (!(mii->mii_media_status & IFM_ACTIVE))
2126                         sc->re_flags &= ~RE_F_LINKED;
2127         } else {
2128                 if (mii->mii_media_status & IFM_ACTIVE &&
2129                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2130                         sc->re_flags |= RE_F_LINKED;
2131                         if (!ifq_is_empty(&ifp->if_snd))
2132                                 if_devstart(ifp);
2133                 }
2134         }
2135
2136         callout_reset(&sc->re_timer, hz, re_tick, sc);
2137 }
2138
2139 #ifdef DEVICE_POLLING
2140
2141 static void
2142 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2143 {
2144         struct re_softc *sc = ifp->if_softc;
2145
2146         ASSERT_SERIALIZED(ifp->if_serializer);
2147
2148         switch(cmd) {
2149         case POLL_REGISTER:
2150                 /* disable interrupts */
2151                 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2152                 break;
2153
2154         case POLL_DEREGISTER:
2155                 /* enable interrupts */
2156                 re_setup_intr(sc, 1, sc->re_imtype);
2157                 break;
2158
2159         default:
2160                 sc->rxcycles = count;
2161                 re_rxeof(sc);
2162                 re_txeof(sc);
2163
2164                 if (!ifq_is_empty(&ifp->if_snd))
2165                         if_devstart(ifp);
2166
2167                 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2168                         uint16_t       status;
2169
2170                         status = CSR_READ_2(sc, RE_ISR);
2171                         if (status == 0xffff)
2172                                 return;
2173                         if (status)
2174                                 CSR_WRITE_2(sc, RE_ISR, status);
2175
2176                         /*
2177                          * XXX check behaviour on receiver stalls.
2178                          */
2179
2180                         if (status & RE_ISR_SYSTEM_ERR)
2181                                 re_init(sc);
2182                 }
2183                 break;
2184         }
2185 }
2186 #endif /* DEVICE_POLLING */
2187
2188 static void
2189 re_intr(void *arg)
2190 {
2191         struct re_softc *sc = arg;
2192         struct ifnet *ifp = &sc->arpcom.ac_if;
2193         uint16_t status;
2194         int rx, tx;
2195
2196         ASSERT_SERIALIZED(ifp->if_serializer);
2197
2198         if ((sc->re_flags & RE_F_SUSPENDED) ||
2199             (ifp->if_flags & IFF_RUNNING) == 0)
2200                 return;
2201
2202         rx = tx = 0;
2203         for (;;) {
2204                 status = CSR_READ_2(sc, RE_ISR);
2205                 /* If the card has gone away the read returns 0xffff. */
2206                 if (status == 0xffff)
2207                         break;
2208                 if (status)
2209                         CSR_WRITE_2(sc, RE_ISR, status);
2210
2211                 if ((status & sc->re_intrs) == 0)
2212                         break;
2213
2214                 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR))
2215                         rx |= re_rxeof(sc);
2216
2217                 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR))
2218                         tx |= re_txeof(sc);
2219
2220                 if (status & RE_ISR_SYSTEM_ERR)
2221                         re_init(sc);
2222
2223                 if (status & RE_ISR_LINKCHG) {
2224                         callout_stop(&sc->re_timer);
2225                         re_tick_serialized(sc);
2226                 }
2227         }
2228
2229         if (sc->re_imtype == RE_IMTYPE_SIM) {
2230                 if ((sc->re_flags & RE_F_TIMER_INTR)) {
2231                         if ((tx | rx) == 0) {
2232                                 /*
2233                                  * Nothing needs to be processed, fallback
2234                                  * to use TX/RX interrupts.
2235                                  */
2236                                 re_setup_intr(sc, 1, RE_IMTYPE_NONE);
2237
2238                                 /*
2239                                  * Recollect, mainly to avoid the possible
2240                                  * race introduced by changing interrupt
2241                                  * masks.
2242                                  */
2243                                 re_rxeof(sc);
2244                                 tx = re_txeof(sc);
2245                         } else {
2246                                 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
2247                         }
2248                 } else if (tx | rx) {
2249                         /*
2250                          * Assume that using simulated interrupt moderation
2251                          * (hardware timer based) could reduce the interript
2252                          * rate.
2253                          */
2254                         re_setup_intr(sc, 1, RE_IMTYPE_SIM);
2255                 }
2256         }
2257
2258         if (tx && !ifq_is_empty(&ifp->if_snd))
2259                 if_devstart(ifp);
2260 }
2261
2262 static int
2263 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0)
2264 {
2265         struct mbuf *m = *m_head;
2266         bus_dma_segment_t segs[RE_MAXSEGS];
2267         bus_dmamap_t map;
2268         int error, maxsegs, idx, i, nsegs;
2269         struct re_desc *d, *tx_ring;
2270         uint32_t cmd_csum, ctl_csum, vlantag;
2271
2272         KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE,
2273                 ("not enough free TX desc\n"));
2274
2275         map = sc->re_ldata.re_tx_dmamap[*idx0];
2276
2277         /*
2278          * Set up checksum offload. Note: checksum offload bits must
2279          * appear in all descriptors of a multi-descriptor transmit
2280          * attempt. (This is according to testing done with an 8169
2281          * chip. I'm not sure if this is a requirement or a bug.)
2282          */
2283         cmd_csum = ctl_csum = 0;
2284         if (m->m_pkthdr.csum_flags & CSUM_IP) {
2285                 cmd_csum |= RE_TDESC_CMD_IPCSUM;
2286                 ctl_csum |= RE_TDESC_CTL_IPCSUM;
2287         }
2288         if (m->m_pkthdr.csum_flags & CSUM_TCP) {
2289                 cmd_csum |= RE_TDESC_CMD_TCPCSUM;
2290                 ctl_csum |= RE_TDESC_CTL_TCPCSUM;
2291         }
2292         if (m->m_pkthdr.csum_flags & CSUM_UDP) {
2293                 cmd_csum |= RE_TDESC_CMD_UDPCSUM;
2294                 ctl_csum |= RE_TDESC_CTL_UDPCSUM;
2295         }
2296
2297         /* For MAC2 chips, csum flags are set on re_control */
2298         if (sc->re_caps & RE_C_MAC2)
2299                 cmd_csum = 0;
2300         else
2301                 ctl_csum = 0;
2302
2303         if ((sc->re_caps & RE_C_AUTOPAD) == 0) {
2304                 /*
2305                  * With some of the RealTek chips, using the checksum offload
2306                  * support in conjunction with the autopadding feature results
2307                  * in the transmission of corrupt frames. For example, if we
2308                  * need to send a really small IP fragment that's less than 60
2309                  * bytes in size, and IP header checksumming is enabled, the
2310                  * resulting ethernet frame that appears on the wire will
2311                  * have garbled payload. To work around this, if TX checksum
2312                  * offload is enabled, we always manually pad short frames out
2313                  * to the minimum ethernet frame size.
2314                  *
2315                  * Note: this appears unnecessary for TCP, and doing it for TCP
2316                  * with PCIe adapters seems to result in bad checksums.
2317                  */
2318                 if ((m->m_pkthdr.csum_flags &
2319                      (CSUM_DELAY_IP | CSUM_DELAY_DATA)) &&
2320                     (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 &&
2321                     m->m_pkthdr.len < RE_MIN_FRAMELEN) {
2322                         error = m_devpad(m, RE_MIN_FRAMELEN);
2323                         if (error)
2324                                 goto back;
2325                 }
2326         }
2327
2328         vlantag = 0;
2329         if (m->m_flags & M_VLANTAG) {
2330                 vlantag = htobe16(m->m_pkthdr.ether_vlantag) |
2331                           RE_TDESC_CTL_INSTAG;
2332         }
2333
2334         maxsegs = sc->re_ldata.re_tx_free;
2335         if (maxsegs > RE_MAXSEGS)
2336                 maxsegs = RE_MAXSEGS;
2337
2338         error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map,
2339                         m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2340         if (error)
2341                 goto back;
2342
2343         m = *m_head;
2344         bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2345
2346         /*
2347          * Map the segment array into descriptors.  We also keep track
2348          * of the end of the ring and set the end-of-ring bits as needed,
2349          * and we set the ownership bits in all except the very first
2350          * descriptor, whose ownership bits will be turned on later.
2351          */
2352         tx_ring = sc->re_ldata.re_tx_list;
2353         idx = *idx0;
2354         i = 0;
2355         for (;;) {
2356                 uint32_t cmdstat;
2357
2358                 d = &tx_ring[idx];
2359
2360                 cmdstat = segs[i].ds_len;
2361                 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
2362                 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
2363                 if (i == 0)
2364                         cmdstat |= RE_TDESC_CMD_SOF;
2365                 else
2366                         cmdstat |= RE_TDESC_CMD_OWN;
2367                 if (idx == (sc->re_tx_desc_cnt - 1))
2368                         cmdstat |= RE_TDESC_CMD_EOR;
2369                 d->re_cmdstat = htole32(cmdstat | cmd_csum);
2370                 d->re_control = htole32(ctl_csum | vlantag);
2371
2372                 i++;
2373                 if (i == nsegs)
2374                         break;
2375                 RE_TXDESC_INC(sc, idx);
2376         }
2377         d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
2378
2379         /* Transfer ownership of packet to the chip. */
2380         d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2381         if (*idx0 != idx)
2382                 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2383
2384         /*
2385          * Insure that the map for this transmission
2386          * is placed at the array index of the last descriptor
2387          * in this chain.
2388          */
2389         sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx];
2390         sc->re_ldata.re_tx_dmamap[idx] = map;
2391
2392         sc->re_ldata.re_tx_mbuf[idx] = m;
2393         sc->re_ldata.re_tx_free -= nsegs;
2394
2395         RE_TXDESC_INC(sc, idx);
2396         *idx0 = idx;
2397 back:
2398         if (error) {
2399                 m_freem(*m_head);
2400                 *m_head = NULL;
2401         }
2402         return error;
2403 }
2404
2405 /*
2406  * Main transmit routine for C+ and gigE NICs.
2407  */
2408
2409 static void
2410 re_start(struct ifnet *ifp)
2411 {
2412         struct re_softc *sc = ifp->if_softc;
2413         struct mbuf *m_head;
2414         int idx, need_trans, oactive, error;
2415
2416         ASSERT_SERIALIZED(ifp->if_serializer);
2417
2418         if ((sc->re_flags & RE_F_LINKED) == 0) {
2419                 ifq_purge(&ifp->if_snd);
2420                 return;
2421         }
2422
2423         if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
2424                 return;
2425
2426         idx = sc->re_ldata.re_tx_prodidx;
2427
2428         need_trans = 0;
2429         oactive = 0;
2430         while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
2431                 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
2432                         if (!oactive) {
2433                                 if (re_tx_collect(sc)) {
2434                                         oactive = 1;
2435                                         continue;
2436                                 }
2437                         }
2438                         ifp->if_flags |= IFF_OACTIVE;
2439                         break;
2440                 }
2441
2442                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2443                 if (m_head == NULL)
2444                         break;
2445
2446                 error = re_encap(sc, &m_head, &idx);
2447                 if (error) {
2448                         /* m_head is freed by re_encap(), if we reach here */
2449                         ifp->if_oerrors++;
2450
2451                         if (error == EFBIG && !oactive) {
2452                                 if (re_tx_collect(sc)) {
2453                                         oactive = 1;
2454                                         continue;
2455                                 }
2456                         }
2457                         ifp->if_flags |= IFF_OACTIVE;
2458                         break;
2459                 }
2460
2461                 oactive = 0;
2462                 need_trans = 1;
2463
2464                 /*
2465                  * If there's a BPF listener, bounce a copy of this frame
2466                  * to him.
2467                  */
2468                 ETHER_BPF_MTAP(ifp, m_head);
2469         }
2470
2471         /*
2472          * If sc->re_ldata.re_tx_mbuf[idx] is not NULL it is possible
2473          * for IFF_OACTIVE to not be properly set when we also do not
2474          * have sufficient free tx descriptors, leaving packet in
2475          * ifp->if_send.  This can cause if_start_dispatch() to loop
2476          * infinitely so make sure IFF_OACTIVE is set properly.
2477          */
2478         if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
2479                 if ((ifp->if_flags & IFF_OACTIVE) == 0) {
2480                         device_printf(sc->re_dev,
2481                                       "Debug: IFF_OACTIVE was not set when"
2482                                       " re_tx_free was below minimum!\n");
2483                         ifp->if_flags |= IFF_OACTIVE;
2484                 }
2485         }
2486         if (!need_trans)
2487                 return;
2488
2489         sc->re_ldata.re_tx_prodidx = idx;
2490
2491         /*
2492          * RealTek put the TX poll request register in a different
2493          * location on the 8169 gigE chip. I don't know why.
2494          */
2495         CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2496
2497         /*
2498          * Set a timeout in case the chip goes out to lunch.
2499          */
2500         ifp->if_timer = 5;
2501 }
2502
2503 static void
2504 re_init(void *xsc)
2505 {
2506         struct re_softc *sc = xsc;
2507         struct ifnet *ifp = &sc->arpcom.ac_if;
2508         struct mii_data *mii;
2509         int error, framelen;
2510
2511         ASSERT_SERIALIZED(ifp->if_serializer);
2512
2513         mii = device_get_softc(sc->re_miibus);
2514
2515         /*
2516          * Cancel pending I/O and free all RX/TX buffers.
2517          */
2518         re_stop(sc);
2519
2520         if (sc->re_caps & RE_C_CONTIGRX) {
2521                 if (ifp->if_mtu > ETHERMTU) {
2522                         KKASSERT(sc->re_ldata.re_jbuf != NULL);
2523                         sc->re_flags |= RE_F_USE_JPOOL;
2524                         sc->re_rxbuf_size = RE_FRAMELEN_MAX;
2525                         sc->re_newbuf = re_newbuf_jumbo;
2526                 } else {
2527                         sc->re_flags &= ~RE_F_USE_JPOOL;
2528                         sc->re_rxbuf_size = MCLBYTES;
2529                         sc->re_newbuf = re_newbuf_std;
2530                 }
2531         }
2532
2533         /*
2534          * Adjust max read request size according to MTU; mainly to
2535          * improve TX performance for common case (ETHERMTU) on GigE
2536          * NICs.  However, this could _not_ be done on 10/100 only
2537          * NICs; their DMA engines will malfunction using non-default
2538          * max read request size.
2539          */
2540         if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) {
2541                 if (ifp->if_mtu > ETHERMTU) {
2542                         /*
2543                          * 512 seems to be the only value that works
2544                          * reliably with jumbo frame
2545                          */
2546                         pcie_set_max_readrq(sc->re_dev,
2547                                 PCIEM_DEVCTL_MAX_READRQ_512);
2548                 } else {
2549                         pcie_set_max_readrq(sc->re_dev,
2550                                 PCIEM_DEVCTL_MAX_READRQ_4096);
2551                 }
2552         }
2553
2554         /*
2555          * Enable C+ RX and TX mode, as well as VLAN stripping and
2556          * RX checksum offload. We must configure the C+ register
2557          * before all others.
2558          */
2559         CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2560                     RE_CPLUSCMD_PCI_MRW |
2561                     (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ?
2562                      RE_CPLUSCMD_VLANSTRIP : 0) |
2563                     (ifp->if_capenable & IFCAP_RXCSUM ?
2564                      RE_CPLUSCMD_RXCSUM_ENB : 0));
2565
2566         /*
2567          * Init our MAC address.  Even though the chipset
2568          * documentation doesn't mention it, we need to enter "Config
2569          * register write enable" mode to modify the ID registers.
2570          */
2571         CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2572         CSR_WRITE_4(sc, RE_IDR0,
2573             htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2574         CSR_WRITE_2(sc, RE_IDR4,
2575             htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2576         CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2577
2578         /*
2579          * For C+ mode, initialize the RX descriptors and mbufs.
2580          */
2581         error = re_rx_list_init(sc);
2582         if (error) {
2583                 re_stop(sc);
2584                 return;
2585         }
2586         error = re_tx_list_init(sc);
2587         if (error) {
2588                 re_stop(sc);
2589                 return;
2590         }
2591
2592         /*
2593          * Load the addresses of the RX and TX lists into the chip.
2594          */
2595         CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2596             RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2597         CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2598             RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2599
2600         CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2601             RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2602         CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2603             RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2604
2605         /*
2606          * Enable transmit and receive.
2607          */
2608         CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2609
2610         /*
2611          * Set the initial TX and RX configuration.
2612          */
2613         if (sc->re_flags & RE_F_TESTMODE) {
2614                 if (!RE_IS_8139CP(sc))
2615                         CSR_WRITE_4(sc, RE_TXCFG,
2616                                     RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2617                 else
2618                         CSR_WRITE_4(sc, RE_TXCFG,
2619                                     RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2620         } else
2621                 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2622
2623         framelen = RE_FRAMELEN(ifp->if_mtu);
2624         if (framelen < MCLBYTES)
2625                 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128));
2626         else
2627                 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128));
2628
2629         CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2630
2631         /*
2632          * Program the multicast filter, if necessary.
2633          */
2634         re_setmulti(sc);
2635
2636 #ifdef DEVICE_POLLING
2637         /*
2638          * Disable interrupts if we are polling.
2639          */
2640         if (ifp->if_flags & IFF_POLLING)
2641                 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2642         else    /* otherwise ... */
2643 #endif /* DEVICE_POLLING */
2644         /*
2645          * Enable interrupts.
2646          */
2647         if (sc->re_flags & RE_F_TESTMODE)
2648                 CSR_WRITE_2(sc, RE_IMR, 0);
2649         else
2650                 re_setup_intr(sc, 1, sc->re_imtype);
2651         CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2652
2653         /* Start RX/TX process. */
2654         CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2655
2656 #ifdef notdef
2657         /* Enable receiver and transmitter. */
2658         CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2659 #endif
2660
2661         /*
2662          * For 8169 gigE NICs, set the max allowed RX packet
2663          * size so we can receive jumbo frames.
2664          */
2665         if (!RE_IS_8139CP(sc)) {
2666                 if (sc->re_caps & RE_C_CONTIGRX)
2667                         CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size);
2668                 else
2669                         CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2670         }
2671
2672         if (sc->re_flags & RE_F_TESTMODE)
2673                 return;
2674
2675         mii_mediachg(mii);
2676
2677         CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2678
2679         ifp->if_flags |= IFF_RUNNING;
2680         ifp->if_flags &= ~IFF_OACTIVE;
2681
2682         callout_reset(&sc->re_timer, hz, re_tick, sc);
2683 }
2684
2685 /*
2686  * Set media options.
2687  */
2688 static int
2689 re_ifmedia_upd(struct ifnet *ifp)
2690 {
2691         struct re_softc *sc = ifp->if_softc;
2692         struct mii_data *mii;
2693
2694         ASSERT_SERIALIZED(ifp->if_serializer);
2695
2696         mii = device_get_softc(sc->re_miibus);
2697         mii_mediachg(mii);
2698
2699         return(0);
2700 }
2701
2702 /*
2703  * Report current media status.
2704  */
2705 static void
2706 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2707 {
2708         struct re_softc *sc = ifp->if_softc;
2709         struct mii_data *mii;
2710
2711         ASSERT_SERIALIZED(ifp->if_serializer);
2712
2713         mii = device_get_softc(sc->re_miibus);
2714
2715         mii_pollstat(mii);
2716         ifmr->ifm_active = mii->mii_media_active;
2717         ifmr->ifm_status = mii->mii_media_status;
2718 }
2719
2720 static int
2721 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2722 {
2723         struct re_softc *sc = ifp->if_softc;
2724         struct ifreq *ifr = (struct ifreq *) data;
2725         struct mii_data *mii;
2726         int error = 0, mask;
2727
2728         ASSERT_SERIALIZED(ifp->if_serializer);
2729
2730         switch(command) {
2731         case SIOCSIFMTU:
2732                 if (ifr->ifr_mtu > sc->re_maxmtu) {
2733                         error = EINVAL;
2734                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
2735                         ifp->if_mtu = ifr->ifr_mtu;
2736                         if (ifp->if_flags & IFF_RUNNING)
2737                                 ifp->if_init(sc);
2738                 }
2739                 break;
2740
2741         case SIOCSIFFLAGS:
2742                 if (ifp->if_flags & IFF_UP) {
2743                         if (ifp->if_flags & IFF_RUNNING) {
2744                                 if ((ifp->if_flags ^ sc->re_if_flags) &
2745                                     (IFF_PROMISC | IFF_ALLMULTI))
2746                                         re_setmulti(sc);
2747                         } else {
2748                                 re_init(sc);
2749                         }
2750                 } else if (ifp->if_flags & IFF_RUNNING) {
2751                         re_stop(sc);
2752                 }
2753                 sc->re_if_flags = ifp->if_flags;
2754                 break;
2755
2756         case SIOCADDMULTI:
2757         case SIOCDELMULTI:
2758                 re_setmulti(sc);
2759                 break;
2760
2761         case SIOCGIFMEDIA:
2762         case SIOCSIFMEDIA:
2763                 mii = device_get_softc(sc->re_miibus);
2764                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2765                 break;
2766
2767         case SIOCSIFCAP:
2768                 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) &
2769                        ifp->if_capabilities;
2770                 ifp->if_capenable ^= mask;
2771
2772                 if (mask & IFCAP_HWCSUM) {
2773                         if (ifp->if_capenable & IFCAP_TXCSUM)
2774                                 ifp->if_hwassist = RE_CSUM_FEATURES;
2775                         else
2776                                 ifp->if_hwassist = 0;
2777                 }
2778                 if (mask && (ifp->if_flags & IFF_RUNNING))
2779                         re_init(sc);
2780                 break;
2781
2782         default:
2783                 error = ether_ioctl(ifp, command, data);
2784                 break;
2785         }
2786         return(error);
2787 }
2788
2789 static void
2790 re_watchdog(struct ifnet *ifp)
2791 {
2792         struct re_softc *sc = ifp->if_softc;
2793
2794         ASSERT_SERIALIZED(ifp->if_serializer);
2795
2796         if_printf(ifp, "watchdog timeout\n");
2797
2798         ifp->if_oerrors++;
2799
2800         re_txeof(sc);
2801         re_rxeof(sc);
2802
2803         re_init(sc);
2804
2805         if (!ifq_is_empty(&ifp->if_snd))
2806                 if_devstart(ifp);
2807 }
2808
2809 /*
2810  * Stop the adapter and free any mbufs allocated to the
2811  * RX and TX lists.
2812  */
2813 static void
2814 re_stop(struct re_softc *sc)
2815 {
2816         struct ifnet *ifp = &sc->arpcom.ac_if;
2817         int i;
2818
2819         ASSERT_SERIALIZED(ifp->if_serializer);
2820
2821         /* Reset the adapter. */
2822         re_reset(sc, ifp->if_flags & IFF_RUNNING);
2823
2824         ifp->if_timer = 0;
2825         callout_stop(&sc->re_timer);
2826
2827         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2828         sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED);
2829
2830         CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2831         CSR_WRITE_2(sc, RE_IMR, 0x0000);
2832         CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2833
2834         re_free_rxchain(sc);
2835
2836         /* Free the TX list buffers. */
2837         for (i = 0; i < sc->re_tx_desc_cnt; i++) {
2838                 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2839                         bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
2840                                           sc->re_ldata.re_tx_dmamap[i]);
2841                         m_freem(sc->re_ldata.re_tx_mbuf[i]);
2842                         sc->re_ldata.re_tx_mbuf[i] = NULL;
2843                 }
2844         }
2845
2846         /* Free the RX list buffers. */
2847         for (i = 0; i < sc->re_rx_desc_cnt; i++) {
2848                 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2849                         if ((sc->re_flags & RE_F_USE_JPOOL) == 0) {
2850                                 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
2851                                                   sc->re_ldata.re_rx_dmamap[i]);
2852                         }
2853                         m_freem(sc->re_ldata.re_rx_mbuf[i]);
2854                         sc->re_ldata.re_rx_mbuf[i] = NULL;
2855                 }
2856         }
2857 }
2858
2859 /*
2860  * Device suspend routine.  Stop the interface and save some PCI
2861  * settings in case the BIOS doesn't restore them properly on
2862  * resume.
2863  */
2864 static int
2865 re_suspend(device_t dev)
2866 {
2867 #ifndef BURN_BRIDGES
2868         int i;
2869 #endif
2870         struct re_softc *sc = device_get_softc(dev);
2871         struct ifnet *ifp = &sc->arpcom.ac_if;
2872
2873         lwkt_serialize_enter(ifp->if_serializer);
2874
2875         re_stop(sc);
2876
2877 #ifndef BURN_BRIDGES
2878         for (i = 0; i < 5; i++)
2879                 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2880         sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2881         sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2882         sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2883         sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2884 #endif
2885
2886         sc->re_flags |= RE_F_SUSPENDED;
2887
2888         lwkt_serialize_exit(ifp->if_serializer);
2889
2890         return (0);
2891 }
2892
2893 /*
2894  * Device resume routine.  Restore some PCI settings in case the BIOS
2895  * doesn't, re-enable busmastering, and restart the interface if
2896  * appropriate.
2897  */
2898 static int
2899 re_resume(device_t dev)
2900 {
2901         struct re_softc *sc = device_get_softc(dev);
2902         struct ifnet *ifp = &sc->arpcom.ac_if;
2903 #ifndef BURN_BRIDGES
2904         int i;
2905 #endif
2906
2907         lwkt_serialize_enter(ifp->if_serializer);
2908
2909 #ifndef BURN_BRIDGES
2910         /* better way to do this? */
2911         for (i = 0; i < 5; i++)
2912                 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2913         pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2914         pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2915         pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2916         pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2917
2918         /* reenable busmastering */
2919         pci_enable_busmaster(dev);
2920         pci_enable_io(dev, SYS_RES_IOPORT);
2921 #endif
2922
2923         /* reinitialize interface if necessary */
2924         if (ifp->if_flags & IFF_UP)
2925                 re_init(sc);
2926
2927         sc->re_flags &= ~RE_F_SUSPENDED;
2928
2929         lwkt_serialize_exit(ifp->if_serializer);
2930
2931         return (0);
2932 }
2933
2934 /*
2935  * Stop all chip I/O so that the kernel's probe routines don't
2936  * get confused by errant DMAs when rebooting.
2937  */
2938 static void
2939 re_shutdown(device_t dev)
2940 {
2941         struct re_softc *sc = device_get_softc(dev);
2942         struct ifnet *ifp = &sc->arpcom.ac_if;
2943
2944         lwkt_serialize_enter(ifp->if_serializer);
2945         re_stop(sc);
2946         lwkt_serialize_exit(ifp->if_serializer);
2947 }
2948
2949 static int
2950 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS)
2951 {
2952         struct re_softc *sc = arg1;
2953
2954         return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time);
2955 }
2956
2957 static int
2958 re_sysctl_txtime(SYSCTL_HANDLER_ARGS)
2959 {
2960         struct re_softc *sc = arg1;
2961
2962         return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time);
2963 }
2964
2965 static int
2966 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime)
2967 {
2968         struct re_softc *sc = arg1;
2969         struct ifnet *ifp = &sc->arpcom.ac_if;
2970         int error, v;
2971
2972         lwkt_serialize_enter(ifp->if_serializer);
2973
2974         v = *hwtime;
2975         error = sysctl_handle_int(oidp, &v, 0, req);
2976         if (error || req->newptr == NULL)
2977                 goto back;
2978
2979         if (v <= 0) {
2980                 error = EINVAL;
2981                 goto back;
2982         }
2983
2984         if (v != *hwtime) {
2985                 *hwtime = v;
2986
2987                 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
2988                     IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW)
2989                         re_setup_hw_im(sc);
2990         }
2991 back:
2992         lwkt_serialize_exit(ifp->if_serializer);
2993         return error;
2994 }
2995
2996 static int
2997 re_sysctl_simtime(SYSCTL_HANDLER_ARGS)
2998 {
2999         struct re_softc *sc = arg1;
3000         struct ifnet *ifp = &sc->arpcom.ac_if;
3001         int error, v;
3002
3003         lwkt_serialize_enter(ifp->if_serializer);
3004
3005         v = sc->re_sim_time;
3006         error = sysctl_handle_int(oidp, &v, 0, req);
3007         if (error || req->newptr == NULL)
3008                 goto back;
3009
3010         if (v <= 0) {
3011                 error = EINVAL;
3012                 goto back;
3013         }
3014
3015         if (v != sc->re_sim_time) {
3016                 sc->re_sim_time = v;
3017
3018                 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3019                     IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) {
3020 #ifdef foo
3021                         int reg;
3022
3023                         /*
3024                          * Following code causes various strange
3025                          * performance problems.  Hmm ...
3026                          */
3027                         CSR_WRITE_2(sc, RE_IMR, 0);
3028                         if (!RE_IS_8139CP(sc))
3029                                 reg = RE_TIMERINT_8169;
3030                         else
3031                                 reg = RE_TIMERINT;
3032                         CSR_WRITE_4(sc, reg, 0);
3033                         CSR_READ_4(sc, reg); /* flush */
3034
3035                         CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3036                         re_setup_sim_im(sc);
3037 #else
3038                         re_setup_intr(sc, 0, RE_IMTYPE_NONE);
3039                         DELAY(10);
3040                         re_setup_intr(sc, 1, RE_IMTYPE_SIM);
3041 #endif
3042                 }
3043         }
3044 back:
3045         lwkt_serialize_exit(ifp->if_serializer);
3046         return error;
3047 }
3048
3049 static int
3050 re_sysctl_imtype(SYSCTL_HANDLER_ARGS)
3051 {
3052         struct re_softc *sc = arg1;
3053         struct ifnet *ifp = &sc->arpcom.ac_if;
3054         int error, v;
3055
3056         lwkt_serialize_enter(ifp->if_serializer);
3057
3058         v = sc->re_imtype;
3059         error = sysctl_handle_int(oidp, &v, 0, req);
3060         if (error || req->newptr == NULL)
3061                 goto back;
3062
3063         if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) {
3064                 error = EINVAL;
3065                 goto back;
3066         }
3067         if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) {
3068                 /* Can't do hardware interrupt moderation */
3069                 error = EOPNOTSUPP;
3070                 goto back;
3071         }
3072
3073         if (v != sc->re_imtype) {
3074                 sc->re_imtype = v;
3075                 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3076                     IFF_RUNNING)
3077                         re_setup_intr(sc, 1, sc->re_imtype);
3078         }
3079 back:
3080         lwkt_serialize_exit(ifp->if_serializer);
3081         return error;
3082 }
3083
3084 static void
3085 re_setup_hw_im(struct re_softc *sc)
3086 {
3087         KKASSERT(sc->re_caps & RE_C_HWIM);
3088
3089         /*
3090          * Interrupt moderation
3091          *
3092          * 0xABCD
3093          * A - unknown (maybe TX related)
3094          * B - TX timer (unit: 25us)
3095          * C - unknown (maybe RX related)
3096          * D - RX timer (unit: 25us)
3097          *
3098          *
3099          * re(4)'s interrupt moderation is actually controlled by
3100          * two variables, like most other NICs (bge, bce etc.)
3101          * o  timer
3102          * o  number of packets [P]
3103          *
3104          * The logic relationship between these two variables is
3105          * similar to other NICs too:
3106          * if (timer expire || packets > [P])
3107          *     Interrupt is delivered
3108          *
3109          * Currently we only know how to set 'timer', but not
3110          * 'number of packets', which should be ~30, as far as I
3111          * tested (sink ~900Kpps, interrupt rate is 30KHz)
3112          */
3113         CSR_WRITE_2(sc, RE_IM,
3114                     RE_IM_RXTIME(sc->re_rx_time) |
3115                     RE_IM_TXTIME(sc->re_tx_time) |
3116                     RE_IM_MAGIC);
3117 }
3118
3119 static void
3120 re_disable_hw_im(struct re_softc *sc)
3121 {
3122         if (sc->re_caps & RE_C_HWIM)
3123                 CSR_WRITE_2(sc, RE_IM, 0);
3124 }
3125
3126 static void
3127 re_setup_sim_im(struct re_softc *sc)
3128 {
3129         if (!RE_IS_8139CP(sc)) {
3130                 uint32_t ticks;
3131
3132                 /*
3133                  * Datasheet says tick decreases at bus speed,
3134                  * but it seems the clock runs a little bit
3135                  * faster, so we do some compensation here.
3136                  */
3137                 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5;
3138                 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks);
3139         } else {
3140                 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */
3141         }
3142         CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
3143         sc->re_flags |= RE_F_TIMER_INTR;
3144 }
3145
3146 static void
3147 re_disable_sim_im(struct re_softc *sc)
3148 {
3149         if (!RE_IS_8139CP(sc))
3150                 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0);
3151         else
3152                 CSR_WRITE_4(sc, RE_TIMERINT, 0);
3153         sc->re_flags &= ~RE_F_TIMER_INTR;
3154 }
3155
3156 static void
3157 re_config_imtype(struct re_softc *sc, int imtype)
3158 {
3159         switch (imtype) {
3160         case RE_IMTYPE_HW:
3161                 KKASSERT(sc->re_caps & RE_C_HWIM);
3162                 /* FALL THROUGH */
3163         case RE_IMTYPE_NONE:
3164                 sc->re_intrs = RE_INTRS;
3165                 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW |
3166                                 RE_ISR_RX_OVERRUN;
3167                 sc->re_tx_ack = RE_ISR_TX_OK;
3168                 break;
3169
3170         case RE_IMTYPE_SIM:
3171                 sc->re_intrs = RE_INTRS_TIMER;
3172                 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED;
3173                 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED;
3174                 break;
3175
3176         default:
3177                 panic("%s: unknown imtype %d\n",
3178                       sc->arpcom.ac_if.if_xname, imtype);
3179         }
3180 }
3181
3182 static void
3183 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype)
3184 {
3185         re_config_imtype(sc, imtype);
3186
3187         if (enable_intrs)
3188                 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3189         else
3190                 CSR_WRITE_2(sc, RE_IMR, 0); 
3191
3192         switch (imtype) {
3193         case RE_IMTYPE_NONE:
3194                 re_disable_sim_im(sc);
3195                 re_disable_hw_im(sc);
3196                 break;
3197
3198         case RE_IMTYPE_HW:
3199                 KKASSERT(sc->re_caps & RE_C_HWIM);
3200                 re_disable_sim_im(sc);
3201                 re_setup_hw_im(sc);
3202                 break;
3203
3204         case RE_IMTYPE_SIM:
3205                 re_disable_hw_im(sc);
3206                 re_setup_sim_im(sc);
3207                 break;
3208
3209         default:
3210                 panic("%s: unknown imtype %d\n",
3211                       sc->arpcom.ac_if.if_xname, imtype);
3212         }
3213 }
3214
3215 static void
3216 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr)
3217 {
3218         int i;
3219
3220         if (sc->re_macver == RE_MACVER_11 ||
3221             sc->re_macver == RE_MACVER_12 ||
3222             sc->re_macver == RE_MACVER_30 ||
3223             sc->re_macver == RE_MACVER_31) {
3224                 uint16_t re_did;
3225
3226                 re_get_eewidth(sc);
3227                 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
3228                 if (re_did == 0x8128) {
3229                         uint16_t as[ETHER_ADDR_LEN / 2];
3230                         int eaddr_off;
3231
3232                         if (sc->re_macver == RE_MACVER_30 ||
3233                             sc->re_macver == RE_MACVER_31)
3234                                 eaddr_off = RE_EE_EADDR1;
3235                         else
3236                                 eaddr_off = RE_EE_EADDR0;
3237
3238                         /*
3239                          * Get station address from the EEPROM.
3240                          */
3241                         re_read_eeprom(sc, (caddr_t)as, eaddr_off, 3);
3242                         for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
3243                                 as[i] = le16toh(as[i]);
3244                         bcopy(as, eaddr, sizeof(eaddr));
3245                         return;
3246                 }
3247         }
3248
3249         /*
3250          * Get station address from IDRx.
3251          */
3252         for (i = 0; i < ETHER_ADDR_LEN; ++i)
3253                 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
3254 }
3255
3256 static int
3257 re_jpool_alloc(struct re_softc *sc)
3258 {
3259         struct re_list_data *ldata = &sc->re_ldata;
3260         struct re_jbuf *jbuf;
3261         bus_addr_t paddr;
3262         bus_size_t jpool_size;
3263         bus_dmamem_t dmem;
3264         caddr_t buf;
3265         int i, error;
3266
3267         lwkt_serialize_init(&ldata->re_jbuf_serializer);
3268
3269         ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc),
3270                                  M_DEVBUF, M_WAITOK | M_ZERO);
3271
3272         jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE;
3273
3274         error = bus_dmamem_coherent(sc->re_parent_tag,
3275                         RE_RXBUF_ALIGN, 0,
3276                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3277                         jpool_size, BUS_DMA_WAITOK, &dmem);
3278         if (error) {
3279                 device_printf(sc->re_dev, "could not allocate jumbo memory\n");
3280                 return error;
3281         }
3282         ldata->re_jpool_tag = dmem.dmem_tag;
3283         ldata->re_jpool_map = dmem.dmem_map;
3284         ldata->re_jpool = dmem.dmem_addr;
3285         paddr = dmem.dmem_busaddr;
3286
3287         /* ..and split it into 9KB chunks */
3288         SLIST_INIT(&ldata->re_jbuf_free);
3289
3290         buf = ldata->re_jpool;
3291         for (i = 0; i < RE_JBUF_COUNT(sc); i++) {
3292                 jbuf = &ldata->re_jbuf[i];
3293
3294                 jbuf->re_sc = sc;
3295                 jbuf->re_inuse = 0;
3296                 jbuf->re_slot = i;
3297                 jbuf->re_buf = buf;
3298                 jbuf->re_paddr = paddr;
3299
3300                 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3301
3302                 buf += RE_JBUF_SIZE;
3303                 paddr += RE_JBUF_SIZE;
3304         }
3305         return 0;
3306 }
3307
3308 static void
3309 re_jpool_free(struct re_softc *sc)
3310 {
3311         struct re_list_data *ldata = &sc->re_ldata;
3312
3313         if (ldata->re_jpool_tag != NULL) {
3314                 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map);
3315                 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool,
3316                                 ldata->re_jpool_map);
3317                 bus_dma_tag_destroy(ldata->re_jpool_tag);
3318                 ldata->re_jpool_tag = NULL;
3319         }
3320
3321         if (ldata->re_jbuf != NULL) {
3322                 kfree(ldata->re_jbuf, M_DEVBUF);
3323                 ldata->re_jbuf = NULL;
3324         }
3325 }
3326
3327 static struct re_jbuf *
3328 re_jbuf_alloc(struct re_softc *sc)
3329 {
3330         struct re_list_data *ldata = &sc->re_ldata;
3331         struct re_jbuf *jbuf;
3332
3333         lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3334
3335         jbuf = SLIST_FIRST(&ldata->re_jbuf_free);
3336         if (jbuf != NULL) {
3337                 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link);
3338                 jbuf->re_inuse = 1;
3339         }
3340
3341         lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3342
3343         return jbuf;
3344 }
3345
3346 static void
3347 re_jbuf_free(void *arg)
3348 {
3349         struct re_jbuf *jbuf = arg;
3350         struct re_softc *sc = jbuf->re_sc;
3351         struct re_list_data *ldata = &sc->re_ldata;
3352
3353         if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3354                 panic("%s: free wrong jumbo buffer\n",
3355                       sc->arpcom.ac_if.if_xname);
3356         } else if (jbuf->re_inuse == 0) {
3357                 panic("%s: jumbo buffer already freed\n",
3358                       sc->arpcom.ac_if.if_xname);
3359         }
3360
3361         lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3362         atomic_subtract_int(&jbuf->re_inuse, 1);
3363         if (jbuf->re_inuse == 0)
3364                 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3365         lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3366 }
3367
3368 static void
3369 re_jbuf_ref(void *arg)
3370 {
3371         struct re_jbuf *jbuf = arg;
3372         struct re_softc *sc = jbuf->re_sc;
3373         struct re_list_data *ldata = &sc->re_ldata;
3374
3375         if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3376                 panic("%s: ref wrong jumbo buffer\n",
3377                       sc->arpcom.ac_if.if_xname);
3378         } else if (jbuf->re_inuse == 0) {
3379                 panic("%s: jumbo buffer already freed\n",
3380                       sc->arpcom.ac_if.if_xname);
3381         }
3382         atomic_add_int(&jbuf->re_inuse, 1);
3383 }