sys/platform/pc64/amd64/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * Copyright (c) 2008 The DragonFly Project.
   6  * All rights reserved.
   7  *
   8  * This code is derived from software contributed to Berkeley by
   9  * William Jolitz.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions
  13  * are met:
  14  * 1. Redistributions of source code must retain the above copyright
  15  *    notice, this list of conditions and the following disclaimer.
  16  * 2. Redistributions in binary form must reproduce the above copyright
  17  *    notice, this list of conditions and the following disclaimer in the
  18  *    documentation and/or other materials provided with the distribution.
  19  * 3. All advertising materials mentioning features or use of this software
  20  *    must display the following acknowledgement:
  21  *      This product includes software developed by the University of
  22  *      California, Berkeley and its contributors.
  23  * 4. Neither the name of the University nor the names of its contributors
  24  *    may be used to endorse or promote products derived from this software
  25  *    without specific prior written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  28  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  29  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  30  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  31  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  35  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  36  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  37  * SUCH DAMAGE.
  38  *
  39  * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  40  * $DragonFly: src/sys/platform/pc64/amd64/identcpu.c,v 1.2 2008/11/24 13:14:21 swildner Exp $
  41  */
  42
  43 #include "opt_cpu.h"
  44
  45 #include <sys/param.h>
  46 #include <sys/bus.h>
  47 #if JG
  48 #include <sys/cpu.h>
  49 #endif
  50 #include <sys/eventhandler.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/power.h>
  55
  56 #include <machine/asmacros.h>
  57 #include <machine/clock.h>
  58 #include <machine/cputypes.h>
  59 #include <machine/frame.h>
  60 #include <machine_base/isa/intr_machdep.h>
  61 #include <machine/segments.h>
  62 #include <machine/specialreg.h>
  63 #include <machine/md_var.h>
  64
  65 #if JG
  66 #include <amd64/isa/icu.h>
  67 #endif
  68
  69 /* XXX - should be in header file: */
  70 void printcpuinfo(void);
  71 void identify_cpu(void);
  72 void earlysetcpuclass(void);
  73 void panicifcpuunsupported(void);
  74
  75 static void print_AMD_info(void);
  76 static void print_AMD_assoc(int i);
  77
  78 int     cpu_class;
  79 char machine[] = "amd64";
  80 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
  81     machine, 0, "Machine class");
  82
  83 static char cpu_model[128];
  84 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
  85     cpu_model, 0, "Machine model");
  86
  87 static int hw_clockrate;
  88 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
  89     &hw_clockrate, 0, "CPU instruction clock rate");
  90
  91 static char cpu_brand[48];
  92
  93 static struct {
  94         char    *cpu_name;
  95         int     cpu_class;
  96 } amd64_cpus[] = {
  97         { "64-bit-cpu",         CPUCLASS_686 }
  98 };
  99
 100 int cpu_cores;
 101 int cpu_logical;
 102
 103
 104 extern int pq_l2size;
 105 extern int pq_l2nways;
 106
 107 void
 108 printcpuinfo(void)
 109 {
 110         u_int regs[4], i;
 111         char *brand;
 112
 113         cpu_class = amd64_cpus[cpu].cpu_class;
 114         kprintf("CPU: ");
 115         strncpy(cpu_model, amd64_cpus[cpu].cpu_name, sizeof (cpu_model));
 116
 117         /* Check for extended CPUID information and a processor name. */
 118         if (cpu_exthigh >= 0x80000004) {
 119                 brand = cpu_brand;
 120                 for (i = 0x80000002; i < 0x80000005; i++) {
 121                         do_cpuid(i, regs);
 122                         memcpy(brand, regs, sizeof(regs));
 123                         brand += sizeof(regs);
 124                 }
 125         }
 126
 127         if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
 128                 /* Please make up your mind folks! */
 129                 strcat(cpu_model, "EM64T");
 130         } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
 131                 /*
 132                  * Values taken from AMD Processor Recognition
 133                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 134                  * (also describes ``Features'' encodings.
 135                  */
 136                 strcpy(cpu_model, "AMD ");
 137                 switch (cpu_id & 0xF00) {
 138                 case 0xf00:
 139                         strcat(cpu_model, "AMD64 Processor");
 140                         break;
 141                 default:
 142                         strcat(cpu_model, "Unknown");
 143                         break;
 144                 }
 145         }
 146
 147         /*
 148          * Replace cpu_model with cpu_brand minus leading spaces if
 149          * we have one.
 150          */
 151         brand = cpu_brand;
 152         while (*brand == ' ')
 153                 ++brand;
 154         if (*brand != '\0')
 155                 strcpy(cpu_model, brand);
 156
 157         kprintf("%s (", cpu_model);
 158
 159 #if JG
 160         hw_clockrate = (tsc_freq + 5000) / 1000000;
 161         kprintf("%jd.%02d-MHz ",
 162                (intmax_t)(tsc_freq + 4999) / 1000000,
 163                (u_int)((tsc_freq + 4999) / 10000) % 100);
 164 #endif
 165
 166         switch(cpu_class) {
 167         default:
 168                 kprintf("64-bit-class");
 169         }
 170         kprintf("-class CPU)\n");
 171         if(*cpu_vendor)
 172                 kprintf("  Origin = \"%s\"",cpu_vendor);
 173         if(cpu_id)
 174                 kprintf("  Id = 0x%x", cpu_id);
 175
 176         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
 177             strcmp(cpu_vendor, "AuthenticAMD") == 0) {
 178                 kprintf("  Stepping = %u", cpu_id & 0xf);
 179                 if (cpu_high > 0) {
 180                         u_int cmp = 1, htt = 1;
 181
 182                         /*
 183                          * Here we should probably set up flags indicating
 184                          * whether or not various features are available.
 185                          * The interesting ones are probably VME, PSE, PAE,
 186                          * and PGE.  The code already assumes without bothering
 187                          * to check that all CPUs >= Pentium have a TSC and
 188                          * MSRs.
 189                          */
 190                         kprintf("\n  Features=0x%b", cpu_feature,
 191                         "\020"
 192                         "\001FPU"       /* Integral FPU */
 193                         "\002VME"       /* Extended VM86 mode support */
 194                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 195                         "\004PSE"       /* 4MByte page tables */
 196                         "\005TSC"       /* Timestamp counter */
 197                         "\006MSR"       /* Machine specific registers */
 198                         "\007PAE"       /* Physical address extension */
 199                         "\010MCE"       /* Machine Check support */
 200                         "\011CX8"       /* CMPEXCH8 instruction */
 201                         "\012APIC"      /* SMP local APIC */
 202                         "\013oldMTRR"   /* Previous implementation of MTRR */
 203                         "\014SEP"       /* Fast System Call */
 204                         "\015MTRR"      /* Memory Type Range Registers */
 205                         "\016PGE"       /* PG_G (global bit) support */
 206                         "\017MCA"       /* Machine Check Architecture */
 207                         "\020CMOV"      /* CMOV instruction */
 208                         "\021PAT"       /* Page attributes table */
 209                         "\022PSE36"     /* 36 bit address space support */
 210                         "\023PN"        /* Processor Serial number */
 211                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 212                         "\025<b20>"
 213                         "\026DTS"       /* Debug Trace Store */
 214                         "\027ACPI"      /* ACPI support */
 215                         "\030MMX"       /* MMX instructions */
 216                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 217                         "\032SSE"       /* Streaming SIMD Extensions */
 218                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 219                         "\034SS"        /* Self snoop */
 220                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 221                         "\036TM"        /* Thermal Monitor clock slowdown */
 222                         "\037IA64"      /* CPU can execute IA64 instructions */
 223                         "\040PBE"       /* Pending Break Enable */
 224                         );
 225
 226                         if (cpu_feature2 != 0) {
 227                                 kprintf("\n  Features2=0x%b", cpu_feature2,
 228                                 "\020"
 229                                 "\001SSE3"      /* SSE3 */
 230                                 "\002<b1>"
 231                                 "\003DTES64"    /* 64-bit Debug Trace */
 232                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 233                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 234                                 "\006VMX"       /* Virtual Machine Extensions */
 235                                 "\007SMX"       /* Safer Mode Extensions */
 236                                 "\010EST"       /* Enhanced SpeedStep */
 237                                 "\011TM2"       /* Thermal Monitor 2 */
 238                                 "\012SSSE3"     /* SSSE3 */
 239                                 "\013CNXT-ID"   /* L1 context ID available */
 240                                 "\014<b11>"
 241                                 "\015<b12>"
 242                                 "\016CX16"      /* CMPXCHG16B Instruction */
 243                                 "\017xTPR"      /* Send Task Priority Messages*/
 244                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 245                                 "\021<b16>"
 246                                 "\022<b17>"
 247                                 "\023DCA"       /* Direct Cache Access */
 248                                 "\024SSE4.1"
 249                                 "\025SSE4.2"
 250                                 "\026x2APIC"    /* xAPIC Extensions */
 251                                 "\027MOVBE"     /* MOVBE instruction */
 252                                 "\030POPCNT"
 253                                 "\031<b24>"
 254                                 "\032<b25>"
 255                                 "\033XSAVE"
 256                                 "\034OSXSAVE"
 257                                 "\035<b28>"
 258                                 "\036<b29>"
 259                                 "\037<b30>"
 260                                 "\040<b31>"
 261                                 );
 262                         }
 263
 264                         /*
 265                          * AMD64 Architecture Programmer's Manual Volume 3:
 266                          * General-Purpose and System Instructions
 267                          * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
 268                          *
 269                          * IA-32 Intel Architecture Software Developer's Manual,
 270                          * Volume 2A: Instruction Set Reference, A-M
 271                          * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
 272                          */
 273                         if (amd_feature != 0) {
 274                                 kprintf("\n  AMD Features=0x%b", amd_feature,
 275                                 "\020"          /* in hex */
 276                                 "\001<s0>"      /* Same */
 277                                 "\002<s1>"      /* Same */
 278                                 "\003<s2>"      /* Same */
 279                                 "\004<s3>"      /* Same */
 280                                 "\005<s4>"      /* Same */
 281                                 "\006<s5>"      /* Same */
 282                                 "\007<s6>"      /* Same */
 283                                 "\010<s7>"      /* Same */
 284                                 "\011<s8>"      /* Same */
 285                                 "\012<s9>"      /* Same */
 286                                 "\013<b10>"     /* Undefined */
 287                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 288                                 "\015<s12>"     /* Same */
 289                                 "\016<s13>"     /* Same */
 290                                 "\017<s14>"     /* Same */
 291                                 "\020<s15>"     /* Same */
 292                                 "\021<s16>"     /* Same */
 293                                 "\022<s17>"     /* Same */
 294                                 "\023<b18>"     /* Reserved, unknown */
 295                                 "\024MP"        /* Multiprocessor Capable */
 296                                 "\025NX"        /* Has EFER.NXE, NX */
 297                                 "\026<b21>"     /* Undefined */
 298                                 "\027MMX+"      /* AMD MMX Extensions */
 299                                 "\030<s23>"     /* Same */
 300                                 "\031<s24>"     /* Same */
 301                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 302                                 "\033Page1GB"   /* 1-GB large page support */
 303                                 "\034RDTSCP"    /* RDTSCP */
 304                                 "\035<b28>"     /* Undefined */
 305                                 "\036LM"        /* 64 bit long mode */
 306                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 307                                 "\0403DNow!"    /* AMD 3DNow! */
 308                                 );
 309                         }
 310
 311                         if (amd_feature2 != 0) {
 312                                 kprintf("\n  AMD Features2=0x%b", amd_feature2,
 313                                 "\020"
 314                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 315                                 "\002CMP"       /* CMP legacy */
 316                                 "\003SVM"       /* Secure Virtual Mode */
 317                                 "\004ExtAPIC"   /* Extended APIC register */
 318                                 "\005CR8"       /* CR8 in legacy mode */
 319                                 "\006<b5>"
 320                                 "\007<b6>"
 321                                 "\010<b7>"
 322                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 323                                 "\012<b9>"
 324                                 "\013<b10>"
 325                                 "\014<b11>"
 326                                 "\015<b12>"
 327                                 "\016<b13>"
 328                                 "\017<b14>"
 329                                 "\020<b15>"
 330                                 "\021<b16>"
 331                                 "\022<b17>"
 332                                 "\023<b18>"
 333                                 "\024<b19>"
 334                                 "\025<b20>"
 335                                 "\026<b21>"
 336                                 "\027<b22>"
 337                                 "\030<b23>"
 338                                 "\031<b24>"
 339                                 "\032<b25>"
 340                                 "\033<b26>"
 341                                 "\034<b27>"
 342                                 "\035<b28>"
 343                                 "\036<b29>"
 344                                 "\037<b30>"
 345                                 "\040<b31>"
 346                                 );
 347                         }
 348
 349                         if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor,
 350                             "AuthenticAMD") == 0)
 351                                 cpu_feature &= ~CPUID_HTT;
 352
 353                         /*
 354                          * If this CPU supports HTT or CMP then mention the
 355                          * number of physical/logical cores it contains.
 356                          */
 357                         if (cpu_feature & CPUID_HTT)
 358                                 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
 359                         if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
 360                             (amd_feature2 & AMDID2_CMP))
 361                                 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
 362                         else if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
 363                             (cpu_high >= 4)) {
 364                                 cpuid_count(4, 0, regs);
 365                                 if ((regs[0] & 0x1f) != 0)
 366                                         cmp = ((regs[0] >> 26) & 0x3f) + 1;
 367                         }
 368                         cpu_cores = cmp;
 369                         cpu_logical = htt / cmp;
 370                         if (cmp > 1)
 371                                 kprintf("\n  Cores per package: %d", cmp);
 372                         if ((htt / cmp) > 1)
 373                                 kprintf("\n  Logical CPUs per core: %d",
 374                                     cpu_logical);
 375                 }
 376         }
 377         /* Avoid ugly blank lines: only print newline when we have to. */
 378         if (*cpu_vendor || cpu_id)
 379                 kprintf("\n");
 380
 381         if (!bootverbose)
 382                 return;
 383
 384         if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
 385                 print_AMD_info();
 386 }
 387
 388 void
 389 panicifcpuunsupported(void)
 390 {
 391 #ifndef HAMMER_CPU
 392 #error "You need to specify a cpu type"
 393 #endif
 394 #if 0
 395         /*
 396          * Now that we have told the user what they have,
 397          * let them know if that machine type isn't configured.
 398          */
 399         switch (cpu_class) {
 400         /*
 401          * A 286 and 386 should not make it this far, anyway.
 402          */
 403         case CPUCLASS_286:
 404         case CPUCLASS_386:
 405 #if !defined(I486_CPU)
 406         case CPUCLASS_486:
 407 #endif
 408 #if !defined(I586_CPU)
 409         case CPUCLASS_586:
 410 #endif
 411 #if !defined(I686_CPU)
 412         case CPUCLASS_686:
 413 #endif
 414                 panic("CPU class not configured");
 415         default:
 416                 break;
 417         }
 418 #endif
 419 }
 420
 421
 422 #if JG
 423 /* Update TSC freq with the value indicated by the caller. */
 424 static void
 425 tsc_freq_changed(void *arg, const struct cf_level *level, int status)
 426 {
 427         /* If there was an error during the transition, don't do anything. */
 428         if (status != 0)
 429                 return;
 430
 431         /* Total setting for this level gives the new frequency in MHz. */
 432         hw_clockrate = level->total_set.freq;
 433 }
 434
 435 EVENTHANDLER_DEFINE(cpufreq_post_change, tsc_freq_changed, NULL,
 436     EVENTHANDLER_PRI_ANY);
 437 #endif
 438
 439 /*
 440  * Final stage of CPU identification. -- Should I check TI?
 441  */
 442 void
 443 identify_cpu(void)
 444 {
 445         u_int regs[4];
 446
 447         do_cpuid(0, regs);
 448         cpu_high = regs[0];
 449         ((u_int *)&cpu_vendor)[0] = regs[1];
 450         ((u_int *)&cpu_vendor)[1] = regs[3];
 451         ((u_int *)&cpu_vendor)[2] = regs[2];
 452         cpu_vendor[12] = '\0';
 453
 454         do_cpuid(1, regs);
 455         cpu_id = regs[0];
 456         cpu_procinfo = regs[1];
 457         cpu_feature = regs[3];
 458         cpu_feature2 = regs[2];
 459
 460         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
 461             strcmp(cpu_vendor, "AuthenticAMD") == 0) {
 462                 do_cpuid(0x80000000, regs);
 463                 cpu_exthigh = regs[0];
 464         }
 465         if (cpu_exthigh >= 0x80000001) {
 466                 do_cpuid(0x80000001, regs);
 467                 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
 468                 amd_feature2 = regs[2];
 469         }
 470         if (cpu_exthigh >= 0x80000008) {
 471                 do_cpuid(0x80000008, regs);
 472                 cpu_procinfo2 = regs[2];
 473         }
 474
 475         /* XXX */
 476         cpu = 0;
 477 }
 478
 479 static void
 480 print_AMD_assoc(int i)
 481 {
 482         if (i == 255)
 483                 kprintf(", fully associative\n");
 484         else
 485                 kprintf(", %d-way associative\n", i);
 486 }
 487
 488 static void
 489 print_AMD_l2_assoc(int i)
 490 {
 491         switch (i & 0x0f) {
 492         case 0: kprintf(", disabled/not present\n"); break;
 493         case 1: kprintf(", direct mapped\n"); break;
 494         case 2: kprintf(", 2-way associative\n"); break;
 495         case 4: kprintf(", 4-way associative\n"); break;
 496         case 6: kprintf(", 8-way associative\n"); break;
 497         case 8: kprintf(", 16-way associative\n"); break;
 498         case 15: kprintf(", fully associative\n"); break;
 499         default: kprintf(", reserved configuration\n"); break;
 500         }
 501 }
 502
 503 static void
 504 print_AMD_info(void)
 505 {
 506         u_int regs[4];
 507
 508         if (cpu_exthigh < 0x80000005)
 509                 return;
 510
 511         do_cpuid(0x80000005, regs);
 512         kprintf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff);
 513         print_AMD_assoc(regs[0] >> 24);
 514
 515         kprintf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff);
 516         print_AMD_assoc((regs[0] >> 8) & 0xff);
 517
 518         kprintf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff);
 519         print_AMD_assoc(regs[1] >> 24);
 520
 521         kprintf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff);
 522         print_AMD_assoc((regs[1] >> 8) & 0xff);
 523
 524         kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
 525         kprintf(", %d bytes/line", regs[2] & 0xff);
 526         kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
 527         print_AMD_assoc((regs[2] >> 16) & 0xff);
 528
 529         kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
 530         kprintf(", %d bytes/line", regs[3] & 0xff);
 531         kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
 532         print_AMD_assoc((regs[3] >> 16) & 0xff);
 533
 534         if (cpu_exthigh >= 0x80000006) {
 535                 do_cpuid(0x80000006, regs);
 536                 if ((regs[0] >> 16) != 0) {
 537                         kprintf("L2 2MB data TLB: %d entries",
 538                             (regs[0] >> 16) & 0xfff);
 539                         print_AMD_l2_assoc(regs[0] >> 28);
 540                         kprintf("L2 2MB instruction TLB: %d entries",
 541                             regs[0] & 0xfff);
 542                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
 543                 } else {
 544                         kprintf("L2 2MB unified TLB: %d entries",
 545                             regs[0] & 0xfff);
 546                         print_AMD_l2_assoc((regs[0] >> 28) & 0xf);
 547                 }
 548                 if ((regs[1] >> 16) != 0) {
 549                         kprintf("L2 4KB data TLB: %d entries",
 550                             (regs[1] >> 16) & 0xfff);
 551                         print_AMD_l2_assoc(regs[1] >> 28);
 552
 553                         kprintf("L2 4KB instruction TLB: %d entries",
 554                             (regs[1] >> 16) & 0xfff);
 555                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
 556                 } else {
 557                         kprintf("L2 4KB unified TLB: %d entries",
 558                             (regs[1] >> 16) & 0xfff);
 559                         print_AMD_l2_assoc((regs[1] >> 28) & 0xf);
 560                 }
 561                 kprintf("L2 unified cache: %d kbytes", regs[2] >> 16);
 562                 kprintf(", %d bytes/line", regs[2] & 0xff);
 563                 kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
 564                 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f);
 565         }
 566 }