sys/platform/pc32/apic/apic_vector.s

   1 /*
   2  *      from: vector.s, 386BSD 0.1 unknown origin
   3  * $FreeBSD: src/sys/i386/isa/apic_vector.s,v 1.47.2.5 2001/09/01 22:33:38 tegge Exp $
   4  * $DragonFly: src/sys/platform/pc32/apic/apic_vector.s,v 1.39 2008/08/02 01:14:43 dillon Exp $
   5  */
   6
   7 #include "use_npx.h"
   8 #include "opt_auto_eoi.h"
   9
  10 #include <machine/asmacros.h>
  11 #include <machine/lock.h>
  12 #include <machine/psl.h>
  13 #include <machine/trap.h>
  14
  15 #include <machine_base/icu/icu.h>
  16 #include <bus/isa/isa.h>
  17
  18 #include "assym.s"
  19
  20 #include "apicreg.h"
  21 #include "apic_ipl.h"
  22 #include <machine/smp.h>
  23 #include <machine_base/isa/intr_machdep.h>
  24
  25 /* convert an absolute IRQ# into a bitmask */
  26 #define IRQ_LBIT(irq_num)       (1 << (irq_num))
  27
  28 /* make an index into the IO APIC from the IRQ# */
  29 #define REDTBL_IDX(irq_num)     (0x10 + ((irq_num) * 2))
  30
  31 #ifdef SMP
  32 #define MPLOCKED     lock ;
  33 #else
  34 #define MPLOCKED
  35 #endif
  36
  37 /*
  38  * Push an interrupt frame in a format acceptable to doreti, reload
  39  * the segment registers for the kernel.
  40  */
  41 #define PUSH_FRAME                                                      \
  42         pushl   $0 ;            /* dummy error code */                  \
  43         pushl   $0 ;            /* dummy trap type */                   \
  44         pushl   $0 ;            /* dummy xflags type */                 \
  45         pushal ;                                                        \
  46         pushl   %ds ;           /* save data and extra segments ... */  \
  47         pushl   %es ;                                                   \
  48         pushl   %fs ;                                                   \
  49         pushl   %gs ;                                                   \
  50         cld ;                                                           \
  51         mov     $KDSEL,%ax ;                                            \
  52         mov     %ax,%ds ;                                               \
  53         mov     %ax,%es ;                                               \
  54         mov     %ax,%gs ;                                               \
  55         mov     $KPSEL,%ax ;                                            \
  56         mov     %ax,%fs ;                                               \
  57
  58 #define PUSH_DUMMY                                                      \
  59         pushfl ;                /* phys int frame / flags */            \
  60         pushl %cs ;             /* phys int frame / cs */               \
  61         pushl   12(%esp) ;      /* original caller eip */               \
  62         pushl   $0 ;            /* dummy error code */                  \
  63         pushl   $0 ;            /* dummy trap type */                   \
  64         pushl   $0 ;            /* dummy xflags type */                 \
  65         subl    $13*4,%esp ;    /* pushal + 4 seg regs (dummy) + CPL */ \
  66
  67 /*
  68  * Warning: POP_FRAME can only be used if there is no chance of a
  69  * segment register being changed (e.g. by procfs), which is why syscalls
  70  * have to use doreti.
  71  */
  72 #define POP_FRAME                                                       \
  73         popl    %gs ;                                                   \
  74         popl    %fs ;                                                   \
  75         popl    %es ;                                                   \
  76         popl    %ds ;                                                   \
  77         popal ;                                                         \
  78         addl    $3*4,%esp ;     /* dummy xflags, trap & error codes */  \
  79
  80 #define POP_DUMMY                                                       \
  81         addl    $19*4,%esp ;                                            \
  82
  83 #define IOAPICADDR(irq_num) \
  84         CNAME(int_to_apicintpin) + IOAPIC_IM_SIZE * (irq_num) + IOAPIC_IM_ADDR
  85 #define REDIRIDX(irq_num) \
  86         CNAME(int_to_apicintpin) + IOAPIC_IM_SIZE * (irq_num) + IOAPIC_IM_ENTIDX
  87
  88 #define MASK_IRQ(irq_num)                                               \
  89         APIC_IMASK_LOCK ;                       /* into critical reg */ \
  90         testl   $IRQ_LBIT(irq_num), apic_imen ;                         \
  91         jne     7f ;                    /* masked, don't mask */        \
  92         orl     $IRQ_LBIT(irq_num), apic_imen ; /* set the mask bit */  \
  93         movl    IOAPICADDR(irq_num), %ecx ;     /* ioapic addr */       \
  94         movl    REDIRIDX(irq_num), %eax ;       /* get the index */     \
  95         movl    %eax, (%ecx) ;                  /* write the index */   \
  96         orl     $IOART_INTMASK,IOAPIC_WINDOW(%ecx) ;/* set the mask */  \
  97 7: ;                                            /* already masked */    \
  98         APIC_IMASK_UNLOCK ;                                             \
  99
 100 /*
 101  * Test to see whether we are handling an edge or level triggered INT.
 102  *  Level-triggered INTs must still be masked as we don't clear the source,
 103  *  and the EOI cycle would cause redundant INTs to occur.
 104  */
 105 #define MASK_LEVEL_IRQ(irq_num)                                         \
 106         testl   $IRQ_LBIT(irq_num), apic_pin_trigger ;                  \
 107         jz      9f ;                            /* edge, don't mask */  \
 108         MASK_IRQ(irq_num) ;                                             \
 109 9: ;                                                                    \
 110
 111 /*
 112  * Test to see if the source is currntly masked, clear if so.
 113  */
 114 #define UNMASK_IRQ(irq_num)                                     \
 115         cmpl    $0,%eax ;                                               \
 116         jnz     8f ;                                                    \
 117         APIC_IMASK_LOCK ;                       /* into critical reg */ \
 118         testl   $IRQ_LBIT(irq_num), apic_imen ;                         \
 119         je      7f ;                    /* bit clear, not masked */     \
 120         andl    $~IRQ_LBIT(irq_num), apic_imen ;/* clear mask bit */    \
 121         movl    IOAPICADDR(irq_num),%ecx ;      /* ioapic addr */       \
 122         movl    REDIRIDX(irq_num), %eax ;       /* get the index */     \
 123         movl    %eax,(%ecx) ;                   /* write the index */   \
 124         andl    $~IOART_INTMASK,IOAPIC_WINDOW(%ecx) ;/* clear the mask */ \
 125 7: ;                                                                    \
 126         APIC_IMASK_UNLOCK ;                                             \
 127 8: ;                                                                    \
 128
 129 #ifdef APIC_IO
 130
 131 /*
 132  * Fast interrupt call handlers run in the following sequence:
 133  *
 134  *      - Push the trap frame required by doreti
 135  *      - Mask the interrupt and reenable its source
 136  *      - If we cannot take the interrupt set its fpending bit and
 137  *        doreti.  Note that we cannot mess with mp_lock at all
 138  *        if we entered from a critical section!
 139  *      - If we can take the interrupt clear its fpending bit,
 140  *        call the handler, then unmask and doreti.
 141  *
 142  * YYY can cache gd base opitner instead of using hidden %fs prefixes.
 143  */
 144
 145 #define FAST_INTR(irq_num, vec_name)                                    \
 146         .text ;                                                         \
 147         SUPERALIGN_TEXT ;                                               \
 148 IDTVEC(vec_name) ;                                                      \
 149         PUSH_FRAME ;                                                    \
 150         FAKE_MCOUNT(15*4(%esp)) ;                                       \
 151         MASK_LEVEL_IRQ(irq_num) ;                                       \
 152         movl    $0, lapic_eoi ;                                         \
 153         movl    PCPU(curthread),%ebx ;                                  \
 154         movl    $0,%eax ;       /* CURRENT CPL IN FRAME (REMOVED) */    \
 155         pushl   %eax ;                                                  \
 156         testl   $-1,TD_NEST_COUNT(%ebx) ;                               \
 157         jne     1f ;                                                    \
 158         cmpl    $TDPRI_CRIT,TD_PRI(%ebx) ;                              \
 159         jl      2f ;                                                    \
 160 1: ;                                                                    \
 161         /* in critical section, make interrupt pending */               \
 162         /* set the pending bit and return, leave interrupt masked */    \
 163         orl     $IRQ_LBIT(irq_num),PCPU(fpending) ;                     \
 164         orl     $RQF_INTPEND,PCPU(reqflags) ;                           \
 165         jmp     5f ;                                                    \
 166 2: ;                                                                    \
 167         /* clear pending bit, run handler */                            \
 168         andl    $~IRQ_LBIT(irq_num),PCPU(fpending) ;                    \
 169         pushl   $irq_num ;                                              \
 170         pushl   %esp ;                   /* pass frame by reference */  \
 171         call    ithread_fast_handler ;   /* returns 0 to unmask */      \
 172         addl    $8, %esp ;                                              \
 173         UNMASK_IRQ(irq_num) ;                                           \
 174 5: ;                                                                    \
 175         MEXITCOUNT ;                                                    \
 176         jmp     doreti ;                                                \
 177
 178 /*
 179  * Slow interrupt call handlers run in the following sequence:
 180  *
 181  *      - Push the trap frame required by doreti.
 182  *      - Mask the interrupt and reenable its source.
 183  *      - If we cannot take the interrupt set its ipending bit and
 184  *        doreti.  In addition to checking for a critical section
 185  *        and cpl mask we also check to see if the thread is still
 186  *        running.  Note that we cannot mess with mp_lock at all
 187  *        if we entered from a critical section!
 188  *      - If we can take the interrupt clear its ipending bit
 189  *        and schedule the thread.  Leave interrupts masked and doreti.
 190  *
 191  *      Note that calls to sched_ithd() are made with interrupts enabled
 192  *      and outside a critical section.  YYY sched_ithd may preempt us
 193  *      synchronously (fix interrupt stacking).
 194  *
 195  *      YYY can cache gd base pointer instead of using hidden %fs
 196  *      prefixes.
 197  */
 198
 199 #define SLOW_INTR(irq_num, vec_name, maybe_extra_ipending)              \
 200         .text ;                                                         \
 201         SUPERALIGN_TEXT ;                                               \
 202 IDTVEC(vec_name) ;                                                      \
 203         PUSH_FRAME ;                                                    \
 204         maybe_extra_ipending ;                                          \
 205 ;                                                                       \
 206         MASK_LEVEL_IRQ(irq_num) ;                                       \
 207         incl    PCPU(cnt) + V_INTR ;                                    \
 208         movl    $0, lapic_eoi ;                                         \
 209         movl    PCPU(curthread),%ebx ;                                  \
 210         movl    $0,%eax ;       /* CURRENT CPL IN FRAME (REMOVED) */    \
 211         pushl   %eax ;          /* cpl do restore */                    \
 212         testl   $-1,TD_NEST_COUNT(%ebx) ;                               \
 213         jne     1f ;                                                    \
 214         cmpl    $TDPRI_CRIT,TD_PRI(%ebx) ;                              \
 215         jl      2f ;                                                    \
 216 1: ;                                                                    \
 217         /* set the pending bit and return, leave the interrupt masked */ \
 218         orl     $IRQ_LBIT(irq_num), PCPU(ipending) ;                    \
 219         orl     $RQF_INTPEND,PCPU(reqflags) ;                           \
 220         jmp     5f ;                                                    \
 221 2: ;                                                                    \
 222         /* set running bit, clear pending bit, run handler */           \
 223         andl    $~IRQ_LBIT(irq_num), PCPU(ipending) ;                   \
 224         incl    TD_NEST_COUNT(%ebx) ;                                   \
 225         sti ;                                                           \
 226         pushl   $irq_num ;                                              \
 227         call    sched_ithd ;                                            \
 228         addl    $4,%esp ;                                               \
 229         cli ;                                                           \
 230         decl    TD_NEST_COUNT(%ebx) ;                                   \
 231 5: ;                                                                    \
 232         MEXITCOUNT ;                                                    \
 233         jmp     doreti ;                                                \
 234
 235 /*
 236  * Wrong interrupt call handlers.  We program these into APIC vectors
 237  * that should otherwise never occur.  For example, we program the SLOW
 238  * vector for irq N with this when we program the FAST vector with the
 239  * real interrupt.
 240  *
 241  * XXX for now all we can do is EOI it.  We can't call do_wrongintr
 242  * (yet) because we could be in a critical section.
 243  */
 244 #define WRONGINTR(irq_num,vec_name)                                     \
 245         .text ;                                                         \
 246         SUPERALIGN_TEXT  ;                                              \
 247 IDTVEC(vec_name) ;                                                      \
 248         PUSH_FRAME ;                                                    \
 249         movl    $0, lapic_eoi ; /* End Of Interrupt to APIC */          \
 250         /*pushl $irq_num ;*/                                            \
 251         /*call  do_wrongintr ;*/                                        \
 252         /*addl  $4,%esp ;*/                                             \
 253         POP_FRAME ;                                                     \
 254         iret  ;                                                         \
 255
 256 #endif
 257
 258 /*
 259  * Handle "spurious INTerrupts".
 260  * Notes:
 261  *  This is different than the "spurious INTerrupt" generated by an
 262  *   8259 PIC for missing INTs.  See the APIC documentation for details.
 263  *  This routine should NOT do an 'EOI' cycle.
 264  */
 265         .text
 266         SUPERALIGN_TEXT
 267         .globl Xspuriousint
 268 Xspuriousint:
 269
 270         /* No EOI cycle used here */
 271
 272         iret
 273
 274
 275 /*
 276  * Handle TLB shootdowns.
 277  */
 278         .text
 279         SUPERALIGN_TEXT
 280         .globl  Xinvltlb
 281 Xinvltlb:
 282         pushl   %eax
 283
 284         movl    %cr3, %eax              /* invalidate the TLB */
 285         movl    %eax, %cr3
 286
 287         ss                              /* stack segment, avoid %ds load */
 288         movl    $0, lapic_eoi           /* End Of Interrupt to APIC */
 289
 290         popl    %eax
 291         iret
 292
 293
 294 /*
 295  * Executed by a CPU when it receives an Xcpustop IPI from another CPU,
 296  *
 297  *  - Signals its receipt.
 298  *  - Waits for permission to restart.
 299  *  - Processing pending IPIQ events while waiting.
 300  *  - Signals its restart.
 301  */
 302
 303         .text
 304         SUPERALIGN_TEXT
 305         .globl Xcpustop
 306 Xcpustop:
 307         pushl   %ebp
 308         movl    %esp, %ebp
 309         pushl   %eax
 310         pushl   %ecx
 311         pushl   %edx
 312         pushl   %ds                     /* save current data segment */
 313         pushl   %fs
 314
 315         movl    $KDSEL, %eax
 316         mov     %ax, %ds                /* use KERNEL data segment */
 317         movl    $KPSEL, %eax
 318         mov     %ax, %fs
 319
 320         movl    $0, lapic_eoi           /* End Of Interrupt to APIC */
 321
 322         movl    PCPU(cpuid), %eax
 323         imull   $PCB_SIZE, %eax
 324         leal    CNAME(stoppcbs)(%eax), %eax
 325         pushl   %eax
 326         call    CNAME(savectx)          /* Save process context */
 327         addl    $4, %esp
 328
 329
 330         movl    PCPU(cpuid), %eax
 331
 332         /*
 333          * Indicate that we have stopped and loop waiting for permission
 334          * to start again.  We must still process IPI events while in a
 335          * stopped state.
 336          */
 337         MPLOCKED
 338         btsl    %eax, stopped_cpus      /* stopped_cpus |= (1<<id) */
 339 1:
 340         andl    $~RQF_IPIQ,PCPU(reqflags)
 341         pushl   %eax
 342         call    lwkt_smp_stopped
 343         popl    %eax
 344         btl     %eax, started_cpus      /* while (!(started_cpus & (1<<id))) */
 345         jnc     1b
 346
 347         MPLOCKED
 348         btrl    %eax, started_cpus      /* started_cpus &= ~(1<<id) */
 349         MPLOCKED
 350         btrl    %eax, stopped_cpus      /* stopped_cpus &= ~(1<<id) */
 351
 352         test    %eax, %eax
 353         jnz     2f
 354
 355         movl    CNAME(cpustop_restartfunc), %eax
 356         test    %eax, %eax
 357         jz      2f
 358         movl    $0, CNAME(cpustop_restartfunc)  /* One-shot */
 359
 360         call    *%eax
 361 2:
 362         popl    %fs
 363         popl    %ds                     /* restore previous data segment */
 364         popl    %edx
 365         popl    %ecx
 366         popl    %eax
 367         movl    %ebp, %esp
 368         popl    %ebp
 369         iret
 370
 371         /*
 372          * For now just have one ipiq IPI, but what we really want is
 373          * to have one for each source cpu to the APICs don't get stalled
 374          * backlogging the requests.
 375          */
 376         .text
 377         SUPERALIGN_TEXT
 378         .globl Xipiq
 379 Xipiq:
 380         PUSH_FRAME
 381         movl    $0, lapic_eoi           /* End Of Interrupt to APIC */
 382         FAKE_MCOUNT(15*4(%esp))
 383
 384         incl    PCPU(cnt) + V_IPI
 385         movl    PCPU(curthread),%ebx
 386         cmpl    $TDPRI_CRIT,TD_PRI(%ebx)
 387         jge     1f
 388         subl    $8,%esp                 /* make same as interrupt frame */
 389         pushl   %esp                    /* pass frame by reference */
 390         incl    PCPU(intr_nesting_level)
 391         addl    $TDPRI_CRIT,TD_PRI(%ebx)
 392         call    lwkt_process_ipiq_frame
 393         subl    $TDPRI_CRIT,TD_PRI(%ebx)
 394         decl    PCPU(intr_nesting_level)
 395         addl    $12,%esp
 396         pushl   $0                      /* CPL for frame (REMOVED) */
 397         MEXITCOUNT
 398         jmp     doreti
 399 1:
 400         orl     $RQF_IPIQ,PCPU(reqflags)
 401         MEXITCOUNT
 402         POP_FRAME
 403         iret
 404
 405         .text
 406         SUPERALIGN_TEXT
 407         .globl Xtimer
 408 Xtimer:
 409         PUSH_FRAME
 410         movl    $0, lapic_eoi           /* End Of Interrupt to APIC */
 411         FAKE_MCOUNT(15*4(%esp))
 412
 413         incl    PCPU(cnt) + V_TIMER
 414         movl    PCPU(curthread),%ebx
 415         cmpl    $TDPRI_CRIT,TD_PRI(%ebx)
 416         jge     1f
 417         testl   $-1,TD_NEST_COUNT(%ebx)
 418         jne     1f
 419         subl    $8,%esp                 /* make same as interrupt frame */
 420         pushl   %esp                    /* pass frame by reference */
 421         incl    PCPU(intr_nesting_level)
 422         addl    $TDPRI_CRIT,TD_PRI(%ebx)
 423         call    lapic_timer_process_frame
 424         subl    $TDPRI_CRIT,TD_PRI(%ebx)
 425         decl    PCPU(intr_nesting_level)
 426         addl    $12,%esp
 427         pushl   $0                      /* CPL for frame (REMOVED) */
 428         MEXITCOUNT
 429         jmp     doreti
 430 1:
 431         orl     $RQF_TIMER,PCPU(reqflags)
 432         MEXITCOUNT
 433         POP_FRAME
 434         iret
 435
 436 #ifdef APIC_IO
 437
 438 MCOUNT_LABEL(bintr)
 439         FAST_INTR(0,apic_fastintr0)
 440         FAST_INTR(1,apic_fastintr1)
 441         FAST_INTR(2,apic_fastintr2)
 442         FAST_INTR(3,apic_fastintr3)
 443         FAST_INTR(4,apic_fastintr4)
 444         FAST_INTR(5,apic_fastintr5)
 445         FAST_INTR(6,apic_fastintr6)
 446         FAST_INTR(7,apic_fastintr7)
 447         FAST_INTR(8,apic_fastintr8)
 448         FAST_INTR(9,apic_fastintr9)
 449         FAST_INTR(10,apic_fastintr10)
 450         FAST_INTR(11,apic_fastintr11)
 451         FAST_INTR(12,apic_fastintr12)
 452         FAST_INTR(13,apic_fastintr13)
 453         FAST_INTR(14,apic_fastintr14)
 454         FAST_INTR(15,apic_fastintr15)
 455         FAST_INTR(16,apic_fastintr16)
 456         FAST_INTR(17,apic_fastintr17)
 457         FAST_INTR(18,apic_fastintr18)
 458         FAST_INTR(19,apic_fastintr19)
 459         FAST_INTR(20,apic_fastintr20)
 460         FAST_INTR(21,apic_fastintr21)
 461         FAST_INTR(22,apic_fastintr22)
 462         FAST_INTR(23,apic_fastintr23)
 463
 464         /* YYY what is this garbage? */
 465
 466         SLOW_INTR(0,apic_slowintr0,)
 467         SLOW_INTR(1,apic_slowintr1,)
 468         SLOW_INTR(2,apic_slowintr2,)
 469         SLOW_INTR(3,apic_slowintr3,)
 470         SLOW_INTR(4,apic_slowintr4,)
 471         SLOW_INTR(5,apic_slowintr5,)
 472         SLOW_INTR(6,apic_slowintr6,)
 473         SLOW_INTR(7,apic_slowintr7,)
 474         SLOW_INTR(8,apic_slowintr8,)
 475         SLOW_INTR(9,apic_slowintr9,)
 476         SLOW_INTR(10,apic_slowintr10,)
 477         SLOW_INTR(11,apic_slowintr11,)
 478         SLOW_INTR(12,apic_slowintr12,)
 479         SLOW_INTR(13,apic_slowintr13,)
 480         SLOW_INTR(14,apic_slowintr14,)
 481         SLOW_INTR(15,apic_slowintr15,)
 482         SLOW_INTR(16,apic_slowintr16,)
 483         SLOW_INTR(17,apic_slowintr17,)
 484         SLOW_INTR(18,apic_slowintr18,)
 485         SLOW_INTR(19,apic_slowintr19,)
 486         SLOW_INTR(20,apic_slowintr20,)
 487         SLOW_INTR(21,apic_slowintr21,)
 488         SLOW_INTR(22,apic_slowintr22,)
 489         SLOW_INTR(23,apic_slowintr23,)
 490
 491         WRONGINTR(0,apic_wrongintr0)
 492         WRONGINTR(1,apic_wrongintr1)
 493         WRONGINTR(2,apic_wrongintr2)
 494         WRONGINTR(3,apic_wrongintr3)
 495         WRONGINTR(4,apic_wrongintr4)
 496         WRONGINTR(5,apic_wrongintr5)
 497         WRONGINTR(6,apic_wrongintr6)
 498         WRONGINTR(7,apic_wrongintr7)
 499         WRONGINTR(8,apic_wrongintr8)
 500         WRONGINTR(9,apic_wrongintr9)
 501         WRONGINTR(10,apic_wrongintr10)
 502         WRONGINTR(11,apic_wrongintr11)
 503         WRONGINTR(12,apic_wrongintr12)
 504         WRONGINTR(13,apic_wrongintr13)
 505         WRONGINTR(14,apic_wrongintr14)
 506         WRONGINTR(15,apic_wrongintr15)
 507         WRONGINTR(16,apic_wrongintr16)
 508         WRONGINTR(17,apic_wrongintr17)
 509         WRONGINTR(18,apic_wrongintr18)
 510         WRONGINTR(19,apic_wrongintr19)
 511         WRONGINTR(20,apic_wrongintr20)
 512         WRONGINTR(21,apic_wrongintr21)
 513         WRONGINTR(22,apic_wrongintr22)
 514         WRONGINTR(23,apic_wrongintr23)
 515 MCOUNT_LABEL(eintr)
 516
 517 #endif
 518
 519         .data
 520
 521 /* variables used by stop_cpus()/restart_cpus()/Xcpustop */
 522         .globl stopped_cpus, started_cpus
 523 stopped_cpus:
 524         .long   0
 525 started_cpus:
 526         .long   0
 527
 528         .globl CNAME(cpustop_restartfunc)
 529 CNAME(cpustop_restartfunc):
 530         .long 0
 531
 532         .globl  apic_pin_trigger
 533 apic_pin_trigger:
 534         .long   0
 535
 536         .text
 537