1 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.12 2003/06/04 17:56:59 sam Exp $ */
2 /* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */
5 * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
6 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
7 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by Jason L. Wright
22 * 4. The name of the author may not be used to endorse or promote products
23 * derived from this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
34 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
37 * Effort sponsored in part by the Defense Advanced Research Projects
38 * Agency (DARPA) and Air Force Research Laboratory, Air Force
39 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
44 * uBsec 5[56]01, 58xx hardware crypto accelerator
47 #include "opt_ubsec.h"
49 #include <sys/param.h>
50 #include <sys/systm.h>
52 #include <sys/errno.h>
53 #include <sys/malloc.h>
54 #include <sys/kernel.h>
56 #include <sys/sysctl.h>
57 #include <sys/endian.h>
61 #include <sys/random.h>
62 #include <sys/thread2.h>
67 #include <machine/clock.h>
69 #include <crypto/sha1.h>
70 #include <opencrypto/cryptodev.h>
71 #include <opencrypto/cryptosoft.h>
73 #include "cryptodev_if.h"
75 #include <bus/pci/pcivar.h>
76 #include <bus/pci/pcireg.h>
78 /* grr, #defines for gratuitous incompatibility in queue.h */
79 #define SIMPLEQ_HEAD STAILQ_HEAD
80 #define SIMPLEQ_ENTRY STAILQ_ENTRY
81 #define SIMPLEQ_INIT STAILQ_INIT
82 #define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL
83 #define SIMPLEQ_EMPTY STAILQ_EMPTY
84 #define SIMPLEQ_FIRST STAILQ_FIRST
85 #define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD
86 #define SIMPLEQ_FOREACH STAILQ_FOREACH
87 /* ditto for endian.h */
88 #define letoh16(x) le16toh(x)
89 #define letoh32(x) le32toh(x)
92 #include "../rndtest/rndtest.h"
98 * Prototypes and count for the pci_device structure
100 static int ubsec_probe(device_t);
101 static int ubsec_attach(device_t);
102 static int ubsec_detach(device_t);
103 static int ubsec_suspend(device_t);
104 static int ubsec_resume(device_t);
105 static void ubsec_shutdown(device_t);
106 static void ubsec_intr(void *);
107 static int ubsec_newsession(device_t, u_int32_t *, struct cryptoini *);
108 static int ubsec_freesession(device_t, u_int64_t);
109 static int ubsec_process(device_t, struct cryptop *, int);
110 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
111 static void ubsec_feed(struct ubsec_softc *);
112 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
113 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
114 static int ubsec_feed2(struct ubsec_softc *);
115 static void ubsec_rng(void *);
116 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
117 struct ubsec_dma_alloc *, int);
118 #define ubsec_dma_sync(_dma, _flags) \
119 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
120 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
121 static int ubsec_dmamap_aligned(struct ubsec_operand *op);
123 static void ubsec_reset_board(struct ubsec_softc *sc);
124 static void ubsec_init_board(struct ubsec_softc *sc);
125 static void ubsec_init_pciregs(device_t dev);
126 static void ubsec_totalreset(struct ubsec_softc *sc);
128 static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
130 static int ubsec_kprocess(device_t, struct cryptkop *, int);
131 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
132 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
133 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
134 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
135 static int ubsec_ksigbits(struct crparam *);
136 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
137 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
140 static device_method_t ubsec_methods[] = {
141 /* Device interface */
142 DEVMETHOD(device_probe, ubsec_probe),
143 DEVMETHOD(device_attach, ubsec_attach),
144 DEVMETHOD(device_detach, ubsec_detach),
145 DEVMETHOD(device_suspend, ubsec_suspend),
146 DEVMETHOD(device_resume, ubsec_resume),
147 DEVMETHOD(device_shutdown, ubsec_shutdown),
150 DEVMETHOD(bus_print_child, bus_generic_print_child),
151 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
153 /* crypto device methods */
154 DEVMETHOD(cryptodev_newsession, ubsec_newsession),
155 DEVMETHOD(cryptodev_freesession,ubsec_freesession),
156 DEVMETHOD(cryptodev_process, ubsec_process),
157 DEVMETHOD(cryptodev_kprocess, ubsec_kprocess),
161 static driver_t ubsec_driver = {
164 sizeof (struct ubsec_softc)
166 static devclass_t ubsec_devclass;
168 DECLARE_DUMMY_MODULE(ubsec);
169 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, NULL, NULL);
170 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
172 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
175 SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters");
178 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
179 static void ubsec_dump_mcr(struct ubsec_mcr *);
180 static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
182 static int ubsec_debug = 0;
183 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
184 0, "control debugging msgs");
187 #define READ_REG(sc,r) \
188 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
190 #define WRITE_REG(sc,reg,val) \
191 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
193 #define SWAP32(x) (x) = htole32(ntohl((x)))
194 #define HTOLE32(x) (x) = htole32(x)
197 struct ubsec_stats ubsecstats;
198 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
199 ubsec_stats, "driver statistics");
202 ubsec_probe(device_t dev)
204 if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
205 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
206 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
208 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
209 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
210 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
212 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
213 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
214 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
215 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
216 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
217 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
218 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
219 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 ||
220 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825
227 ubsec_partname(struct ubsec_softc *sc)
229 /* XXX sprintf numbers when not decoded */
230 switch (pci_get_vendor(sc->sc_dev)) {
231 case PCI_VENDOR_BROADCOM:
232 switch (pci_get_device(sc->sc_dev)) {
233 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
234 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
235 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
236 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
237 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
238 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
239 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
240 case PCI_PRODUCT_BROADCOM_5825: return "Broadcom 5825";
242 return "Broadcom unknown-part";
243 case PCI_VENDOR_BLUESTEEL:
244 switch (pci_get_device(sc->sc_dev)) {
245 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
247 return "Bluesteel unknown-part";
249 switch (pci_get_device(sc->sc_dev)) {
250 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
251 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
253 return "Sun unknown-part";
255 return "Unknown-vendor unknown-part";
259 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
261 u_int32_t *p = (u_int32_t *)buf;
262 for (count /= sizeof (u_int32_t); count; count--)
263 add_true_randomness(*p++);
267 ubsec_attach(device_t dev)
269 struct ubsec_softc *sc = device_get_softc(dev);
270 struct ubsec_dma *dmap;
274 KASSERT(sc != NULL, ("ubsec_attach: null software carrier!"));
275 bzero(sc, sizeof (*sc));
278 SIMPLEQ_INIT(&sc->sc_queue);
279 SIMPLEQ_INIT(&sc->sc_qchip);
280 SIMPLEQ_INIT(&sc->sc_queue2);
281 SIMPLEQ_INIT(&sc->sc_qchip2);
282 SIMPLEQ_INIT(&sc->sc_q2free);
284 /* XXX handle power management */
286 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
288 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
289 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
290 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
292 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
293 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
294 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
295 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
297 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
298 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
299 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
300 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
302 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
303 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
304 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
305 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 ||
306 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825)) ||
307 (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
308 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
309 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
310 /* NB: the 5821/5822 defines some additional status bits */
311 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
312 BS_STAT_MCR2_ALLEMPTY;
313 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
314 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
317 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
318 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
319 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
320 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
322 if (!(cmd & PCIM_CMD_MEMEN)) {
323 device_printf(dev, "failed to enable memory mapping\n");
327 if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
328 device_printf(dev, "failed to enable bus mastering\n");
333 * Setup memory-mapping of PCI registers.
336 sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
337 0, ~0, 1, RF_ACTIVE);
338 if (sc->sc_sr == NULL) {
339 device_printf(dev, "cannot map register space\n");
342 sc->sc_st = rman_get_bustag(sc->sc_sr);
343 sc->sc_sh = rman_get_bushandle(sc->sc_sr);
346 * Arrange interrupt line.
349 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
350 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE);
351 if (sc->sc_irq == NULL) {
352 device_printf(dev, "could not map interrupt\n");
356 * NB: Network code assumes we are blocked with splimp()
357 * so make sure the IRQ is mapped appropriately.
359 if (bus_setup_intr(dev, sc->sc_irq, 0,
362 device_printf(dev, "could not establish interrupt\n");
366 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
367 if (sc->sc_cid < 0) {
368 device_printf(dev, "could not get crypto driver id\n");
373 * Setup DMA descriptor area.
375 if (bus_dma_tag_create(NULL, /* parent */
376 1, 0, /* alignment, bounds */
377 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
378 BUS_SPACE_MAXADDR, /* highaddr */
379 NULL, NULL, /* filter, filterarg */
380 0x3ffff, /* maxsize */
381 UBS_MAX_SCATTER, /* nsegments */
382 0xffff, /* maxsegsize */
383 BUS_DMA_ALLOCNOW, /* flags */
385 device_printf(dev, "cannot allocate DMA tag\n");
388 SIMPLEQ_INIT(&sc->sc_freequeue);
390 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
393 q = kmalloc(sizeof(struct ubsec_q), M_DEVBUF, M_WAITOK);
394 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
395 &dmap->d_alloc, 0)) {
396 device_printf(dev, "cannot allocate dma buffers\n");
400 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
403 sc->sc_queuea[i] = q;
405 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
408 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
410 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
411 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
412 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
413 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
416 * Reset Broadcom chip
418 ubsec_reset_board(sc);
421 * Init Broadcom specific PCI settings
423 ubsec_init_pciregs(dev);
428 ubsec_init_board(sc);
431 if (sc->sc_flags & UBS_FLAGS_RNG) {
432 sc->sc_statmask |= BS_STAT_MCR2_DONE;
434 sc->sc_rndtest = rndtest_attach(dev);
436 sc->sc_harvest = rndtest_harvest;
438 sc->sc_harvest = default_harvest;
440 sc->sc_harvest = default_harvest;
443 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
444 &sc->sc_rng.rng_q.q_mcr, 0))
447 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
448 &sc->sc_rng.rng_q.q_ctx, 0)) {
449 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
453 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
454 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
455 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
456 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
461 sc->sc_rnghz = hz / 100;
464 callout_init(&sc->sc_rngto);
465 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
469 #endif /* UBSEC_NO_RNG */
471 if (sc->sc_flags & UBS_FLAGS_KEY) {
472 sc->sc_statmask |= BS_STAT_MCR2_DONE;
474 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0);
476 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0);
481 crypto_unregister_all(sc->sc_cid);
483 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
485 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
487 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
493 * Detach a device that successfully probed.
496 ubsec_detach(device_t dev)
498 struct ubsec_softc *sc = device_get_softc(dev);
500 KASSERT(sc != NULL, ("ubsec_detach: null software carrier"));
502 /* XXX wait/abort active ops */
506 callout_stop(&sc->sc_rngto);
508 crypto_unregister_all(sc->sc_cid);
512 rndtest_detach(sc->sc_rndtest);
515 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
518 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
519 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
520 ubsec_dma_free(sc, &q->q_dma->d_alloc);
524 if (sc->sc_flags & UBS_FLAGS_RNG) {
525 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
526 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
527 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
529 #endif /* UBSEC_NO_RNG */
531 bus_generic_detach(dev);
532 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
533 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
535 bus_dma_tag_destroy(sc->sc_dmat);
536 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
544 * Stop all chip i/o so that the kernel's probe routines don't
545 * get confused by errant DMAs when rebooting.
548 ubsec_shutdown(device_t dev)
551 ubsec_stop(device_get_softc(dev));
556 * Device suspend routine.
559 ubsec_suspend(device_t dev)
561 struct ubsec_softc *sc = device_get_softc(dev);
563 KASSERT(sc != NULL, ("ubsec_suspend: null software carrier"));
565 /* XXX stop the device and save PCI settings */
567 sc->sc_suspended = 1;
573 ubsec_resume(device_t dev)
575 struct ubsec_softc *sc = device_get_softc(dev);
577 KASSERT(sc != NULL, ("ubsec_resume: null software carrier"));
579 /* XXX retore PCI settings and start the device */
581 sc->sc_suspended = 0;
586 * UBSEC Interrupt routine
589 ubsec_intr(void *arg)
591 struct ubsec_softc *sc = arg;
592 volatile u_int32_t stat;
594 struct ubsec_dma *dmap;
597 stat = READ_REG(sc, BS_STAT);
598 stat &= sc->sc_statmask;
603 WRITE_REG(sc, BS_STAT, stat); /* IACK */
606 * Check to see if we have any packets waiting for us
608 if ((stat & BS_STAT_MCR1_DONE)) {
609 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
610 q = SIMPLEQ_FIRST(&sc->sc_qchip);
613 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
616 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
618 npkts = q->q_nstacked_mcrs;
619 sc->sc_nqchip -= 1+npkts;
621 * search for further sc_qchip ubsec_q's that share
622 * the same MCR, and complete them too, they must be
625 for (i = 0; i < npkts; i++) {
626 if(q->q_stacked_mcr[i]) {
627 ubsec_callback(sc, q->q_stacked_mcr[i]);
632 ubsec_callback(sc, q);
636 * Don't send any more packet to chip if there has been
639 if (!(stat & BS_STAT_DMAERR))
644 * Check to see if we have any key setups/rng's waiting for us
646 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
647 (stat & BS_STAT_MCR2_DONE)) {
649 struct ubsec_mcr *mcr;
651 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
652 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
654 ubsec_dma_sync(&q2->q_mcr,
655 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
657 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
658 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
659 ubsec_dma_sync(&q2->q_mcr,
660 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
663 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q_next);
664 ubsec_callback2(sc, q2);
666 * Don't send any more packet to chip if there has been
669 if (!(stat & BS_STAT_DMAERR))
675 * Check to see if we got any DMA Error
677 if (stat & BS_STAT_DMAERR) {
680 volatile u_int32_t a = READ_REG(sc, BS_ERR);
682 kprintf("dmaerr %s@%08x\n",
683 (a & BS_ERR_READ) ? "read" : "write",
686 #endif /* UBSEC_DEBUG */
687 ubsecstats.hst_dmaerr++;
688 ubsec_totalreset(sc);
692 if (sc->sc_needwakeup) { /* XXX check high watermark */
693 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
696 device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
698 #endif /* UBSEC_DEBUG */
699 sc->sc_needwakeup &= ~wakeup;
700 crypto_unblock(sc->sc_cid, wakeup);
705 * ubsec_feed() - aggregate and post requests to chip
708 ubsec_feed(struct ubsec_softc *sc)
710 struct ubsec_q *q, *q2;
716 * Decide how many ops to combine in a single MCR. We cannot
717 * aggregate more than UBS_MAX_AGGR because this is the number
718 * of slots defined in the data structure. Note that
719 * aggregation only happens if ops are marked batch'able.
720 * Aggregating ops reduces the number of interrupts to the host
721 * but also (potentially) increases the latency for processing
722 * completed ops as we only get an interrupt when all aggregated
723 * ops have completed.
725 if (sc->sc_nqueue == 0)
727 if (sc->sc_nqueue > 1) {
729 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
731 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
737 * Check device status before going any further.
739 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
740 if (stat & BS_STAT_DMAERR) {
741 ubsec_totalreset(sc);
742 ubsecstats.hst_dmaerr++;
744 ubsecstats.hst_mcr1full++;
747 if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
748 ubsecstats.hst_maxqueue = sc->sc_nqueue;
749 if (npkts > UBS_MAX_AGGR)
750 npkts = UBS_MAX_AGGR;
751 if (npkts < 2) /* special case 1 op */
754 ubsecstats.hst_totbatch += npkts-1;
757 kprintf("merging %d records\n", npkts);
758 #endif /* UBSEC_DEBUG */
760 q = SIMPLEQ_FIRST(&sc->sc_queue);
761 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
764 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
765 if (q->q_dst_map != NULL)
766 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
768 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
770 for (i = 0; i < q->q_nstacked_mcrs; i++) {
771 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
772 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
773 BUS_DMASYNC_PREWRITE);
774 if (q2->q_dst_map != NULL)
775 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
776 BUS_DMASYNC_PREREAD);
777 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
780 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
781 sizeof(struct ubsec_mcr_add));
782 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
783 q->q_stacked_mcr[i] = q2;
785 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
786 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
787 sc->sc_nqchip += npkts;
788 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
789 ubsecstats.hst_maxqchip = sc->sc_nqchip;
790 ubsec_dma_sync(&q->q_dma->d_alloc,
791 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
792 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
793 offsetof(struct ubsec_dmachunk, d_mcr));
797 q = SIMPLEQ_FIRST(&sc->sc_queue);
799 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
800 if (q->q_dst_map != NULL)
801 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
802 ubsec_dma_sync(&q->q_dma->d_alloc,
803 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
805 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
806 offsetof(struct ubsec_dmachunk, d_mcr));
809 kprintf("feed1: q->chip %p %08x stat %08x\n",
810 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
812 #endif /* UBSEC_DEBUG */
813 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
815 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
817 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
818 ubsecstats.hst_maxqchip = sc->sc_nqchip;
823 ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key)
826 /* Go ahead and compute key in ubsec's byte order */
827 if (algo == CRYPTO_DES_CBC) {
828 bcopy(key, &ses->ses_deskey[0], 8);
829 bcopy(key, &ses->ses_deskey[2], 8);
830 bcopy(key, &ses->ses_deskey[4], 8);
832 bcopy(key, ses->ses_deskey, 24);
834 SWAP32(ses->ses_deskey[0]);
835 SWAP32(ses->ses_deskey[1]);
836 SWAP32(ses->ses_deskey[2]);
837 SWAP32(ses->ses_deskey[3]);
838 SWAP32(ses->ses_deskey[4]);
839 SWAP32(ses->ses_deskey[5]);
843 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
849 for (i = 0; i < klen; i++)
850 key[i] ^= HMAC_IPAD_VAL;
852 if (algo == CRYPTO_MD5_HMAC) {
854 MD5Update(&md5ctx, key, klen);
855 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
856 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state));
859 SHA1Update(&sha1ctx, key, klen);
860 SHA1Update(&sha1ctx, hmac_ipad_buffer,
861 SHA1_HMAC_BLOCK_LEN - klen);
862 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
865 for (i = 0; i < klen; i++)
866 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
868 if (algo == CRYPTO_MD5_HMAC) {
870 MD5Update(&md5ctx, key, klen);
871 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
872 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state));
875 SHA1Update(&sha1ctx, key, klen);
876 SHA1Update(&sha1ctx, hmac_opad_buffer,
877 SHA1_HMAC_BLOCK_LEN - klen);
878 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
881 for (i = 0; i < klen; i++)
882 key[i] ^= HMAC_OPAD_VAL;
886 * Allocate a new 'session' and return an encoded session id. 'sidp'
887 * contains our registration id, and should contain an encoded session
888 * id on successful allocation.
891 ubsec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
893 struct ubsec_softc *sc = device_get_softc(dev);
894 struct cryptoini *c, *encini = NULL, *macini = NULL;
895 struct ubsec_session *ses = NULL;
903 KASSERT(sc != NULL, ("ubsec_newsession: null softc"));
904 if (sidp == NULL || cri == NULL || sc == NULL)
907 for (c = cri; c != NULL; c = c->cri_next) {
908 if (c->cri_alg == CRYPTO_MD5_HMAC ||
909 c->cri_alg == CRYPTO_SHA1_HMAC) {
913 } else if (c->cri_alg == CRYPTO_DES_CBC ||
914 c->cri_alg == CRYPTO_3DES_CBC) {
921 if (encini == NULL && macini == NULL)
924 if (sc->sc_sessions == NULL) {
925 ses = sc->sc_sessions = kmalloc(sizeof(struct ubsec_session),
926 M_DEVBUF, M_INTWAIT);
928 sc->sc_nsessions = 1;
930 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
931 if (sc->sc_sessions[sesn].ses_used == 0) {
932 ses = &sc->sc_sessions[sesn];
938 sesn = sc->sc_nsessions;
939 ses = kmalloc((sesn + 1) * sizeof(struct ubsec_session),
940 M_DEVBUF, M_INTWAIT);
941 bcopy(sc->sc_sessions, ses, sesn *
942 sizeof(struct ubsec_session));
943 bzero(sc->sc_sessions, sesn *
944 sizeof(struct ubsec_session));
945 kfree(sc->sc_sessions, M_DEVBUF);
946 sc->sc_sessions = ses;
947 ses = &sc->sc_sessions[sesn];
952 bzero(ses, sizeof(struct ubsec_session));
955 read_random(ses->ses_iv, sizeof(ses->ses_iv));
956 if (encini->cri_key != NULL) {
957 ubsec_setup_enckey(ses, encini->cri_alg,
963 ses->ses_mlen = macini->cri_mlen;
964 if (ses->ses_mlen == 0) {
965 if (macini->cri_alg == CRYPTO_MD5_HMAC)
966 ses->ses_mlen = MD5_HASH_LEN;
968 ses->ses_mlen = SHA1_HASH_LEN;
971 if (macini->cri_key != NULL) {
972 ubsec_setup_mackey(ses, macini->cri_alg,
973 macini->cri_key, macini->cri_klen/8);
977 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
982 * Deallocate a session.
985 ubsec_freesession(device_t dev, u_int64_t tid)
987 struct ubsec_softc *sc = device_get_softc(dev);
989 u_int32_t sid = CRYPTO_SESID2LID(tid);
991 KASSERT(sc != NULL, ("ubsec_freesession: null softc"));
995 session = UBSEC_SESSION(sid);
996 if (session >= sc->sc_nsessions)
999 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
1004 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1006 struct ubsec_operand *op = arg;
1008 KASSERT(nsegs <= UBS_MAX_SCATTER,
1009 ("Too many DMA segments returned when mapping operand"));
1012 kprintf("ubsec_op_cb: mapsize %u nsegs %d error %d\n",
1013 (u_int) mapsize, nsegs, error);
1018 op->mapsize = mapsize;
1020 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1024 ubsec_process(device_t dev, struct cryptop *crp, int hint)
1026 struct ubsec_softc *sc = device_get_softc(dev);
1027 struct ubsec_q *q = NULL;
1028 int err = 0, i, j, nicealign;
1029 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1030 int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1031 int sskip, dskip, stheend, dtheend;
1033 struct ubsec_session *ses;
1034 struct ubsec_pktctx ctx;
1035 struct ubsec_dma *dmap = NULL;
1037 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
1038 ubsecstats.hst_invalid++;
1041 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
1042 ubsecstats.hst_badsession++;
1048 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1049 ubsecstats.hst_queuefull++;
1050 sc->sc_needwakeup |= CRYPTO_SYMQ;
1054 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
1055 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
1058 dmap = q->q_dma; /* Save dma pointer */
1059 bzero(q, sizeof(struct ubsec_q));
1060 bzero(&ctx, sizeof(ctx));
1062 q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1064 ses = &sc->sc_sessions[q->q_sesn];
1066 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1067 q->q_src_m = (struct mbuf *)crp->crp_buf;
1068 q->q_dst_m = (struct mbuf *)crp->crp_buf;
1069 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1070 q->q_src_io = (struct uio *)crp->crp_buf;
1071 q->q_dst_io = (struct uio *)crp->crp_buf;
1073 ubsecstats.hst_badflags++;
1075 goto errout; /* XXX we don't handle contiguous blocks! */
1078 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1080 dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1081 dmap->d_dma->d_mcr.mcr_flags = 0;
1084 crd1 = crp->crp_desc;
1086 ubsecstats.hst_nodesc++;
1090 crd2 = crd1->crd_next;
1093 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1094 crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1097 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1098 crd1->crd_alg == CRYPTO_3DES_CBC) {
1102 ubsecstats.hst_badalg++;
1107 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1108 crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1109 (crd2->crd_alg == CRYPTO_DES_CBC ||
1110 crd2->crd_alg == CRYPTO_3DES_CBC) &&
1111 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1114 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1115 crd1->crd_alg == CRYPTO_3DES_CBC) &&
1116 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1117 crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1118 (crd1->crd_flags & CRD_F_ENCRYPT)) {
1123 * We cannot order the ubsec as requested
1125 ubsecstats.hst_badalg++;
1132 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1133 ubsec_setup_enckey(ses, enccrd->crd_alg,
1137 encoffset = enccrd->crd_skip;
1138 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1140 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1141 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1143 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1144 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1146 ctx.pc_iv[0] = ses->ses_iv[0];
1147 ctx.pc_iv[1] = ses->ses_iv[1];
1150 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1151 crypto_copyback(crp->crp_flags, crp->crp_buf,
1152 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1155 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1157 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1158 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1160 crypto_copydata(crp->crp_flags, crp->crp_buf,
1161 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv);
1165 ctx.pc_deskey[0] = ses->ses_deskey[0];
1166 ctx.pc_deskey[1] = ses->ses_deskey[1];
1167 ctx.pc_deskey[2] = ses->ses_deskey[2];
1168 ctx.pc_deskey[3] = ses->ses_deskey[3];
1169 ctx.pc_deskey[4] = ses->ses_deskey[4];
1170 ctx.pc_deskey[5] = ses->ses_deskey[5];
1171 SWAP32(ctx.pc_iv[0]);
1172 SWAP32(ctx.pc_iv[1]);
1176 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1177 ubsec_setup_mackey(ses, maccrd->crd_alg,
1178 maccrd->crd_key, maccrd->crd_klen / 8);
1181 macoffset = maccrd->crd_skip;
1183 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1184 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1186 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1188 for (i = 0; i < 5; i++) {
1189 ctx.pc_hminner[i] = ses->ses_hminner[i];
1190 ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1192 HTOLE32(ctx.pc_hminner[i]);
1193 HTOLE32(ctx.pc_hmouter[i]);
1197 if (enccrd && maccrd) {
1199 * ubsec cannot handle packets where the end of encryption
1200 * and authentication are not the same, or where the
1201 * encrypted part begins before the authenticated part.
1203 if ((encoffset + enccrd->crd_len) !=
1204 (macoffset + maccrd->crd_len)) {
1205 ubsecstats.hst_lenmismatch++;
1209 if (enccrd->crd_skip < maccrd->crd_skip) {
1210 ubsecstats.hst_skipmismatch++;
1214 sskip = maccrd->crd_skip;
1215 cpskip = dskip = enccrd->crd_skip;
1216 stheend = maccrd->crd_len;
1217 dtheend = enccrd->crd_len;
1218 coffset = enccrd->crd_skip - maccrd->crd_skip;
1219 cpoffset = cpskip + dtheend;
1222 kprintf("mac: skip %d, len %d, inject %d\n",
1223 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1224 kprintf("enc: skip %d, len %d, inject %d\n",
1225 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1226 kprintf("src: skip %d, len %d\n", sskip, stheend);
1227 kprintf("dst: skip %d, len %d\n", dskip, dtheend);
1228 kprintf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1229 coffset, stheend, cpskip, cpoffset);
1233 cpskip = dskip = sskip = macoffset + encoffset;
1234 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1235 cpoffset = cpskip + dtheend;
1238 ctx.pc_offset = htole16(coffset >> 2);
1240 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
1241 ubsecstats.hst_nomap++;
1245 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1246 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1247 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1248 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1249 q->q_src_map = NULL;
1250 ubsecstats.hst_noload++;
1254 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1255 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1256 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1257 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1258 q->q_src_map = NULL;
1259 ubsecstats.hst_noload++;
1264 nicealign = ubsec_dmamap_aligned(&q->q_src);
1266 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1270 kprintf("src skip: %d nicealign: %u\n", sskip, nicealign);
1272 for (i = j = 0; i < q->q_src_nsegs; i++) {
1273 struct ubsec_pktbuf *pb;
1274 bus_size_t packl = q->q_src_segs[i].ds_len;
1275 bus_addr_t packp = q->q_src_segs[i].ds_addr;
1277 if (sskip >= packl) {
1286 if (packl > 0xfffc) {
1292 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1294 pb = &dmap->d_dma->d_sbuf[j - 1];
1296 pb->pb_addr = htole32(packp);
1299 if (packl > stheend) {
1300 pb->pb_len = htole32(stheend);
1303 pb->pb_len = htole32(packl);
1307 pb->pb_len = htole32(packl);
1309 if ((i + 1) == q->q_src_nsegs)
1312 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1313 offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1317 if (enccrd == NULL && maccrd != NULL) {
1318 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1319 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1320 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
1321 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1324 kprintf("opkt: %x %x %x\n",
1325 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1326 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1327 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1330 if (crp->crp_flags & CRYPTO_F_IOV) {
1332 ubsecstats.hst_iovmisaligned++;
1336 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1338 ubsecstats.hst_nomap++;
1342 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1343 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) {
1344 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1345 q->q_dst_map = NULL;
1346 ubsecstats.hst_noload++;
1350 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1352 q->q_dst = q->q_src;
1355 struct mbuf *m, *top, **mp;
1357 ubsecstats.hst_unaligned++;
1358 totlen = q->q_src_mapsize;
1359 if (q->q_src_m->m_flags & M_PKTHDR) {
1361 MGETHDR(m, MB_DONTWAIT, MT_DATA);
1362 if (m && !m_dup_pkthdr(m, q->q_src_m, MB_DONTWAIT)) {
1368 MGET(m, MB_DONTWAIT, MT_DATA);
1371 ubsecstats.hst_nombuf++;
1372 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1375 if (totlen >= MINCLSIZE) {
1376 MCLGET(m, MB_DONTWAIT);
1377 if ((m->m_flags & M_EXT) == 0) {
1379 ubsecstats.hst_nomcl++;
1380 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1389 while (totlen > 0) {
1391 MGET(m, MB_DONTWAIT, MT_DATA);
1394 ubsecstats.hst_nombuf++;
1395 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1400 if (top && totlen >= MINCLSIZE) {
1401 MCLGET(m, MB_DONTWAIT);
1402 if ((m->m_flags & M_EXT) == 0) {
1405 ubsecstats.hst_nomcl++;
1406 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1411 m->m_len = len = min(totlen, len);
1417 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1419 if (bus_dmamap_create(sc->sc_dmat,
1420 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
1421 ubsecstats.hst_nomap++;
1425 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1426 q->q_dst_map, q->q_dst_m,
1427 ubsec_op_cb, &q->q_dst,
1428 BUS_DMA_NOWAIT) != 0) {
1429 bus_dmamap_destroy(sc->sc_dmat,
1431 q->q_dst_map = NULL;
1432 ubsecstats.hst_noload++;
1438 ubsecstats.hst_badflags++;
1445 kprintf("dst skip: %d\n", dskip);
1447 for (i = j = 0; i < q->q_dst_nsegs; i++) {
1448 struct ubsec_pktbuf *pb;
1449 bus_size_t packl = q->q_dst_segs[i].ds_len;
1450 bus_addr_t packp = q->q_dst_segs[i].ds_addr;
1452 if (dskip >= packl) {
1461 if (packl > 0xfffc) {
1467 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1469 pb = &dmap->d_dma->d_dbuf[j - 1];
1471 pb->pb_addr = htole32(packp);
1474 if (packl > dtheend) {
1475 pb->pb_len = htole32(dtheend);
1478 pb->pb_len = htole32(packl);
1482 pb->pb_len = htole32(packl);
1484 if ((i + 1) == q->q_dst_nsegs) {
1486 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1487 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1491 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1492 offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1497 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1498 offsetof(struct ubsec_dmachunk, d_ctx));
1500 if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1501 struct ubsec_pktctx_long *ctxl;
1503 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1504 offsetof(struct ubsec_dmachunk, d_ctx));
1506 /* transform small context into long context */
1507 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1508 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1509 ctxl->pc_flags = ctx.pc_flags;
1510 ctxl->pc_offset = ctx.pc_offset;
1511 for (i = 0; i < 6; i++)
1512 ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1513 for (i = 0; i < 5; i++)
1514 ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1515 for (i = 0; i < 5; i++)
1516 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1517 ctxl->pc_iv[0] = ctx.pc_iv[0];
1518 ctxl->pc_iv[1] = ctx.pc_iv[1];
1520 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1521 offsetof(struct ubsec_dmachunk, d_ctx),
1522 sizeof(struct ubsec_pktctx));
1525 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1527 ubsecstats.hst_ipackets++;
1528 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
1529 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
1536 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1537 m_freem(q->q_dst_m);
1539 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1540 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1541 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1543 if (q->q_src_map != NULL) {
1544 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1545 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1549 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1552 if (err != ERESTART) {
1553 crp->crp_etype = err;
1556 sc->sc_needwakeup |= CRYPTO_SYMQ;
1562 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1564 struct cryptop *crp = (struct cryptop *)q->q_crp;
1565 struct cryptodesc *crd;
1566 struct ubsec_dma *dmap = q->q_dma;
1568 ubsecstats.hst_opackets++;
1569 ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1571 ubsec_dma_sync(&dmap->d_alloc,
1572 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1573 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1574 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1575 BUS_DMASYNC_POSTREAD);
1576 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1577 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1579 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
1580 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1581 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1583 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1584 m_freem(q->q_src_m);
1585 crp->crp_buf = (caddr_t)q->q_dst_m;
1588 /* copy out IV for future use */
1589 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1590 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1591 if (crd->crd_alg != CRYPTO_DES_CBC &&
1592 crd->crd_alg != CRYPTO_3DES_CBC)
1594 crypto_copydata(crp->crp_flags, crp->crp_buf,
1595 crd->crd_skip + crd->crd_len - 8, 8,
1596 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1601 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1602 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1603 crd->crd_alg != CRYPTO_SHA1_HMAC)
1605 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject,
1606 sc->sc_sessions[q->q_sesn].ses_mlen,
1607 (caddr_t)dmap->d_dma->d_macbuf);
1609 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1614 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1616 int i, j, dlen, slen;
1620 sptr = srcm->m_data;
1622 dptr = dstm->m_data;
1626 for (i = 0; i < min(slen, dlen); i++) {
1627 if (j < hoffset || j >= toffset)
1634 srcm = srcm->m_next;
1637 sptr = srcm->m_data;
1641 dstm = dstm->m_next;
1644 dptr = dstm->m_data;
1651 * feed the key generator, must be called at splimp() or higher.
1654 ubsec_feed2(struct ubsec_softc *sc)
1658 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1659 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1661 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1663 ubsec_dma_sync(&q->q_mcr,
1664 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1665 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
1667 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1668 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q_next);
1670 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1676 * Callback for handling random numbers
1679 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1681 struct cryptkop *krp;
1682 struct ubsec_ctx_keyop *ctx;
1684 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1685 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
1687 switch (q->q_type) {
1688 #ifndef UBSEC_NO_RNG
1689 case UBS_CTXOP_RNGBYPASS: {
1690 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1692 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
1693 (*sc->sc_harvest)(sc->sc_rndtest,
1694 rng->rng_buf.dma_vaddr,
1695 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
1697 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1701 case UBS_CTXOP_MODEXP: {
1702 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1706 rlen = (me->me_modbits + 7) / 8;
1707 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1709 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
1710 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
1711 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
1712 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
1715 krp->krp_status = E2BIG;
1717 if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1718 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1719 (krp->krp_param[krp->krp_iparams].crp_nbits
1721 bcopy(me->me_C.dma_vaddr,
1722 krp->krp_param[krp->krp_iparams].crp_p,
1723 (me->me_modbits + 7) / 8);
1725 ubsec_kshift_l(me->me_shiftbits,
1726 me->me_C.dma_vaddr, me->me_normbits,
1727 krp->krp_param[krp->krp_iparams].crp_p,
1728 krp->krp_param[krp->krp_iparams].crp_nbits);
1733 /* bzero all potentially sensitive data */
1734 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1735 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1736 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1737 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1739 /* Can't free here, so put us on the free list. */
1740 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1743 case UBS_CTXOP_RSAPRIV: {
1744 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1748 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
1749 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
1751 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1752 bcopy(rp->rpr_msgout.dma_vaddr,
1753 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1757 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1758 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1759 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1761 /* Can't free here, so put us on the free list. */
1762 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1766 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
1767 letoh16(ctx->ctx_op));
1772 #ifndef UBSEC_NO_RNG
1774 ubsec_rng(void *vsc)
1776 struct ubsec_softc *sc = vsc;
1777 struct ubsec_q2_rng *rng = &sc->sc_rng;
1778 struct ubsec_mcr *mcr;
1779 struct ubsec_ctx_rngbypass *ctx;
1782 if (rng->rng_used) {
1787 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1790 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1791 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1793 mcr->mcr_pkts = htole16(1);
1795 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1796 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1797 mcr->mcr_ipktbuf.pb_len = 0;
1798 mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1799 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1800 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1802 mcr->mcr_opktbuf.pb_next = 0;
1804 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1805 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
1806 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
1808 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
1810 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1813 ubsecstats.hst_rng++;
1820 * Something weird happened, generate our own call back.
1824 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1826 #endif /* UBSEC_NO_RNG */
1829 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1831 bus_addr_t *paddr = (bus_addr_t*) arg;
1832 *paddr = segs->ds_addr;
1837 struct ubsec_softc *sc,
1839 struct ubsec_dma_alloc *dma,
1845 /* XXX could specify sc_dmat as parent but that just adds overhead */
1846 r = bus_dma_tag_create(NULL, /* parent */
1847 1, 0, /* alignment, bounds */
1848 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1849 BUS_SPACE_MAXADDR, /* highaddr */
1850 NULL, NULL, /* filter, filterarg */
1853 size, /* maxsegsize */
1854 BUS_DMA_ALLOCNOW, /* flags */
1857 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1858 "bus_dma_tag_create failed; error %u\n", r);
1862 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map);
1864 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1865 "bus_dmamap_create failed; error %u\n", r);
1869 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1870 BUS_DMA_NOWAIT, &dma->dma_map);
1872 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1873 "bus_dmammem_alloc failed; size %ju, error %u\n",
1878 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1882 mapflags | BUS_DMA_NOWAIT);
1884 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1885 "bus_dmamap_load failed; error %u\n", r);
1889 dma->dma_size = size;
1893 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1895 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1897 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1898 bus_dma_tag_destroy(dma->dma_tag);
1900 dma->dma_map = NULL;
1901 dma->dma_tag = NULL;
1906 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1908 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1909 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1910 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1911 bus_dma_tag_destroy(dma->dma_tag);
1915 * Resets the board. Values in the regesters are left as is
1916 * from the reset (i.e. initial values are assigned elsewhere).
1919 ubsec_reset_board(struct ubsec_softc *sc)
1921 volatile u_int32_t ctrl;
1923 ctrl = READ_REG(sc, BS_CTRL);
1924 ctrl |= BS_CTRL_RESET;
1925 WRITE_REG(sc, BS_CTRL, ctrl);
1928 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
1934 * Init Broadcom registers
1937 ubsec_init_board(struct ubsec_softc *sc)
1941 ctrl = READ_REG(sc, BS_CTRL);
1942 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
1943 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
1945 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
1946 ctrl |= BS_CTRL_MCR2INT;
1948 ctrl &= ~BS_CTRL_MCR2INT;
1950 if (sc->sc_flags & UBS_FLAGS_HWNORM)
1951 ctrl &= ~BS_CTRL_SWNORM;
1953 WRITE_REG(sc, BS_CTRL, ctrl);
1957 * Init Broadcom PCI registers
1960 ubsec_init_pciregs(device_t dev)
1965 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
1966 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
1967 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
1968 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
1969 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
1970 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
1974 * This will set the cache line size to 1, this will
1975 * force the BCM58xx chip just to do burst read/writes.
1976 * Cache line read/writes are to slow
1978 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
1982 * Clean up after a chip crash.
1983 * It is assumed that the caller in splimp()
1986 ubsec_cleanchip(struct ubsec_softc *sc)
1990 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
1991 q = SIMPLEQ_FIRST(&sc->sc_qchip);
1992 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
1993 ubsec_free_q(sc, q);
2000 * It is assumed that the caller is within spimp()
2003 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
2006 struct cryptop *crp;
2010 npkts = q->q_nstacked_mcrs;
2012 for (i = 0; i < npkts; i++) {
2013 if(q->q_stacked_mcr[i]) {
2014 q2 = q->q_stacked_mcr[i];
2016 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2017 m_freem(q2->q_dst_m);
2019 crp = (struct cryptop *)q2->q_crp;
2021 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2023 crp->crp_etype = EFAULT;
2033 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2034 m_freem(q->q_dst_m);
2036 crp = (struct cryptop *)q->q_crp;
2038 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2040 crp->crp_etype = EFAULT;
2046 * Routine to reset the chip and clean up.
2047 * It is assumed that the caller is in splimp()
2050 ubsec_totalreset(struct ubsec_softc *sc)
2052 ubsec_reset_board(sc);
2053 ubsec_init_board(sc);
2054 ubsec_cleanchip(sc);
2058 ubsec_dmamap_aligned(struct ubsec_operand *op)
2062 for (i = 0; i < op->nsegs; i++) {
2063 if (op->segs[i].ds_addr & 3)
2065 if ((i != (op->nsegs - 1)) &&
2066 (op->segs[i].ds_len & 3))
2073 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
2075 switch (q->q_type) {
2076 case UBS_CTXOP_MODEXP: {
2077 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
2079 ubsec_dma_free(sc, &me->me_q.q_mcr);
2080 ubsec_dma_free(sc, &me->me_q.q_ctx);
2081 ubsec_dma_free(sc, &me->me_M);
2082 ubsec_dma_free(sc, &me->me_E);
2083 ubsec_dma_free(sc, &me->me_C);
2084 ubsec_dma_free(sc, &me->me_epb);
2085 kfree(me, M_DEVBUF);
2088 case UBS_CTXOP_RSAPRIV: {
2089 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
2091 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2092 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
2093 ubsec_dma_free(sc, &rp->rpr_msgin);
2094 ubsec_dma_free(sc, &rp->rpr_msgout);
2095 kfree(rp, M_DEVBUF);
2099 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
2105 ubsec_kprocess(device_t dev, struct cryptkop *krp, int hint)
2107 struct ubsec_softc *sc = device_get_softc(dev);
2110 if (krp == NULL || krp->krp_callback == NULL)
2113 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
2116 q = SIMPLEQ_FIRST(&sc->sc_q2free);
2117 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q_next);
2121 switch (krp->krp_op) {
2123 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2124 r = ubsec_kprocess_modexp_hw(sc, krp, hint);
2126 r = ubsec_kprocess_modexp_sw(sc, krp, hint);
2128 case CRK_MOD_EXP_CRT:
2129 return (ubsec_kprocess_rsapriv(sc, krp, hint));
2131 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
2133 krp->krp_status = EOPNOTSUPP;
2137 return (0); /* silence compiler */
2141 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
2144 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2146 struct ubsec_q2_modexp *me;
2147 struct ubsec_mcr *mcr;
2148 struct ubsec_ctx_modexp *ctx;
2149 struct ubsec_pktbuf *epb;
2151 u_int nbits, normbits, mbits, shiftbits, ebits;
2153 me = kmalloc(sizeof *me, M_DEVBUF, M_INTWAIT | M_ZERO);
2155 me->me_q.q_type = UBS_CTXOP_MODEXP;
2157 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2160 else if (nbits <= 768)
2162 else if (nbits <= 1024)
2164 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2166 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2173 shiftbits = normbits - nbits;
2175 me->me_modbits = nbits;
2176 me->me_shiftbits = shiftbits;
2177 me->me_normbits = normbits;
2179 /* Sanity check: result bits must be >= true modulus bits. */
2180 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2185 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2186 &me->me_q.q_mcr, 0)) {
2190 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2192 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2193 &me->me_q.q_ctx, 0)) {
2198 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2199 if (mbits > nbits) {
2203 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2207 ubsec_kshift_r(shiftbits,
2208 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
2209 me->me_M.dma_vaddr, normbits);
2211 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2215 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2217 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2218 if (ebits > nbits) {
2222 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2226 ubsec_kshift_r(shiftbits,
2227 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
2228 me->me_E.dma_vaddr, normbits);
2230 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2235 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2236 epb->pb_addr = htole32(me->me_E.dma_paddr);
2238 epb->pb_len = htole32(normbits / 8);
2247 mcr->mcr_pkts = htole16(1);
2249 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2250 mcr->mcr_reserved = 0;
2251 mcr->mcr_pktlen = 0;
2253 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2254 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2255 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2257 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2258 mcr->mcr_opktbuf.pb_next = 0;
2259 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2262 /* Misaligned output buffer will hang the chip. */
2263 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2264 panic("%s: modexp invalid addr 0x%x\n",
2265 device_get_nameunit(sc->sc_dev),
2266 letoh32(mcr->mcr_opktbuf.pb_addr));
2267 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2268 panic("%s: modexp invalid len 0x%x\n",
2269 device_get_nameunit(sc->sc_dev),
2270 letoh32(mcr->mcr_opktbuf.pb_len));
2273 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2274 bzero(ctx, sizeof(*ctx));
2275 ubsec_kshift_r(shiftbits,
2276 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
2277 ctx->me_N, normbits);
2278 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2279 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2280 ctx->me_E_len = htole16(nbits);
2281 ctx->me_N_len = htole16(nbits);
2285 ubsec_dump_mcr(mcr);
2286 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2291 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2294 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2295 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2296 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2297 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2299 /* Enqueue and we're done... */
2301 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2303 ubsecstats.hst_modexp++;
2310 if (me->me_q.q_mcr.dma_map != NULL)
2311 ubsec_dma_free(sc, &me->me_q.q_mcr);
2312 if (me->me_q.q_ctx.dma_map != NULL) {
2313 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2314 ubsec_dma_free(sc, &me->me_q.q_ctx);
2316 if (me->me_M.dma_map != NULL) {
2317 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2318 ubsec_dma_free(sc, &me->me_M);
2320 if (me->me_E.dma_map != NULL) {
2321 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2322 ubsec_dma_free(sc, &me->me_E);
2324 if (me->me_C.dma_map != NULL) {
2325 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2326 ubsec_dma_free(sc, &me->me_C);
2328 if (me->me_epb.dma_map != NULL)
2329 ubsec_dma_free(sc, &me->me_epb);
2330 kfree(me, M_DEVBUF);
2332 krp->krp_status = err;
2338 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2341 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2343 struct ubsec_q2_modexp *me;
2344 struct ubsec_mcr *mcr;
2345 struct ubsec_ctx_modexp *ctx;
2346 struct ubsec_pktbuf *epb;
2348 u_int nbits, normbits, mbits, shiftbits, ebits;
2350 me = kmalloc(sizeof *me, M_DEVBUF, M_INTWAIT | M_ZERO);
2352 me->me_q.q_type = UBS_CTXOP_MODEXP;
2354 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2357 else if (nbits <= 768)
2359 else if (nbits <= 1024)
2361 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2363 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2370 shiftbits = normbits - nbits;
2373 me->me_modbits = nbits;
2374 me->me_shiftbits = shiftbits;
2375 me->me_normbits = normbits;
2377 /* Sanity check: result bits must be >= true modulus bits. */
2378 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2383 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2384 &me->me_q.q_mcr, 0)) {
2388 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2390 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2391 &me->me_q.q_ctx, 0)) {
2396 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2397 if (mbits > nbits) {
2401 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2405 bzero(me->me_M.dma_vaddr, normbits / 8);
2406 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2407 me->me_M.dma_vaddr, (mbits + 7) / 8);
2409 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2413 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2415 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2416 if (ebits > nbits) {
2420 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2424 bzero(me->me_E.dma_vaddr, normbits / 8);
2425 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2426 me->me_E.dma_vaddr, (ebits + 7) / 8);
2428 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2433 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2434 epb->pb_addr = htole32(me->me_E.dma_paddr);
2436 epb->pb_len = htole32((ebits + 7) / 8);
2445 mcr->mcr_pkts = htole16(1);
2447 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2448 mcr->mcr_reserved = 0;
2449 mcr->mcr_pktlen = 0;
2451 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2452 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2453 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2455 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2456 mcr->mcr_opktbuf.pb_next = 0;
2457 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2460 /* Misaligned output buffer will hang the chip. */
2461 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2462 panic("%s: modexp invalid addr 0x%x\n",
2463 device_get_nameunit(sc->sc_dev),
2464 letoh32(mcr->mcr_opktbuf.pb_addr));
2465 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2466 panic("%s: modexp invalid len 0x%x\n",
2467 device_get_nameunit(sc->sc_dev),
2468 letoh32(mcr->mcr_opktbuf.pb_len));
2471 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2472 bzero(ctx, sizeof(*ctx));
2473 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2475 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2476 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2477 ctx->me_E_len = htole16(ebits);
2478 ctx->me_N_len = htole16(nbits);
2482 ubsec_dump_mcr(mcr);
2483 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2488 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2491 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2492 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2493 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2494 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2496 /* Enqueue and we're done... */
2498 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2506 if (me->me_q.q_mcr.dma_map != NULL)
2507 ubsec_dma_free(sc, &me->me_q.q_mcr);
2508 if (me->me_q.q_ctx.dma_map != NULL) {
2509 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2510 ubsec_dma_free(sc, &me->me_q.q_ctx);
2512 if (me->me_M.dma_map != NULL) {
2513 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2514 ubsec_dma_free(sc, &me->me_M);
2516 if (me->me_E.dma_map != NULL) {
2517 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2518 ubsec_dma_free(sc, &me->me_E);
2520 if (me->me_C.dma_map != NULL) {
2521 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2522 ubsec_dma_free(sc, &me->me_C);
2524 if (me->me_epb.dma_map != NULL)
2525 ubsec_dma_free(sc, &me->me_epb);
2526 kfree(me, M_DEVBUF);
2528 krp->krp_status = err;
2534 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2536 struct ubsec_q2_rsapriv *rp = NULL;
2537 struct ubsec_mcr *mcr;
2538 struct ubsec_ctx_rsapriv *ctx;
2540 u_int padlen, msglen;
2542 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2543 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2544 if (msglen > padlen)
2549 else if (padlen <= 384)
2551 else if (padlen <= 512)
2553 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2555 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2562 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2567 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2572 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2577 rp = kmalloc(sizeof *rp, M_DEVBUF, M_INTWAIT | M_ZERO);
2579 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2581 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2582 &rp->rpr_q.q_mcr, 0)) {
2586 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2588 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2589 &rp->rpr_q.q_ctx, 0)) {
2593 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2594 bzero(ctx, sizeof *ctx);
2597 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2598 &ctx->rpr_buf[0 * (padlen / 8)],
2599 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2602 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2603 &ctx->rpr_buf[1 * (padlen / 8)],
2604 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2607 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2608 &ctx->rpr_buf[2 * (padlen / 8)],
2609 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2612 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2613 &ctx->rpr_buf[3 * (padlen / 8)],
2614 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2617 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2618 &ctx->rpr_buf[4 * (padlen / 8)],
2619 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2621 msglen = padlen * 2;
2623 /* Copy in input message (aligned buffer/length). */
2624 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2625 /* Is this likely? */
2629 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2633 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2634 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2635 rp->rpr_msgin.dma_vaddr,
2636 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2638 /* Prepare space for output message (aligned buffer/length). */
2639 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2640 /* Is this likely? */
2644 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2648 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2650 mcr->mcr_pkts = htole16(1);
2652 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2653 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2654 mcr->mcr_ipktbuf.pb_next = 0;
2655 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2656 mcr->mcr_reserved = 0;
2657 mcr->mcr_pktlen = htole16(msglen);
2658 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2659 mcr->mcr_opktbuf.pb_next = 0;
2660 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2663 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2664 panic("%s: rsapriv: invalid msgin %x(0x%jx)",
2665 device_get_nameunit(sc->sc_dev),
2666 rp->rpr_msgin.dma_paddr,
2667 (uintmax_t)rp->rpr_msgin.dma_size);
2669 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2670 panic("%s: rsapriv: invalid msgout %x(0x%jx)",
2671 device_get_nameunit(sc->sc_dev),
2672 rp->rpr_msgout.dma_paddr,
2673 (uintmax_t)rp->rpr_msgout.dma_size);
2677 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2678 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2679 ctx->rpr_q_len = htole16(padlen);
2680 ctx->rpr_p_len = htole16(padlen);
2683 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2686 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
2687 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
2689 /* Enqueue and we're done... */
2691 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2693 ubsecstats.hst_modexpcrt++;
2699 if (rp->rpr_q.q_mcr.dma_map != NULL)
2700 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2701 if (rp->rpr_msgin.dma_map != NULL) {
2702 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2703 ubsec_dma_free(sc, &rp->rpr_msgin);
2705 if (rp->rpr_msgout.dma_map != NULL) {
2706 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2707 ubsec_dma_free(sc, &rp->rpr_msgout);
2709 kfree(rp, M_DEVBUF);
2711 krp->krp_status = err;
2718 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
2720 kprintf("addr 0x%x (0x%x) next 0x%x\n",
2721 pb->pb_addr, pb->pb_len, pb->pb_next);
2725 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2727 kprintf("CTX (0x%x):\n", c->ctx_len);
2728 switch (letoh16(c->ctx_op)) {
2729 case UBS_CTXOP_RNGBYPASS:
2730 case UBS_CTXOP_RNGSHA1:
2732 case UBS_CTXOP_MODEXP:
2734 struct ubsec_ctx_modexp *cx = (void *)c;
2737 kprintf(" Elen %u, Nlen %u\n",
2738 letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2739 len = (cx->me_N_len + 7)/8;
2740 for (i = 0; i < len; i++)
2741 kprintf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2746 kprintf("unknown context: %x\n", c->ctx_op);
2748 kprintf("END CTX\n");
2752 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2754 volatile struct ubsec_mcr_add *ma;
2758 kprintf(" pkts: %u, flags 0x%x\n",
2759 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2760 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2761 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2762 kprintf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2763 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2764 letoh16(ma->mcr_reserved));
2765 kprintf(" %d: ipkt ", i);
2766 ubsec_dump_pb(&ma->mcr_ipktbuf);
2767 kprintf(" %d: opkt ", i);
2768 ubsec_dump_pb(&ma->mcr_opktbuf);
2771 kprintf("END MCR\n");
2773 #endif /* UBSEC_DEBUG */
2776 * Return the number of significant bits of a big number.
2779 ubsec_ksigbits(struct crparam *cr)
2781 u_int plen = (cr->crp_nbits + 7) / 8;
2782 int i, sig = plen * 8;
2783 u_int8_t c, *p = cr->crp_p;
2785 for (i = plen - 1; i >= 0; i--) {
2788 while ((c & 0x80) == 0) {
2802 u_int8_t *src, u_int srcbits,
2803 u_int8_t *dst, u_int dstbits)
2808 slen = (srcbits + 7) / 8;
2809 dlen = (dstbits + 7) / 8;
2811 for (i = 0; i < slen; i++)
2813 for (i = 0; i < dlen - slen; i++)
2821 dst[di--] = dst[si--];
2828 for (i = dlen - 1; i > 0; i--)
2829 dst[i] = (dst[i] << n) |
2830 (dst[i - 1] >> (8 - n));
2831 dst[0] = dst[0] << n;
2838 u_int8_t *src, u_int srcbits,
2839 u_int8_t *dst, u_int dstbits)
2841 int slen, dlen, i, n;
2843 slen = (srcbits + 7) / 8;
2844 dlen = (dstbits + 7) / 8;
2847 for (i = 0; i < slen; i++)
2848 dst[i] = src[i + n];
2849 for (i = 0; i < dlen - slen; i++)
2854 for (i = 0; i < (dlen - 1); i++)
2855 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2856 dst[dlen - 1] = dst[dlen - 1] >> n;